/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SERIAL_H__ #define __SERIAL_H__ //#define P_AO_UART_WFIFO (0xc81004c0) //#define P_AO_RTI_PIN_MUX_REG (0xc8100014) #define UART_WFIFO (0<<2) #define UART_RFIFO (1<<2) #define UART_CONTROL (2<<2) #define UART_STATUS (3<<2) #define UART_MISC (4<<2) #define UART_PORT_CONS AO_UART_WFIFO //#define UART_CLK_SRC CLK_CLK81 #define P_UART(uart_base,reg) (uart_base+reg) #define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO) #define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO) #define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL) #define UART_CNTL_MASK_BAUD_RATE (0xfff) #define UART_CNTL_MASK_TX_EN (1<<12) #define UART_CNTL_MASK_RX_EN (1<<13) #define UART_CNTL_MASK_2WIRE (1<<15) #define UART_CNTL_MASK_STP_BITS (3<<16) #define UART_CNTL_MASK_STP_1BIT (0<<16) #define UART_CNTL_MASK_STP_2BIT (1<<16) #define UART_CNTL_MASK_PRTY_EVEN (0<<18) #define UART_CNTL_MASK_PRTY_ODD (1<<18) #define UART_CNTL_MASK_PRTY_TYPE (1<<18) #define UART_CNTL_MASK_PRTY_EN (1<<19) #define UART_CNTL_MASK_CHAR_LEN (3<<20) #define UART_CNTL_MASK_CHAR_8BIT (0<<20) #define UART_CNTL_MASK_CHAR_7BIT (1<<20) #define UART_CNTL_MASK_CHAR_6BIT (2<<20) #define UART_CNTL_MASK_CHAR_5BIT (3<<20) #define UART_CNTL_MASK_RST_TX (1<<22) #define UART_CNTL_MASK_RST_RX (1<<23) #define UART_CNTL_MASK_CLR_ERR (1<<24) #define UART_CNTL_MASK_INV_RX (1<<25) #define UART_CNTL_MASK_INV_TX (1<<26) #define UART_CNTL_MASK_RINT_EN (1<<27) #define UART_CNTL_MASK_TINT_EN (1<<28) #define UART_CNTL_MASK_INV_CTS (1<<29) #define UART_CNTL_MASK_MASK_ERR (1<<30) #define UART_CNTL_MASK_INV_RTS (1<<31) #define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS ) #define UART_STAT_MASK_RFIFO_CNT (0x3f<<0) #define UART_STAT_MASK_TFIFO_CNT (0x3f<<8) #define UART_STAT_MASK_PRTY_ERR (1<<16) #define UART_STAT_MASK_FRAM_ERR (1<<17) #define UART_STAT_MASK_WFULL_ERR (1<<18) #define UART_STAT_MASK_RFIFO_FULL (1<<19) #define UART_STAT_MASK_RFIFO_EMPTY (1<<20) #define UART_STAT_MASK_TFIFO_FULL (1<<21) #define UART_STAT_MASK_TFIFO_EMPTY (1<<22) #define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC) void serial_init(unsigned set); int serial_putc(int c); int serial_getc(void); int serial_puts(const char *s); void serial_put_hex(unsigned long data,unsigned int bitlen); void serial_put_dec(unsigned long data); #endif /* __SERIAL_H__ */