typedef unsigned char undefined; typedef unsigned char bool; typedef unsigned char byte; typedef unsigned char uchar; typedef unsigned int uint; typedef unsigned long ulong; typedef unsigned char undefined1; typedef unsigned short undefined2; typedef unsigned int undefined4; typedef unsigned long undefined8; typedef unsigned short ushort; typedef struct struct ddrfw_toc_hdr struct ddrfw_toc_hdr, *Pstruct ddrfw_toc_hdr; typedef uint uint32_t; typedef ulong uint64_t; struct struct ddrfw_toc_hdr { /* gxlimg */ uint32_t magic; uint32_t count; uint64_t flags; }; typedef struct tzram_layout tzram_layout, *Ptzram_layout; struct tzram_layout { undefined8 total_base; undefined8 total_size; undefined8 free_base; undefined8 free_size; undefined8 attr__unk; undefined8 next; }; typedef struct struct ddrfw_toc_entry struct ddrfw_toc_entry, *Pstruct ddrfw_toc_entry; typedef uchar uint8_t; struct struct ddrfw_toc_entry { /* Taken from gxlimg */ uint8_t magic[8]; uint32_t offset; uint32_t size; uint8_t props[16]; uint8_t hash[32]; }; typedef struct _PMU_SMB_LPDDR4_1D_t _PMU_SMB_LPDDR4_1D_t, *P_PMU_SMB_LPDDR4_1D_t; typedef ushort uint16_t; typedef char int8_t; struct _PMU_SMB_LPDDR4_1D_t { uint8_t Reserved00; uint8_t MsgMisc; uint16_t PmuRevision; uint8_t Pstate; uint8_t PllBypassEn; uint16_t DRAMFreq; uint8_t DfiFreqRatio; uint8_t BPZNResVal; uint8_t PhyOdtImpedance; uint8_t PhyDrvImpedance; uint8_t PhyVref; uint8_t Lp4Misc; uint8_t Reserved0E; uint8_t CsTestFail; uint16_t SequenceCtrl; uint8_t HdtCtrl; uint8_t Reserved13; uint8_t Reserved14; uint8_t Reserved15; uint8_t DFIMRLMargin; uint8_t Reserved17; uint8_t UseBroadcastMR; uint8_t Lp4Quickboot; uint8_t Reserved1A; uint8_t CATrainOpt; uint8_t X8Mode; uint8_t Reserved1D; uint8_t Reserved1E; uint8_t Reserved1F; uint8_t Reserved20; uint8_t Reserved21; uint16_t PhyConfigOverride; uint8_t EnabledDQsChA; uint8_t CsPresentChA; int8_t CDD_ChA_RR_1_0; int8_t CDD_ChA_RR_0_1; int8_t CDD_ChA_RW_1_1; int8_t CDD_ChA_RW_1_0; int8_t CDD_ChA_RW_0_1; int8_t CDD_ChA_RW_0_0; int8_t CDD_ChA_WR_1_1; int8_t CDD_ChA_WR_1_0; int8_t CDD_ChA_WR_0_1; int8_t CDD_ChA_WR_0_0; int8_t CDD_ChA_WW_1_0; int8_t CDD_ChA_WW_0_1; uint8_t MR1_A0; uint8_t MR2_A0; uint8_t MR3_A0; uint8_t MR4_A0; uint8_t MR11_A0; uint8_t MR12_A0; uint8_t MR13_A0; uint8_t MR14_A0; uint8_t MR16_A0; uint8_t MR17_A0; uint8_t MR22_A0; uint8_t MR24_A0; uint8_t MR1_A1; uint8_t MR2_A1; uint8_t MR3_A1; uint8_t MR4_A1; uint8_t MR11_A1; uint8_t MR12_A1; uint8_t MR13_A1; uint8_t MR14_A1; uint8_t MR16_A1; uint8_t MR17_A1; uint8_t MR22_A1; uint8_t MR24_A1; uint8_t CATerminatingRankChA; uint8_t Reserved4B; uint8_t Reserved4C; uint8_t Reserved4D; uint8_t Reserved4E; uint8_t Reserved4F; uint8_t Reserved50; uint8_t Reserved51; uint8_t Reserved52; uint8_t Reserved53; uint8_t Reserved54; uint8_t Reserved55; uint8_t Reserved56; uint8_t EnabledDQsChB; uint8_t CsPresentChB; int8_t CDD_ChB_RR_1_0; int8_t CDD_ChB_RR_0_1; int8_t CDD_ChB_RW_1_1; int8_t CDD_ChB_RW_1_0; int8_t CDD_ChB_RW_0_1; int8_t CDD_ChB_RW_0_0; int8_t CDD_ChB_WR_1_1; int8_t CDD_ChB_WR_1_0; int8_t CDD_ChB_WR_0_1; int8_t CDD_ChB_WR_0_0; int8_t CDD_ChB_WW_1_0; int8_t CDD_ChB_WW_0_1; uint8_t MR1_B0; uint8_t MR2_B0; uint8_t MR3_B0; uint8_t MR4_B0; uint8_t MR11_B0; uint8_t MR12_B0; uint8_t MR13_B0; uint8_t MR14_B0; uint8_t MR16_B0; uint8_t MR17_B0; uint8_t MR22_B0; uint8_t MR24_B0; uint8_t MR1_B1; uint8_t MR2_B1; uint8_t MR3_B1; uint8_t MR4_B1; uint8_t MR11_B1; uint8_t MR12_B1; uint8_t MR13_B1; uint8_t MR14_B1; uint8_t MR16_B1; uint8_t MR17_B1; uint8_t MR22_B1; uint8_t MR24_B1; uint8_t CATerminatingRankChB; uint8_t Reserved7E; uint8_t Reserved7F; uint8_t Reserved80; uint8_t Reserved81; uint8_t Reserved82; uint8_t Reserved83; uint8_t Reserved84; uint8_t Reserved85; uint8_t Reserved86; uint8_t Reserved87; uint8_t Reserved88; uint8_t Reserved89; }; typedef struct _PMU_SMB_LPDDR4_1D_t PMU_SMB_LPDDR4_1D_t; #define CONFIG_DDR_SIZE 1024 #define CONFIG_AML_BL33_COMPRESS_ENABLE 1 #define CONFIG_AML_CUSTOMER_ID 0 #define CONFIG_CMD_DTIMG 1 #define CONFIG_AML_RSVD_SIZE 1048576 #define CONFIG_SYS_MALLOC_LEN 67108864 #define CONFIG_CMD_VIU_PROBE 1 #define CONFIG_SYS_TEXT_BASE 16777216 #define CONFIG_OF_LIBFDT_OVERLAY 1 #define CONFIG_DTB_MEM_ADDR 16777216 #define CONFIG_SYS_INIT_SP_ADDR 536870912 #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_AML_MESON 1 #define COUNTER_FREQUENCY 25165824 #define CONFIG_AML_RSVD_ADDR 137363456 #define CONFIG_SYS_LOAD_ADDR 16777216 #define PHYS_SDRAM_1_SIZE 1073741824 #define CONFIG_AML_MESON_G12A 1 #define CONFIG_AML_SECURE_BOOT_V3 1 #define CONFIG_SYS_CBSIZE 512 #define CONFIG_AML_MESON_GX 1 #define PHYS_SDRAM_1_BASE 0 #define DDR_RFC_TYPE_DDR3_512Mbx4 2 #define DDR_RFC_TYPE_DDR3_512Mbx1 0 #define DMC_TEST_SLT_OFFSET_DELAY 2 #define DDR_RFC_TYPE_DDR3_512Mbx2 1 #define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 49 #define DDR_RFC_TYPE_DDR3_512Mbx8 3 #define DDR_RFC_TYPE_LPDDR4_8Gbx1 13 #define CONFIG_DDR_TIMMING_DDR4_2666 19 #define LPDDR_DIE_ROW_COL_R14_C11 4 #define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 0 #define LPDDR_DIE_ROW_COL_R14_C10 2 #define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 0 #define DDR_DDR4_ENABLE 4194304 #define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 32 #define CONFIG_DDR_INIT_RETRY_TOTAL 10 #define CONFIG_DDR0_32BIT_RANK01_CH01 3 #define CONFIG_DDR_ZQ_PD 0 #define DWC_AC_PINMUX_TOTAL 28 #define CONFIG_DIAGNOSE_1D 1 #define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ 16 #define DDR_16BIT_ENABLE 65536 #define CONFIG_DIAGNOSE_2D 2 #define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 #define CONFIG_DDR0_RANK0 2 #define DWC_DQ_PINMUX_TOTAL 32 #define CONFIG_DDR0_16BIT_2 4 #define DDR_RANK0_SIZE_CTRL 0 #define CFG_DDR_START_OFFSET 0 #define DDR_DDR4_BG_ENABLE 1048576 #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 5 #define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING 64 #define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP 0 #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 6 #define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1 #define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2 #define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3 #define CONFIG_DDR0_32BIT_RANK0_CH0 2 #define CONFIG_DIAGNOSE_DISABLE 0 #define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 64 #define CONFIG_DDR_FUNC_LPDDR3_CA 0 #define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0 #define CONFIG_DDR_CHL_AUTO 15 #define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 65 #define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS 4 #define DDR_RANK1_ENABLE 2097152 #define CONFIG_DDR_FULL_TEST 0 #define CONFIG_DDR_TIMMING_DDR4_3200 20 #define CONFIG_DDR_TYPE_AUTO 15 #define DWC_DFI_PINMUX_TOTAL 26 #define CONFIG_DDR_TYPE_LPDDR2 4 #define CONFIG_DDR_TYPE_LPDDR3 3 #define CONFIG_DDR_TYPE_LPDDR4 2 #define DDR_FUNC_LP 0 #define DDR_RANK1_SIZE_CTRL 3 #define CONFIG_DDR4_TIMING_TEST 0 #define CONFIG_DDR_FUNC_PRINT_WINDOW 0 #define CONFIG_DDR_TIMMING_DDR3_12 12 #define CONFIG_DDR_TIMMING_DDR3_11 11 #define CONFIG_DDR_TIMMING_DDR3_14 14 #define CONFIG_DDR_TIMMING_DDR3_13 13 #define DDR_FUNC_PRINT_WINDOW 0 #define LPDDR_DIE_ROW_COL_R13_C9 0 #define DDR_FUNC_EXT_VREF 0 #define CONFIG_DDR0_32BIT_RANK01_CH0 7 #define DDR_FUNC_ZQ_PD 0 #define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 0 #define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 0 #define CONFIG_DDR_TIMMING_DDR4_1600 15 #define DRAM_CFG_MAGIC 778528355 #define DDR_FUNC_DDR4_TIMING_TEST 0 #define DDR_RFC_TYPE_LPDDR4_6Gbx1 12 #define CONFIG_DDR_TIMMING_DDR4_2133 17 #define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 16 #define CONFIG_DDR0_16BIT 1 #define DDR_NONSEC_SCRAMBLE 0 #define CONFIG_DDR0_16BIT_CH0 1 #define CONFIG_LPDDR_REMAP_SET 1 #define CONFIG_DDR_PCTL_RETRY_TOTAL 100 #define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS 2 #define CONFIG_DDR_TIMMING_DDR3_9 9 #define CONFIG_DDR_TIMMING_DDR3_7 7 #define CONFIG_DDR_TIMMING_DDR4_1866 16 #define CONFIG_DDR_FUNC_TEST 1 #define BL2_INIT_STAGE_9 9 #define BL2_INIT_STAGE_8 8 #define BL2_INIT_STAGE_7 7 #define BL2_INIT_STAGE_6 6 #define BL2_INIT_STAGE_5 5 #define LPDDR_DIE_ROW_COL_R14_C9 1 #define CONFIG_DDR_LOW_POWER 0 #define CONFIG_DDR0_16BIT_RANK01_CH0 4 #define CONFIG_DDR_PLL_BYPASS 0 #define LPDDR_DIE_ROW_COL_R13_C10 3 #define CONFIG_BOARD_ID_MASK 255 #define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 #define BL2_INIT_STAGE_4 4 #define BL2_INIT_STAGE_3 3 #define BL2_INIT_STAGE_2 2 #define DDR_FUNC_DDR_PLL_BYPASS 0 #define BL2_INIT_STAGE_1 1 #define BL2_INIT_STAGE_0 0 #define CONFIG_DIAGNOSE_1D_2D 3 #define DDR_FUNC_RDBI 0 #define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ 8 #define DMC_TEST_SLT_SCAN_FREQUENCY 1 #define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 17 #define CONFIG_DDR_USE_EXT_VREF 0 #define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 48 #define CFG_DDR_BASE_ADDR 0 #define DMC_TEST_SLT_ENABLE_DDR_DVFS 128 #define CONFIG_DDR0_RANK01 3 #define DDR_FUNC_D2PLL 0 #define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY 1 #define CONFIG_DDR_FUNC_RDBI 0 #define DDR_FULL_TEST 0 #define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 16 #define DDR_FUNC_LPDDR3_CA 0 #define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 33 #define CONFIG_CMD_DDR_D2PLL 0 #define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 32 #define DDR_RFC_TYPE_DDR3_512Mbx16 4 #define CONFIG_DDR_NONSEC_SCRAMBLE 0 #define CONFIG_DDR0_32BIT_RANK0_CH01 8 #define CONFIG_DDR_TYPE_DDR3 0 #define CONFIG_DDR_TYPE_DDR4 1 #define DDR_RFC_TYPE_DDR4_2Gbx4 7 #define DDR_RFC_TYPE_DDR4_2Gbx8 8 #define CONFIG_DDR_TIMMING_DDR4_2400 18 #define CONFIG_DDR_TIMMING_LPDDR3 3 #define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 #define DDR_RFC_TYPE_DDR4_2Gbx1 5 #define CONFIG_DDR_TIMMING_LPDDR2 2 #define DDR_RFC_TYPE_DDR4_2Gbx2 6 #define IO_AXI_BUS_BASE 4289724416 #define IO_APB_HDMI_BUS_BASE 4292870144 #define IO_AHB_BUS_BASE 4283432960 #define IO_CBUS_BASE 4291821568 #define IO_VPU_BUS_BASE 4287627264 #define IO_APB_BUS_BASE 4294705152 #define AO_SEC_GP_CFG7_W0_BIT 8 #define BOOT_ID_SPI 3 #define BOOT_ID_EMMC 1 #define BOOT_ID_NAND 2 #define AO_SEC_GP_CFG7_W0 256 #define AO_SEC_SD_CFG10_CB 2147483648 #define BOOT_ID_RESERVED 0 #define BOOT_ID_SDCARD 4 #define BOOT_ID_USB 5 typedef struct _PMU_SMB_DDR3U_1D_t _PMU_SMB_DDR3U_1D_t, *P_PMU_SMB_DDR3U_1D_t; typedef struct _PMU_SMB_DDR3U_1D_t PMU_SMB_DDR3U_1D_t; struct _PMU_SMB_DDR3U_1D_t { uint8_t Reserved00; uint8_t MsgMisc; uint16_t PmuRevision; uint8_t Pstate; uint8_t PllBypassEn; uint16_t DRAMFreq; uint8_t DfiFreqRatio; uint8_t BPZNResVal; uint8_t PhyOdtImpedance; uint8_t PhyDrvImpedance; uint8_t PhyVref; uint8_t DramType; uint8_t DisabledDbyte; uint8_t EnabledDQs; uint8_t CsPresent; uint8_t CsPresentD0; uint8_t CsPresentD1; uint8_t AddrMirror; uint8_t CsTestFail; uint8_t PhyCfg; uint16_t SequenceCtrl; uint8_t HdtCtrl; uint8_t Reserved19; uint8_t Reserved1A; uint8_t Reserved1B; uint8_t Reserved1C; uint8_t Reserved1D; uint8_t Reserved1E; uint8_t Reserved1F; uint8_t Reserved20; uint8_t Reserved21; uint16_t PhyConfigOverride; uint8_t DFIMRLMargin; int8_t CDD_RR_3_2; int8_t CDD_RR_3_1; int8_t CDD_RR_3_0; int8_t CDD_RR_2_3; int8_t CDD_RR_2_1; int8_t CDD_RR_2_0; int8_t CDD_RR_1_3; int8_t CDD_RR_1_2; int8_t CDD_RR_1_0; int8_t CDD_RR_0_3; int8_t CDD_RR_0_2; int8_t CDD_RR_0_1; int8_t CDD_WW_3_2; int8_t CDD_WW_3_1; int8_t CDD_WW_3_0; int8_t CDD_WW_2_3; int8_t CDD_WW_2_1; int8_t CDD_WW_2_0; int8_t CDD_WW_1_3; int8_t CDD_WW_1_2; int8_t CDD_WW_1_0; int8_t CDD_WW_0_3; int8_t CDD_WW_0_2; int8_t CDD_WW_0_1; int8_t CDD_RW_3_3; int8_t CDD_RW_3_2; int8_t CDD_RW_3_1; int8_t CDD_RW_3_0; int8_t CDD_RW_2_3; int8_t CDD_RW_2_2; int8_t CDD_RW_2_1; int8_t CDD_RW_2_0; int8_t CDD_RW_1_3; int8_t CDD_RW_1_2; int8_t CDD_RW_1_1; int8_t CDD_RW_1_0; int8_t CDD_RW_0_3; int8_t CDD_RW_0_2; int8_t CDD_RW_0_1; int8_t CDD_RW_0_0; int8_t CDD_WR_3_3; int8_t CDD_WR_3_2; int8_t CDD_WR_3_1; int8_t CDD_WR_3_0; int8_t CDD_WR_2_3; int8_t CDD_WR_2_2; int8_t CDD_WR_2_1; int8_t CDD_WR_2_0; int8_t CDD_WR_1_3; int8_t CDD_WR_1_2; int8_t CDD_WR_1_1; int8_t CDD_WR_1_0; int8_t CDD_WR_0_3; int8_t CDD_WR_0_2; int8_t CDD_WR_0_1; int8_t CDD_WR_0_0; uint8_t Reserved5D; uint16_t MR0; uint16_t MR1; uint16_t MR2; uint8_t Reserved64; uint8_t Reserved65; uint8_t Reserved66; uint8_t Reserved67; uint8_t Reserved68; uint8_t Reserved69; uint8_t Reserved6A; uint8_t Reserved6B; uint8_t Reserved6C; uint8_t Reserved6D; uint8_t Reserved6E; uint8_t Reserved6F; uint8_t Reserved70; uint8_t Reserved71; uint8_t Reserved72; uint8_t Reserved73; uint8_t AcsmOdtCtrl0; uint8_t AcsmOdtCtrl1; uint8_t AcsmOdtCtrl2; uint8_t AcsmOdtCtrl3; uint8_t AcsmOdtCtrl4; uint8_t AcsmOdtCtrl5; uint8_t AcsmOdtCtrl6; uint8_t AcsmOdtCtrl7; uint8_t Reserved7C; uint8_t Reserved7D; uint8_t Reserved7E; uint8_t Reserved7F; uint8_t Reserved80; uint8_t Reserved81; uint8_t Reserved82; uint8_t Reserved83; uint8_t Reserved84; uint8_t Reserved85; uint8_t Reserved86; uint8_t Reserved87; uint8_t Reserved88; uint8_t Reserved89; uint8_t Reserved8A; uint8_t Reserved8B; uint8_t Reserved8C; uint8_t Reserved8D; uint8_t Reserved8E; uint8_t Reserved8F; uint8_t Reserved90; uint8_t Reserved91; uint8_t Reserved92; uint8_t Reserved93; uint8_t Reserved94; uint8_t Reserved95; uint8_t Reserved96; uint8_t Reserved97; uint8_t Reserved98; uint8_t Reserved99; uint8_t Reserved9A; uint8_t Reserved9B; uint8_t Reserved9C; uint8_t Reserved9D; uint8_t Reserved9E; uint8_t Reserved9F; uint8_t ReservedA0; uint8_t ReservedA1; uint8_t ReservedA2; uint8_t ReservedA3; }; typedef ulong * uint64ptr_t; typedef long __off_t; typedef int int32_t; typedef uchar * uint8ptr_t; typedef short * int16ptr_t; typedef long * int64ptr_t; typedef int * int32ptr_t; typedef long int64_t; typedef char * int8ptr_t; typedef long __off64_t; typedef short int16_t; typedef ushort * uint16ptr_t; typedef uint * uint32ptr_t; typedef struct _PMU_SMB_DDR4U_2D_t _PMU_SMB_DDR4U_2D_t, *P_PMU_SMB_DDR4U_2D_t; typedef struct _PMU_SMB_DDR4U_2D_t PMU_SMB_DDR4U_2D_t; struct _PMU_SMB_DDR4U_2D_t { uint8_t Reserved00; uint8_t MsgMisc; uint16_t PmuRevision; uint8_t Pstate; uint8_t PllBypassEn; uint16_t DRAMFreq; uint8_t DfiFreqRatio; uint8_t BPZNResVal; uint8_t PhyOdtImpedance; uint8_t PhyDrvImpedance; uint8_t PhyVref; uint8_t DramType; uint8_t DisabledDbyte; uint8_t EnabledDQs; uint8_t CsPresent; uint8_t CsPresentD0; uint8_t CsPresentD1; uint8_t AddrMirror; uint8_t CsTestFail; uint8_t PhyCfg; uint16_t SequenceCtrl; uint8_t HdtCtrl; uint8_t RX2D_TrainOpt; uint8_t TX2D_TrainOpt; uint8_t Share2DVrefResult; uint8_t Delay_Weight2D; uint8_t Voltage_Weight2D; uint8_t Reserved1E; uint8_t Reserved1F; uint8_t Reserved20; uint8_t Reserved21; uint16_t PhyConfigOverride; uint8_t DFIMRLMargin; uint8_t R0_RxClkDly_Margin; uint8_t R0_VrefDac_Margin; uint8_t R0_TxDqDly_Margin; uint8_t R0_DeviceVref_Margin; uint8_t Reserved29; uint8_t Reserved2A; uint8_t Reserved2B; uint8_t Reserved2C; uint8_t Reserved2D; uint8_t Reserved2E; uint8_t Reserved2F; uint8_t Reserved30; uint8_t Reserved31; uint8_t Reserved32; uint8_t R1_RxClkDly_Margin; uint8_t R1_VrefDac_Margin; uint8_t R1_TxDqDly_Margin; uint8_t R1_DeviceVref_Margin; uint8_t Reserved37; uint8_t Reserved38; uint8_t Reserved39; uint8_t Reserved3A; uint8_t Reserved3B; uint8_t Reserved3C; uint8_t Reserved3D; uint8_t Reserved3E; uint8_t Reserved3F; uint8_t Reserved40; uint8_t R2_RxClkDly_Margin; uint8_t R2_VrefDac_Margin; uint8_t R2_TxDqDly_Margin; uint8_t R2_DeviceVref_Margin; uint8_t Reserved45; uint8_t Reserved46; uint8_t Reserved47; uint8_t Reserved48; uint8_t Reserved49; uint8_t Reserved4A; uint8_t Reserved4B; uint8_t Reserved4C; uint8_t Reserved4D; uint8_t Reserved4E; uint8_t R3_RxClkDly_Margin; uint8_t R3_VrefDac_Margin; uint8_t R3_TxDqDly_Margin; uint8_t R3_DeviceVref_Margin; uint8_t Reserved53; uint8_t Reserved54; uint8_t Reserved55; uint8_t Reserved56; uint8_t Reserved57; uint8_t Reserved58; uint8_t Reserved59; uint8_t Reserved5A; uint8_t Reserved5B; uint8_t Reserved5C; uint8_t Reserved5D; uint16_t MR0; uint16_t MR1; uint16_t MR2; uint16_t MR3; uint16_t MR4; uint16_t MR5; uint16_t MR6; uint8_t X16Present; uint8_t CsSetupGDDec; uint16_t RTT_NOM_WR_PARK0; uint16_t RTT_NOM_WR_PARK1; uint16_t RTT_NOM_WR_PARK2; uint16_t RTT_NOM_WR_PARK3; uint16_t RTT_NOM_WR_PARK4; uint16_t RTT_NOM_WR_PARK5; uint16_t RTT_NOM_WR_PARK6; uint16_t RTT_NOM_WR_PARK7; uint8_t AcsmOdtCtrl0; uint8_t AcsmOdtCtrl1; uint8_t AcsmOdtCtrl2; uint8_t AcsmOdtCtrl3; uint8_t AcsmOdtCtrl4; uint8_t AcsmOdtCtrl5; uint8_t AcsmOdtCtrl6; uint8_t AcsmOdtCtrl7; uint8_t VrefDqR0Nib0; uint8_t VrefDqR0Nib1; uint8_t VrefDqR0Nib2; uint8_t VrefDqR0Nib3; uint8_t VrefDqR0Nib4; uint8_t VrefDqR0Nib5; uint8_t VrefDqR0Nib6; uint8_t VrefDqR0Nib7; uint8_t VrefDqR0Nib8; uint8_t VrefDqR0Nib9; uint8_t VrefDqR0Nib10; uint8_t VrefDqR0Nib11; uint8_t VrefDqR0Nib12; uint8_t VrefDqR0Nib13; uint8_t VrefDqR0Nib14; uint8_t VrefDqR0Nib15; uint8_t VrefDqR0Nib16; uint8_t VrefDqR0Nib17; uint8_t VrefDqR0Nib18; uint8_t VrefDqR0Nib19; uint8_t VrefDqR1Nib0; uint8_t VrefDqR1Nib1; uint8_t VrefDqR1Nib2; uint8_t VrefDqR1Nib3; uint8_t VrefDqR1Nib4; uint8_t VrefDqR1Nib5; uint8_t VrefDqR1Nib6; uint8_t VrefDqR1Nib7; uint8_t VrefDqR1Nib8; uint8_t VrefDqR1Nib9; uint8_t VrefDqR1Nib10; uint8_t VrefDqR1Nib11; uint8_t VrefDqR1Nib12; uint8_t VrefDqR1Nib13; uint8_t VrefDqR1Nib14; uint8_t VrefDqR1Nib15; uint8_t VrefDqR1Nib16; uint8_t VrefDqR1Nib17; uint8_t VrefDqR1Nib18; uint8_t VrefDqR1Nib19; uint8_t VrefDqR2Nib0; uint8_t VrefDqR2Nib1; uint8_t VrefDqR2Nib2; uint8_t VrefDqR2Nib3; uint8_t VrefDqR2Nib4; uint8_t VrefDqR2Nib5; uint8_t VrefDqR2Nib6; uint8_t VrefDqR2Nib7; uint8_t VrefDqR2Nib8; uint8_t VrefDqR2Nib9; uint8_t VrefDqR2Nib10; uint8_t VrefDqR2Nib11; uint8_t VrefDqR2Nib12; uint8_t VrefDqR2Nib13; uint8_t VrefDqR2Nib14; uint8_t VrefDqR2Nib15; uint8_t VrefDqR2Nib16; uint8_t VrefDqR2Nib17; uint8_t VrefDqR2Nib18; uint8_t VrefDqR2Nib19; uint8_t VrefDqR3Nib0; uint8_t VrefDqR3Nib1; uint8_t VrefDqR3Nib2; uint8_t VrefDqR3Nib3; uint8_t VrefDqR3Nib4; uint8_t VrefDqR3Nib5; uint8_t VrefDqR3Nib6; uint8_t VrefDqR3Nib7; uint8_t VrefDqR3Nib8; uint8_t VrefDqR3Nib9; uint8_t VrefDqR3Nib10; uint8_t VrefDqR3Nib11; uint8_t VrefDqR3Nib12; uint8_t VrefDqR3Nib13; uint8_t VrefDqR3Nib14; uint8_t VrefDqR3Nib15; uint8_t VrefDqR3Nib16; uint8_t VrefDqR3Nib17; uint8_t VrefDqR3Nib18; uint8_t VrefDqR3Nib19; uint8_t ReservedD6; uint8_t ReservedD7; uint8_t ReservedD8; uint8_t ReservedD9; uint8_t ReservedDA; uint8_t ReservedDB; uint8_t ReservedDC; uint8_t ReservedDD; uint8_t ReservedDE; uint8_t ReservedDF; uint8_t ReservedE0; uint8_t ReservedE1; uint8_t ReservedE2; uint8_t ReservedE3; uint8_t ReservedE4; uint8_t ReservedE5; uint8_t ReservedE6; uint8_t ReservedE7; uint8_t ReservedE8; uint8_t ReservedE9; uint8_t ReservedEA; uint8_t ReservedEB; uint8_t ReservedEC; uint8_t ReservedED; uint8_t ReservedEE; uint8_t ReservedEF; uint8_t ReservedF0; uint8_t ReservedF1; uint8_t ReservedF2; uint8_t ReservedF3; uint8_t ReservedF4; uint8_t ReservedF5; uint8_t ReservedF6; uint8_t ReservedF7; uint8_t ReservedF8; uint8_t ReservedF9; uint8_t ReservedFA; uint8_t ReservedFB; uint8_t ReservedFC; uint8_t ReservedFD; uint8_t ReservedFE; uint8_t ReservedFF; uint8_t Reserved100; uint8_t Reserved101; uint8_t Reserved102; uint8_t Reserved103; uint8_t Reserved104; uint8_t Reserved105; uint8_t Reserved106; uint8_t Reserved107; uint8_t Reserved108; uint8_t Reserved109; uint8_t Reserved10A; uint8_t Reserved10B; uint8_t Reserved10C; uint8_t Reserved10D; uint8_t Reserved10E; uint8_t Reserved10F; uint8_t Reserved110; uint8_t Reserved111; uint8_t Reserved112; uint8_t Reserved113; uint8_t Reserved114; uint8_t Reserved115; uint8_t Reserved116; uint8_t Reserved117; uint8_t Reserved118; uint8_t Reserved119; uint8_t Reserved11A; uint8_t Reserved11B; uint8_t Reserved11C; uint8_t Reserved11D; uint8_t Reserved11E; uint8_t Reserved11F; uint8_t Reserved120; uint8_t Reserved121; uint8_t Reserved122; uint8_t Reserved123; uint8_t Reserved124; uint8_t Reserved125; uint8_t Reserved126; uint8_t Reserved127; uint8_t Reserved128; uint8_t Reserved129; uint8_t Reserved12A; uint8_t Reserved12B; uint8_t Reserved12C; uint8_t Reserved12D; uint8_t Reserved12E; uint8_t Reserved12F; uint8_t Reserved130; uint8_t Reserved131; uint8_t Reserved132; uint8_t Reserved133; uint8_t Reserved134; uint8_t Reserved135; uint8_t Reserved136; uint8_t Reserved137; uint8_t Reserved138; uint8_t Reserved139; uint8_t Reserved13A; uint8_t Reserved13B; uint8_t Reserved13C; uint8_t Reserved13D; uint8_t Reserved13E; uint8_t Reserved13F; uint8_t Reserved140; uint8_t Reserved141; uint8_t Reserved142; uint8_t Reserved143; uint8_t Reserved144; uint8_t Reserved145; uint8_t Reserved146; uint8_t Reserved147; uint8_t Reserved148; uint8_t Reserved149; uint8_t Reserved14A; uint8_t Reserved14B; uint8_t Reserved14C; uint8_t Reserved14D; uint8_t Reserved14E; uint8_t Reserved14F; uint8_t Reserved150; uint8_t Reserved151; uint8_t Reserved152; uint8_t Reserved153; uint8_t Reserved154; uint8_t Reserved155; uint8_t Reserved156; uint8_t Reserved157; uint8_t Reserved158; uint8_t Reserved159; uint8_t Reserved15A; uint8_t Reserved15B; uint8_t Reserved15C; uint8_t Reserved15D; uint8_t Reserved15E; uint8_t Reserved15F; uint8_t Reserved160; uint8_t Reserved161; uint8_t Reserved162; uint8_t Reserved163; uint8_t Reserved164; uint8_t Reserved165; uint8_t Reserved166; uint8_t Reserved167; uint8_t Reserved168; uint8_t Reserved169; uint8_t Reserved16A; uint8_t Reserved16B; uint8_t Reserved16C; uint8_t Reserved16D; uint8_t Reserved16E; uint8_t Reserved16F; uint8_t Reserved170; uint8_t Reserved171; uint8_t Reserved172; uint8_t Reserved173; uint8_t Reserved174; uint8_t Reserved175; uint8_t Reserved176; uint8_t Reserved177; uint8_t Reserved178; uint8_t Reserved179; uint8_t Reserved17A; uint8_t Reserved17B; uint8_t Reserved17C; uint8_t Reserved17D; uint8_t Reserved17E; uint8_t Reserved17F; uint8_t Reserved180; uint8_t Reserved181; uint8_t Reserved182; uint8_t Reserved183; uint8_t Reserved184; uint8_t Reserved185; uint8_t Reserved186; uint8_t Reserved187; uint8_t Reserved188; uint8_t Reserved189; uint8_t Reserved18A; uint8_t Reserved18B; uint8_t Reserved18C; uint8_t Reserved18D; uint8_t Reserved18E; uint8_t Reserved18F; uint8_t Reserved190; uint8_t Reserved191; uint8_t Reserved192; uint8_t Reserved193; uint8_t Reserved194; uint8_t Reserved195; uint8_t Reserved196; uint8_t Reserved197; uint8_t Reserved198; uint8_t Reserved199; uint8_t Reserved19A; uint8_t Reserved19B; uint8_t Reserved19C; uint8_t Reserved19D; uint8_t Reserved19E; uint8_t Reserved19F; uint8_t Reserved1A0; uint8_t Reserved1A1; uint8_t Reserved1A2; uint8_t Reserved1A3; uint8_t Reserved1A4; uint8_t Reserved1A5; uint8_t Reserved1A6; uint8_t Reserved1A7; uint8_t Reserved1A8; uint8_t Reserved1A9; uint8_t Reserved1AA; uint8_t Reserved1AB; uint8_t Reserved1AC; uint8_t Reserved1AD; uint8_t Reserved1AE; uint8_t Reserved1AF; uint8_t Reserved1B0; uint8_t Reserved1B1; uint8_t Reserved1B2; uint8_t Reserved1B3; uint8_t Reserved1B4; uint8_t Reserved1B5; uint8_t Reserved1B6; uint8_t Reserved1B7; uint8_t Reserved1B8; uint8_t Reserved1B9; uint8_t Reserved1BA; uint8_t Reserved1BB; uint8_t Reserved1BC; uint8_t Reserved1BD; uint8_t Reserved1BE; uint8_t Reserved1BF; uint8_t Reserved1C0; uint8_t Reserved1C1; uint8_t Reserved1C2; uint8_t Reserved1C3; uint8_t Reserved1C4; uint8_t Reserved1C5; uint8_t Reserved1C6; uint8_t Reserved1C7; uint8_t Reserved1C8; uint8_t Reserved1C9; uint8_t Reserved1CA; uint8_t Reserved1CB; uint8_t Reserved1CC; uint8_t Reserved1CD; uint8_t Reserved1CE; uint8_t Reserved1CF; uint8_t Reserved1D0; uint8_t Reserved1D1; uint8_t Reserved1D2; uint8_t Reserved1D3; uint8_t Reserved1D4; uint8_t Reserved1D5; uint8_t Reserved1D6; uint8_t Reserved1D7; uint8_t Reserved1D8; uint8_t Reserved1D9; uint8_t Reserved1DA; uint8_t Reserved1DB; uint8_t Reserved1DC; uint8_t Reserved1DD; uint8_t Reserved1DE; uint8_t Reserved1DF; uint8_t Reserved1E0; uint8_t Reserved1E1; uint8_t Reserved1E2; uint8_t Reserved1E3; uint8_t Reserved1E4; uint8_t Reserved1E5; uint8_t Reserved1E6; uint8_t Reserved1E7; uint8_t Reserved1E8; uint8_t Reserved1E9; uint8_t Reserved1EA; uint8_t Reserved1EB; uint8_t Reserved1EC; uint8_t Reserved1ED; uint8_t Reserved1EE; uint8_t Reserved1EF; uint8_t Reserved1F0; uint8_t Reserved1F1; uint8_t Reserved1F2; uint8_t Reserved1F3; uint8_t Reserved1F4; uint8_t Reserved1F5; uint8_t Reserved1F6; uint8_t Reserved1F7; uint8_t Reserved1F8; uint8_t Reserved1F9; uint8_t Reserved1FA; uint8_t Reserved1FB; uint8_t Reserved1FC; uint8_t Reserved1FD; uint8_t Reserved1FE; uint8_t Reserved1FF; uint8_t Reserved200; uint8_t Reserved201; uint8_t Reserved202; uint8_t Reserved203; uint8_t Reserved204; uint8_t Reserved205; uint8_t Reserved206; uint8_t Reserved207; uint8_t Reserved208; uint8_t Reserved209; uint8_t Reserved20A; uint8_t Reserved20B; uint8_t Reserved20C; uint8_t Reserved20D; uint8_t Reserved20E; uint8_t Reserved20F; uint8_t Reserved210; uint8_t Reserved211; uint8_t Reserved212; uint8_t Reserved213; uint8_t Reserved214; uint8_t Reserved215; uint8_t Reserved216; uint8_t Reserved217; uint8_t Reserved218; uint8_t Reserved219; uint8_t Reserved21A; uint8_t Reserved21B; uint8_t Reserved21C; uint8_t Reserved21D; uint8_t Reserved21E; uint8_t Reserved21F; uint8_t Reserved220; uint8_t Reserved221; uint8_t Reserved222; uint8_t Reserved223; uint8_t Reserved224; uint8_t Reserved225; uint8_t Reserved226; uint8_t Reserved227; uint8_t Reserved228; uint8_t Reserved229; uint8_t Reserved22A; uint8_t Reserved22B; uint8_t Reserved22C; uint8_t Reserved22D; uint8_t Reserved22E; uint8_t Reserved22F; uint8_t Reserved230; uint8_t Reserved231; uint8_t Reserved232; uint8_t Reserved233; uint8_t Reserved234; uint8_t Reserved235; uint8_t Reserved236; uint8_t Reserved237; uint8_t Reserved238; uint8_t Reserved239; uint8_t Reserved23A; uint8_t Reserved23B; uint8_t Reserved23C; uint8_t Reserved23D; uint8_t Reserved23E; uint8_t Reserved23F; uint8_t Reserved240; uint8_t Reserved241; uint8_t Reserved242; uint8_t Reserved243; uint8_t Reserved244; uint8_t Reserved245; uint8_t Reserved246; uint8_t Reserved247; uint8_t Reserved248; uint8_t Reserved249; uint8_t Reserved24A; uint8_t Reserved24B; uint8_t Reserved24C; uint8_t Reserved24D; uint8_t Reserved24E; uint8_t Reserved24F; uint8_t Reserved250; uint8_t Reserved251; uint8_t Reserved252; uint8_t Reserved253; uint8_t Reserved254; uint8_t Reserved255; uint8_t Reserved256; uint8_t Reserved257; uint8_t Reserved258; uint8_t Reserved259; uint8_t Reserved25A; uint8_t Reserved25B; uint8_t Reserved25C; uint8_t Reserved25D; uint8_t Reserved25E; uint8_t Reserved25F; uint8_t Reserved260; uint8_t Reserved261; uint8_t Reserved262; uint8_t Reserved263; uint8_t Reserved264; uint8_t Reserved265; uint8_t Reserved266; uint8_t Reserved267; uint8_t Reserved268; uint8_t Reserved269; uint8_t Reserved26A; uint8_t Reserved26B; uint8_t Reserved26C; uint8_t Reserved26D; uint8_t Reserved26E; uint8_t Reserved26F; uint8_t Reserved270; uint8_t Reserved271; uint8_t Reserved272; uint8_t Reserved273; uint8_t Reserved274; uint8_t Reserved275; uint8_t Reserved276; uint8_t Reserved277; uint8_t Reserved278; uint8_t Reserved279; uint8_t Reserved27A; uint8_t Reserved27B; uint8_t Reserved27C; uint8_t Reserved27D; uint8_t Reserved27E; uint8_t Reserved27F; uint8_t Reserved280; uint8_t Reserved281; uint8_t Reserved282; uint8_t Reserved283; uint8_t Reserved284; uint8_t Reserved285; uint8_t Reserved286; uint8_t Reserved287; uint8_t Reserved288; uint8_t Reserved289; uint8_t Reserved28A; uint8_t Reserved28B; uint8_t Reserved28C; uint8_t Reserved28D; uint8_t Reserved28E; uint8_t Reserved28F; uint8_t Reserved290; uint8_t Reserved291; uint8_t Reserved292; uint8_t Reserved293; uint8_t Reserved294; uint8_t Reserved295; uint8_t Reserved296; uint8_t Reserved297; uint8_t Reserved298; uint8_t Reserved299; uint8_t Reserved29A; uint8_t Reserved29B; uint8_t Reserved29C; uint8_t Reserved29D; uint8_t Reserved29E; uint8_t Reserved29F; uint8_t Reserved2A0; uint8_t Reserved2A1; uint8_t Reserved2A2; uint8_t Reserved2A3; uint8_t Reserved2A4; uint8_t Reserved2A5; uint8_t Reserved2A6; uint8_t Reserved2A7; uint8_t Reserved2A8; uint8_t Reserved2A9; uint8_t Reserved2AA; uint8_t Reserved2AB; uint8_t Reserved2AC; uint8_t Reserved2AD; uint8_t Reserved2AE; uint8_t Reserved2AF; uint8_t Reserved2B0; uint8_t Reserved2B1; uint8_t Reserved2B2; uint8_t Reserved2B3; uint8_t Reserved2B4; uint8_t Reserved2B5; uint8_t Reserved2B6; uint8_t Reserved2B7; uint8_t Reserved2B8; uint8_t Reserved2B9; uint8_t Reserved2BA; uint8_t Reserved2BB; uint8_t Reserved2BC; uint8_t Reserved2BD; uint8_t Reserved2BE; uint8_t Reserved2BF; uint8_t Reserved2C0; uint8_t Reserved2C1; uint8_t Reserved2C2; uint8_t Reserved2C3; uint8_t Reserved2C4; uint8_t Reserved2C5; uint8_t Reserved2C6; uint8_t Reserved2C7; uint8_t Reserved2C8; uint8_t Reserved2C9; uint8_t Reserved2CA; uint8_t Reserved2CB; uint8_t Reserved2CC; uint8_t Reserved2CD; uint8_t Reserved2CE; uint8_t Reserved2CF; uint8_t Reserved2D0; uint8_t Reserved2D1; uint8_t Reserved2D2; uint8_t Reserved2D3; uint8_t Reserved2D4; uint8_t Reserved2D5; uint8_t Reserved2D6; uint8_t Reserved2D7; uint8_t Reserved2D8; uint8_t Reserved2D9; uint8_t Reserved2DA; uint8_t Reserved2DB; uint8_t Reserved2DC; uint8_t Reserved2DD; uint8_t Reserved2DE; uint8_t Reserved2DF; uint8_t Reserved2E0; uint8_t Reserved2E1; uint8_t Reserved2E2; uint8_t Reserved2E3; uint8_t Reserved2E4; uint8_t Reserved2E5; uint8_t Reserved2E6; uint8_t Reserved2E7; uint8_t Reserved2E8; uint8_t Reserved2E9; uint8_t Reserved2EA; uint8_t Reserved2EB; uint8_t Reserved2EC; uint8_t Reserved2ED; uint8_t Reserved2EE; uint8_t Reserved2EF; uint8_t Reserved2F0; uint8_t Reserved2F1; uint8_t Reserved2F2; uint8_t Reserved2F3; uint8_t Reserved2F4; uint8_t Reserved2F5; uint8_t Reserved2F6; uint8_t Reserved2F7; uint8_t Reserved2F8; uint8_t Reserved2F9; uint8_t Reserved2FA; uint8_t Reserved2FB; uint8_t Reserved2FC; uint8_t Reserved2FD; uint8_t Reserved2FE; uint8_t Reserved2FF; uint8_t Reserved300; uint8_t Reserved301; uint8_t Reserved302; uint8_t Reserved303; uint8_t Reserved304; uint8_t Reserved305; uint8_t Reserved306; uint8_t Reserved307; uint8_t Reserved308; uint8_t Reserved309; uint8_t Reserved30A; uint8_t Reserved30B; uint8_t Reserved30C; uint8_t Reserved30D; uint8_t Reserved30E; uint8_t Reserved30F; uint8_t Reserved310; uint8_t Reserved311; uint8_t Reserved312; uint8_t Reserved313; uint8_t Reserved314; uint8_t Reserved315; uint8_t Reserved316; uint8_t Reserved317; uint8_t Reserved318; uint8_t Reserved319; uint8_t Reserved31A; uint8_t Reserved31B; uint8_t Reserved31C; uint8_t Reserved31D; uint8_t Reserved31E; uint8_t Reserved31F; uint8_t Reserved320; uint8_t Reserved321; uint8_t Reserved322; uint8_t Reserved323; uint8_t Reserved324; uint8_t Reserved325; uint8_t Reserved326; uint8_t Reserved327; uint8_t Reserved328; uint8_t Reserved329; uint8_t Reserved32A; uint8_t Reserved32B; uint8_t Reserved32C; uint8_t Reserved32D; uint8_t Reserved32E; uint8_t Reserved32F; uint8_t Reserved330; uint8_t Reserved331; uint8_t Reserved332; uint8_t Reserved333; uint8_t Reserved334; uint8_t Reserved335; uint8_t Reserved336; uint8_t Reserved337; uint8_t Reserved338; uint8_t Reserved339; uint8_t Reserved33A; uint8_t Reserved33B; uint8_t Reserved33C; uint8_t Reserved33D; uint8_t Reserved33E; uint8_t Reserved33F; uint8_t Reserved340; uint8_t Reserved341; uint8_t Reserved342; uint8_t Reserved343; uint8_t Reserved344; uint8_t Reserved345; uint8_t Reserved346; uint8_t Reserved347; uint8_t Reserved348; uint8_t Reserved349; uint8_t Reserved34A; uint8_t Reserved34B; uint8_t Reserved34C; uint8_t Reserved34D; uint8_t Reserved34E; uint8_t Reserved34F; uint8_t Reserved350; uint8_t Reserved351; uint8_t Reserved352; uint8_t Reserved353; uint8_t Reserved354; uint8_t Reserved355; uint8_t Reserved356; uint8_t Reserved357; uint8_t Reserved358; uint8_t Reserved359; uint8_t Reserved35A; uint8_t Reserved35B; uint8_t Reserved35C; uint8_t Reserved35D; uint8_t Reserved35E; uint8_t Reserved35F; uint8_t Reserved360; uint8_t Reserved361; uint8_t Reserved362; uint8_t Reserved363; uint8_t Reserved364; uint8_t Reserved365; uint8_t Reserved366; uint8_t Reserved367; uint8_t Reserved368; uint8_t Reserved369; uint8_t Reserved36A; uint8_t Reserved36B; uint8_t Reserved36C; uint8_t Reserved36D; uint8_t Reserved36E; uint8_t Reserved36F; uint8_t Reserved370; uint8_t Reserved371; uint8_t Reserved372; uint8_t Reserved373; uint8_t Reserved374; uint8_t Reserved375; uint8_t Reserved376; uint8_t Reserved377; uint8_t Reserved378; uint8_t Reserved379; uint8_t Reserved37A; uint8_t Reserved37B; uint8_t Reserved37C; uint8_t Reserved37D; uint8_t Reserved37E; uint8_t Reserved37F; uint8_t Reserved380; uint8_t Reserved381; uint8_t Reserved382; uint8_t Reserved383; uint8_t Reserved384; uint8_t Reserved385; uint8_t Reserved386; uint8_t Reserved387; uint8_t Reserved388; uint8_t Reserved389; uint8_t Reserved38A; uint8_t Reserved38B; uint8_t Reserved38C; uint8_t Reserved38D; uint8_t Reserved38E; uint8_t Reserved38F; uint8_t Reserved390; uint8_t Reserved391; uint8_t Reserved392; uint8_t Reserved393; uint8_t Reserved394; uint8_t Reserved395; uint8_t Reserved396; uint8_t Reserved397; uint8_t Reserved398; uint8_t Reserved399; uint8_t Reserved39A; uint8_t Reserved39B; uint8_t Reserved39C; uint8_t Reserved39D; uint8_t Reserved39E; uint8_t Reserved39F; uint8_t Reserved3A0; uint8_t Reserved3A1; uint8_t Reserved3A2; uint8_t Reserved3A3; uint8_t Reserved3A4; uint8_t Reserved3A5; uint8_t Reserved3A6; uint8_t Reserved3A7; uint8_t Reserved3A8; uint8_t Reserved3A9; uint8_t Reserved3AA; uint8_t Reserved3AB; uint8_t Reserved3AC; uint8_t Reserved3AD; uint8_t Reserved3AE; uint8_t Reserved3AF; uint8_t Reserved3B0; uint8_t Reserved3B1; uint8_t Reserved3B2; uint8_t Reserved3B3; uint8_t Reserved3B4; uint8_t Reserved3B5; uint8_t Reserved3B6; uint8_t Reserved3B7; uint8_t Reserved3B8; uint8_t Reserved3B9; uint8_t Reserved3BA; uint8_t Reserved3BB; uint8_t Reserved3BC; uint8_t Reserved3BD; uint8_t Reserved3BE; uint8_t Reserved3BF; uint8_t Reserved3C0; uint8_t Reserved3C1; uint8_t Reserved3C2; uint8_t Reserved3C3; uint8_t Reserved3C4; uint8_t Reserved3C5; uint8_t Reserved3C6; uint8_t Reserved3C7; uint8_t Reserved3C8; uint8_t Reserved3C9; uint8_t Reserved3CA; uint8_t Reserved3CB; uint8_t Reserved3CC; uint8_t Reserved3CD; uint8_t Reserved3CE; uint8_t Reserved3CF; uint8_t Reserved3D0; uint8_t Reserved3D1; uint8_t Reserved3D2; uint8_t Reserved3D3; uint8_t Reserved3D4; uint8_t Reserved3D5; uint8_t Reserved3D6; uint8_t Reserved3D7; uint8_t Reserved3D8; uint8_t Reserved3D9; uint8_t Reserved3DA; uint8_t Reserved3DB; uint8_t Reserved3DC; uint8_t Reserved3DD; uint8_t Reserved3DE; uint8_t Reserved3DF; uint8_t Reserved3E0; uint8_t Reserved3E1; uint8_t Reserved3E2; uint8_t Reserved3E3; uint8_t Reserved3E4; uint8_t Reserved3E5; uint8_t Reserved3E6; uint8_t Reserved3E7; uint8_t Reserved3E8; uint8_t Reserved3E9; uint8_t Reserved3EA; uint8_t Reserved3EB; uint8_t Reserved3EC; uint8_t Reserved3ED; uint8_t Reserved3EE; uint8_t Reserved3EF; uint8_t Reserved3F0; uint8_t Reserved3F1; uint8_t Reserved3F2; uint8_t Reserved3F3; uint8_t Reserved3F4; uint8_t Reserved3F5; uint16_t ALT_CAS_L; uint8_t ALT_WCAS_L; uint8_t D4Misc; }; #define GPIOC_7 48 #define GPIOC_6 47 #define GPIOC_5 46 #define GPIOC_4 45 #define GPIOC_3 44 #define GPIOC_2 43 #define GPIOC_1 42 #define GPIOC_0 41 #define GPIOAO_11 11 #define GPIOAO_10 10 #define GPIOZ_7 7 #define GPIOZ_6 6 #define GPIOZ_5 5 #define GPIOZ_4 4 #define GPIOZ_3 3 #define GPIOZ_2 2 #define GPIOZ_1 1 #define GPIOZ_0 0 #define BOOT_9 34 #define GPIOA_13 62 #define GPIOA_12 61 #define GPIOA_11 60 #define GPIOA_10 59 #define GPIOZ_9 9 #define GPIOA_15 64 #define GPIOZ_8 8 #define GPIOA_14 63 #define GPIOA_0 49 #define BOOT_0 25 #define BOOT_1 26 #define BOOT_2 27 #define BOOT_3 28 #define BOOT_4 29 #define BOOT_5 30 #define BOOT_6 31 #define BOOT_7 32 #define BOOT_8 33 #define GPIOE_2 14 #define GPIOE_1 13 #define GPIOE_0 12 #define GPIOX_18 83 #define GPIOX_17 82 #define GPIOX_19 84 #define BOOT_12 37 #define BOOT_13 38 #define BOOT_10 35 #define BOOT_11 36 #define BOOT_14 39 #define BOOT_15 40 #define GPIOX_14 79 #define GPIOX_13 78 #define GPIOX_16 81 #define GPIOX_15 80 #define GPIOX_10 75 #define GPIOX_12 77 #define GPIOX_11 76 #define GPIOZ_10 10 #define GPIOZ_15 15 #define GPIOZ_13 13 #define GPIOZ_14 14 #define GPIOZ_11 11 #define GPIOZ_12 12 #define EE_OFFSET 15 #define GPIOA_9 58 #define GPIOA_8 57 #define GPIOA_7 56 #define GPIOA_6 55 #define GPIOA_5 54 #define GPIOA_4 53 #define GPIOA_3 52 #define GPIOA_2 51 #define GPIOA_1 50 #define GPIOH_8 24 #define GPIOH_7 23 #define GPIOH_6 22 #define GPIOH_5 21 #define GPIOH_4 20 #define GPIOH_3 19 #define GPIOH_2 18 #define GPIOH_1 17 #define GPIOH_0 16 #define GPIOX_9 74 #define GPIOX_8 73 #define GPIOX_7 72 #define GPIOX_6 71 #define GPIOX_5 70 #define GPIOX_4 69 #define GPIOX_3 68 #define GPIOX_2 67 #define GPIOX_1 66 #define GPIOX_0 65 #define GPIOAO_8 8 #define GPIOAO_9 9 #define GPIOAO_6 6 #define GPIOAO_7 7 #define GPIOAO_0 0 #define GPIOAO_1 1 #define GPIOAO_4 4 #define GPIOAO_5 5 #define GPIOAO_2 2 #define GPIOAO_3 3 #define CLK81 7 typedef struct astruct astruct, *Pastruct; struct astruct { undefined field0_0x0; undefined field1_0x1; undefined field2_0x2; undefined field3_0x3; undefined field4_0x4; undefined field5_0x5; undefined field6_0x6; undefined field7_0x7; undefined field8_0x8; undefined field9_0x9; undefined field10_0xa; undefined field11_0xb; undefined field12_0xc; undefined field13_0xd; undefined field14_0xe; undefined field15_0xf; undefined field16_0x10; undefined field17_0x11; undefined field18_0x12; undefined field19_0x13; undefined field20_0x14; undefined field21_0x15; undefined field22_0x16; undefined field23_0x17; undefined field24_0x18; undefined field25_0x19; undefined field26_0x1a; undefined field27_0x1b; undefined field28_0x1c; undefined field29_0x1d; undefined field30_0x1e; undefined field31_0x1f; undefined field32_0x20; undefined field33_0x21; undefined field34_0x22; undefined field35_0x23; undefined field36_0x24; undefined field37_0x25; undefined field38_0x26; undefined field39_0x27; undefined field40_0x28; undefined field41_0x29; undefined field42_0x2a; undefined field43_0x2b; undefined field44_0x2c; undefined field45_0x2d; undefined field46_0x2e; undefined field47_0x2f; undefined field48_0x30; undefined field49_0x31; undefined field50_0x32; undefined field51_0x33; undefined field52_0x34; undefined field53_0x35; undefined field54_0x36; undefined field55_0x37; undefined field56_0x38; undefined field57_0x39; undefined field58_0x3a; undefined field59_0x3b; undefined field60_0x3c; undefined field61_0x3d; undefined field62_0x3e; undefined field63_0x3f; undefined field64_0x40; undefined field65_0x41; undefined field66_0x42; undefined field67_0x43; undefined field68_0x44; undefined field69_0x45; undefined field70_0x46; undefined field71_0x47; undefined field72_0x48; undefined field73_0x49; undefined field74_0x4a; undefined field75_0x4b; undefined field76_0x4c; undefined field77_0x4d; undefined field78_0x4e; undefined field79_0x4f; undefined field80_0x50; undefined field81_0x51; undefined field82_0x52; undefined field83_0x53; undefined field84_0x54; undefined field85_0x55; undefined field86_0x56; undefined field87_0x57; undefined field88_0x58; undefined field89_0x59; undefined field90_0x5a; undefined field91_0x5b; undefined field92_0x5c; undefined field93_0x5d; undefined field94_0x5e; undefined field95_0x5f; undefined field96_0x60; undefined field97_0x61; undefined field98_0x62; undefined field99_0x63; undefined field100_0x64; undefined field101_0x65; undefined field102_0x66; undefined field103_0x67; undefined field104_0x68; undefined field105_0x69; undefined field106_0x6a; undefined field107_0x6b; undefined field108_0x6c; undefined field109_0x6d; undefined field110_0x6e; undefined field111_0x6f; undefined field112_0x70; undefined field113_0x71; undefined field114_0x72; undefined field115_0x73; undefined field116_0x74; undefined field117_0x75; undefined field118_0x76; undefined field119_0x77; undefined field120_0x78; undefined field121_0x79; undefined field122_0x7a; undefined field123_0x7b; undefined field124_0x7c; undefined field125_0x7d; undefined field126_0x7e; undefined field127_0x7f; undefined field128_0x80; undefined field129_0x81; undefined field130_0x82; undefined field131_0x83; undefined field132_0x84; undefined field133_0x85; undefined field134_0x86; undefined field135_0x87; undefined field136_0x88; undefined field137_0x89; undefined field138_0x8a; undefined field139_0x8b; undefined field140_0x8c; undefined field141_0x8d; undefined field142_0x8e; undefined field143_0x8f; undefined field144_0x90; undefined field145_0x91; undefined field146_0x92; undefined field147_0x93; undefined field148_0x94; undefined field149_0x95; undefined field150_0x96; undefined field151_0x97; undefined field152_0x98; undefined field153_0x99; undefined field154_0x9a; undefined field155_0x9b; undefined field156_0x9c; undefined field157_0x9d; undefined field158_0x9e; undefined field159_0x9f; undefined field160_0xa0; undefined field161_0xa1; undefined field162_0xa2; undefined field163_0xa3; undefined field164_0xa4; undefined field165_0xa5; undefined field166_0xa6; undefined field167_0xa7; undefined * field168_0xa8; undefined8 field169_0xb0; long field170_0xb8; undefined field171_0xc0; undefined field172_0xc1; undefined field173_0xc2; undefined field174_0xc3; undefined field175_0xc4; undefined field176_0xc5; undefined field177_0xc6; undefined field178_0xc7; undefined field179_0xc8; undefined field180_0xc9; undefined field181_0xca; undefined field182_0xcb; undefined field183_0xcc; undefined field184_0xcd; undefined field185_0xce; undefined field186_0xcf; undefined field187_0xd0; undefined field188_0xd1; undefined field189_0xd2; undefined field190_0xd3; undefined field191_0xd4; undefined field192_0xd5; undefined field193_0xd6; undefined field194_0xd7; undefined field195_0xd8; undefined field196_0xd9; undefined field197_0xda; undefined field198_0xdb; undefined field199_0xdc; undefined field200_0xdd; undefined field201_0xde; undefined field202_0xdf; undefined field203_0xe0; undefined field204_0xe1; undefined field205_0xe2; undefined field206_0xe3; undefined2 field207_0xe4; char field208_0xe6; undefined field209_0xe7; undefined field210_0xe8; undefined field211_0xe9; undefined field212_0xea; undefined field213_0xeb; undefined field214_0xec; undefined field215_0xed; undefined field216_0xee; undefined field217_0xef; undefined field218_0xf0; undefined field219_0xf1; undefined field220_0xf2; undefined field221_0xf3; undefined field222_0xf4; undefined field223_0xf5; undefined field224_0xf6; undefined field225_0xf7; undefined field226_0xf8; undefined field227_0xf9; undefined field228_0xfa; undefined field229_0xfb; undefined field230_0xfc; undefined field231_0xfd; undefined field232_0xfe; undefined field233_0xff; undefined field234_0x100; undefined field235_0x101; undefined field236_0x102; undefined field237_0x103; undefined field238_0x104; undefined field239_0x105; undefined field240_0x106; undefined field241_0x107; undefined field242_0x108; undefined field243_0x109; undefined field244_0x10a; undefined field245_0x10b; undefined field246_0x10c; undefined field247_0x10d; undefined field248_0x10e; undefined field249_0x10f; undefined field250_0x110; undefined field251_0x111; undefined field252_0x112; undefined field253_0x113; undefined field254_0x114; undefined field255_0x115; undefined field256_0x116; undefined field257_0x117; undefined field258_0x118; undefined field259_0x119; undefined field260_0x11a; undefined field261_0x11b; undefined field262_0x11c; undefined field263_0x11d; undefined field264_0x11e; undefined field265_0x11f; undefined field266_0x120; undefined field267_0x121; undefined field268_0x122; undefined field269_0x123; undefined field270_0x124; undefined field271_0x125; undefined field272_0x126; undefined field273_0x127; undefined field274_0x128; undefined field275_0x129; undefined field276_0x12a; undefined field277_0x12b; undefined field278_0x12c; undefined field279_0x12d; undefined field280_0x12e; undefined field281_0x12f; undefined field282_0x130; undefined field283_0x131; undefined field284_0x132; undefined field285_0x133; undefined field286_0x134; undefined field287_0x135; undefined field288_0x136; undefined field289_0x137; undefined field290_0x138; undefined field291_0x139; undefined field292_0x13a; undefined field293_0x13b; undefined field294_0x13c; undefined field295_0x13d; undefined field296_0x13e; undefined field297_0x13f; undefined field298_0x140; undefined field299_0x141; undefined field300_0x142; undefined field301_0x143; undefined field302_0x144; undefined field303_0x145; undefined field304_0x146; undefined field305_0x147; undefined field306_0x148; undefined field307_0x149; undefined field308_0x14a; undefined field309_0x14b; undefined field310_0x14c; undefined field311_0x14d; undefined field312_0x14e; undefined field313_0x14f; undefined field314_0x150; undefined field315_0x151; undefined field316_0x152; undefined field317_0x153; undefined field318_0x154; undefined field319_0x155; undefined field320_0x156; undefined field321_0x157; undefined field322_0x158; undefined field323_0x159; undefined field324_0x15a; undefined field325_0x15b; undefined field326_0x15c; undefined field327_0x15d; undefined field328_0x15e; undefined field329_0x15f; undefined field330_0x160; undefined field331_0x161; undefined field332_0x162; undefined field333_0x163; undefined field334_0x164; undefined field335_0x165; undefined field336_0x166; undefined field337_0x167; undefined field338_0x168; undefined field339_0x169; undefined field340_0x16a; undefined field341_0x16b; undefined field342_0x16c; undefined field343_0x16d; undefined field344_0x16e; undefined field345_0x16f; undefined field346_0x170; undefined field347_0x171; undefined field348_0x172; undefined field349_0x173; undefined field350_0x174; undefined field351_0x175; undefined field352_0x176; undefined field353_0x177; undefined field354_0x178; undefined field355_0x179; undefined field356_0x17a; undefined field357_0x17b; undefined field358_0x17c; undefined field359_0x17d; undefined field360_0x17e; undefined field361_0x17f; undefined field362_0x180; undefined field363_0x181; undefined field364_0x182; undefined field365_0x183; undefined field366_0x184; undefined field367_0x185; undefined field368_0x186; undefined field369_0x187; undefined field370_0x188; undefined field371_0x189; undefined field372_0x18a; undefined field373_0x18b; undefined field374_0x18c; undefined field375_0x18d; undefined field376_0x18e; undefined field377_0x18f; undefined field378_0x190; undefined field379_0x191; undefined field380_0x192; undefined field381_0x193; undefined field382_0x194; undefined field383_0x195; undefined field384_0x196; undefined field385_0x197; undefined field386_0x198; undefined field387_0x199; undefined field388_0x19a; undefined field389_0x19b; undefined field390_0x19c; undefined field391_0x19d; undefined field392_0x19e; undefined field393_0x19f; undefined field394_0x1a0; undefined field395_0x1a1; undefined field396_0x1a2; undefined field397_0x1a3; undefined field398_0x1a4; undefined field399_0x1a5; undefined field400_0x1a6; undefined field401_0x1a7; undefined field402_0x1a8; undefined field403_0x1a9; undefined field404_0x1aa; undefined field405_0x1ab; undefined field406_0x1ac; undefined field407_0x1ad; undefined field408_0x1ae; undefined field409_0x1af; undefined field410_0x1b0; undefined field411_0x1b1; undefined field412_0x1b2; undefined field413_0x1b3; undefined field414_0x1b4; undefined field415_0x1b5; undefined field416_0x1b6; undefined field417_0x1b7; undefined field418_0x1b8; undefined field419_0x1b9; undefined field420_0x1ba; undefined field421_0x1bb; undefined field422_0x1bc; undefined field423_0x1bd; undefined field424_0x1be; undefined field425_0x1bf; undefined field426_0x1c0; undefined field427_0x1c1; undefined field428_0x1c2; undefined field429_0x1c3; undefined field430_0x1c4; undefined field431_0x1c5; undefined field432_0x1c6; undefined field433_0x1c7; undefined field434_0x1c8; undefined field435_0x1c9; undefined field436_0x1ca; undefined field437_0x1cb; undefined field438_0x1cc; undefined field439_0x1cd; undefined field440_0x1ce; undefined field441_0x1cf; undefined field442_0x1d0; undefined field443_0x1d1; undefined field444_0x1d2; undefined field445_0x1d3; undefined field446_0x1d4; undefined field447_0x1d5; undefined field448_0x1d6; undefined field449_0x1d7; undefined field450_0x1d8; undefined field451_0x1d9; undefined field452_0x1da; undefined field453_0x1db; undefined field454_0x1dc; undefined field455_0x1dd; undefined field456_0x1de; undefined field457_0x1df; undefined field458_0x1e0; undefined field459_0x1e1; undefined field460_0x1e2; undefined field461_0x1e3; undefined field462_0x1e4; undefined field463_0x1e5; undefined field464_0x1e6; undefined field465_0x1e7; undefined field466_0x1e8; undefined field467_0x1e9; undefined field468_0x1ea; undefined field469_0x1eb; undefined field470_0x1ec; undefined field471_0x1ed; undefined field472_0x1ee; undefined field473_0x1ef; undefined field474_0x1f0; undefined field475_0x1f1; undefined field476_0x1f2; undefined field477_0x1f3; undefined field478_0x1f4; undefined field479_0x1f5; undefined field480_0x1f6; undefined field481_0x1f7; undefined field482_0x1f8; undefined field483_0x1f9; undefined field484_0x1fa; undefined field485_0x1fb; undefined field486_0x1fc; undefined field487_0x1fd; undefined field488_0x1fe; undefined field489_0x1ff; undefined field490_0x200; undefined field491_0x201; undefined field492_0x202; undefined field493_0x203; undefined field494_0x204; undefined field495_0x205; undefined field496_0x206; undefined field497_0x207; undefined field498_0x208; undefined field499_0x209; undefined field500_0x20a; undefined field501_0x20b; undefined field502_0x20c; undefined field503_0x20d; undefined field504_0x20e; undefined field505_0x20f; undefined field506_0x210; undefined field507_0x211; undefined field508_0x212; undefined field509_0x213; undefined field510_0x214; undefined field511_0x215; undefined field512_0x216; undefined field513_0x217; undefined field514_0x218; undefined field515_0x219; undefined field516_0x21a; undefined field517_0x21b; undefined field518_0x21c; undefined field519_0x21d; undefined field520_0x21e; undefined field521_0x21f; undefined field522_0x220; undefined field523_0x221; undefined field524_0x222; undefined field525_0x223; undefined field526_0x224; undefined field527_0x225; undefined field528_0x226; undefined field529_0x227; undefined field530_0x228; undefined field531_0x229; undefined field532_0x22a; undefined field533_0x22b; undefined field534_0x22c; undefined field535_0x22d; undefined field536_0x22e; undefined field537_0x22f; undefined field538_0x230; undefined field539_0x231; undefined field540_0x232; undefined field541_0x233; undefined field542_0x234; undefined field543_0x235; undefined field544_0x236; undefined field545_0x237; undefined field546_0x238; undefined field547_0x239; undefined field548_0x23a; undefined field549_0x23b; undefined field550_0x23c; undefined field551_0x23d; undefined field552_0x23e; undefined field553_0x23f; undefined field554_0x240; undefined field555_0x241; undefined field556_0x242; undefined field557_0x243; undefined field558_0x244; undefined field559_0x245; undefined field560_0x246; undefined field561_0x247; undefined field562_0x248; undefined field563_0x249; undefined field564_0x24a; undefined field565_0x24b; undefined field566_0x24c; undefined field567_0x24d; undefined field568_0x24e; undefined field569_0x24f; undefined field570_0x250; undefined field571_0x251; undefined field572_0x252; undefined field573_0x253; undefined field574_0x254; undefined field575_0x255; undefined field576_0x256; undefined field577_0x257; undefined field578_0x258; undefined field579_0x259; undefined field580_0x25a; undefined field581_0x25b; undefined field582_0x25c; undefined field583_0x25d; undefined field584_0x25e; undefined field585_0x25f; undefined field586_0x260; undefined field587_0x261; undefined field588_0x262; undefined field589_0x263; undefined field590_0x264; undefined field591_0x265; undefined field592_0x266; undefined field593_0x267; undefined4 field594_0x268; }; typedef struct astruct_3 astruct_3, *Pastruct_3; struct astruct_3 { undefined8 field0_0x0; undefined field1_0x8; undefined field2_0x9; undefined field3_0xa; undefined field4_0xb; undefined field5_0xc; undefined field6_0xd; undefined field7_0xe; undefined field8_0xf; undefined field9_0x10; undefined field10_0x11; undefined field11_0x12; undefined field12_0x13; undefined field13_0x14; undefined field14_0x15; undefined field15_0x16; undefined field16_0x17; undefined8 field17_0x18; undefined field18_0x20; undefined field19_0x21; undefined field20_0x22; undefined field21_0x23; undefined field22_0x24; undefined field23_0x25; undefined field24_0x26; undefined field25_0x27; undefined8 field26_0x28; undefined8 field27_0x30; undefined * field28_0x38; undefined field29_0x40; undefined field30_0x41; undefined field31_0x42; undefined field32_0x43; undefined field33_0x44; undefined field34_0x45; undefined field35_0x46; undefined field36_0x47; undefined field37_0x48; undefined field38_0x49; undefined field39_0x4a; undefined field40_0x4b; undefined field41_0x4c; undefined field42_0x4d; undefined field43_0x4e; undefined field44_0x4f; undefined field45_0x50; undefined field46_0x51; undefined field47_0x52; undefined field48_0x53; undefined field49_0x54; undefined field50_0x55; undefined field51_0x56; undefined field52_0x57; undefined field53_0x58; undefined field54_0x59; undefined field55_0x5a; undefined field56_0x5b; undefined field57_0x5c; undefined field58_0x5d; undefined field59_0x5e; undefined field60_0x5f; undefined field61_0x60; undefined field62_0x61; undefined field63_0x62; undefined field64_0x63; undefined field65_0x64; undefined field66_0x65; undefined field67_0x66; undefined field68_0x67; undefined field69_0x68; undefined field70_0x69; undefined field71_0x6a; undefined field72_0x6b; undefined field73_0x6c; undefined field74_0x6d; undefined field75_0x6e; undefined field76_0x6f; undefined field77_0x70; undefined field78_0x71; undefined field79_0x72; undefined field80_0x73; undefined field81_0x74; undefined field82_0x75; undefined field83_0x76; undefined field84_0x77; undefined8 field85_0x78; undefined8 field86_0x80; undefined8 field87_0x88; undefined8 field88_0x90; undefined8 field89_0x98; undefined8 field90_0xa0; undefined field91_0xa8; undefined field92_0xa9; undefined field93_0xaa; undefined field94_0xab; undefined field95_0xac; undefined field96_0xad; undefined field97_0xae; undefined field98_0xaf; undefined field99_0xb0; undefined field100_0xb1; undefined field101_0xb2; undefined field102_0xb3; undefined field103_0xb4; undefined field104_0xb5; undefined field105_0xb6; undefined field106_0xb7; undefined field107_0xb8; undefined field108_0xb9; undefined field109_0xba; undefined field110_0xbb; undefined field111_0xbc; undefined field112_0xbd; undefined field113_0xbe; undefined field114_0xbf; undefined field115_0xc0; undefined field116_0xc1; undefined field117_0xc2; undefined field118_0xc3; undefined field119_0xc4; undefined field120_0xc5; undefined field121_0xc6; undefined field122_0xc7; undefined field123_0xc8; undefined field124_0xc9; undefined field125_0xca; undefined field126_0xcb; undefined field127_0xcc; undefined field128_0xcd; undefined field129_0xce; undefined field130_0xcf; undefined field131_0xd0; undefined field132_0xd1; undefined field133_0xd2; undefined field134_0xd3; undefined field135_0xd4; undefined field136_0xd5; undefined field137_0xd6; undefined field138_0xd7; undefined field139_0xd8; undefined field140_0xd9; undefined field141_0xda; undefined field142_0xdb; undefined field143_0xdc; undefined field144_0xdd; undefined field145_0xde; undefined field146_0xdf; undefined field147_0xe0; undefined field148_0xe1; undefined field149_0xe2; undefined field150_0xe3; undefined field151_0xe4; undefined field152_0xe5; undefined field153_0xe6; undefined field154_0xe7; undefined field155_0xe8; undefined field156_0xe9; undefined field157_0xea; undefined field158_0xeb; undefined field159_0xec; undefined field160_0xed; undefined field161_0xee; undefined field162_0xef; undefined field163_0xf0; undefined field164_0xf1; undefined field165_0xf2; undefined field166_0xf3; undefined field167_0xf4; undefined field168_0xf5; undefined field169_0xf6; undefined field170_0xf7; undefined field171_0xf8; undefined field172_0xf9; undefined field173_0xfa; undefined field174_0xfb; undefined field175_0xfc; undefined field176_0xfd; undefined field177_0xfe; undefined field178_0xff; undefined field179_0x100; undefined field180_0x101; undefined field181_0x102; undefined field182_0x103; undefined field183_0x104; undefined field184_0x105; undefined field185_0x106; undefined field186_0x107; undefined field187_0x108; undefined field188_0x109; undefined field189_0x10a; undefined field190_0x10b; undefined field191_0x10c; undefined field192_0x10d; undefined field193_0x10e; undefined field194_0x10f; undefined field195_0x110; undefined field196_0x111; undefined field197_0x112; undefined field198_0x113; undefined field199_0x114; undefined field200_0x115; undefined field201_0x116; undefined field202_0x117; undefined field203_0x118; undefined field204_0x119; undefined field205_0x11a; undefined field206_0x11b; undefined field207_0x11c; undefined field208_0x11d; undefined field209_0x11e; undefined field210_0x11f; undefined field211_0x120; undefined field212_0x121; undefined field213_0x122; undefined field214_0x123; undefined field215_0x124; undefined field216_0x125; undefined field217_0x126; undefined field218_0x127; undefined field219_0x128; undefined field220_0x129; undefined field221_0x12a; undefined field222_0x12b; undefined field223_0x12c; undefined field224_0x12d; undefined field225_0x12e; undefined field226_0x12f; undefined field227_0x130; undefined field228_0x131; undefined field229_0x132; undefined field230_0x133; undefined field231_0x134; undefined field232_0x135; undefined field233_0x136; undefined field234_0x137; undefined field235_0x138; undefined field236_0x139; undefined field237_0x13a; undefined field238_0x13b; undefined field239_0x13c; undefined field240_0x13d; undefined field241_0x13e; undefined field242_0x13f; undefined field243_0x140; undefined field244_0x141; undefined field245_0x142; undefined field246_0x143; undefined field247_0x144; undefined field248_0x145; undefined field249_0x146; undefined field250_0x147; undefined field251_0x148; undefined field252_0x149; undefined field253_0x14a; undefined field254_0x14b; undefined field255_0x14c; undefined field256_0x14d; undefined field257_0x14e; undefined field258_0x14f; undefined field259_0x150; undefined field260_0x151; undefined field261_0x152; undefined field262_0x153; undefined field263_0x154; undefined field264_0x155; undefined field265_0x156; undefined field266_0x157; undefined field267_0x158; undefined field268_0x159; undefined field269_0x15a; undefined field270_0x15b; undefined field271_0x15c; undefined field272_0x15d; undefined field273_0x15e; undefined field274_0x15f; undefined field275_0x160; undefined field276_0x161; undefined field277_0x162; undefined field278_0x163; undefined field279_0x164; undefined field280_0x165; undefined field281_0x166; undefined field282_0x167; undefined field283_0x168; undefined field284_0x169; undefined field285_0x16a; undefined field286_0x16b; undefined field287_0x16c; undefined field288_0x16d; undefined field289_0x16e; undefined field290_0x16f; undefined field291_0x170; undefined field292_0x171; undefined field293_0x172; undefined field294_0x173; undefined field295_0x174; undefined field296_0x175; undefined field297_0x176; undefined field298_0x177; undefined field299_0x178; undefined field300_0x179; undefined field301_0x17a; undefined field302_0x17b; undefined field303_0x17c; undefined field304_0x17d; undefined field305_0x17e; undefined field306_0x17f; undefined field307_0x180; undefined field308_0x181; undefined field309_0x182; undefined field310_0x183; undefined field311_0x184; undefined field312_0x185; undefined field313_0x186; undefined field314_0x187; undefined field315_0x188; undefined field316_0x189; undefined field317_0x18a; undefined field318_0x18b; undefined field319_0x18c; undefined field320_0x18d; undefined field321_0x18e; undefined field322_0x18f; undefined8 * field323_0x190; undefined8 * field324_0x198; undefined * field325_0x1a0; undefined * field326_0x1a8; undefined * field327_0x1b0; char field328_0x1b8; undefined field329_0x1b9; undefined field330_0x1ba; undefined field331_0x1bb; undefined field332_0x1bc; undefined field333_0x1bd; undefined field334_0x1be; undefined field335_0x1bf; undefined field336_0x1c0; undefined field337_0x1c1; undefined field338_0x1c2; undefined field339_0x1c3; undefined field340_0x1c4; undefined field341_0x1c5; undefined field342_0x1c6; undefined field343_0x1c7; undefined field344_0x1c8; undefined field345_0x1c9; undefined field346_0x1ca; undefined field347_0x1cb; undefined field348_0x1cc; undefined field349_0x1cd; undefined field350_0x1ce; undefined field351_0x1cf; undefined field352_0x1d0; undefined field353_0x1d1; undefined field354_0x1d2; undefined field355_0x1d3; undefined field356_0x1d4; undefined field357_0x1d5; undefined field358_0x1d6; undefined field359_0x1d7; undefined field360_0x1d8; undefined field361_0x1d9; undefined field362_0x1da; undefined field363_0x1db; undefined field364_0x1dc; undefined field365_0x1dd; undefined field366_0x1de; undefined field367_0x1df; undefined field368_0x1e0; undefined field369_0x1e1; undefined field370_0x1e2; undefined field371_0x1e3; undefined field372_0x1e4; undefined field373_0x1e5; undefined field374_0x1e6; undefined field375_0x1e7; undefined field376_0x1e8; undefined field377_0x1e9; undefined field378_0x1ea; undefined field379_0x1eb; undefined field380_0x1ec; undefined field381_0x1ed; undefined field382_0x1ee; undefined field383_0x1ef; undefined field384_0x1f0; undefined field385_0x1f1; undefined field386_0x1f2; undefined field387_0x1f3; undefined field388_0x1f4; undefined field389_0x1f5; undefined field390_0x1f6; undefined field391_0x1f7; undefined field392_0x1f8; undefined field393_0x1f9; undefined field394_0x1fa; undefined field395_0x1fb; undefined field396_0x1fc; undefined field397_0x1fd; undefined field398_0x1fe; undefined field399_0x1ff; undefined field400_0x200; undefined field401_0x201; undefined field402_0x202; undefined field403_0x203; undefined field404_0x204; undefined field405_0x205; }; typedef struct astruct_2 astruct_2, *Pastruct_2; struct astruct_2 { undefined * field0_0x0; undefined field1_0x8; undefined field2_0x9; undefined field3_0xa; undefined field4_0xb; undefined field5_0xc; undefined field6_0xd; undefined field7_0xe; undefined field8_0xf; undefined field9_0x10; undefined field10_0x11; undefined field11_0x12; undefined field12_0x13; undefined field13_0x14; undefined field14_0x15; undefined field15_0x16; undefined field16_0x17; undefined * field17_0x18; undefined field18_0x20; undefined field19_0x21; undefined field20_0x22; undefined field21_0x23; undefined field22_0x24; undefined field23_0x25; undefined field24_0x26; undefined field25_0x27; undefined * field26_0x28; undefined * field27_0x30; undefined * field28_0x38; undefined field29_0x40; undefined field30_0x41; undefined field31_0x42; undefined field32_0x43; undefined field33_0x44; undefined field34_0x45; undefined field35_0x46; undefined field36_0x47; undefined * field37_0x48; undefined * field38_0x50; undefined * field39_0x58; undefined * field40_0x60; undefined * field41_0x68; undefined * field42_0x70; undefined * field43_0x78; undefined * field44_0x80; undefined * field45_0x88; undefined * field46_0x90; undefined8 field47_0x98; undefined * field48_0xa0; undefined field49_0xa8; undefined field50_0xa9; undefined field51_0xaa; undefined field52_0xab; undefined field53_0xac; undefined field54_0xad; undefined field55_0xae; undefined field56_0xaf; long field57_0xb0; long * field58_0xb8; undefined * field59_0xc0; undefined field60_0xc8; undefined field61_0xc9; undefined field62_0xca; undefined field63_0xcb; undefined field64_0xcc; undefined field65_0xcd; undefined field66_0xce; undefined field67_0xcf; undefined field68_0xd0; undefined field69_0xd1; undefined field70_0xd2; undefined field71_0xd3; undefined field72_0xd4; undefined field73_0xd5; undefined field74_0xd6; undefined field75_0xd7; undefined field76_0xd8; undefined field77_0xd9; undefined field78_0xda; undefined field79_0xdb; undefined field80_0xdc; undefined field81_0xdd; undefined field82_0xde; undefined field83_0xdf; undefined field84_0xe0; undefined field85_0xe1; undefined field86_0xe2; undefined field87_0xe3; undefined field88_0xe4; undefined field89_0xe5; byte field90_0xe6; byte field91_0xe7; char field92_0xe8; char field93_0xe9; char field94_0xea; undefined field95_0xeb; undefined field96_0xec; undefined field97_0xed; undefined field98_0xee; undefined field99_0xef; undefined field100_0xf0; undefined field101_0xf1; undefined field102_0xf2; undefined field103_0xf3; undefined field104_0xf4; undefined field105_0xf5; undefined field106_0xf6; undefined field107_0xf7; undefined field108_0xf8; undefined field109_0xf9; undefined field110_0xfa; undefined field111_0xfb; undefined field112_0xfc; undefined field113_0xfd; undefined field114_0xfe; undefined field115_0xff; int field116_0x100; uint field117_0x104; long field118_0x108; undefined4 field119_0x110; undefined4 field120_0x114; long field121_0x118; undefined field122_0x120; undefined field123_0x121; undefined field124_0x122; undefined field125_0x123; undefined field126_0x124; undefined field127_0x125; undefined field128_0x126; undefined field129_0x127; undefined field130_0x128; undefined field131_0x129; undefined field132_0x12a; undefined field133_0x12b; undefined field134_0x12c; undefined field135_0x12d; undefined field136_0x12e; undefined field137_0x12f; undefined field138_0x130; undefined field139_0x131; undefined field140_0x132; undefined field141_0x133; undefined field142_0x134; undefined field143_0x135; undefined field144_0x136; undefined field145_0x137; undefined field146_0x138; undefined field147_0x139; undefined field148_0x13a; undefined field149_0x13b; undefined field150_0x13c; undefined field151_0x13d; undefined field152_0x13e; undefined field153_0x13f; undefined field154_0x140; undefined field155_0x141; undefined field156_0x142; undefined field157_0x143; undefined field158_0x144; undefined field159_0x145; undefined field160_0x146; undefined field161_0x147; undefined field162_0x148; undefined field163_0x149; undefined field164_0x14a; undefined field165_0x14b; undefined field166_0x14c; undefined field167_0x14d; undefined field168_0x14e; undefined field169_0x14f; undefined field170_0x150; undefined field171_0x151; undefined field172_0x152; undefined field173_0x153; undefined field174_0x154; undefined field175_0x155; undefined field176_0x156; undefined field177_0x157; undefined field178_0x158; undefined field179_0x159; undefined field180_0x15a; undefined field181_0x15b; undefined field182_0x15c; undefined field183_0x15d; undefined field184_0x15e; undefined field185_0x15f; undefined field186_0x160; undefined field187_0x161; undefined field188_0x162; undefined field189_0x163; undefined field190_0x164; undefined field191_0x165; undefined field192_0x166; undefined field193_0x167; undefined field194_0x168; undefined field195_0x169; undefined field196_0x16a; undefined field197_0x16b; undefined field198_0x16c; undefined field199_0x16d; undefined field200_0x16e; undefined field201_0x16f; undefined field202_0x170; undefined field203_0x171; undefined field204_0x172; undefined field205_0x173; undefined field206_0x174; undefined field207_0x175; undefined field208_0x176; undefined field209_0x177; undefined field210_0x178; undefined field211_0x179; undefined field212_0x17a; undefined field213_0x17b; undefined field214_0x17c; undefined field215_0x17d; undefined field216_0x17e; undefined field217_0x17f; undefined field218_0x180; undefined field219_0x181; undefined field220_0x182; undefined field221_0x183; undefined field222_0x184; undefined field223_0x185; undefined field224_0x186; undefined field225_0x187; undefined field226_0x188; undefined field227_0x189; undefined field228_0x18a; undefined field229_0x18b; undefined field230_0x18c; undefined field231_0x18d; undefined field232_0x18e; undefined field233_0x18f; int * field234_0x190; int * field235_0x198; undefined * field236_0x1a0; undefined * field237_0x1a8; undefined * field238_0x1b0; char field239_0x1b8; byte field240_0x1b9; undefined field241_0x1ba; undefined field242_0x1bb; undefined4 field243_0x1bc; undefined4 field244_0x1c0; uint field245_0x1c4; byte field246_0x1c8; char field247_0x1c9; short field248_0x1ca; undefined field249_0x1cc; char field250_0x1cd; char field251_0x1ce; undefined field252_0x1cf; uint field253_0x1d0; uint field254_0x1d4; char field255_0x1d8; undefined field256_0x1d9; undefined field257_0x1da; undefined field258_0x1db; uint field259_0x1dc; uint field260_0x1e0; char field261_0x1e4; undefined field262_0x1e5; undefined field263_0x1e6; undefined field264_0x1e7; uint field265_0x1e8; uint field266_0x1ec; undefined field267_0x1f0; undefined field268_0x1f1; undefined field269_0x1f2; undefined field270_0x1f3; uint field271_0x1f4; uint field272_0x1f8; uint field273_0x1fc; uint field274_0x200; undefined field275_0x204; undefined field276_0x205; char field277_0x206; undefined field278_0x207; char field279_0x208; char field280_0x209; undefined field281_0x20a; undefined field282_0x20b; uint field283_0x20c; char field284_0x210; undefined field285_0x211; undefined field286_0x212; undefined field287_0x213; uint field288_0x214; char field289_0x218; char field290_0x219; char field291_0x21a; char field292_0x21b; char field293_0x21c; char field294_0x21d; undefined field295_0x21e; undefined field296_0x21f; undefined4 field297_0x220; char field298_0x224; undefined field299_0x225; undefined field300_0x226; undefined field301_0x227; undefined4 field302_0x228; undefined field303_0x22c; undefined field304_0x22d; undefined field305_0x22e; undefined field306_0x22f; undefined field307_0x230; undefined field308_0x231; undefined field309_0x232; undefined field310_0x233; byte field311_0x234; byte field312_0x235; char field313_0x236; undefined field314_0x237; undefined4 field315_0x238; undefined field316_0x23c; undefined field317_0x23d; undefined field318_0x23e; undefined field319_0x23f; undefined field320_0x240; undefined field321_0x241; undefined field322_0x242; undefined field323_0x243; undefined field324_0x244; undefined field325_0x245; undefined field326_0x246; undefined field327_0x247; undefined field328_0x248; undefined field329_0x249; undefined field330_0x24a; undefined field331_0x24b; undefined field332_0x24c; undefined field333_0x24d; undefined field334_0x24e; undefined field335_0x24f; undefined field336_0x250; undefined field337_0x251; undefined field338_0x252; undefined field339_0x253; byte field340_0x254; byte field341_0x255; byte field342_0x256; undefined field343_0x257; undefined4 field344_0x258; undefined field345_0x25c; char field346_0x25d; undefined field347_0x25e; undefined field348_0x25f; undefined field349_0x260; undefined field350_0x261; undefined field351_0x262; byte field352_0x263; undefined field353_0x264; undefined field354_0x265; char field355_0x266; undefined field356_0x267; uint field357_0x268; undefined field358_0x26c; undefined field359_0x26d; undefined field360_0x26e; undefined field361_0x26f; undefined4 field362_0x270; }; typedef struct astruct_1 astruct_1, *Pastruct_1; struct astruct_1 { undefined field0_0x0; undefined field1_0x1; undefined field2_0x2; undefined field3_0x3; undefined field4_0x4; undefined field5_0x5; undefined field6_0x6; undefined field7_0x7; undefined field8_0x8; undefined field9_0x9; undefined field10_0xa; undefined field11_0xb; undefined field12_0xc; undefined field13_0xd; undefined field14_0xe; undefined field15_0xf; undefined field16_0x10; undefined field17_0x11; undefined field18_0x12; undefined field19_0x13; undefined field20_0x14; undefined field21_0x15; undefined field22_0x16; undefined field23_0x17; undefined field24_0x18; undefined field25_0x19; undefined field26_0x1a; undefined field27_0x1b; undefined field28_0x1c; undefined field29_0x1d; undefined field30_0x1e; undefined field31_0x1f; undefined field32_0x20; undefined field33_0x21; undefined field34_0x22; undefined field35_0x23; undefined field36_0x24; undefined field37_0x25; undefined field38_0x26; undefined field39_0x27; undefined field40_0x28; undefined field41_0x29; undefined field42_0x2a; undefined field43_0x2b; undefined field44_0x2c; undefined field45_0x2d; undefined field46_0x2e; undefined field47_0x2f; undefined field48_0x30; undefined field49_0x31; undefined field50_0x32; undefined field51_0x33; undefined field52_0x34; undefined field53_0x35; undefined field54_0x36; undefined field55_0x37; undefined field56_0x38; undefined field57_0x39; undefined field58_0x3a; undefined field59_0x3b; undefined field60_0x3c; undefined field61_0x3d; undefined field62_0x3e; undefined field63_0x3f; undefined field64_0x40; undefined field65_0x41; undefined field66_0x42; undefined field67_0x43; undefined field68_0x44; undefined field69_0x45; undefined field70_0x46; undefined field71_0x47; undefined field72_0x48; undefined field73_0x49; undefined field74_0x4a; undefined field75_0x4b; undefined field76_0x4c; undefined field77_0x4d; undefined field78_0x4e; undefined field79_0x4f; undefined field80_0x50; undefined field81_0x51; undefined field82_0x52; undefined field83_0x53; undefined field84_0x54; undefined field85_0x55; undefined field86_0x56; undefined field87_0x57; undefined field88_0x58; undefined field89_0x59; undefined field90_0x5a; undefined field91_0x5b; undefined field92_0x5c; undefined field93_0x5d; undefined field94_0x5e; undefined field95_0x5f; undefined field96_0x60; undefined field97_0x61; undefined field98_0x62; undefined field99_0x63; undefined field100_0x64; undefined field101_0x65; undefined field102_0x66; undefined field103_0x67; undefined field104_0x68; undefined field105_0x69; undefined field106_0x6a; undefined field107_0x6b; undefined field108_0x6c; undefined field109_0x6d; undefined field110_0x6e; undefined field111_0x6f; undefined field112_0x70; undefined field113_0x71; undefined field114_0x72; undefined field115_0x73; undefined field116_0x74; undefined field117_0x75; undefined field118_0x76; undefined field119_0x77; undefined field120_0x78; undefined field121_0x79; undefined field122_0x7a; undefined field123_0x7b; undefined field124_0x7c; undefined field125_0x7d; undefined field126_0x7e; undefined field127_0x7f; undefined field128_0x80; undefined field129_0x81; undefined field130_0x82; undefined field131_0x83; undefined field132_0x84; undefined field133_0x85; undefined field134_0x86; undefined field135_0x87; undefined field136_0x88; undefined field137_0x89; undefined field138_0x8a; undefined field139_0x8b; undefined field140_0x8c; undefined field141_0x8d; undefined field142_0x8e; undefined field143_0x8f; undefined field144_0x90; undefined field145_0x91; undefined field146_0x92; undefined field147_0x93; undefined field148_0x94; undefined field149_0x95; undefined field150_0x96; undefined field151_0x97; undefined field152_0x98; undefined field153_0x99; undefined field154_0x9a; undefined field155_0x9b; undefined field156_0x9c; undefined field157_0x9d; undefined field158_0x9e; undefined field159_0x9f; undefined field160_0xa0; undefined field161_0xa1; undefined field162_0xa2; undefined field163_0xa3; undefined field164_0xa4; undefined field165_0xa5; undefined field166_0xa6; undefined field167_0xa7; undefined field168_0xa8; undefined field169_0xa9; undefined field170_0xaa; undefined field171_0xab; undefined field172_0xac; undefined field173_0xad; undefined field174_0xae; undefined field175_0xaf; undefined field176_0xb0; undefined field177_0xb1; undefined field178_0xb2; undefined field179_0xb3; undefined field180_0xb4; undefined field181_0xb5; undefined field182_0xb6; undefined field183_0xb7; undefined field184_0xb8; undefined field185_0xb9; undefined field186_0xba; undefined field187_0xbb; undefined field188_0xbc; undefined field189_0xbd; undefined field190_0xbe; undefined field191_0xbf; undefined * field192_0xc0; undefined field193_0xc8; undefined field194_0xc9; undefined field195_0xca; undefined field196_0xcb; undefined field197_0xcc; undefined field198_0xcd; undefined field199_0xce; undefined field200_0xcf; undefined field201_0xd0; undefined field202_0xd1; undefined field203_0xd2; undefined field204_0xd3; undefined field205_0xd4; undefined field206_0xd5; undefined field207_0xd6; undefined field208_0xd7; undefined field209_0xd8; undefined field210_0xd9; undefined field211_0xda; undefined field212_0xdb; undefined field213_0xdc; undefined field214_0xdd; undefined field215_0xde; undefined field216_0xdf; undefined field217_0xe0; undefined field218_0xe1; undefined field219_0xe2; undefined field220_0xe3; undefined field221_0xe4; undefined field222_0xe5; undefined field223_0xe6; undefined field224_0xe7; undefined field225_0xe8; undefined field226_0xe9; char field227_0xea; undefined field228_0xeb; undefined field229_0xec; undefined field230_0xed; undefined field231_0xee; undefined field232_0xef; undefined field233_0xf0; undefined field234_0xf1; undefined field235_0xf2; undefined field236_0xf3; undefined field237_0xf4; undefined field238_0xf5; undefined field239_0xf6; undefined field240_0xf7; undefined field241_0xf8; undefined field242_0xf9; undefined field243_0xfa; undefined field244_0xfb; undefined field245_0xfc; undefined field246_0xfd; undefined field247_0xfe; undefined field248_0xff; int field249_0x100; uint field250_0x104; long field251_0x108; undefined4 field252_0x110; undefined4 field253_0x114; long field254_0x118; undefined field255_0x120; undefined field256_0x121; undefined field257_0x122; undefined field258_0x123; undefined field259_0x124; undefined field260_0x125; undefined field261_0x126; undefined field262_0x127; undefined field263_0x128; undefined field264_0x129; undefined field265_0x12a; undefined field266_0x12b; undefined field267_0x12c; undefined field268_0x12d; undefined field269_0x12e; undefined field270_0x12f; undefined field271_0x130; undefined field272_0x131; undefined field273_0x132; undefined field274_0x133; undefined field275_0x134; undefined field276_0x135; undefined field277_0x136; undefined field278_0x137; undefined field279_0x138; undefined field280_0x139; undefined field281_0x13a; undefined field282_0x13b; undefined field283_0x13c; undefined field284_0x13d; undefined field285_0x13e; undefined field286_0x13f; undefined field287_0x140; undefined field288_0x141; undefined field289_0x142; undefined field290_0x143; undefined field291_0x144; undefined field292_0x145; undefined field293_0x146; undefined field294_0x147; undefined field295_0x148; undefined field296_0x149; undefined field297_0x14a; undefined field298_0x14b; undefined field299_0x14c; undefined field300_0x14d; undefined field301_0x14e; undefined field302_0x14f; undefined field303_0x150; undefined field304_0x151; undefined field305_0x152; undefined field306_0x153; undefined field307_0x154; undefined field308_0x155; undefined field309_0x156; undefined field310_0x157; undefined field311_0x158; undefined field312_0x159; undefined field313_0x15a; undefined field314_0x15b; undefined field315_0x15c; undefined field316_0x15d; undefined field317_0x15e; undefined field318_0x15f; undefined field319_0x160; undefined field320_0x161; undefined field321_0x162; undefined field322_0x163; undefined field323_0x164; undefined field324_0x165; undefined field325_0x166; undefined field326_0x167; undefined field327_0x168; undefined field328_0x169; undefined field329_0x16a; undefined field330_0x16b; undefined field331_0x16c; undefined field332_0x16d; undefined field333_0x16e; undefined field334_0x16f; undefined field335_0x170; undefined field336_0x171; undefined field337_0x172; undefined field338_0x173; undefined field339_0x174; undefined field340_0x175; undefined field341_0x176; undefined field342_0x177; undefined field343_0x178; undefined field344_0x179; undefined field345_0x17a; undefined field346_0x17b; undefined field347_0x17c; undefined field348_0x17d; undefined field349_0x17e; undefined field350_0x17f; undefined field351_0x180; undefined field352_0x181; undefined field353_0x182; undefined field354_0x183; undefined field355_0x184; undefined field356_0x185; undefined field357_0x186; undefined field358_0x187; undefined field359_0x188; undefined field360_0x189; undefined field361_0x18a; undefined field362_0x18b; undefined field363_0x18c; undefined field364_0x18d; undefined field365_0x18e; undefined field366_0x18f; int * field367_0x190; int * field368_0x198; undefined field369_0x1a0; undefined field370_0x1a1; undefined field371_0x1a2; undefined field372_0x1a3; undefined field373_0x1a4; undefined field374_0x1a5; undefined field375_0x1a6; undefined field376_0x1a7; undefined field377_0x1a8; undefined field378_0x1a9; undefined field379_0x1aa; undefined field380_0x1ab; undefined field381_0x1ac; undefined field382_0x1ad; undefined field383_0x1ae; undefined field384_0x1af; undefined field385_0x1b0; undefined field386_0x1b1; undefined field387_0x1b2; undefined field388_0x1b3; undefined field389_0x1b4; undefined field390_0x1b5; undefined field391_0x1b6; undefined field392_0x1b7; undefined field393_0x1b8; undefined field394_0x1b9; undefined field395_0x1ba; undefined field396_0x1bb; undefined field397_0x1bc; undefined field398_0x1bd; undefined field399_0x1be; undefined field400_0x1bf; undefined field401_0x1c0; undefined field402_0x1c1; undefined field403_0x1c2; undefined field404_0x1c3; undefined field405_0x1c4; undefined field406_0x1c5; undefined field407_0x1c6; undefined field408_0x1c7; undefined field409_0x1c8; undefined field410_0x1c9; undefined field411_0x1ca; undefined field412_0x1cb; undefined field413_0x1cc; undefined field414_0x1cd; undefined field415_0x1ce; undefined field416_0x1cf; undefined field417_0x1d0; undefined field418_0x1d1; undefined field419_0x1d2; undefined field420_0x1d3; undefined field421_0x1d4; undefined field422_0x1d5; undefined field423_0x1d6; undefined field424_0x1d7; undefined field425_0x1d8; undefined field426_0x1d9; undefined field427_0x1da; undefined field428_0x1db; undefined field429_0x1dc; undefined field430_0x1dd; undefined field431_0x1de; undefined field432_0x1df; undefined field433_0x1e0; undefined field434_0x1e1; undefined field435_0x1e2; undefined field436_0x1e3; undefined field437_0x1e4; undefined field438_0x1e5; undefined field439_0x1e6; undefined field440_0x1e7; undefined field441_0x1e8; undefined field442_0x1e9; undefined field443_0x1ea; undefined field444_0x1eb; undefined field445_0x1ec; undefined field446_0x1ed; undefined field447_0x1ee; undefined field448_0x1ef; undefined field449_0x1f0; undefined field450_0x1f1; undefined field451_0x1f2; undefined field452_0x1f3; undefined field453_0x1f4; undefined field454_0x1f5; undefined field455_0x1f6; undefined field456_0x1f7; undefined field457_0x1f8; undefined field458_0x1f9; undefined field459_0x1fa; undefined field460_0x1fb; undefined field461_0x1fc; undefined field462_0x1fd; undefined field463_0x1fe; undefined field464_0x1ff; undefined field465_0x200; undefined field466_0x201; undefined field467_0x202; undefined field468_0x203; undefined field469_0x204; undefined field470_0x205; undefined field471_0x206; undefined field472_0x207; undefined field473_0x208; undefined field474_0x209; undefined field475_0x20a; undefined field476_0x20b; undefined field477_0x20c; undefined field478_0x20d; undefined field479_0x20e; undefined field480_0x20f; undefined field481_0x210; undefined field482_0x211; undefined field483_0x212; undefined field484_0x213; undefined field485_0x214; undefined field486_0x215; undefined field487_0x216; undefined field488_0x217; undefined field489_0x218; undefined field490_0x219; undefined field491_0x21a; undefined field492_0x21b; undefined field493_0x21c; undefined field494_0x21d; undefined field495_0x21e; undefined field496_0x21f; undefined field497_0x220; undefined field498_0x221; undefined field499_0x222; undefined field500_0x223; undefined field501_0x224; undefined field502_0x225; undefined field503_0x226; undefined field504_0x227; undefined field505_0x228; undefined field506_0x229; undefined field507_0x22a; undefined field508_0x22b; undefined field509_0x22c; undefined field510_0x22d; undefined field511_0x22e; undefined field512_0x22f; undefined field513_0x230; undefined field514_0x231; undefined field515_0x232; undefined field516_0x233; undefined field517_0x234; undefined field518_0x235; undefined field519_0x236; undefined field520_0x237; undefined field521_0x238; undefined field522_0x239; undefined field523_0x23a; undefined field524_0x23b; undefined field525_0x23c; undefined field526_0x23d; undefined field527_0x23e; undefined field528_0x23f; undefined field529_0x240; undefined field530_0x241; undefined field531_0x242; undefined field532_0x243; undefined field533_0x244; undefined field534_0x245; undefined field535_0x246; undefined field536_0x247; undefined field537_0x248; undefined field538_0x249; undefined field539_0x24a; undefined field540_0x24b; undefined field541_0x24c; undefined field542_0x24d; undefined field543_0x24e; undefined field544_0x24f; undefined field545_0x250; undefined field546_0x251; undefined field547_0x252; undefined field548_0x253; undefined field549_0x254; undefined field550_0x255; undefined field551_0x256; undefined field552_0x257; undefined field553_0x258; undefined field554_0x259; undefined field555_0x25a; undefined field556_0x25b; undefined field557_0x25c; char field558_0x25d; }; typedef union eth_aml_reg0 eth_aml_reg0, *Peth_aml_reg0; typedef union eth_aml_reg0 eth_aml_reg0_t; typedef struct _struct_34 _struct_34, *P_struct_34; struct _struct_34 { uint phy_intf_sel:3; uint rx_clk_rmii_invert:1; uint rgmii_tx_clk_src:1; uint rgmii_tx_clk_phase:2; uint rgmii_tx_clk_ratio:3; uint phy_ref_clk_enable:1; uint clk_rmii_i_invert:1; uint clk_en:1; uint adj_enable:1; uint adj_setup:1; uint adj_delay:5; uint adj_skew:5; uint cali_start:1; uint cali_rise:1; uint cali_sel:3; uint rgmii_rx_reuse:1; uint eth_urgent:1; }; union eth_aml_reg0 { uint d32; struct _struct_34 b; }; typedef struct eth_clock_conf eth_clock_conf, *Peth_clock_conf; struct eth_clock_conf { int enable; int clock_50MHZ_phase; }; typedef struct eth_board_socket eth_board_socket, *Peth_board_socket; struct eth_board_socket { char * name; int (* eth_clock_configure)(struct eth_clock_conf); int (* eth_pinmux_setup)(void); int (* eth_hw_reset)(void); }; #define ETH_BASE 4282318848 #define CLK_1M 1000000 #define ETH_PLL_CNTL_DESEND 8 #define ETH_CLKSRC_SYS_PLL_CLK 1 #define ETH_CLKSRC_VID_PLL_CLK 5 #define ETH_PLL_CNTL_DIVEN 1 #define ETH_CLKSRC_VID2_PLL_CLK 6 #define ETH_CLKSRC_XTAL 0 #define ETH_PLL_CNTL_MACSPD 2 #define ETH_CLKSRC_DDR_PLL_CLK 3 #define ETH_CLKSRC_SYS_PLL_DIV2_CLK 7 #define ETH_PLL_CNTL_DATEND 4 #define ETH_PLL_CNTL 4291854656 #define ETH_CLKSRC_MISC_PLL_CLK 2 typedef ulong size_t; typedef struct ddr_reg ddr_reg, *Pddr_reg; struct ddr_reg { uint reg; uint value; uint mask; ushort udelay; uchar flag; uchar rsv_0; }; typedef struct bl2_reg bl2_reg, *Pbl2_reg; typedef struct bl2_reg bl2_reg_t; struct bl2_reg { uint reg; uint value; uint mask; ushort udelay; uchar flag; uchar rsv_0; }; typedef struct ddr_reg ddr_reg_t; typedef struct ddr_set ddr_set, *Pddr_set; struct ddr_set { uint magic; uchar fast_boot[4]; uchar board_id; uchar version; uchar DramType; uchar DisabledDbyte; uchar Is2Ttiming; uchar HdtCtrl; uchar dram_rank_config; uchar diagnose; uint imem_load_addr; uint dmem_load_addr; ushort imem_load_size; ushort dmem_load_size; uint ddr_base_addr; uint ddr_start_offset; ushort dram_cs0_size_MB; ushort dram_cs1_size_MB; ushort training_SequenceCtrl[2]; uchar phy_odt_config_rank[2]; uchar rever1; uchar rever2; uint dfi_odt_config; ushort DRAMFreq[4]; uchar PllBypassEn; uchar ddr_rdbi_wr_enable; uchar ddr_rfc_type; uchar enable_lpddr4x_mode; uint pll_ssc_mode; ushort clk_drv_ohm; ushort cs_drv_ohm; ushort ac_drv_ohm; ushort soc_data_drv_ohm_p; ushort soc_data_drv_ohm_n; ushort soc_data_odt_ohm_p; ushort soc_data_odt_ohm_n; ushort dram_data_drv_ohm; ushort dram_data_odt_ohm; ushort dram_ac_odt_ohm; ushort soc_clk_slew_rate; ushort soc_cs_slew_rate; ushort soc_ac_slew_rate; ushort soc_data_slew_rate; ushort vref_output_permil; ushort vref_receiver_permil; ushort vref_dram_permil; ushort max_core_timmming_frequency; uchar ac_trace_delay[10]; uchar lpddr4_dram_vout_voltage_1_3_2_5_setting; uchar lpddr4_x8_mode; uchar ac_pinmux[28]; uchar dfi_pinmux[26]; uchar slt_test_function[2]; ushort tdqs2dq; uchar dram_data_wr_odt_ohm; uchar bitTimeControl_2d; uint ddr_dmc_remap[5]; uchar ddr_lpddr34_ca_remap[4]; uchar ddr_lpddr34_dq_remap[32]; uint dram_rtt_nom_wr_park[2]; uint ddr_func; uchar read_dqs_delay[16]; uchar read_dq_bit_delay[72]; ushort write_dqs_delay[16]; ushort write_dq_bit_delay[72]; ushort read_dqs_gate_delay[16]; uchar soc_bit_vref[32]; uchar dram_bit_vref[32]; uchar rever3; uchar dfi_mrl; uchar dfi_hwtmrl; uchar ARdPtrInitVal; uchar retraining[16]; }; typedef struct dmem_cfg dmem_cfg, *Pdmem_cfg; typedef struct _PMU_SMB_DDR4U_1D_t _PMU_SMB_DDR4U_1D_t, *P_PMU_SMB_DDR4U_1D_t; typedef struct _PMU_SMB_DDR4U_1D_t PMU_SMB_DDR4U_1D_t; typedef struct _PMU_SMB_LPDDR3_1D_t _PMU_SMB_LPDDR3_1D_t, *P_PMU_SMB_LPDDR3_1D_t; typedef struct _PMU_SMB_LPDDR3_1D_t PMU_SMB_LPDDR3_1D_t; typedef struct _PMU_SMB_LPDDR4_2D_t _PMU_SMB_LPDDR4_2D_t, *P_PMU_SMB_LPDDR4_2D_t; typedef struct _PMU_SMB_LPDDR4_2D_t PMU_SMB_LPDDR4_2D_t; struct _PMU_SMB_DDR4U_1D_t { uint8_t Reserved00; uint8_t MsgMisc; uint16_t PmuRevision; uint8_t Pstate; uint8_t PllBypassEn; uint16_t DRAMFreq; uint8_t DfiFreqRatio; uint8_t BPZNResVal; uint8_t PhyOdtImpedance; uint8_t PhyDrvImpedance; uint8_t PhyVref; uint8_t DramType; uint8_t DisabledDbyte; uint8_t EnabledDQs; uint8_t CsPresent; uint8_t CsPresentD0; uint8_t CsPresentD1; uint8_t AddrMirror; uint8_t CsTestFail; uint8_t PhyCfg; uint16_t SequenceCtrl; uint8_t HdtCtrl; uint8_t Reserved19; uint8_t Reserved1A; uint8_t Reserved1B; uint8_t Reserved1C; uint8_t Reserved1D; uint8_t Reserved1E; uint8_t Reserved1F; uint8_t Reserved20; uint8_t Reserved21; uint16_t PhyConfigOverride; uint8_t DFIMRLMargin; int8_t CDD_RR_3_2; int8_t CDD_RR_3_1; int8_t CDD_RR_3_0; int8_t CDD_RR_2_3; int8_t CDD_RR_2_1; int8_t CDD_RR_2_0; int8_t CDD_RR_1_3; int8_t CDD_RR_1_2; int8_t CDD_RR_1_0; int8_t CDD_RR_0_3; int8_t CDD_RR_0_2; int8_t CDD_RR_0_1; int8_t CDD_WW_3_2; int8_t CDD_WW_3_1; int8_t CDD_WW_3_0; int8_t CDD_WW_2_3; int8_t CDD_WW_2_1; int8_t CDD_WW_2_0; int8_t CDD_WW_1_3; int8_t CDD_WW_1_2; int8_t CDD_WW_1_0; int8_t CDD_WW_0_3; int8_t CDD_WW_0_2; int8_t CDD_WW_0_1; int8_t CDD_RW_3_3; int8_t CDD_RW_3_2; int8_t CDD_RW_3_1; int8_t CDD_RW_3_0; int8_t CDD_RW_2_3; int8_t CDD_RW_2_2; int8_t CDD_RW_2_1; int8_t CDD_RW_2_0; int8_t CDD_RW_1_3; int8_t CDD_RW_1_2; int8_t CDD_RW_1_1; int8_t CDD_RW_1_0; int8_t CDD_RW_0_3; int8_t CDD_RW_0_2; int8_t CDD_RW_0_1; int8_t CDD_RW_0_0; int8_t CDD_WR_3_3; int8_t CDD_WR_3_2; int8_t CDD_WR_3_1; int8_t CDD_WR_3_0; int8_t CDD_WR_2_3; int8_t CDD_WR_2_2; int8_t CDD_WR_2_1; int8_t CDD_WR_2_0; int8_t CDD_WR_1_3; int8_t CDD_WR_1_2; int8_t CDD_WR_1_1; int8_t CDD_WR_1_0; int8_t CDD_WR_0_3; int8_t CDD_WR_0_2; int8_t CDD_WR_0_1; int8_t CDD_WR_0_0; uint8_t Reserved5D; uint16_t MR0; uint16_t MR1; uint16_t MR2; uint16_t MR3; uint16_t MR4; uint16_t MR5; uint16_t MR6; uint8_t X16Present; uint8_t CsSetupGDDec; uint16_t RTT_NOM_WR_PARK0; uint16_t RTT_NOM_WR_PARK1; uint16_t RTT_NOM_WR_PARK2; uint16_t RTT_NOM_WR_PARK3; uint16_t RTT_NOM_WR_PARK4; uint16_t RTT_NOM_WR_PARK5; uint16_t RTT_NOM_WR_PARK6; uint16_t RTT_NOM_WR_PARK7; uint8_t AcsmOdtCtrl0; uint8_t AcsmOdtCtrl1; uint8_t AcsmOdtCtrl2; uint8_t AcsmOdtCtrl3; uint8_t AcsmOdtCtrl4; uint8_t AcsmOdtCtrl5; uint8_t AcsmOdtCtrl6; uint8_t AcsmOdtCtrl7; uint8_t VrefDqR0Nib0; uint8_t VrefDqR0Nib1; uint8_t VrefDqR0Nib2; uint8_t VrefDqR0Nib3; uint8_t VrefDqR0Nib4; uint8_t VrefDqR0Nib5; uint8_t VrefDqR0Nib6; uint8_t VrefDqR0Nib7; uint8_t VrefDqR0Nib8; uint8_t VrefDqR0Nib9; uint8_t VrefDqR0Nib10; uint8_t VrefDqR0Nib11; uint8_t VrefDqR0Nib12; uint8_t VrefDqR0Nib13; uint8_t VrefDqR0Nib14; uint8_t VrefDqR0Nib15; uint8_t VrefDqR0Nib16; uint8_t VrefDqR0Nib17; uint8_t VrefDqR0Nib18; uint8_t VrefDqR0Nib19; uint8_t VrefDqR1Nib0; uint8_t VrefDqR1Nib1; uint8_t VrefDqR1Nib2; uint8_t VrefDqR1Nib3; uint8_t VrefDqR1Nib4; uint8_t VrefDqR1Nib5; uint8_t VrefDqR1Nib6; uint8_t VrefDqR1Nib7; uint8_t VrefDqR1Nib8; uint8_t VrefDqR1Nib9; uint8_t VrefDqR1Nib10; uint8_t VrefDqR1Nib11; uint8_t VrefDqR1Nib12; uint8_t VrefDqR1Nib13; uint8_t VrefDqR1Nib14; uint8_t VrefDqR1Nib15; uint8_t VrefDqR1Nib16; uint8_t VrefDqR1Nib17; uint8_t VrefDqR1Nib18; uint8_t VrefDqR1Nib19; uint8_t VrefDqR2Nib0; uint8_t VrefDqR2Nib1; uint8_t VrefDqR2Nib2; uint8_t VrefDqR2Nib3; uint8_t VrefDqR2Nib4; uint8_t VrefDqR2Nib5; uint8_t VrefDqR2Nib6; uint8_t VrefDqR2Nib7; uint8_t VrefDqR2Nib8; uint8_t VrefDqR2Nib9; uint8_t VrefDqR2Nib10; uint8_t VrefDqR2Nib11; uint8_t VrefDqR2Nib12; uint8_t VrefDqR2Nib13; uint8_t VrefDqR2Nib14; uint8_t VrefDqR2Nib15; uint8_t VrefDqR2Nib16; uint8_t VrefDqR2Nib17; uint8_t VrefDqR2Nib18; uint8_t VrefDqR2Nib19; uint8_t VrefDqR3Nib0; uint8_t VrefDqR3Nib1; uint8_t VrefDqR3Nib2; uint8_t VrefDqR3Nib3; uint8_t VrefDqR3Nib4; uint8_t VrefDqR3Nib5; uint8_t VrefDqR3Nib6; uint8_t VrefDqR3Nib7; uint8_t VrefDqR3Nib8; uint8_t VrefDqR3Nib9; uint8_t VrefDqR3Nib10; uint8_t VrefDqR3Nib11; uint8_t VrefDqR3Nib12; uint8_t VrefDqR3Nib13; uint8_t VrefDqR3Nib14; uint8_t VrefDqR3Nib15; uint8_t VrefDqR3Nib16; uint8_t VrefDqR3Nib17; uint8_t VrefDqR3Nib18; uint8_t VrefDqR3Nib19; uint8_t ReservedD6; uint8_t ReservedD7; uint8_t ReservedD8; uint8_t ReservedD9; uint8_t ReservedDA; uint8_t ReservedDB; uint8_t ReservedDC; uint8_t ReservedDD; uint8_t ReservedDE; uint8_t ReservedDF; uint8_t ReservedE0; uint8_t ReservedE1; uint8_t ReservedE2; uint8_t ReservedE3; uint8_t ReservedE4; uint8_t ReservedE5; uint8_t ReservedE6; uint8_t ReservedE7; uint8_t ReservedE8; uint8_t ReservedE9; uint8_t ReservedEA; uint8_t ReservedEB; uint8_t ReservedEC; uint8_t ReservedED; uint8_t ReservedEE; uint8_t ReservedEF; uint8_t ReservedF0; uint8_t ReservedF1; uint8_t ReservedF2; uint8_t ReservedF3; uint8_t ReservedF4; uint8_t ReservedF5; uint8_t ReservedF6; uint8_t ReservedF7; uint8_t ReservedF8; uint8_t ReservedF9; uint8_t ReservedFA; uint8_t ReservedFB; uint8_t ReservedFC; uint8_t ReservedFD; uint8_t ReservedFE; uint8_t ReservedFF; uint8_t Reserved100; uint8_t Reserved101; uint8_t Reserved102; uint8_t Reserved103; uint8_t Reserved104; uint8_t Reserved105; uint8_t Reserved106; uint8_t Reserved107; uint8_t Reserved108; uint8_t Reserved109; uint8_t Reserved10A; uint8_t Reserved10B; uint8_t Reserved10C; uint8_t Reserved10D; uint8_t Reserved10E; uint8_t Reserved10F; uint8_t Reserved110; uint8_t Reserved111; uint8_t Reserved112; uint8_t Reserved113; uint8_t Reserved114; uint8_t Reserved115; uint8_t Reserved116; uint8_t Reserved117; uint8_t Reserved118; uint8_t Reserved119; uint8_t Reserved11A; uint8_t Reserved11B; uint8_t Reserved11C; uint8_t Reserved11D; uint8_t Reserved11E; uint8_t Reserved11F; uint8_t Reserved120; uint8_t Reserved121; uint8_t Reserved122; uint8_t Reserved123; uint8_t Reserved124; uint8_t Reserved125; uint8_t Reserved126; uint8_t Reserved127; uint8_t Reserved128; uint8_t Reserved129; uint8_t Reserved12A; uint8_t Reserved12B; uint8_t Reserved12C; uint8_t Reserved12D; uint8_t Reserved12E; uint8_t Reserved12F; uint8_t Reserved130; uint8_t Reserved131; uint8_t Reserved132; uint8_t Reserved133; uint8_t Reserved134; uint8_t Reserved135; uint8_t Reserved136; uint8_t Reserved137; uint8_t Reserved138; uint8_t Reserved139; uint8_t Reserved13A; uint8_t Reserved13B; uint8_t Reserved13C; uint8_t Reserved13D; uint8_t Reserved13E; uint8_t Reserved13F; uint8_t Reserved140; uint8_t Reserved141; uint8_t Reserved142; uint8_t Reserved143; uint8_t Reserved144; uint8_t Reserved145; uint8_t Reserved146; uint8_t Reserved147; uint8_t Reserved148; uint8_t Reserved149; uint8_t Reserved14A; uint8_t Reserved14B; uint8_t Reserved14C; uint8_t Reserved14D; uint8_t Reserved14E; uint8_t Reserved14F; uint8_t Reserved150; uint8_t Reserved151; uint8_t Reserved152; uint8_t Reserved153; uint8_t Reserved154; uint8_t Reserved155; uint8_t Reserved156; uint8_t Reserved157; uint8_t Reserved158; uint8_t Reserved159; uint8_t Reserved15A; uint8_t Reserved15B; uint8_t Reserved15C; uint8_t Reserved15D; uint8_t Reserved15E; uint8_t Reserved15F; uint8_t Reserved160; uint8_t Reserved161; uint8_t Reserved162; uint8_t Reserved163; uint8_t Reserved164; uint8_t Reserved165; uint8_t Reserved166; uint8_t Reserved167; uint8_t Reserved168; uint8_t Reserved169; uint8_t Reserved16A; uint8_t Reserved16B; uint8_t Reserved16C; uint8_t Reserved16D; uint8_t Reserved16E; uint8_t Reserved16F; uint8_t Reserved170; uint8_t Reserved171; uint8_t Reserved172; uint8_t Reserved173; uint8_t Reserved174; uint8_t Reserved175; uint8_t Reserved176; uint8_t Reserved177; uint8_t Reserved178; uint8_t Reserved179; uint8_t Reserved17A; uint8_t Reserved17B; uint8_t Reserved17C; uint8_t Reserved17D; uint8_t Reserved17E; uint8_t Reserved17F; uint8_t Reserved180; uint8_t Reserved181; uint8_t Reserved182; uint8_t Reserved183; uint8_t Reserved184; uint8_t Reserved185; uint8_t Reserved186; uint8_t Reserved187; uint8_t Reserved188; uint8_t Reserved189; uint8_t Reserved18A; uint8_t Reserved18B; uint8_t Reserved18C; uint8_t Reserved18D; uint8_t Reserved18E; uint8_t Reserved18F; uint8_t Reserved190; uint8_t Reserved191; uint8_t Reserved192; uint8_t Reserved193; uint8_t Reserved194; uint8_t Reserved195; uint8_t Reserved196; uint8_t Reserved197; uint8_t Reserved198; uint8_t Reserved199; uint8_t Reserved19A; uint8_t Reserved19B; uint8_t Reserved19C; uint8_t Reserved19D; uint8_t Reserved19E; uint8_t Reserved19F; uint8_t Reserved1A0; uint8_t Reserved1A1; uint8_t Reserved1A2; uint8_t Reserved1A3; uint8_t Reserved1A4; uint8_t Reserved1A5; uint8_t Reserved1A6; uint8_t Reserved1A7; uint8_t Reserved1A8; uint8_t Reserved1A9; uint8_t Reserved1AA; uint8_t Reserved1AB; uint8_t Reserved1AC; uint8_t Reserved1AD; uint8_t Reserved1AE; uint8_t Reserved1AF; uint8_t Reserved1B0; uint8_t Reserved1B1; uint8_t Reserved1B2; uint8_t Reserved1B3; uint8_t Reserved1B4; uint8_t Reserved1B5; uint8_t Reserved1B6; uint8_t Reserved1B7; uint8_t Reserved1B8; uint8_t Reserved1B9; uint8_t Reserved1BA; uint8_t Reserved1BB; uint8_t Reserved1BC; uint8_t Reserved1BD; uint8_t Reserved1BE; uint8_t Reserved1BF; uint8_t Reserved1C0; uint8_t Reserved1C1; uint8_t Reserved1C2; uint8_t Reserved1C3; uint8_t Reserved1C4; uint8_t Reserved1C5; uint8_t Reserved1C6; uint8_t Reserved1C7; uint8_t Reserved1C8; uint8_t Reserved1C9; uint8_t Reserved1CA; uint8_t Reserved1CB; uint8_t Reserved1CC; uint8_t Reserved1CD; uint8_t Reserved1CE; uint8_t Reserved1CF; uint8_t Reserved1D0; uint8_t Reserved1D1; uint8_t Reserved1D2; uint8_t Reserved1D3; uint8_t Reserved1D4; uint8_t Reserved1D5; uint8_t Reserved1D6; uint8_t Reserved1D7; uint8_t Reserved1D8; uint8_t Reserved1D9; uint8_t Reserved1DA; uint8_t Reserved1DB; uint8_t Reserved1DC; uint8_t Reserved1DD; uint8_t Reserved1DE; uint8_t Reserved1DF; uint8_t Reserved1E0; uint8_t Reserved1E1; uint8_t Reserved1E2; uint8_t Reserved1E3; uint8_t Reserved1E4; uint8_t Reserved1E5; uint8_t Reserved1E6; uint8_t Reserved1E7; uint8_t Reserved1E8; uint8_t Reserved1E9; uint8_t Reserved1EA; uint8_t Reserved1EB; uint8_t Reserved1EC; uint8_t Reserved1ED; uint8_t Reserved1EE; uint8_t Reserved1EF; uint8_t Reserved1F0; uint8_t Reserved1F1; uint8_t Reserved1F2; uint8_t Reserved1F3; uint8_t Reserved1F4; uint8_t Reserved1F5; uint8_t Reserved1F6; uint8_t Reserved1F7; uint8_t Reserved1F8; uint8_t Reserved1F9; uint8_t Reserved1FA; uint8_t Reserved1FB; uint8_t Reserved1FC; uint8_t Reserved1FD; uint8_t Reserved1FE; uint8_t Reserved1FF; uint8_t Reserved200; uint8_t Reserved201; uint8_t Reserved202; uint8_t Reserved203; uint8_t Reserved204; uint8_t Reserved205; uint8_t Reserved206; uint8_t Reserved207; uint8_t Reserved208; uint8_t Reserved209; uint8_t Reserved20A; uint8_t Reserved20B; uint8_t Reserved20C; uint8_t Reserved20D; uint8_t Reserved20E; uint8_t Reserved20F; uint8_t Reserved210; uint8_t Reserved211; uint8_t Reserved212; uint8_t Reserved213; uint8_t Reserved214; uint8_t Reserved215; uint8_t Reserved216; uint8_t Reserved217; uint8_t Reserved218; uint8_t Reserved219; uint8_t Reserved21A; uint8_t Reserved21B; uint8_t Reserved21C; uint8_t Reserved21D; uint8_t Reserved21E; uint8_t Reserved21F; uint8_t Reserved220; uint8_t Reserved221; uint8_t Reserved222; uint8_t Reserved223; uint8_t Reserved224; uint8_t Reserved225; uint8_t Reserved226; uint8_t Reserved227; uint8_t Reserved228; uint8_t Reserved229; uint8_t Reserved22A; uint8_t Reserved22B; uint8_t Reserved22C; uint8_t Reserved22D; uint8_t Reserved22E; uint8_t Reserved22F; uint8_t Reserved230; uint8_t Reserved231; uint8_t Reserved232; uint8_t Reserved233; uint8_t Reserved234; uint8_t Reserved235; uint8_t Reserved236; uint8_t Reserved237; uint8_t Reserved238; uint8_t Reserved239; uint8_t Reserved23A; uint8_t Reserved23B; uint8_t Reserved23C; uint8_t Reserved23D; uint8_t Reserved23E; uint8_t Reserved23F; uint8_t Reserved240; uint8_t Reserved241; uint8_t Reserved242; uint8_t Reserved243; uint8_t Reserved244; uint8_t Reserved245; uint8_t Reserved246; uint8_t Reserved247; uint8_t Reserved248; uint8_t Reserved249; uint8_t Reserved24A; uint8_t Reserved24B; uint8_t Reserved24C; uint8_t Reserved24D; uint8_t Reserved24E; uint8_t Reserved24F; uint8_t Reserved250; uint8_t Reserved251; uint8_t Reserved252; uint8_t Reserved253; uint8_t Reserved254; uint8_t Reserved255; uint8_t Reserved256; uint8_t Reserved257; uint8_t Reserved258; uint8_t Reserved259; uint8_t Reserved25A; uint8_t Reserved25B; uint8_t Reserved25C; uint8_t Reserved25D; uint8_t Reserved25E; uint8_t Reserved25F; uint8_t Reserved260; uint8_t Reserved261; uint8_t Reserved262; uint8_t Reserved263; uint8_t Reserved264; uint8_t Reserved265; uint8_t Reserved266; uint8_t Reserved267; uint8_t Reserved268; uint8_t Reserved269; uint8_t Reserved26A; uint8_t Reserved26B; uint8_t Reserved26C; uint8_t Reserved26D; uint8_t Reserved26E; uint8_t Reserved26F; uint8_t Reserved270; uint8_t Reserved271; uint8_t Reserved272; uint8_t Reserved273; uint8_t Reserved274; uint8_t Reserved275; uint8_t Reserved276; uint8_t Reserved277; uint8_t Reserved278; uint8_t Reserved279; uint8_t Reserved27A; uint8_t Reserved27B; uint8_t Reserved27C; uint8_t Reserved27D; uint8_t Reserved27E; uint8_t Reserved27F; uint8_t Reserved280; uint8_t Reserved281; uint8_t Reserved282; uint8_t Reserved283; uint8_t Reserved284; uint8_t Reserved285; uint8_t Reserved286; uint8_t Reserved287; uint8_t Reserved288; uint8_t Reserved289; uint8_t Reserved28A; uint8_t Reserved28B; uint8_t Reserved28C; uint8_t Reserved28D; uint8_t Reserved28E; uint8_t Reserved28F; uint8_t Reserved290; uint8_t Reserved291; uint8_t Reserved292; uint8_t Reserved293; uint8_t Reserved294; uint8_t Reserved295; uint8_t Reserved296; uint8_t Reserved297; uint8_t Reserved298; uint8_t Reserved299; uint8_t Reserved29A; uint8_t Reserved29B; uint8_t Reserved29C; uint8_t Reserved29D; uint8_t Reserved29E; uint8_t Reserved29F; uint8_t Reserved2A0; uint8_t Reserved2A1; uint8_t Reserved2A2; uint8_t Reserved2A3; uint8_t Reserved2A4; uint8_t Reserved2A5; uint8_t Reserved2A6; uint8_t Reserved2A7; uint8_t Reserved2A8; uint8_t Reserved2A9; uint8_t Reserved2AA; uint8_t Reserved2AB; uint8_t Reserved2AC; uint8_t Reserved2AD; uint8_t Reserved2AE; uint8_t Reserved2AF; uint8_t Reserved2B0; uint8_t Reserved2B1; uint8_t Reserved2B2; uint8_t Reserved2B3; uint8_t Reserved2B4; uint8_t Reserved2B5; uint8_t Reserved2B6; uint8_t Reserved2B7; uint8_t Reserved2B8; uint8_t Reserved2B9; uint8_t Reserved2BA; uint8_t Reserved2BB; uint8_t Reserved2BC; uint8_t Reserved2BD; uint8_t Reserved2BE; uint8_t Reserved2BF; uint8_t Reserved2C0; uint8_t Reserved2C1; uint8_t Reserved2C2; uint8_t Reserved2C3; uint8_t Reserved2C4; uint8_t Reserved2C5; uint8_t Reserved2C6; uint8_t Reserved2C7; uint8_t Reserved2C8; uint8_t Reserved2C9; uint8_t Reserved2CA; uint8_t Reserved2CB; uint8_t Reserved2CC; uint8_t Reserved2CD; uint8_t Reserved2CE; uint8_t Reserved2CF; uint8_t Reserved2D0; uint8_t Reserved2D1; uint8_t Reserved2D2; uint8_t Reserved2D3; uint8_t Reserved2D4; uint8_t Reserved2D5; uint8_t Reserved2D6; uint8_t Reserved2D7; uint8_t Reserved2D8; uint8_t Reserved2D9; uint8_t Reserved2DA; uint8_t Reserved2DB; uint8_t Reserved2DC; uint8_t Reserved2DD; uint8_t Reserved2DE; uint8_t Reserved2DF; uint8_t Reserved2E0; uint8_t Reserved2E1; uint8_t Reserved2E2; uint8_t Reserved2E3; uint8_t Reserved2E4; uint8_t Reserved2E5; uint8_t Reserved2E6; uint8_t Reserved2E7; uint8_t Reserved2E8; uint8_t Reserved2E9; uint8_t Reserved2EA; uint8_t Reserved2EB; uint8_t Reserved2EC; uint8_t Reserved2ED; uint8_t Reserved2EE; uint8_t Reserved2EF; uint8_t Reserved2F0; uint8_t Reserved2F1; uint8_t Reserved2F2; uint8_t Reserved2F3; uint8_t Reserved2F4; uint8_t Reserved2F5; uint8_t Reserved2F6; uint8_t Reserved2F7; uint8_t Reserved2F8; uint8_t Reserved2F9; uint8_t Reserved2FA; uint8_t Reserved2FB; uint8_t Reserved2FC; uint8_t Reserved2FD; uint8_t Reserved2FE; uint8_t Reserved2FF; uint8_t Reserved300; uint8_t Reserved301; uint8_t Reserved302; uint8_t Reserved303; uint8_t Reserved304; uint8_t Reserved305; uint8_t Reserved306; uint8_t Reserved307; uint8_t Reserved308; uint8_t Reserved309; uint8_t Reserved30A; uint8_t Reserved30B; uint8_t Reserved30C; uint8_t Reserved30D; uint8_t Reserved30E; uint8_t Reserved30F; uint8_t Reserved310; uint8_t Reserved311; uint8_t Reserved312; uint8_t Reserved313; uint8_t Reserved314; uint8_t Reserved315; uint8_t Reserved316; uint8_t Reserved317; uint8_t Reserved318; uint8_t Reserved319; uint8_t Reserved31A; uint8_t Reserved31B; uint8_t Reserved31C; uint8_t Reserved31D; uint8_t Reserved31E; uint8_t Reserved31F; uint8_t Reserved320; uint8_t Reserved321; uint8_t Reserved322; uint8_t Reserved323; uint8_t Reserved324; uint8_t Reserved325; uint8_t Reserved326; uint8_t Reserved327; uint8_t Reserved328; uint8_t Reserved329; uint8_t Reserved32A; uint8_t Reserved32B; uint8_t Reserved32C; uint8_t Reserved32D; uint8_t Reserved32E; uint8_t Reserved32F; uint8_t Reserved330; uint8_t Reserved331; uint8_t Reserved332; uint8_t Reserved333; uint8_t Reserved334; uint8_t Reserved335; uint8_t Reserved336; uint8_t Reserved337; uint8_t Reserved338; uint8_t Reserved339; uint8_t Reserved33A; uint8_t Reserved33B; uint8_t Reserved33C; uint8_t Reserved33D; uint8_t Reserved33E; uint8_t Reserved33F; uint8_t Reserved340; uint8_t Reserved341; uint8_t Reserved342; uint8_t Reserved343; uint8_t Reserved344; uint8_t Reserved345; uint8_t Reserved346; uint8_t Reserved347; uint8_t Reserved348; uint8_t Reserved349; uint8_t Reserved34A; uint8_t Reserved34B; uint8_t Reserved34C; uint8_t Reserved34D; uint8_t Reserved34E; uint8_t Reserved34F; uint8_t Reserved350; uint8_t Reserved351; uint8_t Reserved352; uint8_t Reserved353; uint8_t Reserved354; uint8_t Reserved355; uint8_t Reserved356; uint8_t Reserved357; uint8_t Reserved358; uint8_t Reserved359; uint8_t Reserved35A; uint8_t Reserved35B; uint8_t Reserved35C; uint8_t Reserved35D; uint8_t Reserved35E; uint8_t Reserved35F; uint8_t Reserved360; uint8_t Reserved361; uint8_t Reserved362; uint8_t Reserved363; uint8_t Reserved364; uint8_t Reserved365; uint8_t Reserved366; uint8_t Reserved367; uint8_t Reserved368; uint8_t Reserved369; uint8_t Reserved36A; uint8_t Reserved36B; uint8_t Reserved36C; uint8_t Reserved36D; uint8_t Reserved36E; uint8_t Reserved36F; uint8_t Reserved370; uint8_t Reserved371; uint8_t Reserved372; uint8_t Reserved373; uint8_t Reserved374; uint8_t Reserved375; uint8_t Reserved376; uint8_t Reserved377; uint8_t Reserved378; uint8_t Reserved379; uint8_t Reserved37A; uint8_t Reserved37B; uint8_t Reserved37C; uint8_t Reserved37D; uint8_t Reserved37E; uint8_t Reserved37F; uint8_t Reserved380; uint8_t Reserved381; uint8_t Reserved382; uint8_t Reserved383; uint8_t Reserved384; uint8_t Reserved385; uint8_t Reserved386; uint8_t Reserved387; uint8_t Reserved388; uint8_t Reserved389; uint8_t Reserved38A; uint8_t Reserved38B; uint8_t Reserved38C; uint8_t Reserved38D; uint8_t Reserved38E; uint8_t Reserved38F; uint8_t Reserved390; uint8_t Reserved391; uint8_t Reserved392; uint8_t Reserved393; uint8_t Reserved394; uint8_t Reserved395; uint8_t Reserved396; uint8_t Reserved397; uint8_t Reserved398; uint8_t Reserved399; uint8_t Reserved39A; uint8_t Reserved39B; uint8_t Reserved39C; uint8_t Reserved39D; uint8_t Reserved39E; uint8_t Reserved39F; uint8_t Reserved3A0; uint8_t Reserved3A1; uint8_t Reserved3A2; uint8_t Reserved3A3; uint8_t Reserved3A4; uint8_t Reserved3A5; uint8_t Reserved3A6; uint8_t Reserved3A7; uint8_t Reserved3A8; uint8_t Reserved3A9; uint8_t Reserved3AA; uint8_t Reserved3AB; uint8_t Reserved3AC; uint8_t Reserved3AD; uint8_t Reserved3AE; uint8_t Reserved3AF; uint8_t Reserved3B0; uint8_t Reserved3B1; uint8_t Reserved3B2; uint8_t Reserved3B3; uint8_t Reserved3B4; uint8_t Reserved3B5; uint8_t Reserved3B6; uint8_t Reserved3B7; uint8_t Reserved3B8; uint8_t Reserved3B9; uint8_t Reserved3BA; uint8_t Reserved3BB; uint8_t Reserved3BC; uint8_t Reserved3BD; uint8_t Reserved3BE; uint8_t Reserved3BF; uint8_t Reserved3C0; uint8_t Reserved3C1; uint8_t Reserved3C2; uint8_t Reserved3C3; uint8_t Reserved3C4; uint8_t Reserved3C5; uint8_t Reserved3C6; uint8_t Reserved3C7; uint8_t Reserved3C8; uint8_t Reserved3C9; uint8_t Reserved3CA; uint8_t Reserved3CB; uint8_t Reserved3CC; uint8_t Reserved3CD; uint8_t Reserved3CE; uint8_t Reserved3CF; uint8_t Reserved3D0; uint8_t Reserved3D1; uint8_t Reserved3D2; uint8_t Reserved3D3; uint8_t Reserved3D4; uint8_t Reserved3D5; uint8_t Reserved3D6; uint8_t Reserved3D7; uint8_t Reserved3D8; uint8_t Reserved3D9; uint8_t Reserved3DA; uint8_t Reserved3DB; uint8_t Reserved3DC; uint8_t Reserved3DD; uint8_t Reserved3DE; uint8_t Reserved3DF; uint8_t Reserved3E0; uint8_t Reserved3E1; uint8_t Reserved3E2; uint8_t Reserved3E3; uint8_t Reserved3E4; uint8_t Reserved3E5; uint8_t Reserved3E6; uint8_t Reserved3E7; uint8_t Reserved3E8; uint8_t Reserved3E9; uint8_t Reserved3EA; uint8_t Reserved3EB; uint8_t Reserved3EC; uint8_t Reserved3ED; uint8_t Reserved3EE; uint8_t Reserved3EF; uint8_t Reserved3F0; uint8_t Reserved3F1; uint8_t Reserved3F2; uint8_t Reserved3F3; uint8_t Reserved3F4; uint8_t Reserved3F5; uint16_t ALT_CAS_L; uint8_t ALT_WCAS_L; uint8_t D4Misc; }; struct _PMU_SMB_LPDDR4_2D_t { uint8_t Reserved00; uint8_t MsgMisc; uint16_t PmuRevision; uint8_t Pstate; uint8_t PllBypassEn; uint16_t DRAMFreq; uint8_t DfiFreqRatio; uint8_t BPZNResVal; uint8_t PhyOdtImpedance; uint8_t PhyDrvImpedance; uint8_t PhyVref; uint8_t Lp4Misc; uint8_t Reserved0E; uint8_t CsTestFail; uint16_t SequenceCtrl; uint8_t HdtCtrl; uint8_t Reserved13; uint8_t Reserved14; uint8_t Reserved15; uint8_t DFIMRLMargin; uint8_t Reserved17; uint8_t UseBroadcastMR; uint8_t Reserved19; uint8_t Reserved1A; uint8_t CATrainOpt; uint8_t X8Mode; uint8_t RX2D_TrainOpt; uint8_t TX2D_TrainOpt; uint8_t Share2DVrefResult; uint8_t Delay_Weight2D; uint8_t Voltage_Weight2D; uint16_t PhyConfigOverride; uint8_t EnabledDQsChA; uint8_t CsPresentChA; int8_t CDD_ChA_RR_1_0; int8_t CDD_ChA_RR_0_1; int8_t CDD_ChA_RW_1_1; int8_t CDD_ChA_RW_1_0; int8_t CDD_ChA_RW_0_1; int8_t CDD_ChA_RW_0_0; int8_t CDD_ChA_WR_1_1; int8_t CDD_ChA_WR_1_0; int8_t CDD_ChA_WR_0_1; int8_t CDD_ChA_WR_0_0; int8_t CDD_ChA_WW_1_0; int8_t CDD_ChA_WW_0_1; uint8_t MR1_A0; uint8_t MR2_A0; uint8_t MR3_A0; uint8_t MR4_A0; uint8_t MR11_A0; uint8_t MR12_A0; uint8_t MR13_A0; uint8_t MR14_A0; uint8_t MR16_A0; uint8_t MR17_A0; uint8_t MR22_A0; uint8_t MR24_A0; uint8_t MR1_A1; uint8_t MR2_A1; uint8_t MR3_A1; uint8_t MR4_A1; uint8_t MR11_A1; uint8_t MR12_A1; uint8_t MR13_A1; uint8_t MR14_A1; uint8_t MR16_A1; uint8_t MR17_A1; uint8_t MR22_A1; uint8_t MR24_A1; uint8_t CATerminatingRankChA; uint8_t Reserved4B; uint8_t Reserved4C; uint8_t TrainedVREFDQ_A0; uint8_t TrainedVREFDQ_A1; uint8_t RxClkDly_Margin_A0; uint8_t VrefDac_Margin_A0; uint8_t TxDqDly_Margin_A0; uint8_t DeviceVref_Margin_A0; uint8_t RxClkDly_Margin_A1; uint8_t VrefDac_Margin_A1; uint8_t TxDqDly_Margin_A1; uint8_t DeviceVref_Margin_A1; uint8_t EnabledDQsChB; uint8_t CsPresentChB; int8_t CDD_ChB_RR_1_0; int8_t CDD_ChB_RR_0_1; int8_t CDD_ChB_RW_1_1; int8_t CDD_ChB_RW_1_0; int8_t CDD_ChB_RW_0_1; int8_t CDD_ChB_RW_0_0; int8_t CDD_ChB_WR_1_1; int8_t CDD_ChB_WR_1_0; int8_t CDD_ChB_WR_0_1; int8_t CDD_ChB_WR_0_0; int8_t CDD_ChB_WW_1_0; int8_t CDD_ChB_WW_0_1; uint8_t MR1_B0; uint8_t MR2_B0; uint8_t MR3_B0; uint8_t MR4_B0; uint8_t MR11_B0; uint8_t MR12_B0; uint8_t MR13_B0; uint8_t MR14_B0; uint8_t MR16_B0; uint8_t MR17_B0; uint8_t MR22_B0; uint8_t MR24_B0; uint8_t MR1_B1; uint8_t MR2_B1; uint8_t MR3_B1; uint8_t MR4_B1; uint8_t MR11_B1; uint8_t MR12_B1; uint8_t MR13_B1; uint8_t MR14_B1; uint8_t MR16_B1; uint8_t MR17_B1; uint8_t MR22_B1; uint8_t MR24_B1; uint8_t CATerminatingRankChB; uint8_t Reserved7E; uint8_t Reserved7F; uint8_t TrainedVREFDQ_B0; uint8_t TrainedVREFDQ_B1; uint8_t RxClkDly_Margin_B0; uint8_t VrefDac_Margin_B0; uint8_t TxDqDly_Margin_B0; uint8_t DeviceVref_Margin_B0; uint8_t RxClkDly_Margin_B1; uint8_t VrefDac_Margin_B1; uint8_t TxDqDly_Margin_B1; uint8_t DeviceVref_Margin_B1; }; struct _PMU_SMB_LPDDR3_1D_t { uint8_t Reserved00; uint8_t MsgMisc; uint16_t PmuRevision; uint8_t Pstate; uint8_t PllBypassEn; uint16_t DRAMFreq; uint8_t DfiFreqRatio; uint8_t BPZNResVal; uint8_t PhyOdtImpedance; uint8_t PhyDrvImpedance; uint8_t PhyVref; uint8_t Reserved0D; uint8_t Reserved0E; uint8_t CsTestFail; uint16_t SequenceCtrl; uint8_t HdtCtrl; uint8_t Reserved13; uint8_t DFIMRLMargin; uint8_t Reserved15; uint8_t UseBroadcastMR; uint8_t Reserved17; uint8_t LogToPhyByteMap0; uint8_t LogToPhyByteMap1; uint8_t LogToPhyByteMap2; uint8_t LogToPhyByteMap3; uint8_t LogToPhyByteMap4; uint8_t LogToPhyByteMap5; uint8_t LogToPhyByteMap6; uint8_t LogToPhyByteMap7; uint8_t LogToPhyByteMap8; uint8_t LogToPhyByteMap9; uint8_t EnabledDQsChA; uint8_t CsPresentChA; int8_t CDD_ChA_RR_1_0; int8_t CDD_ChA_RR_0_1; int8_t CDD_ChA_RW_1_1; int8_t CDD_ChA_RW_1_0; int8_t CDD_ChA_RW_0_1; int8_t CDD_ChA_RW_0_0; int8_t CDD_ChA_WR_1_1; int8_t CDD_ChA_WR_1_0; int8_t CDD_ChA_WR_0_1; int8_t CDD_ChA_WR_0_0; int8_t CDD_ChA_WW_1_0; int8_t CDD_ChA_WW_0_1; uint8_t Reserved30; uint8_t MR1_A0; uint8_t MR2_A0; uint8_t MR3_A0; uint8_t Reserved34; uint8_t MR11_A0; uint8_t MR16_A0; uint8_t MR17_A0; uint8_t Reserved38; uint8_t MR1_A1; uint8_t MR2_A1; uint8_t MR3_A1; uint8_t Reserved3C; uint8_t MR11_A1; uint8_t MR16_A1; uint8_t MR17_A1; uint8_t Reserved40; uint8_t Reserved41; uint8_t Reserved42; uint8_t Reserved43; uint8_t Reserved44; uint8_t Reserved45; uint8_t Reserved46; uint8_t Reserved47; uint8_t EnabledDQsChB; uint8_t CsPresentChB; int8_t CDD_ChB_RR_1_0; int8_t CDD_ChB_RR_0_1; int8_t CDD_ChB_RW_1_1; int8_t CDD_ChB_RW_1_0; int8_t CDD_ChB_RW_0_1; int8_t CDD_ChB_RW_0_0; int8_t CDD_ChB_WR_1_1; int8_t CDD_ChB_WR_1_0; int8_t CDD_ChB_WR_0_1; int8_t CDD_ChB_WR_0_0; int8_t CDD_ChB_WW_1_0; int8_t CDD_ChB_WW_0_1; uint8_t Reserved56; uint8_t MR1_B0; uint8_t MR2_B0; uint8_t MR3_B0; uint8_t Reserved5A; uint8_t MR11_B0; uint8_t MR16_B0; uint8_t MR17_B0; uint8_t Reserved5E; uint8_t MR1_B1; uint8_t MR2_B1; uint8_t MR3_B1; uint8_t Reserved62; uint8_t MR11_B1; uint8_t MR16_B1; uint8_t MR17_B1; uint8_t Reserved66; uint8_t Reserved67; uint8_t Reserved68; uint8_t Reserved69; uint8_t Reserved6A; uint8_t Reserved6B; uint8_t Reserved6C; uint8_t Reserved6D; uint16_t PhyConfigOverride; uint8_t Reserved70; }; struct dmem_cfg { PMU_SMB_DDR3U_1D_t ddr3u; PMU_SMB_DDR4U_1D_t ddr4u; PMU_SMB_DDR4U_2D_t ddr4u_2d; PMU_SMB_LPDDR3_1D_t lpddr3u; PMU_SMB_LPDDR4_1D_t lpddr4u; PMU_SMB_LPDDR4_2D_t lpddr4u_2d; }; typedef struct ddr_set ddr_set_t; typedef struct pll_set pll_set, *Ppll_set; struct pll_set { ushort cpu_clk; ushort pxp; uint spi_ctrl; ushort vddee; ushort vcck; uchar szPad[4]; ulong lCustomerID; ushort debug_mode; ushort rsv1; ushort rsv2; ushort rsv3; uint sys_pll_cntl[8]; uint ddr_pll_cntl[8]; uint fix_pll_cntl[8]; }; typedef struct pll_set pll_set_t; typedef struct dmem_cfg dmem_cfg_t; #define PWM_CFG3 3 #define PWM_CFG1 1 #define PWM_CFG2 2 #define BL2_INIT_STAGE_PWM_CHK_HW 130 #define BL2_INIT_STAGE_PWM_INIT 192 #define PWM_CFG0 0 #define BL2_INIT_STAGE_PWM_PRE_INIT 129 #define BL2_INIT_STAGE_PWM_CFG_GROUP 131 #define PLL_TEST_HDMI_TOTAL 4 #define PLL_TEST_SYS_TOTAL 8 typedef void _IO_lock_t; typedef struct _IO_marker _IO_marker, *P_IO_marker; typedef struct _IO_FILE _IO_FILE, *P_IO_FILE; struct _IO_FILE { int _flags; char * _IO_read_ptr; char * _IO_read_end; char * _IO_read_base; char * _IO_write_base; char * _IO_write_ptr; char * _IO_write_end; char * _IO_buf_base; char * _IO_buf_end; char * _IO_save_base; char * _IO_backup_base; char * _IO_save_end; struct _IO_marker * _markers; struct _IO_FILE * _chain; int _fileno; int _flags2; __off_t _old_offset; ushort _cur_column; char _vtable_offset; char _shortbuf[1]; _IO_lock_t * _lock; __off64_t _offset; void * __pad1; void * __pad2; void * __pad3; void * __pad4; size_t __pad5; int _mode; char _unused2[20]; }; struct _IO_marker { struct _IO_marker * _next; struct _IO_FILE * _sbuf; int _pos; }; typedef struct sd_emmc_delay sd_emmc_delay, *Psd_emmc_delay; struct sd_emmc_delay { uint32_t dat0:6; uint32_t dat1:6; uint32_t dat2:6; uint32_t dat3:6; uint32_t dat4:6; uint32_t spare:2; }; typedef struct sd_emmc_start sd_emmc_start, *Psd_emmc_start; struct sd_emmc_start { uint32_t init:1; uint32_t busy:1; uint32_t addr:30; }; typedef struct sd_emmc_delay1 sd_emmc_delay1, *Psd_emmc_delay1; struct sd_emmc_delay1 { uint32_t dat5:6; uint32_t dat6:6; uint32_t dat7:6; uint32_t dat8:6; uint32_t dat9:6; uint32_t spare:2; }; typedef struct sd_emmc_global_regs sd_emmc_global_regs, *Psd_emmc_global_regs; struct sd_emmc_global_regs { uint32_t gclock; uint32_t gdelay; uint32_t gdelay1; uint32_t gadjust; uint32_t gcalout; uint32_t reserved_14[11]; uint32_t gstart; uint32_t gcfg; uint32_t gstatus; uint32_t girq_en; uint32_t gcmd_cfg; uint32_t gcmd_arg; uint32_t gcmd_dat; uint32_t gcmd_rsp0; uint32_t gcmd_rsp1; uint32_t gcmd_rsp2; uint32_t gcmd_rsp3; uint32_t reserved_6c; uint32_t gcurr_cfg; uint32_t gcurr_arg; uint32_t gcurr_dat; uint32_t gcurr_rsp; uint32_t gnext_cfg; uint32_t gnext_arg; uint32_t gnext_dat; uint32_t gnext_rsp; uint32_t grxd; uint32_t gtxd; uint32_t reserved_98[90]; uint32_t gdesc[128]; uint32_t gping[128]; uint32_t gpong[128]; }; typedef struct _struct_16 _struct_16, *P_struct_16; struct _struct_16 { uint bw:3; uint fast:1; uint par:3; uint hcs:1; uint sd:1; uint sdhc:1; uint type:6; uint rca:16; }; typedef struct sd_emmc_status sd_emmc_status, *Psd_emmc_status; struct sd_emmc_status { uint32_t rxd_err:8; uint32_t txd_err:1; uint32_t desc_err:1; uint32_t resp_err:1; uint32_t resp_timeout:1; uint32_t desc_timeout:1; uint32_t end_of_chain:1; uint32_t desc_irq:1; uint32_t irq_sdio:1; uint32_t dat_i:8; uint32_t cmd_i:1; uint32_t ds:1; uint32_t bus_fsm:4; uint32_t desc_wr_rdy:1; uint32_t core_rdy:1; }; typedef struct sd_emmc_config sd_emmc_config, *Psd_emmc_config; struct sd_emmc_config { uint32_t bus_width:2; uint32_t ddr:1; uint32_t dc_ugt:1; uint32_t bl_len:4; uint32_t resp_timeout:4; uint32_t rc_cc:4; uint32_t out_fall:1; uint32_t blk_gap_ip:1; uint32_t spare:1; uint32_t ignore_owner:1; uint32_t chk_ds:1; uint32_t cmd_low:1; uint32_t stop_clk:1; uint32_t auto_clk:1; uint32_t txd_add_err:1; uint32_t txd_retry:1; uint32_t revd:8; }; typedef struct sd_emmc_irq_en sd_emmc_irq_en, *Psd_emmc_irq_en; struct sd_emmc_irq_en { uint32_t rxd_err:8; uint32_t txd_err:1; uint32_t desc_err:1; uint32_t resp_err:1; uint32_t resp_timeout:1; uint32_t desc_timeout:1; uint32_t end_of_chain:1; uint32_t desc_irq:1; uint32_t irq_sdio:1; uint32_t revd:16; }; typedef struct sd_emmc_clock sd_emmc_clock, *Psd_emmc_clock; struct sd_emmc_clock { uint32_t div:6; uint32_t src:2; uint32_t core_phase:2; uint32_t tx_phase:2; uint32_t rx_phase:2; uint32_t reserved14:2; uint32_t tx_delay:6; uint32_t rx_delay:6; uint32_t always_on:1; uint32_t irq_sdio_sleep:1; uint32_t irq_sdio_sleep_ds:1; uint32_t reserved26:1; }; typedef struct sd_emmc_adjust sd_emmc_adjust, *Psd_emmc_adjust; struct sd_emmc_adjust { uint32_t cmd_delay:4; uint32_t ds_delay:4; uint32_t cali_sel:4; uint32_t cali_enable:1; uint32_t adj_enable:1; uint32_t cali_rise:1; uint32_t ds_enable:1; uint32_t adj_delay:6; uint32_t adj_auto:1; uint32_t reserved23:9; }; typedef struct sd_emmc_card_info sd_emmc_card_info, *Psd_emmc_card_info; struct sd_emmc_card_info { uint32_t txd_cnt:10; uint32_t txd_blk:9; uint32_t revd:30; }; typedef struct cmd_cfg cmd_cfg, *Pcmd_cfg; struct cmd_cfg { uint32_t length:9; uint32_t block_mode:1; uint32_t r1b:1; uint32_t end_of_chain:1; uint32_t timeout:4; uint32_t no_resp:1; uint32_t no_cmd:1; uint32_t data_io:1; uint32_t data_wr:1; uint32_t resp_nocrc:1; uint32_t resp_128:1; uint32_t resp_num:1; uint32_t data_num:1; uint32_t cmd_index:6; uint32_t error:1; uint32_t owner:1; }; typedef struct sd_emmc_calout sd_emmc_calout, *Psd_emmc_calout; struct sd_emmc_calout { uint32_t cali_idx:6; uint32_t reserved6:1; uint32_t cali_vld:1; uint32_t cali_setup:8; uint32_t reserved16:16; }; typedef union sd_emmc_setup sd_emmc_setup, *Psd_emmc_setup; union sd_emmc_setup { uint32_t d32; struct _struct_16 b; }; typedef struct sd_emmc_data_info sd_emmc_data_info, *Psd_emmc_data_info; struct sd_emmc_data_info { uint32_t cnt:10; uint32_t blk:9; uint32_t revd:30; }; typedef struct sd_emmc_desc_info sd_emmc_desc_info, *Psd_emmc_desc_info; struct sd_emmc_desc_info { uint32_t cmd_info; uint32_t cmd_arg; uint32_t data_addr; uint32_t resp_addr; }; #define SD_EMMC_RESP_TIMEOUT_ERROR 16 #define Cfg_src 6 #define SD_EMMC_RXD_ERROR 1 #define SD_EMMC_RESP_CRC_ERROR 8 #define Cfg_sram_pd 14 #define Cfg_tx_phase 10 #define Cfg_rx_phase 12 #define SDIO_PORT_A 0 #define SD_EMMC_DESC_TIMEOUT_ERROR 32 #define Cfg_irq_sdio_sleep 29 #define SD_EMMC_DESC_ERROR 4 #define Cfg_always_on 28 #define SDIO_PORT_B 1 #define SDIO_PORT_C 2 #define Cfg_tx_delay 16 #define SD_EMMC_TXD_ERROR 2 #define Cfg_co_phase 8 #define SD_EMMC_BASE_C 4292898816 #define Cfg_irq_sdio_sleep_ds 30 #define Cfg_rx_delay 22 #define Cfg_div 0 #define SD_EMMC_BASE_A 4292882432 #define SD_EMMC_BASE_B 4292890624 #define MAX_BLOCK_COUNTS 256 #define CARD_SD_SDIO_PWR_OFF 16 #define SD_EMMC_CLKSRC_24M 24000000 #define SD_EMMC_CLKSRC_DIV2 1000000000 #define NEWSD_IRQ_ALL 16383 #define NEWSD_BOUNCE_REQ_SIZE 524288 #define CARD_SD_SDIO_PWR_PREPARE 4 #define NEWSD_MAX_DESC_MUN 512 #define CARD_SD_SDIO_INIT 1 #define RESPONSE_R2_CID_CSD_LENGTH 17 #define MMC_ADJ_FIXED 1 #define MAX_RESPONSE_BYTES 4 #define RESPONSE_R1_R3_R6_R7_LENGTH 6 #define CARD_SD_SDIO_PWR_ON 8 #define SD_EMMC_CLKSRC 24000000 #define RESPONSE_R4_R5_NONE_LENGTH 0 #define CARD_SD_SDIO_DETECT 2 #define MMC_RSP_136_NUM 4 typedef struct i2c_msg i2c_msg, *Pi2c_msg; struct i2c_msg { }; #define MESON_I2C_SLAVE_JTAG_TDO_BIT 2097152 #define MESON_I2C_MASTER_A_GPIOZ_18_REG 4284696292 #define I2C_M_REV_DIR_ADDR 8192 #define MESON_I2C_MASTER_A_GPIOZ_17_BIT 128 #define MESON_I2C_MASTER_C_END 4291940383 #define MESON_I2C_MASTER_C_GPIOX_1_BIT 8388608 #define MESON_I2C_MASTER_B_GPIOY_13_BIT 32768 #define MESON_I2C_SLAVE_GPIOC_17_BIT 67108864 #define MESON_I2C_MASTER_C_START 4291940352 #define MESON_I2C_SLAVE_JTAG_TMS_BIT 8192 #define MESON_I2C_MASTER_AO_GPIOAO_4_BIT 256 #define MESON_I2C_MASTER_A_END 4291948575 #define MESON_I2C_SLAVE_GPIOC_16_REG 21430606672 #define MESON_I2C_MASTER_AO_GPIOAO_5_REG 4286578708 #define AML_I2C_SPPED_400K 400000 #define MESON_I2C_MASTER_A_GPIOW_0_REG 4284696276 #define I2C_M_IGNORE_NAK 4096 #define MESON_I2C_MASTER_D_GPIOH_6_REG 4284696284 #define I2C_M_NO_RD_ACK 2048 #define MESON_I2C_SLAVE_GPIOC_22_REG 21430606704 #define AML_I2C_SPPED_100K 100000 #define MESON_I2C_MASTER_A_GPIOW_1_BIT 8388608 #define MESON_I2C_SLAVE_GPIOC_21_BIT 1024 #define MESON_I2C_SLAVE_GPIOB_1_BIT 8 #define MESON_I2C_SLAVE_GPIOC_13_REG 21430606640 #define MESON_I2C_SLAVE_JTAG_TDI_BIT 8192 #define MESON_I2C_SLAVE_GPIOC_14_BIT 67108864 #define MESON_I2C_SLAVE_GPIOB_2_REG 21430606624 #define MESON_I2C_MASTER_D_GPIOH_5_BIT 8388608 #define MESON_I2C_SLAVE_JTAG_TCK_REG 21430606608 #define MESON_I2C_MASTER_C_GPIOY_7_BIT 268435456 #define MESON_I2C_MASTER_B_GPIOH_4_REG 4284696284 #define MESON_I2C_MASTER_C_GPIOY_8_REG 4284696272 #define MESON_I2C_MASTER_C_GPIOX_1_REG 4284696260 #define MESON_I2C_MASTER_D_GPIOY_11_BIT 2048 #define AML_I2C_MASTER_B 2 #define MESON_I2C_MASTER_A_START 4291948544 #define MESON_I2C_SLAVE_GPIOB_3_BIT 1024 #define AML_I2C_MASTER_A 1 #define AML_I2C_MASTER_D 4 #define AML_I2C_MASTER_C 3 #define MESON_I2C_SLAVE_GPIOB_0_REG 21430606624 #define MESON_I2C_MASTER_B_GPIOH_3_BIT 64 #define MESON_I2C_MASTER_A_GPIOZ_18_BIT 256 #define AML_I2C_SPPED_300K 300000 #define MESON_I2C_SLAVE_JTAG_TMS_REG 21430606608 #define MESON_I2C_SLAVE_JTAG_TDO_REG 21430606608 #define MESON_I2C_MASTER_D_END 4291936287 #define MESON_I2C_MASTER_AO_GPIOAO_4_REG 4286578708 #define MESON_I2C_SLAVE_GPIOC_17_REG 21430606672 #define MESON_I2C_MASTER_A_GPIOZ_17_REG 4284696292 #define MESON_I2C_MASTER_AO_GPIOAO_5_BIT 512 #define MESON_I2C_MASTER_C_GPIOX_0_BIT 4194304 #define MESON_I2C_SLAVE_GPIOC_16_BIT 268435456 #define AML_I2C_SLAVE_ADDR 108 #define MESON_I2C_MASTER_B_END 4291944479 #define MESON_I2C_MASTER_B_START 4291944448 #define I2C_M_RECV_LEN 1024 #define MESON_I2C_MASTER_A_GPIOW_1_REG 4284696276 #define MESON_I2C_MASTER_D_GPIOH_6_BIT 16777216 #define I2C_M_NOSTART 16384 #define MESON_I2C_SLAVE_GPIOC_13_BIT 536870912 #define AML_I2C_MASTER_AO 0 #define MESON_I2C_MASTER_D_GPIOH_5_REG 4284696284 #define MESON_I2C_SLAVE_GPIOC_14_REG 21430606640 #define MESON_I2C_SLAVE_GPIOB_3_REG 21430606624 #define MESON_I2C_SLAVE_GPIOB_0_BIT 64 #define MESON_I2C_MASTER_D_GPIOY_10_BIT 1024 #define MESON_I2C_MASTER_C_GPIOX_0_REG 4284696260 #define MESON_I2C_MASTER_C_GPIOY_7_REG 4284696272 #define MESON_I2C_MASTER_A_GPIOW_0_BIT 4194304 #define MESON_I2C_MASTER_B_GPIOH_4_BIT 128 #define MESON_I2C_SLAVE_GPIOC_22_BIT 128 #define MESON_I2C_SLAVE_GPIOC_21_REG 21430606704 #define MESON_I2C_SLAVE_JTAG_TDI_REG 21430606608 #define MESON_I2C_SLAVE_JTAG_TCK_BIT 131072 #define I2C_M_TEN 16 #define AML_I2C_SPPED_200K 200000 #define I2C_M_RD 1 #define AML_I2C_SPPED_50K 50000 #define MESON_I2C_MASTER_AO_START 4286599168 #define MESON_I2C_MASTER_C_GPIOY_8_BIT 536870912 #define MESON_I2C_MASTER_B_GPIOY_12_BIT 16384 #define MESON_I2C_MASTER_B_GPIOH_3_REG 4284696284 #define MESON_I2C_SLAVE_GPIOB_2_BIT 16384 #define MESON_I2C_MASTER_D_START 4291936256 #define MESON_I2C_SLAVE_GPIOB_1_REG 21430606624 typedef struct acs_setting acs_setting, *Pacs_setting; typedef struct acs_setting acs_set_t; struct acs_setting { char acs_magic[5]; uchar chip_type; ushort version; ulong acs_set_length; char ddr_magic[5]; uchar ddr_set_version; ushort ddr_set_length; ulong ddr_set_addr; char ddr_reg_magic[5]; uchar ddr_reg_version; ushort ddr_reg_length; ulong ddr_reg_addr; char pll_magic[5]; uchar pll_set_version; ushort pll_set_length; ulong pll_set_addr; char sto_magic[5]; uchar sto_set_version; ushort sto_set_length; ulong sto_set_addr; char bl2_regs_magic[5]; uchar bl2_regs_version; ushort bl2_regs_length; ulong bl2_regs_addr; char rsv_magic[5]; uchar rsv_set_version; ushort rsv_set_length; ulong rsv_set_addr; }; #define RESET5_LEVEL 1061 #define P_SANA_STREAM_CONTROL 4291870848 #define AFBC_SIZE_OUT 6888 #define VIU_OSD1_BLK2_CFG_W3 6694 #define VIU_OSD1_BLK2_CFG_W4 6677 #define P_HEVC_PARSER_LCU_START 4284662928 #define VIU_OSD1_BLK2_CFG_W1 6692 #define VIU_OSD1_BLK2_CFG_W2 6693 #define HEVC_CM_HEADER_LENGTH 13865 #define VIU_OSD1_BLK2_CFG_W0 6691 #define P_VDEC2_SLICE_START_BYTE_23 4284657716 #define P_HEVC_PSCALE_DUMMY 4284671072 #define ENCP_VIDEO_EQPULS_BLINE 7073 #define P_VD2_IF0_GEN_REG2 4287654452 #define P_VD2_IF0_GEN_REG3 4287654560 #define HEVCD_IPP_TOP_LCUCONFIG 13318 #define P_ENCP_INFO_READ 4287667316 #define VPP_VD1_CLIP_MISC0 7649 #define DOLBY_CORE2A_DMA_CTRL 13369 #define VPP_VD1_CLIP_MISC1 7650 #define P_ENCP_MACV_PSSYNC_STRT 4287655692 #define VDIN1_BLKBAR_CTRL0 5216 #define HCODEC_BLOCK_NUM 7210 #define P_HCODEC_DECODER_BUFFER_INFO 4284641340 #define VPU_PROT3_RBUF_ROOM 10104 #define VDIN1_BLKBAR_CTRL1 5215 #define P_VDEC2_IQIDCT_CONTROL 4284659768 #define L_VSYNC_HE_ADDR 5210 #define SHARP_DB_FLT_CTRL 12919 #define CINDEX1_REG 811 #define P_VDEC2_SLICE_START_BYTE_01 4284657712 #define P_HCODEC_VLC_IPRED_MODE_LO 4284642544 #define HEVC_PSCALE_FILT0_COEF1 14618 #define P_STV2_VE_ADDR 4287648440 #define HEVC_PSCALE_FILT0_COEF0 14617 #define AUDIN_FIFO0_UG 15 #define DBLK_Y_HFILT 2396 #define P_HCODEC_VLD_STATUS 4284641512 #define REG_CM2_ENH_COEFF4_H00 260 #define REG_CM2_ENH_COEFF4_H01 268 #define REG_CM2_ENH_COEFF4_H02 276 #define HEVC_MPRED_L1_REF09_POC 12857 #define REG_CM2_ENH_COEFF4_H03 284 #define REG_CM2_ENH_COEFF4_H04 292 #define MIPI_DSI_DWC_CLKMGR_CFG_OS 7170 #define REG_CM2_ENH_COEFF4_H05 300 #define REG_CM2_ENH_COEFF4_H06 308 #define REG_CM2_ENH_COEFF4_H07 316 #define REG_CM2_ENH_COEFF4_H08 324 #define REG_CM2_ENH_COEFF4_H09 332 #define P_VD2_IF0_URGENT_CTRL 4287654460 #define OSDSR_RKE_EXTWIN 12602 #define OEV3_HE_ADDR 5304 #define P_DI_INP_GEN_REG 4287651640 #define REG_CM2_ENH_COEFF4_H10 340 #define REG_CM2_ENH_COEFF4_H11 348 #define REG_CM2_ENH_COEFF4_H12 356 #define REG_CM2_ENH_COEFF4_H13 364 #define P_DOS_VDIN_FCNT 4284677168 #define P_DNR_DM_VAR_THD 4287673756 #define ENCT_SYNC_PIXEL_EN 7241 #define AUDIN_FIFO0_LOAD 2 #define HCODEC_IGNORE_CONFIG 7938 #define QDCT_TOP_MEM_CTL 7969 #define P_STREAM_BUS_CONFIG 4291866640 #define P_VDEC2_HDEC_MC_OMEM_AUTO 4284654784 #define MCDI_RO_FLD_MTN_CNT 12198 #define P_HCODEC_IE_MB_POSITION 4284644612 #define ENCI_VIDEO_BRIGHT 6915 #define ENCI_VBI_TTX_HTIME 6954 #define DBLK_Y_BVFILT 2393 #define P_VDEC2_CDB_CTRL 4284648692 #define P_VENC_VDAC_DAC3_GAINCTRL 4287655896 #define P_HCODEC_VLC_IPRED_MODE_HI 4284642540 #define P_AIU_AIFIFO_CTRL 4291842560 #define P_HEVC_LMEM_DMA_CTRL 4284665152 #define MCDI_HIGH_VERT_FRQ_DIF_THD 12111 #define P_HCODEC_VLC_VB_END_PTR 4284642372 #define HEVC_VLD_MEM_VIFIFO_CONTROL 15428 #define VDEC2_DBLK_Y_BHFILT_HIGH 10584 #define ENCL_VFIFO2VD_CTL 7312 #define V3_TOP_INTRA_INFO 8054 #define P_DI_IF2_RANGE_MAP_CR 4287660148 #define P_HEVC_MDEC_PIC_DC_STATUS 4284671548 #define P_PARSER_VIDEO_HOLE 4291879440 #define MLVDS_CONFIG_HI 5319 #define P_HEVC_SHIFT_BYTE_COUNT 4284662836 #define HCODEC_PSCALE_STATUS 6430 #define SPI_FLASH_SE 24 #define P_DBLK_Y_BVFILT 4284622180 #define QDCT_MB_LEVEL 7956 #define P_ENCI_VIDEO_CONT 4287654928 #define P_DI_IF2_RANGE_MAP_CB 4287660144 #define P_HEVC_MBREAK1_REG 4284664916 #define P_MCW_DBLK_WRRSP_CNT 4284622572 #define VPP2_PIC_IN_HEIGHT 6402 #define HCODEC_DBLK_RV8_QUANT 6518 #define P_VENC_VDAC_DAC4_FILT_CTRL0 4287656272 #define P_I2C_M_3_TOKEN_LIST1 4291936268 #define P_I2C_M_3_TOKEN_LIST0 4291936264 #define P_VENC_VDAC_DAC4_FILT_CTRL1 4287656276 #define MLVDS_CONFIG_LO 5320 #define SPI_FLASH_PP 25 #define P_UART2_MISC 4291960848 #define VLD_MEM_VIFIFO_LEVEL 3143 #define VKS_OUT_WIN_SIZE 12545 #define GE2D_VSC_INI_CTRL 187 #define VDIN1_MATRIX_PRE_OFFSET0_1 5144 #define P_VIU_SW_RESET 4287653892 #define D2D3_DWMIF_VPOS 11046 #define AFBC_MIF_HOR_SCOPE 6893 #define P_I2C_M_3_SLAVE_ADDR 4291936260 #define P_L_OEV2_HE_ADDR 4287647952 #define P_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 4287653512 #define P_DI_MEM_GEN_REG2 4287651400 #define P_HEVC_SHIFT_STARTCODE 4284662820 #define P_DI_MEM_GEN_REG3 4287660708 #define VDIN_MATRIX_COEF00_01 4625 #define VDEC2_MC_MBBOT_ST_ODD_ADDR 10565 #define P_L_INV_CNT_ADDR 4287648000 #define VDIN0_LCNT_STATUS 4612 #define P_HEVC_ASSIST_MBOX1_IRQ_REG 4284662224 #define DOS_VDIN_FCNT 16140 #define P_VPU_DI_MTNWR_MMC_CTRL 4287667240 #define VDEC2_VLD_TIME_STAMP_LENGTH 11344 #define HEVC_MPRED_L0_REF11_POC 12843 #define P_HEVC_HDEC_MC_MBRIGHT_IDX 4284671172 #define P_XVYCC_POST_RGB_DLUT_0_3 4287677916 #define P_ENCP_VIDEO_VSPULS_END 4287655536 #define ANC19_CANVAS_ADDR 2467 #define PSCALE_SRCKEY_CTRL1 2347 #define PSCALE_SRCKEY_CTRL0 2346 #define P_VENC_VDAC_SETTING 4287655416 #define P_VPP_MATRIX_OFFSET0_1 4287657364 #define HEVC_ASSIST_MBOX1_CLR_REG 12405 #define VPP2_MATRIX_COEF22 6500 #define P_HEVC_MPRED_TILE_SIZE_LCU 4284663840 #define VIUB_GCLK_CTRL0 8199 #define CIPLUS_KEY2 6394 #define VIUB_GCLK_CTRL1 8200 #define CIPLUS_KEY3 6395 #define VIUB_GCLK_CTRL2 8201 #define CIPLUS_KEY0 6392 #define VIUB_GCLK_CTRL3 8202 #define CIPLUS_KEY1 6393 #define VPU_VLOCK_OUTPUT0_PLL_LMT 12298 #define P_AIU_958_PAUSE_NUM 4291842192 #define VPP_PREBLEND_VD1_H_START_END 7450 #define P_ENCL_VIDEO_YFP1_HTIME 4287656628 #define P_HCODEC_CINDEX5_REG 4284632252 #define P_HCODEC_VLD_MEM_VIFIFO_START_PTR 4284641536 #define VDEC_ASSIST_MBOX2_CLR_REG 121 #define P_VPU_VENCL_DITH_EN 4287667492 #define P_MCDI_LMV_GAINTHD 4287675444 #define DOLBY_TV_ADAPTIVE_SCALE_LUTADDR 13282 #define P_ENCP_VIDEO_EQPULS_END 4287655552 #define SHARP_SATPRT_DIVM 12917 #define P_DI_IF2_CHROMA0_RPT_PAT 4287660128 #define NR4_MCNR_MV_CTRL_REG 11710 #define HEVC_VIFF_BIT_CNT 15386 #define DNR_DM_CTRL 11616 #define NR4_TOP_CTRL 11775 #define COMM_DESC_KEY_RW 6391 #define P_HCODEC_MDB_ADDR_REG 4284632172 #define VDEC2_DBLK_Y_VFILT 10590 #define ENCI_DVI_VSO_BLINE_ODD 7171 #define SPI_FLASH_DP 21 #define VDEC2_IMEM_DMA_CTRL 9024 #define ENCP_VIDEO_YFP2_HTIME 7061 #define ENCI_DVI_HSO_BEGIN 7168 #define VIU2_OSD1_BLK1_CFG_W4 7781 #define P_HCODEC_MDEC_EXTIF_STS0 4284639128 #define VIU2_OSD1_BLK1_CFG_W0 7711 #define I2C_M_3_CONTROL_REG 28672 #define VIU2_OSD1_BLK1_CFG_W1 7712 #define VIU2_OSD1_BLK1_CFG_W2 7713 #define VIU2_OSD1_BLK1_CFG_W3 7714 #define SPI_FLASH_CE 22 #define P_ATOM_LOCK 4291870908 #define SPI_FLASH_C5 20501 #define SPI_FLASH_C6 20502 #define SPI_FLASH_C7 20503 #define P_MCDI_REF_ERR_FRQ_CHK 4287675508 #define SPI_FLASH_C0 20496 #define SPI_FLASH_C1 20497 #define SPI_FLASH_C2 20498 #define SPI_FLASH_C3 20499 #define VPP_VADJ1_BLACK_VAL 7575 #define SPI_FLASH_C4 20500 #define SPI_FLASH_BE 23 #define P_HCODEC_QDCT_MB_MAGIC_WORD 4284644448 #define P_RESET6_REGISTER 4291825692 #define SPI_FLASH_B8 20504 #define SPI_FLASH_B9 20505 #define P_HEVC_DBLK_CB_BFILT 4284671336 #define P_VPU_VLOCK_LOOP1_IMISSYNC_MAX 4287676436 #define P_VPU_VLOCK_STBDET_ABS_WIN1 4287676520 #define MCDI_REF_BADW_THD_GAIN 12056 #define P_VPU_VLOCK_STBDET_ABS_WIN0 4287676516 #define MCDI_BLKTOTAL 12034 #define ANC5_CANVAS_ADDR 2453 #define ENCL_TST_CLRBAR_STRT 7325 #define DOS_SECURE_CTL_INDEX 16256 #define P_HCODEC_DBKR_CANVAS_ADDR 4284638912 #define SHARP_SR2_MISC 12896 #define HCODEC_QDCT_JPEG_DCT_STATUS1 7980 #define VPP2_MATRIX_COEF00_01 6496 #define P_HCODEC_MFDIN_REG4_LNR0 4284629040 #define HCODEC_QDCT_JPEG_DCT_STATUS0 7979 #define mLVDS_double_pattern 14 #define P_AFBC_SIZE_OUT 4287654816 #define P_AIU_CLK_CTRL 4291842136 #define SRSHARP1_HCTI_BST_GAIN 13359 #define P_HEVC_CBREAK3_REG 4284665052 #define HEVC_VLD_DBG_DATA 15423 #define P_HLTI_FLT_CLP_DC 4287678672 #define P_DNR_RO_GBS_STAT_DIF 4287673452 #define ENCI_SYNC_MODE 6920 #define SRSHARP0_PK_OS_ADPT_MISC 12837 #define P_VDEC2_MC_MBBOT_ST_EVEN_ADDR 4284654864 #define SRSHARP1_DB_FLT_YC_THRD 13432 #define HCODEC_ME_SUB_FIX_MIN_SAD 8029 #define VPP_WRAP_OSD3_MATRIX_COEF11_12 15794 #define P_AIU_I2S_SYNC 4291842116 #define P_UART0_RFIFO 4291969028 #define VDEC2_FST_FOR_MV_Y 11281 #define VDEC2_FST_FOR_MV_X 11280 #define P_L_CPV2_VS_ADDR 4287647892 #define MDEC_PIC_DC_STATUS 2447 #define P_VPP_DUMMY_DATA1 4287657380 #define HCODEC_ANC5_CANVAS_ADDR 6549 #define HEVC_DBLK_OST_YBASE 14717 #define HEVC_MPRED_L1_REF10_POC 12858 #define HEVC_CSP 13088 #define VPP2_HSC_START_PHASE_STEP 6419 #define P_AUDIN_FIFO2_WRAP 4291875136 #define P_ANC17_CANVAS_ADDR 4284622468 #define LVDS_PHY_CNTL1 5346 #define P_AIU_MEM_AIFIFO2_BUF_CNTL 4291842504 #define LVDS_PHY_CNTL2 5347 #define LVDS_PHY_CNTL0 5345 #define LVDS_PHY_CNTL7 5362 #define LVDS_PHY_CNTL8 5363 #define LVDS_PHY_CNTL5 5350 #define LVDS_PHY_CNTL6 5361 #define LVDS_PHY_CNTL3 5348 #define LVDS_PHY_CNTL4 5349 #define P_VP9_QUANT_WR 4284663064 #define P_VI_HIST_SPL_VAL 4287674384 #define P_VPU_VLOCK_LOOP1_IMISSYNC_MIN 4287676440 #define HCODEC_CBREAK2_REG 4918 #define DOLBY_INT_STAT 6661 #define VDEC2_DCAC_DMA_CTRL 11794 #define VDIN0_MATRIX_COEF20_21 4628 #define P_IMEM_DMA_COUNT 4284615944 #define HEVCD_IPP_TOP_STATUS 13313 #define P_VDEC2_VLD_MEM_VBUF_RD_PTR 4284657996 #define NR2_MATNR_MTN_CRTL2 5995 #define P_VD1_IF0_CANVAS1 4287654216 #define PK_CON_2CIRHPGAIN_LIMIT 12806 #define P_VD1_IF0_CANVAS0 4287654212 #define RDMA_AHB_END_ADDR_4 4361 #define RDMA_AHB_END_ADDR_3 4359 #define RDMA_AHB_END_ADDR_2 4357 #define P_VDEC_ASSIST_MBOX2_IRQ_REG 4284613088 #define RDMA_AHB_END_ADDR_1 4355 #define RDMA_AHB_END_ADDR_7 4367 #define RDMA_AHB_END_ADDR_6 4365 #define RDMA_AHB_END_ADDR_5 4363 #define P_DOLBY_TV_AXI2DMA_CTRL1 4287680492 #define P_DOLBY_TV_AXI2DMA_CTRL2 4287680496 #define P_DOLBY_TV_AXI2DMA_CTRL3 4287680500 #define VCOM_VS_ADDR 5277 #define P_DOLBY_TV_AXI2DMA_CTRL0 4287680488 #define P_ANC28_CANVAS_ADDR 4284622512 #define HEVC_STREAM_PACKET_LENGTH 12601 #define VPP_MATRIX_COEF02_10 7521 #define LCD_PWM1_LO_ADDR 5310 #define P_AIFIFO2_TIME_STAMP_CNTL 4291842656 #define P_SPICC0_STATREG 4291899412 #define SRSHARP0_PK_OS_HORZ_CORE_GAIN 12835 #define PWM_TIME_AB 27652 #define CPV1_SEL 6 #define I2SIN_EN 15 #define P_CIPLUS_KEY_WR 4291847152 #define AUDOUT_BUF1_WPTR 13447 #define DNLP_09 12879 #define DNLP_07 12877 #define DNLP_08 12878 #define DNLP_05 12875 #define DNLP_06 12876 #define DNLP_03 12873 #define DNLP_04 12874 #define DNLP_01 12871 #define AUDIN_FIFO0_CTRL 13349 #define DNLP_02 12872 #define DNLP_00 12870 #define ENCL_VIDEO_VSO_BLINE 7353 #define PWM_TIME_CD 26628 #define MIPI_DSI_DWC_VID_HLINE_TIME_OS 7188 #define HCODEC_ANC12_CANVAS_ADDR 6556 #define DNLP_14 12884 #define DNLP_15 12885 #define DNLP_12 12882 #define DNLP_13 12883 #define DNLP_10 12880 #define DNLP_11 12881 #define LCD_MCU_CTL 5341 #define AUDIN_FIFO1_HOLD0_SEL 22 #define ENCI_CFILT7 6997 #define VPP_WRAP_OSD3_MATRIX_COEF23_24 15798 #define LDIM_STTS_MATRIX_COEF00_01 6851 #define P_VPP2_VSC_START_PHASE_STEP 4287652896 #define P_VPU_HDMI_DATA_OVR 4287667356 #define PWM_TIME_EF 25604 #define P_QDCT_JPEG_DCT_COEFF23 4284644536 #define VIU2_OSD2_CTRL_STAT 7728 #define P_VIU_OSD1_TCOLOR_AG1 4287653984 #define ADV_MV_CTL0 8041 #define P_VIU_OSD1_TCOLOR_AG0 4287653980 #define P_VIU_OSD1_TCOLOR_AG3 4287653992 #define P_M4_TABLE_SELECT 4284625056 #define P_VIU_OSD1_TCOLOR_AG2 4287653988 #define ADV_MV_CTL2 8043 #define ADV_MV_CTL1 8042 #define DOLBY_TV_AXI2DMA_CTRL0 13306 #define DOLBY_TV_AXI2DMA_CTRL1 13307 #define DOLBY_TV_AXI2DMA_CTRL2 13308 #define DOLBY_TV_AXI2DMA_CTRL3 13309 #define P_HENC_SCRATCH_I 4284640072 #define P_HENC_SCRATCH_J 4284640076 #define P_ENCP_VIDEO_VAVON_BLINE 4287655576 #define P_HENC_SCRATCH_G 4284640064 #define P_HENC_SCRATCH_H 4284640068 #define P_HENC_SCRATCH_M 4284640088 #define P_HENC_SCRATCH_N 4284640092 #define P_HENC_SCRATCH_K 4284640080 #define P_HENC_SCRATCH_L 4284640084 #define P_HENC_SCRATCH_A 4284640040 #define P_HENC_SCRATCH_B 4284640044 #define P_HENC_SCRATCH_E 4284640056 #define P_HENC_SCRATCH_F 4284640060 #define SPICC0_DMAREG 19460 #define P_HENC_SCRATCH_C 4284640048 #define P_HENC_SCRATCH_D 4284640052 #define P_HENC_SCRATCH_9 4284640036 #define P_HENC_SCRATCH_7 4284640028 #define P_HENC_SCRATCH_8 4284640032 #define P_QDCT_JPEG_DCT_COEFF01 4284644532 #define P_HENC_SCRATCH_1 4284640004 #define P_HENC_SCRATCH_2 4284640008 #define P_HENC_SCRATCH_0 4284640000 #define P_HENC_SCRATCH_5 4284640020 #define P_HENC_SCRATCH_6 4284640024 #define P_HENC_SCRATCH_3 4284640012 #define P_HENC_SCRATCH_4 4284640016 #define AUDIN_FIFO1_PTR 13365 #define HCODEC_ANC23_CANVAS_ADDR 6567 #define P_ENCP_VIDEO_RGBIN_CTRL 4287655668 #define SRSHARP0_SHARP_SR2_CBIC_VCOEF1 12895 #define HEVC_MPSR 13057 #define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 12894 #define P_HCODEC_MINDEX3_REG 4284632116 #define P_VPP2_VSC_PHASE_CTRL 4287652916 #define P_ENCP_DVI_VSO_BLINE_ODD 4287656140 #define HEVC_DCAC_MB_COUNT 15894 #define HEVCD_IPP_SWMPREDIF_STATUS 13329 #define VPP_LINE_IN_LENGTH 7425 #define D2D3_CBDG_STATUS_2 11068 #define P_HCODEC_QDCT_MB_LEVEL 4284644432 #define D2D3_CBDG_STATUS_1 11056 #define P_RDMA_ACCESS_AUTO4 4287644768 #define P_RDMA_ACCESS_AUTO2 4287644740 #define P_RDMA_ACCESS_AUTO3 4287644744 #define HCODEC_DBLK_Y_BVFILT 6489 #define P_HEVC_IQIT_SCALELUT_IDX_4 4284668948 #define L_GAMMA_ADDR_PORT 5122 #define P_HCODEC_MFDIN_REG9_ENDN 4284629060 #define HEVC_ANC16_CANVAS_ADDR 14752 #define ENCP_VIDEO_PB_OFFST 7049 #define HCODEC_V3_SKIP_CONTROL 8044 #define ENCI_DE_H_END 6935 #define HEVC_ANC27_CANVAS_ADDR 14763 #define P_DE_HS_ADDR 4287648580 #define HEVC_IQIT_SCALELUT_IDX_4 14085 #define GE2D_DP_ONOFF_CTRL 211 #define P_VPP2_MATRIX_OFFSET2 4287653272 #define P_MCDI_BLKTOTAL 4287675400 #define SHARP_SATPRT_LMT_RGB 12918 #define LCD_PWM0_HI_ADDR 5309 #define HEVC_IQIT_SCALELUT_IDX_8 14086 #define IE_C_PRED_MODE 8007 #define P_SPICC0_ENHANCE_CNTL 4291899448 #define SMARTCARD_REG8 37896 #define P_VDEC2_IQIDCT_DEBUG_INFO_0 4284659772 #define SMARTCARD_REG6 37894 #define SMARTCARD_REG5 37893 #define SMARTCARD_REG2 37890 #define SMARTCARD_REG0 37888 #define SMARTCARD_REG1 37889 #define P_XVYCC_INV_LUT_U_DATA_PORT 4287677804 #define P_NR4_ALP0Y_ERR2CURV_LIMIT1 4287674040 #define P_NR4_ALP0Y_ERR2CURV_LIMIT0 4287674036 #define ENCT_VIDEO_HAVON_END 7281 #define VDEC2_MINDEX5_REG 8975 #define P_PSCALE_PICO_SHIFT_XY 4284621984 #define HEVC_ASSIST_AFIFO_CTRL 12289 #define P_DOLBY_TV_ADAPTIVE_SCALE_REGADDR 4287680384 #define P_VPU_HDMI_DITH_10_37 4287668188 #define P_VPP_PEAKING_DNLP 4287657696 #define HCODEC_QDCT_TOP_MEM_CTL 7969 #define P_HDEC_MC_OMEM_AUTO 4284622016 #define P_VLC_COEFF_RD_REQ 4284642564 #define P_HEVC_MC_STATUS0 4284671012 #define P_PSCALE_CANVAS_WR_ADDR 4284622004 #define P_I2C_M_3_RDATA_REG0 4291936280 #define P_I2C_M_3_RDATA_REG1 4291936284 #define P_HEVC_MC_STATUS1 4284671016 #define VPP_POSTBLEND_H_SIZE 7457 #define P_ENCI_DVI_VSO_BEGIN_EVN 4287655960 #define P_SHARP_DB_FLT_YC_THRD 4287678944 #define P_HCODEC_VLD_MEM_VIFIFO_END_PTR 4284641544 #define P_VPU_HDMI_DITH_10_26 4287668184 #define P_VIU_OSD1_MATRIX_PRE_OFFSET0_1 4287654496 #define P_QDCT_JPEG_Y_START_END 4284644508 #define P_NR2_SNR_SAD_CFG 4287651140 #define P_MCDI_RPTMV_FLG 4287675464 #define P_AIU_MEM_I2S_END_PTR 4291842440 #define P_SPICC0_DMAREG 4291899408 #define DOLBY_TV_SWAP_CTRL7 13305 #define DOLBY_TV_SWAP_CTRL6 13304 #define DOLBY_TV_SWAP_CTRL5 13303 #define ME_STEP0_CLOSE_MV 8018 #define DOLBY_TV_SWAP_CTRL0 13298 #define DOLBY_TV_SWAP_CTRL4 13302 #define DOLBY_TV_SWAP_CTRL3 13301 #define DOLBY_TV_SWAP_CTRL2 13300 #define DOLBY_TV_SWAP_CTRL1 13299 #define P_ANC2_CANVAS_ADDR 4284622408 #define P_OSD1_AFBCD_ENABLE 4287678080 #define P_HCODEC_V3_SKIP_CONTROL 4284644784 #define HEVC_SLICE_VER_POS_PIC_TYPE 15364 #define P_MCDI_LMV_RT 4287675440 #define P_GCLK_EN 4284622348 #define VDEC2_MC_CTRL0 10503 #define VDEC2_MC_CTRL2 10575 #define VDEC2_MC_CTRL1 10507 #define P_V3_L2_SKIP_WEIGHT 4284644808 #define HEVC_MPRED_MV_WR_ROW_JUMP 12823 #define P_VPP_VSC_REGION1_PHASE_SLOPE 4287657000 #define P_VLC_COEFF_INFO 4284642572 #define P_HCODEC_PSCALE_DRAM_BUF_CTRL 4284638340 #define HCODEC_MDEC_PICW_BUF_STATUS 6586 #define P_LDIM_STTS_MATRIX_COEF11_12 4287654676 #define AIU_958_BRST 5121 #define VLD_DBG_INDEX 3134 #define P_ENCL_SYNC_PIXEL_EN 4287656244 #define P_HEVC_VLD_C3D 4284674292 #define P_VENC_VDAC_DAC1_GAINCTRL 4287655880 #define P_ADAPTIVE_SCALE_DATA 4287677784 #define L_OEV3_VE_ADDR 5178 #define VIU2_OSD2_HL1_V_START_END 7732 #define P_HEVC_VLD_C38 4284674272 #define P_HEVC_VLD_C39 4284674276 #define VIU_OSD_BLEND_RO_CURRENT_XY 14783 #define HEVC_SAO_Y_WPTR 13839 #define P_PSCALE_MCMD_CTRL 4284621960 #define WRRSP_FIFO_PICW_MC 2495 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD0 4287678188 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD2 4287678196 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD1 4287678192 #define VKS_FILL_VAL 12550 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD4 4287678204 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD3 4287678200 #define VPP2_HSC_REGION4_PHASE_SLOPE 6423 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD5 4287678208 #define P_MCDI_RO_FLD_PD_22_FOR_CNT2 4287676216 #define P_MCDI_RO_FLD_PD_22_FOR_CNT1 4287676204 #define VLC_INPUT_STATUS 7476 #define ENCI_DVI_VSO_END_ODD 7177 #define VDIN0_BLKBAR_IND_RIGHT2_CNT 4714 #define P_ENCI_DE_H_END 4287655004 #define NR4_ALP1C_ERR2CURV_LIMIT1 11698 #define NR4_ALP1C_ERR2CURV_LIMIT0 11697 #define P_AFBC_ENABLE 4287654784 #define P_ENCP_VIDEO_VSO_BEGIN 4287655588 #define DET3D_HV_MUTE 5943 #define SRSHARP1_PKOSHT_VSLUMA_LUT_L 13315 #define SRSHARP1_PKOSHT_VSLUMA_LUT_H 13316 #define P_ENCL_VIDEO_BLANKY_VAL 4287656688 #define ENCP_VIDEO_YFP1_HTIME 7060 #define VPP_VADJ2_Y 7492 #define VDEC2_PSCALE_CMD_CTRL 10523 #define HCODEC_VLC_IPRED_MODE_HI 7483 #define HCODEC_QDCT_MB_START_PTR 7952 #define VDIN_HIST_CTRL 4656 #define P_DI_POST_SIZE 4287650824 #define VDEC2_ANC26_CANVAS_ADDR 10666 #define P_HCODEC_INTRA_QUANT_MATRIX 4284643336 #define P_HEVC_MC_DPDN_MB_XY 4284671256 #define P_REC_CANVAS_ADDR 4284622536 #define SRSHARP0_DEJ_ALPHA 12901 #define VPU_PROT1_STAT_2 10075 #define VPU_PROT1_STAT_1 10074 #define VPU_PROT1_STAT_0 10073 #define P_VPU_HDMI_DITH_10_15 4287668180 #define P_DI_INP_LUMA_X0 4287651648 #define P_ENCI_DBG_PX_INT 4287655208 #define VPU_RDARB_MODE_L2C1 10141 #define HCODEC_VOFF_STATUS 7228 #define DNLP_EN 12869 #define P_DNR_RO_GBS_STAT_CNT 4287673456 #define HCODEC_VLC_IPRED_MODE_LO 7484 #define VPP_POST2_MATRIX_PRE_OFFSET2 14764 #define P_VPU_HDMI_DITH_10_04 4287668176 #define P_DI_INP_LUMA_Y0 4287651652 #define P_QDCT_VLC_QUANT_CTL_0 4284644592 #define P_QDCT_VLC_QUANT_CTL_1 4284644596 #define P_HCODEC_ME_SAD_2 4284644748 #define P_HCODEC_ME_SAD_3 4284644752 #define HEVC_MPRED_LT_COLREF 12811 #define P_VENC_VDAC_DAC5_GAINCTRL 4287655912 #define VDIN1_BLKBAR_IND_LEFT_START_END 5221 #define P_SHARP_SR3_DERING_LUMA2PKOS_4TO6 4287678908 #define P_VDEC2_MINDEX3_REG 4284648500 #define P_NR4_DRT_CSAD_GAIN 4287674008 #define VD1_IF0_RPT_LOOP 6747 #define P_GE2D_DST_CLIPY_START_END 4287890132 #define DI_MEM_LUMA0_RPT_PAT 6114 #define HEVC_CPU_TRACE 13184 #define P_VPP_MATRIX_COEF02_10 4287657348 #define VPU_VIU2VDIN_HDN_CTRL 10112 #define P_COMM_DESC_KEY1 4291847128 #define P_HEVC_SAO_C_WPTR 4284667968 #define HCODEC_ME_START_POSITION 8010 #define HCODEC_POWER_CTL_MC 6405 #define VBO_PXL_CTRL 5229 #define P_COMM_DESC_KEY0 4291847124 #define P_VIU2_OSD2_HL2_V_START_END 4287658200 #define HCODEC_MDEC_EXTIF_STS0 6630 #define VIU_OSD2_MATRIX_COEF11_12 6835 #define SRSHARP1_NR_ALP0Y_ERR2CURV_TH_RATE 13333 #define HCODEC_VLC_ELEMENT_DATA 7457 #define P_VDEC2_DBLK_Y_BHFILT_HIGH 4284654944 #define P_SHARP_SATPRT_LMT_RGB 4287678936 #define VLTI_CON_2_GAIN_1 12862 #define VLTI_CON_2_GAIN_0 12861 #define P_XVYCC_LUT_B_DATA_PORT 4287677836 #define SRSHARP0_DB_FLT_YC_THRD 12920 #define AUDIN_FIFO1_HOLD1_EN 20 #define DI_CLKG_CTRL 5912 #define VDEC2_ANC15_CANVAS_ADDR 10655 #define P_MCDI_SAD_GAIN 4287675420 #define P_HEVC_MPRED_L0_REF01_POC 4284663940 #define P_HCODEC_ME_SAD_0 4284644740 #define P_HCODEC_ME_SAD_1 4284644744 #define VDEC2_DBLK_CBPY_ADJ 10609 #define HEVC_MPRED_TILE_SIZE_LCU 12808 #define NR2_RO_POLAR3_M1 11679 #define NR2_RO_POLAR3_M2 11681 #define VDIN0_MATRIX_COEF22 4629 #define VPP2_GCLK_CTRL1 6515 #define VPP2_GCLK_CTRL0 6514 #define P_HCODEC_VLC_VB_LEFT 4284642388 #define P_MCDI_TXT_THD 4287675424 #define VDIN_LCNT_SHADOW_STATUS 4615 #define P_VLD_DBG_INDEX 4284625144 #define VDEC2_MINT_VEC_BASE 8962 #define HCODEC_QDCT_MB_LEVEL 7956 #define TOP_LEFT_READY 7506 #define SPICC1_CONREG 21506 #define P_HEVC_WRRSP_IMEM 4284665100 #define VLC_VB_CONTROL 7446 #define OSD1_AFBCD_MODE 12705 #define V3_SKIP_WEIGHT 8048 #define P_AFBC_MODE 4287654788 #define WRRSP_VLD 2522 #define SHARP_PKGAIN_VSLUMA_LUT_H 12927 #define SHARP_PKGAIN_VSLUMA_LUT_L 12926 #define P_D2D3_DWMIF_SIZE 4287671452 #define P_VDIN_VSC_INI_CTRL 4287645840 #define NR2_RO_POLAR3_P1 11680 #define NR2_RO_POLAR3_P2 11682 #define P_HEVC_MPRED_MV_RD_START_ADDR 4284663888 #define P_VDIN_HSC_PHASE_STEP 4287645744 #define P_VBO_GCLK_LANE_L 4287648192 #define P_VBO_GCLK_LANE_H 4287648196 #define P_NR4_MCNR_RO_U_SUM 4287674312 #define CPV2_HE_ADDR 5284 #define VPP2_VSC_REGION0_PHASE_SLOPE 6409 #define P_RV_AI_MB_COUNT 4284626992 #define P_VCTI_FLT_CON_CLP 4287678716 #define CDB_ADDR_REG 827 #define P_HEVC_VLD_MEM_VIFIFO_CURR_PTR 4284674308 #define VPU_RDARB_MODE_L1C2 10137 #define P_VPP2_OFIFO_SIZE 4287658140 #define PARSER_VIDEO2_RP 14486 #define VPU_RDARB_MODE_L1C1 10128 #define P_CBREAK1_REG 4284615892 #define MCDI_REL_SAD_THD_MIN_MAX 12072 #define VPU_VLOCK_STBDET_WIN0_WIN1 12311 #define P_HEVC_CINDEX0_REG 4284665000 #define P_HCODEC_VLD_DBG_INDEX 4284641528 #define PARSER_AV2_WRAP_COUNT 14488 #define VDEC2_CINDEX7_REG 9009 #define P_HCODEC_ANC7_CANVAS_ADDR 4284638812 #define P_VPP2_OSD_SCALE_COEF_IDX 4287653680 #define P_WM_SYMBOLS_YPOS 4287678176 #define GE2D_DST_Y_START_END 183 #define ENCT_VIDEO_RGBIN_CTRL 7303 #define ENCP_VIDEO_VSPULS_ELINE 7070 #define ENCL_TST_CR 7324 #define HCODEC_CSP 4896 #define MIPI_DSI_DWC_DPI_CFG_POL_OS 7173 #define P_VIU_OSD1_EOTF_LUT_DATA_PORT 4287654764 #define P_AIU_AIFIFO2_CTRL 4291842304 #define VLC_DBG_READ 7511 #define P_OEV3_HS_ADDR 4287648476 #define OSD_DB_FLT_LUMA_THRD 12610 #define P_VD2_IF0_CHROMA_PSEL 4287654404 #define P_ENCI_DVI_VSO_BLINE_ODD 4287655948 #define ENCL_TST_EN 7320 #define HSYNC_VS_ADDR 5335 #define GE2D_MATRIX_COEF20_21 201 #define DBLK_CBPY 2416 #define PARSER_VIDEO2_WP 14485 #define P_VLC_INT_CONTROL_INTER 4284642492 #define PSCALE_STATUS 2334 #define VDIN0_MEAS_HS_RANGE 4701 #define OEH_SEL 10 #define HEVC_SAO_MMU_WPTR 13884 #define VDEC2_MC_MPORT_CTRL 10560 #define P_GPIO_INTR_GPIO_SEL0 4291883140 #define P_VDEC2_DBLK_MB_XY 4284654932 #define P_GPIO_INTR_GPIO_SEL1 4291883144 #define DBLK_CBPC 2418 #define P_VDEC2_IQIDCT_DEBUG_IDCT 4284659780 #define VP9D_MPP_REFINFO_TBL_ACCCONFIG 13378 #define ENCL_TST_CB 7323 #define P_ENCP_VIDEO_Y_SCL 4287655436 #define VPP_VADJ1_Y 7489 #define CVBS_IRQ1_CNTL 15397 #define VDEC2_DBLK_CBPC_ADJ 10611 #define P_VDEC2_DBLK_RST 4284654912 #define P_VPP_OSD_HSC_INI_PAT_CTRL 4287657752 #define DNR_GBS 11524 #define P_VENC_VIDEO_TST_Y 4287655368 #define P_VPU_TVD3D_MMC_CTRL 4287667264 #define SPI_FLASH_BYTES_LEN 24 #define VDIN0_SCALE_COEF 4609 #define P_HCODEC_ANC22_CANVAS_ADDR 4284638872 #define P_VPP2_VSC_REGION4_PHASE_SLOPE 4287652912 #define HEVC_DBLK_Y_HFILT 14684 #define P_MB_WIDTH 4284624932 #define DI_IF1_URGENT_CTRL 8355 #define ENCI_SYNC_VSO_EVNLN 6926 #define HCODEC_ME_DEBUG 8012 #define NR4_RO_NM_VAR_SUM 14113 #define L_GAMMA_VCOM_HSWITCH_ADDR 5123 #define P_VPU_VLOCK_OROW_OCOL_MAX 4287676480 #define P_MCDI_RO_COL_CFD_25 4287676196 #define P_MCDI_RO_COL_CFD_24 4287676192 #define VBO_TMCHK_VSYNC_STATE_L 5364 #define VBO_TMCHK_VSYNC_STATE_H 5365 #define P_MCDI_RO_COL_CFD_21 4287676180 #define P_MCDI_RO_COL_CFD_20 4287676176 #define P_VPP_HSC_REGION12_STARTP 4287657024 #define P_MCDI_RO_COL_CFD_23 4287676188 #define P_MCDI_RO_COL_CFD_22 4287676184 #define SRSHARP0_NR_ALP0C_ERR2CURV_LIMIT 12824 #define SRSHARP0_PK_CON_2DRTHPGAIN_LIMIT 12810 #define P_VDEC_ASSIST_DMA_INT_MSK2 4284613020 #define P_ENCP_VIDEO_BLANKPR_VAL 4287655632 #define VPP2_OSD_SC_CTRL0 6600 #define P_NR4_MCNR_SKIN_GAIN_PAR0 4287674188 #define P_NR4_MCNR_SKIN_GAIN_PAR1 4287674192 #define P_MCDI_RO_COL_CFD_14 4287676152 #define P_MCDI_RO_COL_CFD_13 4287676148 #define P_ENCL_VIDEO_YFP2_HTIME 4287656632 #define P_MCDI_RO_COL_CFD_16 4287676160 #define P_MCDI_RO_COL_CFD_15 4287676156 #define P_MCDI_RO_COL_CFD_18 4287676168 #define P_MCDI_RO_COL_CFD_17 4287676164 #define P_MCDI_RO_COL_CFD_19 4287676172 #define P_HEVC_STREAM_LEVEL 4284662808 #define P_MCDI_RO_COL_CFD_10 4287676136 #define P_HCODEC_ANC11_CANVAS_ADDR 4284638828 #define P_MCDI_RO_COL_CFD_12 4287676144 #define P_MCDI_RO_COL_CFD_11 4287676140 #define P_AUDIN_FIFO0_START 4291874944 #define P_VIU2_OSD2_COLOR 4287658184 #define V5_SIMPLE_MB_DQUANT 8063 #define P_ENCL_TST_CLRBAR_STRT 4287656564 #define P_MCDI_REL_SAD_GAIN_OFFST_23 4287675544 #define P_VIU_OSD1_MATRIX_COEF31_32 4287654520 #define P_HENC_LEFT_MV_2 4284642624 #define P_HENC_LEFT_MV_3 4284642628 #define P_HENC_LEFT_MV_0 4284642616 #define P_PFIFO_MONITOR 4291879392 #define P_HENC_LEFT_MV_1 4284642620 #define P_DOS_VDEC2_INT_EN 4284677160 #define ENCP_VIDEO_BLANKY_VAL 7090 #define NR2_RO_POLAR3_32 11683 #define AUDIN_FIFO1_RST 1 #define P_WM_THRES_DATA_PORT 4287678260 #define EE_ASSIST_MBOX1_FIQ_SEL 8311 #define P_MCDI_REL_SAD_GAIN_OFFST_01 4287675540 #define ENCL_VIDEO_VAVON_ELINE 7347 #define P_XVYCC_POST_RGB_DLUT_4_7 4287677920 #define HCODEC_QDCT_MB_MEM_CTL 7958 #define HEVC_VLD_TIME_STAMP_LENGTH 15440 #define DNR_LUMA 11530 #define VI_HIST_PIC_SIZE 11816 #define P_HEVC_CMAX_REG 4284665036 #define HCODEC_V3_MV_SAD_TABLE 8051 #define SPI_FLASH_CTRL1 20483 #define SPI_FLASH_CTRL2 20485 #define P_HEVC_PARSER_SLICE_INFO 4284662852 #define VPP2_VSC_INI_PHASE 6414 #define P_VPP_OSDSC_DITHER_LUT_3 4287677644 #define P_VPP_OSDSC_DITHER_LUT_2 4287677640 #define P_VPP_OSDSC_DITHER_LUT_5 4287677652 #define P_VPP_OSDSC_DITHER_LUT_4 4287677648 #define P_VPP_OSDSC_DITHER_LUT_7 4287677660 #define P_VPP_OSDSC_DITHER_LUT_6 4287677656 #define P_VPU_ARB_DBG_CTRL_L2C1 4287667932 #define P_VPP_OSDSC_DITHER_LUT_9 4287677668 #define P_VPP_OSDSC_DITHER_LUT_8 4287677664 #define ENCP_DBG_PX_RST 7056 #define VPP_MATRIX_OFFSET0_1 7525 #define P_VERSION_CTRL 4291825664 #define MCDI_REL_DET_LPF_DIF_THD 12087 #define MCDI_REL_DET_LMV_DIF_CHK 12080 #define P_VPP_OSDSC_DITHER_LUT_1 4287677636 #define P_IE_SAD_0 4284644756 #define P_MC_CTRL_REG 4284621824 #define P_IE_SAD_2 4284644764 #define VIU_OSD1_OETF_LUT_ADDR_PORT 6877 #define P_IE_SAD_1 4284644760 #define P_IE_SAD_3 4284644768 #define ENCI_VBI_TTX_LN 6955 #define MIPI_DSI_DWC_VID_NULL_SIZE_OS 7185 #define P_NR4_MCNR_MV_CTRL_REG 4287674104 #define P_DC_CAV_LUT_RDATAH 4284711000 #define P_DC_CAV_LUT_RDATAL 4284710996 #define P_VPU_PROT1_CLK_GATE 4287667520 #define VDEC2_VLD_MEM_VIFIFO_CONTROL 11332 #define P_DI_IF1_GEN_REG2 4287651392 #define SPI_FLASH_USER2 20489 #define SPI_FLASH_USER1 20488 #define SPI_FLASH_USER4 20491 #define SPI_FLASH_USER3 20490 #define HCODEC_PSCALE_FILT0_COEF0 6425 #define HCODEC_PSCALE_FILT0_COEF1 6426 #define SPI_FLASH_READ 31 #define SRSHARP0_SATPRT_CTRL 12916 #define P_HEVC_DBLK_VLD_HCMD0 4284671472 #define P_HEVC_DBLK_VLD_HCMD2 4284671464 #define P_HEVC_DBLK_VLD_HCMD1 4284671468 #define P_HEVC_MDEC_DOUBLEW_CFG4 4284671868 #define P_HEVC_MDEC_DOUBLEW_CFG3 4284671864 #define P_HEVC_MDEC_DOUBLEW_CFG6 4284671876 #define P_HEVC_MDEC_DOUBLEW_CFG5 4284671872 #define P_HEVC_MDEC_DOUBLEW_CFG7 4284671880 #define HEVC_INTRA_QUANT_MATRIX 15874 #define HCODEC_QDCT_DBG_IDX 7971 #define P_HEVC_MDEC_DOUBLEW_CFG0 4284671852 #define P_DI_IF1_GEN_REG3 4287660700 #define P_HEVC_MDEC_DOUBLEW_CFG2 4284671860 #define P_HEVC_MDEC_DOUBLEW_CFG1 4284671856 #define VPU_PROT1_Y_START_END 10067 #define P_VI_DNLP_HIST30 4287674516 #define P_VI_DNLP_HIST32 4287674524 #define P_VI_DNLP_HIST31 4287674520 #define AUDIN_FIFO0_EN 0 #define P_VI_DNLP_HIST29 4287674512 #define P_VI_DNLP_HIST28 4287674508 #define P_HCODEC_QDCT_STATUS_CTRL 4284644352 #define IGNORE_CONFIG 7938 #define P_MC_STATUS1 4284621864 #define P_MC_STATUS0 4284621860 #define P_NR2_MATNR_SNR_USF_GAIN 4287651160 #define HEVCD_IPP_TOP_CNTL 13312 #define SRSHARP0_SHARP_HVSIZE 12800 #define VDEC2_MC_MPORT_DAT 10561 #define P_HCODEC_SLICE_QP 4284641320 #define VDEC2_MMAX_REG 8979 #define XVYCC_LUT_R_ADDR_PORT 12638 #define HEVC_ASSIST_MBOX2_IRQ_REG 12408 #define HCODEC_CINDEX0_REG 4906 #define AUDIN_FIFO1_LVL2 13378 #define AUDIN_FIFO1_LVL0 13376 #define AUDIN_FIFO1_LVL1 13377 #define HCODEC_ME_SUB_ACT_CTL 8031 #define P_DI_PRE_CTRL 4287650816 #define L_OEV1_HE_ADDR 5168 #define L_TCON_DOUBLE_CTL 5193 #define P_ENCI_YC_DELAY 4287655256 #define AUDIN_FIFO0_HOLD2_SEL 26 #define P_HEVC_ASSIST_DMA_INT 4284662160 #define P_VDEC_ASSIST_AMR1_INTD 4284612808 #define I2C_M_3_WDATA_REG1 28677 #define P_VDEC_ASSIST_AMR1_INTC 4284612804 #define I2C_M_3_WDATA_REG0 28676 #define P_VDEC_ASSIST_AMR1_INTB 4284612800 #define P_VDEC_ASSIST_AMR1_INTA 4284612796 #define P_VDEC_ASSIST_AMR1_INTF 4284612816 #define P_VDEC_ASSIST_AMR1_INTE 4284612812 #define ENCL_VFIFO2VD_LINE_TOP_END 7316 #define P_VPU_SECURE_DUMMY 4287667488 #define P_VDEC_ASSIST_AMR1_INT4 4284612772 #define P_VDEC_ASSIST_AMR1_INT3 4284612768 #define P_VDEC_ASSIST_AMR1_INT2 4284612764 #define P_HEVC_MPRED_L1_REF11_POC 4284664044 #define P_VDEC_ASSIST_AMR1_INT1 4284612760 #define P_VDEC_ASSIST_AMR1_INT8 4284612788 #define P_VDEC_ASSIST_AMR1_INT7 4284612784 #define AIU_I2S_OUT_CFG 5139 #define P_VDEC_ASSIST_AMR1_INT6 4284612780 #define P_VDEC_ASSIST_AMR1_INT5 4284612776 #define P_VDEC_ASSIST_AMR1_INT9 4284612792 #define VPP_POST_BLEND_BLEND_DUMMY_DATA 14696 #define ENCI_CFILT_CTRL 6996 #define P_HCODEC_PSCALE_FILT0_COEF0 4284638308 #define P_HCODEC_PSCALE_FILT0_COEF1 4284638312 #define STH1_VE_ADDR 5267 #define P_OSD_BLENDO_V_START_END 4287654568 #define P_LDIM_STTS_HIST_REGION_IDX 4287654720 #define VDIN0_WIN_V_START_END 4718 #define ENCP_VIDEO_HSO_BEGIN 7079 #define VLD_DBG_DATA 3135 #define P_NR4_MCNR_ALP1_LP_PRAM 4287683696 #define VIU2_VD1_IF0_RPT_LOOP 7771 #define P_VD2_IF0_LUMA1_RPT_PAT 4287654392 #define P_VDEC_ASSIST_AMR1_INT0 4284612756 #define VIDEO_PTS 14451 #define P_VIU_OSD1_MATRIX_COLMOD_COEF42 4287654484 #define P_VI_DNLP_HIST16 4287674460 #define P_VI_DNLP_HIST15 4287674456 #define P_VI_DNLP_HIST14 4287674452 #define P_VI_DNLP_HIST13 4287674448 #define P_VI_DNLP_HIST12 4287674444 #define P_VI_DNLP_HIST11 4287674440 #define P_VI_DNLP_HIST10 4287674436 #define P_VI_DNLP_HIST09 4287674432 #define P_VI_DNLP_HIST08 4287674428 #define SRSHARP0_PK_CIRFB_HP_CORING 12815 #define P_VI_DNLP_HIST07 4287674424 #define P_VI_DNLP_HIST06 4287674420 #define MEDIA_CPU_CTL 15457 #define SANA_ELEMENT_RESULT 12334 #define HEVC_DBLK_CBUS_HCMD0 14713 #define HEVC_DBLK_CBUS_HCMD1 14712 #define HEVC_DBLK_CBUS_HCMD2 14711 #define P_VI_DNLP_HIST27 4287674504 #define P_VI_DNLP_HIST26 4287674500 #define P_VI_DNLP_HIST25 4287674496 #define P_VI_DNLP_HIST24 4287674492 #define P_VI_DNLP_HIST23 4287674488 #define P_VI_DNLP_HIST22 4287674484 #define P_VI_DNLP_HIST21 4287674480 #define VSYNC_HS_ADDR 5337 #define P_VI_DNLP_HIST20 4287674476 #define ABUF_WR_CUR_BLK_LSB 0 #define P_VI_DNLP_HIST19 4287674472 #define P_VI_DNLP_HIST18 4287674468 #define VBO_VIN_CTRL 5220 #define P_VI_DNLP_HIST17 4287674464 #define P_GE2D_DST_X_START_END 4287890136 #define VDEC2_MDEC_PIC_DC_STATUS 10639 #define P_HCODEC_VLC_INT_CONTROL 4284642496 #define AIU_MEM_AIFIFO2_LEVEL 5233 #define VPP_EOTF_3X3_OFST_1 12761 #define VPP_EOTF_3X3_OFST_0 12760 #define SPICC1_DRADDR 21512 #define P_VI_DNLP_HIST05 4287674416 #define P_VI_DNLP_HIST04 4287674412 #define P_VI_DNLP_HIST03 4287674408 #define P_VI_DNLP_HIST02 4287674404 #define P_VI_DNLP_HIST01 4287674400 #define P_VI_DNLP_HIST00 4287674396 #define HEVC_CCPU_INTR_REQ 13093 #define SRSHARP1_NR_GAUSSIAN_MODE 13314 #define P_RESET2_REGISTER 4291825676 #define VDIN0_DOLBY_AXI_CTRL0 4729 #define ENCT_VIDEO_Y_SCL 7265 #define VDIN0_DOLBY_AXI_CTRL3 4732 #define VDIN0_DOLBY_AXI_CTRL2 4731 #define VDIN0_COM_GCLK_CTRL2 4720 #define VDIN0_DOLBY_AXI_CTRL1 4730 #define P_VPU_PROT2_STAT_1 4287667624 #define P_VPU_PROT2_STAT_0 4287667620 #define P_VPU_PROT2_STAT_2 4287667628 #define L_OEV1_VS_ADDR 5169 #define HEVC_DBLK_RV8_QUANT 14710 #define P_VDEC2_ANC27_CANVAS_ADDR 4284655276 #define VPU_VPU_PWM_V0 10032 #define QDCT_MB_PAUSE_CTL 7966 #define ENCT_VIDEO_HSO_END 7286 #define HCODEC_HENC_LEFT_MV_2 7504 #define HCODEC_HENC_LEFT_MV_3 7505 #define HCODEC_HENC_LEFT_MV_0 7502 #define HCODEC_HENC_LEFT_MV_1 7503 #define VPU_VPU_PWM_V3 10035 #define VPU_VPU_PWM_V2 10034 #define VPU_VPU_PWM_V1 10033 #define HEVC_CURR_CANVAS_CTRL 14771 #define P_VLC_HCMD_DBLK_INFO 4284642644 #define P_DBLK_CR_FILT 4284622208 #define P_MDEC_PICW_BUF2_STATUS 4284622580 #define DI_CONTP2RD_X 6053 #define DI_CONTP2RD_Y 6054 #define RAM_TEST_ADDR 3 #define P_DI_INP_LUMA0_RPT_PAT 4287651668 #define P_QDCT_MB_CONTROL 4284644436 #define P_VC1_BITPLANE_CTL 4284627040 #define P_VPP_GCLK_CTRL1 4287657420 #define P_VPP_GCLK_CTRL0 4287657416 #define HEVCD_IPP_INTR_MASK 13322 #define P_NR4_COEFBLT_LUT20 4287683624 #define P_NR4_COEFBLT_LUT22 4287683632 #define P_NR4_COEFBLT_LUT21 4287683628 #define P_VPU_RDMA_MMC_CTRL 4287667344 #define P_VDEC2_MSFTINT1 4284648572 #define P_VDEC2_MSFTINT0 4284648568 #define VP9_SHADOW_CTRL 12624 #define VDEC2_DBLK_CB_FILT 10591 #define P_NR4_COEFBLT_LUT31 4287683640 #define P_NR4_COEFBLT_LUT30 4287683636 #define P_NR4_COEFBLT_LUT32 4287683644 #define HCODEC_DBLK_MB_WID_HEIGHT 6482 #define P_ENCP_VIDEO_HOFFST 4287655636 #define VPP_OSD_SCALE_COEF_IDX 7628 #define P_VLC_VB_PRE_BUFF_LOW 4284642420 #define MIPI_DSI_DWC_PCKHDL_CFG_OS 7179 #define P_VDEC2_DCAC_CPU_DATA 4284659796 #define P_ENCL_VIDEO_HSO_END 4287656664 #define AIUout_FIFO_THRESHOLD_MSB 11 #define VDEC2_ASSIST_TIMER1_LO 8290 #define P_VDEC2_MMIN_REG 4284648520 #define P_ENCL_VIDEO_VOFFST 4287656704 #define VDIN0_HSC_INI_CTRL 4621 #define P_NR4_COEFBLT_LUT11 4287683616 #define P_NR4_COEFBLT_LUT10 4287683612 #define P_HCODEC_V5_SIMPLE_MB_CTL 4284644856 #define VD2_IF0_RPT_LOOP 6779 #define P_NR4_COEFBLT_LUT12 4287683620 #define P_PSCALE_RBUF_START_BLKY 4284621976 #define P_PSCALE_RBUF_START_BLKX 4284621972 #define P_VPU_PROT3_RPT_PAT 4287667672 #define NR4_MCNR_SAD2BET1_LUT0 11754 #define NR4_MCNR_SAD2BET1_LUT1 11755 #define P_VPP_OSD_SC_DUMMY_DATA 4287657756 #define NR4_MCNR_SAD2BET1_LUT2 11756 #define NR4_MCNR_SAD2BET1_LUT3 11757 #define VDEC2_MAC_CTRL1 9056 #define VDEC2_MAC_CTRL2 9072 #define SRSHARP0_PK_OS_STATIC 12838 #define VDIN0_VSC_PHASE_STEP 4643 #define P_VDIN_LDIM_STTS_HIST_REGION_IDX 4287646044 #define P_HEVC_CABAC_CONTROL 4284662848 #define HSYNC_HE_ADDR 5334 #define P_VBO_INTR_STATE 4287648736 #define P_UART2_RFIFO 4291960836 #define VDEC2_ASSIST_TIMER1_HI 8291 #define HCODEC_MBREAK1_REG 4885 #define SRSHARP0_NR_ALP1_MIERR_CORING 12826 #define D2D3_DBLD_PATH_CTRL 11030 #define P_HEVC_ANC17_CANVAS_ADDR 4284671620 #define VPU_ARB_URG_CTRL 10055 #define HCODEC_V5_SIMPLE_MB_CTL 8062 #define P_VPP2_HSC_START_PHASE_STEP 4287652940 #define VIU_OSD2_MATRIX_OFFSET2 6839 #define DI_CANVAS_URGENT1 5899 #define DI_CANVAS_URGENT0 5898 #define P_VPP_EOTF_LUT_DATA_PORT 4287678300 #define P_DI_IF1_LUMA0_RPT_PAT 4287651772 #define AIU_958_SYNWORD1_MASK 5151 #define VPP2_POSTBLEND_H_SIZE 6433 #define DI_CANVAS_URGENT2 5902 #define P_HEVCD_IPP_TOP_STATUS 4284665860 #define P_HEVC_STREAM_PACKET_LENGTH 4284663012 #define PARSER_INT_STATUS 14444 #define P_HEVC_VLD_REVERVED_19 4284674148 #define P_HCODEC_CDB_DATA_REG 4284632304 #define VIU2_OSD1_TEST_RDDATA 7756 #define P_VIU_OSD1_OETF_CTL 4287654768 #define VBO_TMCHK_VDE_STATE_H 5367 #define VPU_VPU_PWM_H2 10038 #define VBO_TMCHK_VDE_STATE_L 5366 #define VPU_VPU_PWM_H1 10037 #define VPU_VPU_PWM_H0 10036 #define VDEC2_ASSIST_AMR2_INT3 8248 #define VDEC2_ASSIST_AMR2_INT4 8249 #define VDEC2_ASSIST_AMR2_INT1 8246 #define VDEC2_ASSIST_AMR2_INT2 8247 #define VDEC2_ASSIST_AMR2_INT0 8245 #define VPP2_SC_MISC 6425 #define VPU_VPU_PWM_H3 10039 #define VDEC2_ASSIST_AMR2_INTC 8257 #define VDEC2_ASSIST_AMR2_INTD 8258 #define VDEC2_ASSIST_AMR2_INTA 8255 #define HEVC_ANC5_CANVAS_ADDR 14741 #define VDEC2_ASSIST_AMR2_INTB 8256 #define P_SPICC0_INTREG 4291899404 #define AIU_958_SYNWORD3 5150 #define GE2D_STATUS1 165 #define GE2D_STATUS2 233 #define AIU_958_SYNWORD1 5148 #define VDEC2_ASSIST_AMR2_INT9 8254 #define AIU_958_SYNWORD2 5149 #define VDEC2_ASSIST_AMR2_INT7 8252 #define VDEC2_ASSIST_AMR2_INT8 8253 #define VDEC2_ASSIST_AMR2_INT5 8250 #define GE2D_STATUS0 164 #define VDEC2_ASSIST_AMR2_INT6 8251 #define SRSHARP0_HCTI_OS_MARGIN 12851 #define SRSHARP1_PK_CIRFB_HP_CORING 13327 #define P_VENC_VDAC_DAC1_OFFSET 4287655884 #define VDEC2_ASSIST_AMR2_INTE 8259 #define VDIN_MATRIX_PROBE_COLOR 4648 #define VDEC2_ASSIST_AMR2_INTF 8260 #define P_VBO_INTR_UNMASK 4287648244 #define NR4_MCNR_MV_GAIN0 11711 #define VDIN0_MEAS_CTRL0 4698 #define VPP_EOTF_COEF20_21 12756 #define P_LAST_SLICE_MV_ADDR 4284625088 #define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 5261 #define P_VPP_SC_MISC 4287657060 #define P_ENCP_DVI_VSO_END_ODD 4287656164 #define SRSHARP1_HCTI_OS_MARGIN 13363 #define P_VDEC2_MDEC_DOUBLEW_CFG2 4284655476 #define P_VDEC2_MDEC_DOUBLEW_CFG1 4284655472 #define P_VDEC2_MDEC_DOUBLEW_CFG4 4284655484 #define P_VDEC2_MDEC_DOUBLEW_CFG3 4284655480 #define P_VDEC2_MDEC_DOUBLEW_CFG0 4284655468 #define P_VDEC2_MDEC_DOUBLEW_CFG6 4284655492 #define P_VDEC2_MDEC_DOUBLEW_CFG5 4284655488 #define P_VDEC2_MDEC_DOUBLEW_CFG7 4284655496 #define VLC_WRRSP 7449 #define P_STH1_VS_ADDR 4287648328 #define P_MCDI_REF_BADW_THD_GAIN 4287675488 #define AIFIFO_TIME_STAMP_3 5270 #define SRSHARP0_DEJ_CTRL 12900 #define AIFIFO_TIME_STAMP_0 5267 #define AIFIFO_TIME_STAMP_1 5268 #define AIFIFO_TIME_STAMP_2 5269 #define P_VIU2_VD1_IF0_RANGE_MAP_Y 4287658408 #define VDIN_MATRIX_PRE_OFFSET0_1 4632 #define P_HCODEC_ME_SUB_FIX_MIN_SAD 4284644724 #define P_VCTI_BST_CORE 4287678724 #define VDIN_DOLBY_DSC_STATUS1 4734 #define VDIN_DOLBY_DSC_STATUS0 4733 #define VDIN_DOLBY_DSC_STATUS3 4637 #define VDIN_DOLBY_DSC_STATUS2 4735 #define SHARP_HVSIZE 12800 #define HCODEC_IGNORE_CONFIG_2 7939 #define PK_OS_STATIC 12838 #define HEVCD_MPP_DECOMP_PERFMON_CTL 13509 #define P_ENCP_VIDEO_HSO_BEGIN 4287655580 #define P_VDEC2_VLD_REVERVED_19 4284657764 #define P_AIU_I2S_MISC 4291842120 #define VDEC2_WRRSP_DCAC 10713 #define P_HCODEC_IGNORE_CONFIG 4284644360 #define VDEC2_ANC27_CANVAS_ADDR 10667 #define P_AUDIN_FIFO2_LVL2 4291875128 #define P_AUDIN_FIFO2_LVL0 4291875120 #define P_AUDIN_FIFO2_LVL1 4291875124 #define DEMO_POI_Y_REG 530 #define L_CPV2_VE_ADDR 5158 #define AIU_I2S_CBUS_DDR_ADDR 5291 #define HCODEC_INTRA_QUANT_MATRIX 7682 #define P_HCODEC_MC_PIC_W_H 4284638240 #define HCODEC_ASSIST_MBOX1_IRQ_REG 4212 #define P_ISA_TIMER_MUX1 4291883408 #define P_VDEC_ASSIST_MBOX2_CLR_REG 4284613092 #define P_HEVCD_MPP_WEIGHT_ADDR 4284666368 #define HCODEC_RV_AI_MB_COUNT 7692 #define VDEC2_PSCALE_SRCKEY_CTRL1 10539 #define VD1_IF0_LUMA0_RPT_PAT 6748 #define P_SHARP_PKGAIN_VSLUMA_LUT_H 4287678972 #define VDEC2_PSCALE_SRCKEY_CTRL0 10538 #define P_SHARP_PKGAIN_VSLUMA_LUT_L 4287678968 #define HCODEC_ASSIST_MBOX1_MASK 4214 #define P_MCDI_REL_SAD_THD_MIN_MAX 4287675552 #define P_L_VCOM_VE_ADDR 4287647864 #define MCDI_LMV_LOCK_ABS_DIF_THD 12106 #define P_HCODEC_IQ_QUANT 4284643420 #define HEVC_MPRED_LT_REF 12810 #define VLC_MB_INFO 7477 #define P_HCODEC_DBLK_CMD_CTRL 4284638544 #define P_VDEC_ASSIST_MMC_CTRL1 4284612616 #define P_VDEC_ASSIST_MMC_CTRL2 4284612620 #define P_VDEC_ASSIST_MMC_CTRL3 4284612624 #define P_VDEC_ASSIST_MMC_CTRL0 4284612612 #define VPU_PROT3_X_START_END 10098 #define VDEC2_IQIDCT_CONTROL 11790 #define P_HCODEC_VLC_ADV_CONFIG 4284642452 #define VLD_MEM_VIFIFO_BYTES_AVAIL 3139 #define I2SIN_CHAN_EN 10 #define ENCI_VBI_CGMS_LN 6953 #define SRSHARP1_HCTI_FLT_CLP_DC 13358 #define UART3_DF_REG_A129 33825 #define UART3_DF_REG_A128 33824 #define P_HEVC_MPRED_MV_WPTR 4284663892 #define VI_HIST_CHROMA_SUM 11782 #define UART3_DF_REG_A130 33826 #define UART3_DF_REG_A136 33832 #define UART3_DF_REG_A135 33831 #define P_HCODEC_MC_DPDN_MB_XY 4284638488 #define UART3_DF_REG_A132 33828 #define HCODEC_ANC6_CANVAS_ADDR 6550 #define UART3_DF_REG_A131 33827 #define UART3_DF_REG_A134 33830 #define UART3_DF_REG_A133 33829 #define VDIN_HIST_SPL_PIX_CNT 4661 #define P_HEVC_MPRED_L0_REF13_POC 4284663988 #define P_HSYNC_VS_ADDR 4287648604 #define PK_DRT_SAD_MISC 12840 #define P_HCODEC_ANC23_CANVAS_ADDR 4284638876 #define XVYCC_LUT_CTL 12645 #define P_HCODEC_V3_IPRED_TYPE_WEIGHT_1 4284644836 #define P_VDEC2_DBLK_CB_BFILT 4284654952 #define L_CPV1_VS_ADDR 5153 #define P_HCODEC_V3_IPRED_TYPE_WEIGHT_0 4284644832 #define VENC_INTFLAG 7023 #define P_DI_MTNWR_X 4287651596 #define P_DI_MTNWR_Y 4287651600 #define OSDSR_ABIC_HCOEF 12594 #define ENCP_VIDEO_SYNC_SCL 7046 #define P_VIU_VD1_FMT_W 4287654308 #define AUDOUT_FIFO_RPTR 13448 #define P_HCODEC_VLC_PIC_INFO 4284642504 #define VPP2_POSTBLEND_CURRENT_XY 6437 #define P_VLD_ERROR_MASK 4284625080 #define RESET3_LEVEL 1059 #define P_VIU_OSD2_HL1_H_START_END 4287654092 #define PWM_PWM_C 26624 #define PWM_PWM_B 27649 #define PWM_PWM_E 25600 #define PWM_PWM_D 26625 #define PWM_PWM_A 27648 #define ENCP_DE_V_END_ODD 7231 #define ENCI_MACV_MAX_AMP 6992 #define P_VDEC2_ANC0_CANVAS_ADDR 4284655168 #define P_HCODEC_PSCALE_CANVAS_RD_ADDR 4284638384 #define SRSHARP1_SR3_PK_CTRL1 13411 #define PWM_PWM_F 25601 #define SRSHARP1_SR3_PK_CTRL0 13410 #define P_HEVC_DBLK_CBUS_HCMD0 4284671460 #define P_HEVC_DBLK_CBUS_HCMD1 4284671456 #define P_HEVC_DBLK_CBUS_HCMD2 4284671452 #define SRSHARP0_PK_CON_2CIRBPGAIN_LIMIT 12808 #define P_VDEC2_VCOP_CTRL_REG 4284659712 #define P_STB_TOP_CONFIG 4291847104 #define VIU2_OSD2_PROT_CTRL 7758 #define P_SHARP_SATPRT_CTRL 4287678928 #define MCDI_LMV_LOCK_CNT_THD_GAIN 12105 #define VDIN1_VSC_PHASE_STEP 5155 #define P_ENCI_DBG_MAXPX 4287655216 #define DECOMB_MODE 11662 #define P_HCODEC_MMIN_REG 4284632136 #define RESET2_LEVEL 1058 #define P_ENCI_VBI_CCDT_EVN 4287655044 #define P_DBLK_VLD_HCMD2 4284622312 #define P_GE2D_SRC1_KEY_MASK 4287890236 #define ENCL_VIDEO_PB_OFFST 7333 #define P_VDEC2_QP_VALUE_REG 4284657684 #define P_HEVC_MPRED_LT_COLREF 4284663852 #define P_HEVC_ANC9_CANVAS_ADDR 4284671588 #define HEVC_MPRED_INT_STATUS 12804 #define AIUout_FIFO_THRESHOLD_LSB 6 #define P_HCODEC_ANC6_CANVAS_ADDR 4284638808 #define VIU_OSD1_MATRIX_OFFSET2 6807 #define P_VPU_ARB_DBG_STAT_L2C1 4287667936 #define P_DOS_GCLK_EN0 4284677124 #define P_DOS_GCLK_EN1 4284677156 #define P_DOS_GCLK_EN4 4284677344 #define P_DOS_GCLK_EN3 4284677332 #define VPP2_VSC_START_PHASE_STEP 6408 #define VDEC2_DBLK_CBPC 10610 #define LDIM_STTS_HIST_SET_REGION 6865 #define VDEC2_DBLK_CBPY 10608 #define P_VIU_OSD2_MATRIX_COEF11_12 4287654604 #define DOS_MEM_PD_VDEC2 16177 #define VDEC2_MBREAK_CTRL 8985 #define P_VPP_VADJ_CTRL 4287657216 #define RESET7_LEVEL 1063 #define AUDIN_FIFO0_RST 1 #define P_AUDIN_FIFO1_RDPTR 4291875036 #define P_UART1_RFIFO 4291964932 #define P_WM_VIDEO_RESOLUTION 4287678184 #define VDIN_SCALE_COEF_IDX 4608 #define P_DNR_DB_HGAP 4287673396 #define P_MDEC_DOUBLEW_CFG7 4284622728 #define P_MDEC_DOUBLEW_CFG6 4284622724 #define P_MDEC_DOUBLEW_CFG5 4284622720 #define P_MDEC_DOUBLEW_CFG4 4284622716 #define HEVCD_IPP_LINEBUFF_BASE 13321 #define P_HCODEC_ME_MV_WEIGHT_01 4284644696 #define HCODEC_MDEC_PICR_BUF_STATUS 6585 #define P_ENCP_VIDEO_SYNC_MODE 4287655428 #define P_ENCT_VIDEO_YFP1_HTIME 4287656372 #define AUDIN_FIFO0_HOLD0_EN 19 #define CBREAK3_REG 823 #define VDEC2_ANC0_CANVAS_ADDR 10640 #define P_VPP_VE_H_V_SIZE 4287657616 #define L_STV1_HS_ADDR 5159 #define VDEC_ASSIST_TIMER0_HI 97 #define XVYCC_VSCP_REG 542 #define P_HCODEC_ME_MV_WEIGHT_23 4284644700 #define VDIN1_LCNT_STATUS 5124 #define SPI_CLK_DIV0 12 #define P_DI_INP_FMT_CTRL 4287651684 #define P_HCODEC_VLC_CONFIG 4284642308 #define MC_IDCT_DAT 2380 #define VDIN1_DOLBY_DSC_CTRL0 5237 #define VDIN1_DOLBY_DSC_CTRL1 5238 #define GE2D_SRC1_LUT_ADDR 172 #define P_MDEC_DOUBLEW_CFG3 4284622712 #define P_MDEC_DOUBLEW_CFG2 4284622708 #define P_MDEC_DOUBLEW_CFG1 4284622704 #define P_MDEC_DOUBLEW_CFG0 4284622700 #define P_MCDI_HV_SIZEIN 4287675392 #define VDIN1_DOLBY_DSC_CTRL2 5239 #define VDIN1_DOLBY_DSC_CTRL3 5240 #define ANC31_CANVAS_ADDR 2479 #define P_ENCI_DBG_MAXLN 4287655220 #define ENCP_MAX_LINE_SWITCH_POINT 7183 #define P_MCDI_BI_MVDST 4287675416 #define VDEC2_MC_MB_INFO 10497 #define DI_EI_CTRL8 5918 #define DI_EI_CTRL9 5919 #define DI_EI_CTRL2 5894 #define DI_EI_CTRL3 5913 #define DI_EI_CTRL0 5892 #define DI_EI_CTRL1 5893 #define DI_EI_CTRL6 5916 #define DI_EI_CTRL7 5917 #define DI_EI_CTRL4 5914 #define DI_EI_CTRL5 5915 #define VDEC2_SCD_BAK_MV_X 11286 #define VDEC2_SCD_BAK_MV_Y 11287 #define VDIN1_MATRIX_COEF22 5141 #define SHARP_SR3_PK_CTRL0 12898 #define SHARP_SR3_PK_CTRL1 12899 #define P_MBREAK0_REG 4284615760 #define VIU_OSD2_CTRL_STAT2 6733 #define VDEC_ASSIST_TIMER0_LO 96 #define POWER_CTL_MC 2309 #define P_SANA_STREAM_START_ADDR 4291870852 #define P_DBLK_VLD_HCMD1 4284622316 #define P_DBLK_VLD_HCMD0 4284622320 #define P_DI_ARB_CTRL 4287650876 #define P_HEVC_MB_INFO 4284674224 #define HUE_ADJ_LIMT_REG 535 #define VPU_ARB4_V2_MMC_CTRL 10028 #define HEVC_DBLK_MB_WID_HEIGHT 14674 #define P_DOS_SECURE_CTL_INDEX 4284677632 #define P_VDEC2_PSCALE_DUMMY 4284654688 #define XVYCC_VADJ2_CURV_1 12651 #define HEVC_MPRED_INT_EN 12803 #define XVYCC_VADJ2_CURV_2 12652 #define XVYCC_VADJ2_CURV_0 12650 #define P_ENCT_DBG_PX_RST 4287656356 #define VIU_VD1_FMT_W 6761 #define XVYCC_VADJ2_CURV_3 12653 #define P_VP9_EMD_CMD 4284663044 #define HEVC_MBA_INC 15366 #define P_HCODEC_PSCALE_STATUS 4284638328 #define GAMMA_PROBE_CTRL 5257 #define P_VPP2_OSD_SCI_WH_M1 4287653668 #define P_DI_CHAN2_FMT_W 4287651556 #define VPP_VADJ_CTRL 7488 #define NR_ALP0_MIN_MAX 12825 #define P_DI_MEM_LUMA0_RPT_PAT 4287651720 #define AVS2_DEC_INFO 12627 #define P_CPV2_HS_ADDR 4287648396 #define VENC_STATA 7021 #define VIU_VD2_FMT_W 6793 #define VLC_VB_PRE_BUFF_HI 7452 #define DI_IF2_FMT_CTRL 8223 #define ISA_TIMERC 15443 #define SRSHARP0_NR_ALP1_MIN_MAX 12829 #define ISA_TIMERD 15444 #define ISA_TIMERA 15441 #define ISA_TIMERB 15442 #define ISA_TIMERG 15462 #define ISA_TIMERH 15463 #define ISA_TIMERE 15458 #define ISA_TIMERF 15461 #define HEVC_CINDEX4_REG 13102 #define ISA_TIMERI 15464 #define MINDEX0_REG 778 #define P_MC_MIX_RATIO1 4284621876 #define L_HSYNC_VE_ADDR 5208 #define P_MC_MIX_RATIO0 4284621872 #define P_HEVC_MPRED_MV_WR_ROW_JUMP 4284663900 #define P_HCODEC_DC_AC_CTRL 4284643348 #define P_PK_DRTFB_BP_CORING 4287678536 #define P_PK_ALP2_MIN_MAX 4287678596 #define VDEC2_IQIDCT_DEBUG_INFO_0 11791 #define NR_DB_FLT_RANDLUT 14138 #define HEVCD_IPP_DBG_DATA 13361 #define LDIM_BL_DATA_PORT 5199 #define P_HCODEC_VCOP_CTRL_REG 4284643328 #define VDEC2_PSCALE_PICO_START_Y 10519 #define VDEC2_PSCALE_PICO_START_X 10518 #define VENC_VIDEO_PROG_MODE 7016 #define P_VCOM_HSWITCH_ADDR 4287648368 #define VDIN1_BLKBAR_ROW_TH1_TH2 5220 #define P_NR4_MCNR_SAD2BET1_LUT1 4287674284 #define P_NR4_MCNR_SAD2BET1_LUT2 4287674288 #define P_HEVC_VCOP_CTRL_REG 4284676096 #define P_NR4_MCNR_SAD2BET1_LUT0 4287674280 #define P_NR4_MCNR_SAD2BET1_LUT3 4287674292 #define P_VDEC2_ANC17_CANVAS_ADDR 4284655236 #define P_AFBC_SIZE_IN 4287654792 #define VDIN_MATRIX_PRE_OFFSET2 4633 #define P_HEVC_MPRED_PIC_SIZE 4284663828 #define VDIN0_BLKBAR_CTRL1 4703 #define VDIN0_BLKBAR_CTRL0 4704 #define P_ENCT_VIDEO_PR_SCL 4287656332 #define P_VDEC2_CBREAK_CTRL 4284648676 #define OSDSR_YBIC_VCOEF 12598 #define P_HEVC_ANC27_CANVAS_ADDR 4284671660 #define P_HEVC_MPRED_REF_NUM 4284663844 #define HEVC_MDEC_EXTIF_STS0 14822 #define VDEC2_PSCALE_CTRL 10513 #define P_PSCALE_STATUS 4284621944 #define VIU2_OSD1_MATRIX_COEF20_21 7795 #define P_STH1_HE_ADDR 4287648324 #define HEVC_ASSIST_SCRATCH_N 12503 #define ENCI_VFIFO2VD_LINE_TOP_END 7196 #define HEVC_ASSIST_SCRATCH_J 12499 #define HEVC_ASSIST_SCRATCH_K 12500 #define P_HCODEC_ASSIST_MBOX1_MASK 4284629464 #define HEVC_ASSIST_SCRATCH_L 12501 #define HEVC_ASSIST_SCRATCH_M 12502 #define HCODEC_ME_MV_WEIGHT_23 8023 #define P_VIU_OSD1_CTRL_STAT2 4287654068 #define HEVC_CDB_DATA_REG 13116 #define P_IQIDCT_DEBUG_IDCT 4284627012 #define HEVC_HDEC_MC_MBRIGHT_RD 14642 #define P_VDEC2_WRRSP_FIFO_PICW_MC 4284655356 #define PSCALE_RBUF_START_BLKX 2341 #define PSCALE_RBUF_START_BLKY 2342 #define P_AIU_I2S_MUTE_SWAP 4291842096 #define P_EE_ASSIST_MBOX0_FIQ_SEL 4291854796 #define P_IGNORE_CONFIG 4284644360 #define VI_HIST_BLACK_WHITE_VALUE 11817 #define HEVC_ASSIST_SCRATCH_F 12495 #define HEVC_ASSIST_SCRATCH_G 12496 #define HEVC_ASSIST_SCRATCH_H 12497 #define HEVC_ASSIST_SCRATCH_I 12498 #define HEVC_ASSIST_SCRATCH_B 12491 #define HEVC_ASSIST_SCRATCH_C 12492 #define HEVC_ASSIST_SCRATCH_D 12493 #define P_VLC_VB_INT_PTR 4284642400 #define HEVC_ASSIST_SCRATCH_E 12494 #define MCDI_SAD_GAIN 12039 #define HEVC_ASSIST_SCRATCH_A 12490 #define P_VPU_ARB_DBG_STAT_L1C2 4287667928 #define P_VPU_ARB_DBG_STAT_L1C1 4287667920 #define HCODEC_HENC_SCRATCH_G 6864 #define P_VD1_IF0_GEN_REG3 4287654556 #define HEVC_ASSIST_SCRATCH_6 12486 #define HCODEC_HENC_SCRATCH_H 6865 #define P_VD1_IF0_GEN_REG2 4287654324 #define HEVC_ASSIST_SCRATCH_7 12487 #define HCODEC_HENC_SCRATCH_E 6862 #define P_HCODEC_ASSIST_MBOX2_CLR_REG 4284629476 #define HEVC_ASSIST_SCRATCH_8 12488 #define HCODEC_HENC_SCRATCH_F 6863 #define HEVC_ASSIST_SCRATCH_9 12489 #define HCODEC_HENC_SCRATCH_K 6868 #define HEVC_ASSIST_SCRATCH_2 12482 #define HCODEC_HENC_SCRATCH_L 6869 #define HEVC_ASSIST_SCRATCH_3 12483 #define HCODEC_HENC_SCRATCH_I 6866 #define HEVC_ASSIST_SCRATCH_4 12484 #define HCODEC_HENC_SCRATCH_J 6867 #define HEVC_ASSIST_SCRATCH_5 12485 #define HCODEC_HENC_SCRATCH_M 6870 #define HEVC_ASSIST_SCRATCH_0 12480 #define HCODEC_HENC_SCRATCH_N 6871 #define HEVC_ASSIST_SCRATCH_1 12481 #define ENCT_VIDEO_PB_OFFST 7269 #define P_AUDIN_FIFO1_CTRL 4291875040 #define HCODEC_HENC_SCRATCH_7 6855 #define HCODEC_HENC_SCRATCH_8 6856 #define HCODEC_HENC_SCRATCH_5 6853 #define HCODEC_HENC_SCRATCH_6 6854 #define HCODEC_HENC_SCRATCH_9 6857 #define ACC0REG1 865 #define ACC0REG2 881 #define HCODEC_HENC_SCRATCH_C 6860 #define HCODEC_HENC_SCRATCH_D 6861 #define HCODEC_HENC_SCRATCH_A 6858 #define HCODEC_HENC_SCRATCH_B 6859 #define P_I2C_M_2_TOKEN_LIST1 4291940364 #define P_I2C_M_2_TOKEN_LIST0 4291940360 #define HCODEC_HENC_SCRATCH_0 6848 #define HCODEC_HENC_SCRATCH_3 6851 #define HCODEC_HENC_SCRATCH_4 6852 #define HCODEC_MFDIN_REG4_LNR0 4108 #define HCODEC_HENC_SCRATCH_1 6849 #define HCODEC_HENC_SCRATCH_2 6850 #define P_VCOP_CTRL_REG 4284626944 #define P_VDEC2_RV_AI_Y_X 4284659748 #define HCODEC_ASSIST_MBOX2_IRQ_REG 4216 #define P_HEVC_PSCALE_RBUF_START_BLKY 4284671128 #define NR2_MATNR_MTNB_BRT 6007 #define DI_INP_CANVAS0 6095 #define P_HCODEC_MDEC_PIC_DC_CTRL 4284638776 #define HEVC_MINDEX1_REG 13067 #define VPP_HSHARP_LUMA_GAIN 7509 #define P_HEVC_PSCALE_RBUF_START_BLKX 4284671124 #define WRRSP_FIFO_PICW_DBK 2494 #define P_NR4_MCNR_LUMA_DIF_CALC 4287674092 #define VCOM_SEL 9 #define P_DOS_VDEC_MCRCC_STALL_CTRL 4284677376 #define P_VPP_POSTBLEND_H_SIZE 4287657092 #define ENCT_VIDEO_VOFFST 7296 #define P_D2D3_INTF_CTRL0 4287653924 #define CIPLUS_KEY_WR 6396 #define QDCT_CONFIG 7937 #define VLD_MEM_VBUF2_RD_PTR 3156 #define P_VDEC2_WRRSP_CO_MB 4284655456 #define P_VPP_INT_LINE_NUM 4287657784 #define VENC_VIDEO_TST_VDCNT_STSET 7031 #define HEVC_ANC28_CANVAS_ADDR 14764 #define HEVC_MPRED_DBG2_DATA_0 12872 #define P_HCODEC_AVSP_IQ_CTL 4284643440 #define HEVC_MPRED_DBG2_DATA_2 12874 #define HEVC_MPRED_DBG2_DATA_1 12873 #define HEVC_MPRED_DBG2_DATA_3 12875 #define VLD_ERROR_MASK 3118 #define P_HEVC_SHIFT_STATUS 4284662828 #define HCODEC_ME_MV_WEIGHT_01 8022 #define RESET6_LEVEL 1062 #define VDEC2_PATTERN_CODE 11307 #define DI_PRE_HOLD 5939 #define LTI_DIR_CORE_ALPHA 12842 #define P_SPI_FLASH_SLAVE 4291903536 #define HCODEC_POWER_CTL_VLD 7176 #define P_DI_MTN_1_CTRL9 4287651504 #define P_DI_MTN_1_CTRL8 4287651500 #define DBLK_STRONG 2421 #define P_L_OEV2_VS_ADDR 4287647956 #define P_HEVC_PARSER_CMD_STATUS 4284662868 #define SRSHARP0_PK_CON_2DRTBPGAIN_TH_RATE 12811 #define ABUF_RD_PLY_RPT_LVL 1 #define VKS_IWIN_HSIZE 12551 #define MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS 7206 #define P_ENCP_MACV_ENDLINE 4287655712 #define P_VDEC2_CINDEX4_REG 4284648632 #define P_OEH_VS_ADDR 4287648360 #define VLC_ELEMENT_DATA 7457 #define QDCT_MB_MAGIC_WORD 7960 #define P_DI_MTN_1_CTRL1 4287651072 #define P_DI_MTN_1_CTRL3 4287651080 #define HEVCD_MCRCC_PERFMON_DATA 13556 #define P_DI_MTN_1_CTRL2 4287651076 #define P_DI_MTN_1_CTRL5 4287651088 #define P_DI_MTN_1_CTRL4 4287651084 #define P_DI_MTN_1_CTRL7 4287651496 #define P_DI_MTN_1_CTRL6 4287651492 #define MCDI_PD22_CHK_GAIN_OFFST_0 12103 #define MCDI_PD22_CHK_GAIN_OFFST_1 12104 #define AIFIFO2_TIME_STAMP_SYNC_0 5273 #define NR2_RO_POLAR3_NUMOFPIX 11677 #define AIFIFO2_TIME_STAMP_SYNC_1 5274 #define HEVC_DBLK_GCLK_OFF 14701 #define OEV2_SEL 1 #define P_HCODEC_V3_MV_SAD_TABLE 4284644812 #define P_DNR_DM_FLT_THD 4287673752 #define VDEC_ASSIST_MBOX2_IRQ_REG 120 #define VPP_VE_DITHER_CTRL 12576 #define PK_OS_ADPT_MISC 12837 #define ANC30_CANVAS_ADDR 2478 #define P_EE_ASSIST_MBOX2_MASK 4291854824 #define P_MCDI_MCVECWR_CTRL 4287675984 #define SRSHARP0_PK_DRTFB_LPF_MODE 12814 #define REG_CHROMA_CONTROL 48 #define PSCALE_MCMD_XSIZE 2339 #define P_VBO_LANE_OUTPUT 4287648212 #define P_VPU_PROT2_RPT_PAT 4287667608 #define P_ENCI_VFIFO2VD_LINE_BOT_START 4287656052 #define VDEC2_VLD_STATUS_CTRL 11264 #define SRSHARP0_NR_ALP0_MIN_MAX 12825 #define ABUF_WR_AHB_RST_PLS 3 #define VPP_VE_DITHER_LUT_1 12577 #define VPP_VE_DITHER_LUT_2 12578 #define P_HEVC_VLD_ERROR_MASK 4284674232 #define P_HCODEC_CINDEX6_REG 4284632256 #define VPP_VE_DITHER_LUT_3 12579 #define VPP_VE_DITHER_LUT_4 12580 #define VPP_VE_DITHER_LUT_5 12581 #define VPP_VE_DITHER_LUT_6 12582 #define P_L_STV2_HS_ADDR 4287647916 #define VPP_VE_DITHER_LUT_7 12583 #define VPP_VE_DITHER_LUT_8 12584 #define P_RESET0_REGISTER 4291825668 #define VPP_VE_DITHER_LUT_9 12585 #define L_OEV2_VS_ADDR 5173 #define VPP_WRAP_OSD2_MATRIX_COEF11_12 15730 #define L_STH1_HS_ADDR 5136 #define VDIN_HIST_V_START_END 4658 #define HEVC_HDEC_MC_MBRIGHT_IDX 14641 #define P_BLOCK_NUM 4284625064 #define MCDI_MOTION_REF_THD 12116 #define SHARP_DB_FLT_YC_THRD 12920 #define D2D3_CG_PARAM_1 11017 #define D2D3_CG_PARAM_2 11018 #define P_ENCT_VIDEO_VSO_END 4287656416 #define DNR_DM_AVG_VAR_DIF_THD 11626 #define P_VLD_MEM_VIFIFO_CURR_PTR 4284625156 #define VDIN_LDIM_STTS_HIST_REGION_IDX 4695 #define MBREAK2_REG 790 #define P_NR4_MCNR_GREEN_CLIP0 4287674176 #define P_NR4_MCNR_GREEN_CLIP2 4287674180 #define VENC_C656_CTRL 7011 #define PARSER_PARAMETER 14447 #define VPP_WRAP_OSD2_MATRIX_COEF23_24 15734 #define DI_MTN_CTRL1 5900 #define P_DET3D_HV_MUTE 4287651036 #define AUDIN_FIFO0_WRAP 13361 #define P_HCODEC_QDCT_MB_RD_PTR 4284644428 #define HEVC_MPRED_L0_REF10_POC 12842 #define ENCP_VIDEO_Y_OFFST 7048 #define P_VPP2_OSD_VSC_PHASE_STEP 4287653632 #define P_L_GAMMA_CNTL_PORT 4287647744 #define P_HCODEC_VLD_DBG_DATA 4284641532 #define P_VDEC2_ASSIST_MBOX2_FIQ_SEL 4284645868 #define MCDI_MCINFOWR_X 12184 #define MCDI_MCINFOWR_Y 12185 #define mLVDS_pair_num 5 #define VPU_WRARB_MODE_L2C1 10146 #define P_HEVC_DBLK_STS1 4284666936 #define P_HEVC_DBLK_STS0 4284666932 #define mLVDS_ins_reset 8 #define HEVC_MPC_E 13064 #define HEVC_MPC_D 13063 #define P_VKS_TOP_MISC 4287677476 #define P_NR_DB_FLT_PXI_THRD 4287683820 #define HEVC_VLD_MEM_VIFIFO_BUF_CNTL 15432 #define QDCT_VLC_QUANT_CTL_0 7996 #define QDCT_VLC_QUANT_CTL_1 7997 #define HEVC_MPC_P 13062 #define HEVC_MPC_W 13065 #define DC_CAV_LUT_DATAH 76 #define DC_CAV_LUT_DATAL 72 #define ASYNC_FIFO_SOURCE_MSB 24 #define MCDI_MCVECRD_CTRL 12183 #define MCDI_MC_COL_CFD_8 12160 #define MCDI_MC_COL_CFD_9 12161 #define MCDI_MC_COL_CFD_6 12158 #define MCDI_MC_COL_CFD_7 12159 #define MCDI_MC_COL_CFD_0 12152 #define MCDI_MC_COL_CFD_1 12153 #define MCDI_MC_COL_CFD_4 12156 #define P_DNR_STAT_Y_START_END 4287673380 #define MCDI_MC_COL_CFD_5 12157 #define CINDEX0_REG 810 #define MCDI_MC_COL_CFD_2 12154 #define MCDI_MC_COL_CFD_3 12155 #define P_VDIN_LFIFO_URG_CTRL 4287645816 #define P_MCDI_REL_DET_LPF_MSK_13_21 4287675624 #define P_HEVC_SAO_ABV_START_ADDR 4284667972 #define ENCP_DVI_VSO_BLINE_EVN 7218 #define P_RESET4_MASK 4291825744 #define HEVCD_MPP_ANC_CANVAS_DATA_ADDR 13505 #define P_IQIDCT_DEBUG_INFO_0 4284627004 #define P_VDIN_DOLBY_DSC_STATUS0 4287646196 #define VPU_CLK_GATE 10019 #define P_VDIN_DOLBY_DSC_STATUS2 4287646204 #define P_VDIN_DOLBY_DSC_STATUS1 4287646200 #define P_VDIN_DOLBY_DSC_STATUS3 4287645812 #define HEVC_MDEC_PICW_BUF_STATUS 14778 #define P_HEVC_DCAC_CPU_DATA 4284676180 #define VPU_WRARB_MODE_L1C2 10158 #define VPU_WRARB_MODE_L1C1 10132 #define P_ENCI_DVI_VSO_END_ODD 4287655972 #define P_ANC16_CANVAS_ADDR 4284622464 #define P_HEVC_CBREAK2_REG 4284665048 #define P_DCAC_CPU_DATA 4284627028 #define P_HCODEC_MC_MIX_RATIO1 4284638260 #define P_HCODEC_MC_MIX_RATIO0 4284638256 #define RDMA_SRAM_REGADDR 4385 #define HCODEC_ADV_MV_CTL2 8043 #define HCODEC_ADV_MV_CTL1 8042 #define HCODEC_ADV_MV_CTL0 8041 #define SRSHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 13420 #define P_HEVC_IQIT_SCALELUT_IDX_16_32 4284668956 #define HEVC_MDB_ADDR_REG 13083 #define P_HCODEC_DBLK_CTRL 4284638532 #define IE_CUR_REF_SEL 8008 #define VPP2_VADJ2_MC_MD 6470 #define P_L_DE_HE_ADDR 4287648072 #define VD1_IF0_RANGE_MAP_Y 6762 #define ENCI_VFIFO2VD_LINE_BOT_END 7198 #define HCODEC_VLC_INT_CONTROL 7472 #define GE2D_SRC2_CLIPY_START_END 177 #define VPP_POST2_MATRIX_COEF15_25 14759 #define P_VDEC2_LMEM_DMA_CTRL 4284648768 #define HEVC_ACC0REG2 13169 #define HEVC_ACC0REG1 13153 #define VPU_PROT2_X_START_END 10082 #define V3_LEFT_SMALL_MAX_SAD 8058 #define SHARP_SR3_DRTLPF_THETA 12915 #define VIU_OSD1_MATRIX_COEF11_12 6803 #define VPP_VE_ENABLE_CTRL 7585 #define GE2D_HSC_ADV_CTRL 191 #define P_VPP_VADJ2_BLACK_VAL 4287657568 #define ENCL_VIDEO_RGBIN_CTRL 7367 #define P_MEDIA_CPU_CTL 4291883396 #define SRSHARP1_DB_FLT_PXI_THRD 13434 #define DOS_SCRATCH9 16153 #define DOS_SCRATCH7 16151 #define DOS_SCRATCH8 16152 #define P_VD2_AFBC_VD_CFMT_CTRL 4287677996 #define P_VENC_UPSAMPLE_CTRL0 4287655312 #define P_VENC_UPSAMPLE_CTRL1 4287655316 #define P_VENC_UPSAMPLE_CTRL2 4287655320 #define P_VPU_ASYNC_WR_MODE2 4287667888 #define DOS_SCRATCH1 16145 #define P_VPU_ASYNC_WR_MODE1 4287667884 #define DOS_SCRATCH2 16146 #define DOS_SCRATCH0 16144 #define L_STH2_HS_ADDR 5140 #define DOS_SCRATCH5 16149 #define DOS_SCRATCH6 16150 #define P_VPU_ASYNC_WR_MODE0 4287667880 #define DOS_SCRATCH3 16147 #define DOS_SCRATCH4 16148 #define P_HEVC_STREAM_START_ADDR 4284662792 #define P_HCODEC_LMEM_DMA_CTRL 4284632384 #define P_WM_STATUS_RAM_RO 4287678248 #define P_ENCP_MACV_TIME_UP 4287655732 #define VPP_CCORING_CTRL 7584 #define P_VPU_WRARB_WEIGH1_SLV_L1C1 4287667804 #define P_VPU_WRARB_WEIGH1_SLV_L1C2 4287667908 #define P_ANC1_CANVAS_ADDR 4284622404 #define P_VI_HIST_H_START_END 4287674372 #define ASYNC_FIFO_REG0 10240 #define ASYNC_FIFO_REG1 10241 #define ASYNC_FIFO_REG2 10242 #define ASYNC_FIFO_REG3 10243 #define ASYNC_FIFO_REG4 10244 #define ASYNC_FIFO_REG5 10245 #define VDIN1_MATRIX_COEF00_01 5137 #define P_VP9_MEM_OPERATION 4284663092 #define P_VD2_IF0_PROT_CNTL 4287654456 #define P_VSYNC_HS_ADDR 4287648612 #define DI_IF2_URGENT_CTRL 8225 #define ENCL_VIDEO_FILT_CTRL 7362 #define VDIN1_HIST_SPL_VAL 5172 #define HCODEC_MC_OM_MB_XY 6415 #define P_HEVC_MC_OM_MB_XY 4284671036 #define ENCP_VIDEO_VSO_BEGIN 7081 #define MSP 768 #define HEVC_MPRED_L0_REF09_POC 12841 #define HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR 13439 #define ENCP_VIDEO_BLANKPR_VAL 7092 #define P_VP9D_MPP_REFINFO_TBL_ACCCONFIG 4284666120 #define FST_BAK_MV_Y 3093 #define FST_BAK_MV_X 3092 #define VIU2_OSD1_CTRL_STAT 7728 #define P_VLTI_BST_GAIN 4287678700 #define VPP_MATRIX_COEF00_01 7520 #define VPP_OSD_HSC_INI_PHASE 7620 #define P_ENCT_VFIFO2VD_LINE_TOP_END 4287656080 #define MCDI_REL_DET_LUT_12_15 12097 #define DOLBY_TV_CLKGATE_CTRL 13297 #define P_MCDI_PD_22_CHK_FLG_CNT 4287675768 #define SRSHARP0_SATPRT_LMT_RGB 12918 #define OSD_BLENDO_V_START_END 6826 #define DI_MEM_URGENT_CTRL 8357 #define VDEC2_MC_PIC_INFO 10498 #define P_VDEC2_ASSIST_TIMER1_LO 4284645768 #define ENCI_TST_Y 7186 #define HEVC_ANC4_CANVAS_ADDR 14740 #define VIU2_VD1_IF0_LUMA_FIFO_SIZE 7779 #define VPP_GAINOFF_CTRL3 7533 #define VPP_GAINOFF_CTRL4 7534 #define P_QP_VALUE_REG 4284624916 #define VPP_GAINOFF_CTRL1 7531 #define VPP_GAINOFF_CTRL2 7532 #define VPP_GAINOFF_CTRL0 7530 #define P_ENCP_SYNC_TO_PIXEL 4287656220 #define ENCL_VIDEO_VSO_END 7352 #define P_ENCP_MACV_TIME_LO 4287655728 #define HCODEC_VLD_DBG_INDEX 7230 #define MC_WT_PRED_CTRL 2370 #define PARSER_AV_WRAP_COUNT 14481 #define MIPI_DSI_DWC_VID_PKT_SIZE_OS 7183 #define D2D3_DBLD_STATUS 11069 #define AIU_MEM_IEC958_MEM_CTL 5241 #define SRSHARP1_DEJ_ALPHA 13413 #define HEVC_CBREAK_CTRL 13113 #define POWER_CTL_VLD 3080 #define P_OSD_DB_FLT_LUMA_THRD 4287677704 #define P_L_OEV3_VS_ADDR 4287647972 #define ABUF_FIFO_CTL0 15481 #define VDEC2_CINT_VEC_BASE 8994 #define P_HCODEC_VLC_VB_START_PTR 4284642368 #define P_VPP2_HSC_REGION4_ENDP 4287652936 #define P_OEV1_VE_ADDR 4287648456 #define P_AIU_MEM_I2S_BUF_CNTL 4291842520 #define P_VDEC2_ASSIST_TIMER1_HI 4284645772 #define SRSHARP0_SR3_DERING_LUMA2PKGAIN_4TO6 12909 #define P_SPI_FLASH_SLAVE1 4291903540 #define HEVC_CCPU_INTR_MSK 13092 #define P_SPI_FLASH_SLAVE2 4291903544 #define P_SPI_FLASH_SLAVE3 4291903548 #define P_VENC_VIDEO_TST_CLRBAR_STRT 4287655380 #define MIPI_DSI_DWC_LP_WR_TO_CNT_OS 7202 #define HCODEC_HDEC_MC_MBRIGHT_RD 6450 #define VPP_OSDSC_DITHER_LUT_2 12594 #define VPP_OSDSC_DITHER_LUT_1 12593 #define VLD_SHIFT_STATUS 3131 #define VPP_OSDSC_DITHER_LUT_4 12596 #define VPP_OSDSC_DITHER_LUT_3 12595 #define VENC_VDAC_DAC5_GAINCTRL 7162 #define VPP_OSDSC_DITHER_LUT_6 12598 #define VPP_OSDSC_DITHER_LUT_5 12597 #define VPP_OSDSC_DITHER_LUT_8 12600 #define VPP_OSDSC_DITHER_LUT_7 12599 #define VPP_OSDSC_DITHER_LUT_9 12601 #define SPICC0_LD_WADDR 19469 #define HCODEC_MC_HCMD_H 6474 #define SANA_SHIFT_BYTE_COUNT 12332 #define HCODEC_MC_HCMD_L 6475 #define VIU_OSD_BLEND_BLEND1_SIZE 14780 #define P_NR2_SAD2NORM_LUT3 4287651204 #define P_VPP_VSC_PHASE_CTRL 4287657012 #define P_NR2_SAD2NORM_LUT2 4287651200 #define P_NR2_SAD2NORM_LUT1 4287651196 #define P_NR2_SAD2NORM_LUT0 4287651192 #define P_ENCI_VFIFO2VD_PIXEL_END 4287656040 #define EE_ASSIST_MBOX1_MASK 8310 #define VDIN_MATRIX_OFFSET0_1 4630 #define DI_CHAN2_CHROMA_Y0 6138 #define P_VDEC2_MDEC_PIC_DC_STATUS 4284655164 #define P_SHARP_SR2_YBIC_VCOEF0 4287678832 #define VPU_VDISP_ASYNC_HOLD_CTRL 10053 #define P_SHARP_SR2_YBIC_VCOEF1 4287678836 #define VDEC_ASSIST_DMA_INT_MSK2 103 #define DI_CHAN2_CHROMA_X0 6137 #define P_VLC_VB_SW_RD_PTR 4284642384 #define P_RDMA_AHB_END_ADDR_MAN 4287644676 #define P_HEVC_CM_BODY_LENGTH 4284668060 #define VIU2_OSD2_BLK1_CFG_W4 7781 #define HEVC_MDEC_PIC_DC_MUX_CTRL 14733 #define VIU2_OSD2_BLK1_CFG_W3 7746 #define VIU2_OSD2_BLK1_CFG_W2 7745 #define VIU2_OSD2_BLK1_CFG_W1 7744 #define VIU2_OSD2_BLK1_CFG_W0 7743 #define HCODEC_ANC11_CANVAS_ADDR 6555 #define P_L_STV1_HS_ADDR 4287647900 #define ENCI_SYNC_TO_PIXEL 7235 #define AIU_CRC_SHIFT_REG 5190 #define ENCI_SYNC_HSO_END 6923 #define P_CTI_DIR_ALPHA 4287678636 #define ENCP_VIDEO_MACV_OFFST 7052 #define ASYNC_FIFO_SOURCE_LSB 23 #define P_HEVC_MDEC_PICR_BUF_STATUS 4284671716 #define VENC_VDAC_DAC4_OFFSET 7161 #define P_CIPLUS_ENDIAN 4291847160 #define SRSHARP1_SATPRT_LMT_RGB 13430 #define P_AUDIN_ATV_DEMOD_CTRL 4291875648 #define VLC_PIC_INFO 7474 #define HEVC_CDB_ADDR_REG 13115 #define VPU_PROT3_MMC_CTRL 10026 #define P_HCODEC_DBLK_GCLK_FREE 4284638640 #define P_SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 4287678896 #define P_VDEC2_ANC18_CANVAS_ADDR 4284655240 #define HEVC_SAO_INT_EN 13827 #define VPU_RDARB_WEIGH0_SLV_L1C1 10130 #define P_HEVC_ASSIST_GCLK_EN 4284661772 #define VPU_RDARB_WEIGH0_SLV_L1C2 10139 #define VIU2_OSD2_BLK2_CFG_W0 7747 #define VIU2_OSD2_BLK2_CFG_W1 7748 #define VIU2_OSD2_BLK2_CFG_W2 7749 #define VIU2_OSD2_BLK2_CFG_W3 7750 #define VPP_HSHARP_CHROMA_THRESH01 7507 #define VIU2_OSD2_BLK2_CFG_W4 7782 #define P_BYTE_ALIGN_PEAK_HI 4284625004 #define P_NR_TI_DNLP_BLEND 4287678628 #define VDEC2_PSCALE_BMEM_DAT 10528 #define VPP_HSHARP_CHROMA_THRESH23 7508 #define HEVC_MDEC_PIC_DC_STATUS 14735 #define HCODEC_MFDIN_REG5_LNR1 4109 #define P_HEVC_MC_CTRL_REG 4284670976 #define P_VDIN_MATRIX_HL_COLOR 4287645860 #define SRSHARP0_SR3_DERING_CTRL 12907 #define VDIN_ASFIFO_CTRL3 4719 #define VDIN_ASFIFO_CTRL2 4623 #define VDIN_ASFIFO_CTRL1 4617 #define VDIN_ASFIFO_CTRL0 4616 #define GE2D_ANTIFLICK_ALPHA_FILT0 222 #define GE2D_ANTIFLICK_ALPHA_FILT1 223 #define GE2D_ANTIFLICK_ALPHA_FILT2 224 #define GE2D_ANTIFLICK_ALPHA_FILT3 225 #define P_VDEC2_MINDEX4_REG 4284648504 #define P_BYTE_ALIGN_PEAK_LO 4284625008 #define P_C656_VS_LNED_E 4287655824 #define P_MCDI_MOTION_REF_THD 4287675728 #define P_C656_VS_LNED_O 4287655828 #define RESET0_LEVEL 1056 #define MDB_ADDR_REG 795 #define ENCL_VFIFO2VD_LINE_TOP_START 7315 #define VPP_WRAP_OSD3_MATRIX_CLIP 15800 #define P_ENCT_VFIFO2VD_CTL2 4287656092 #define P_DNR_DB_YVDELTA_GAIN 4287673432 #define RESET3_REGISTER 1028 #define VIU_VD1_FMT_CTRL 6760 #define P_VIU2_OSD2_BLK3_CFG_W0 4287658268 #define P_VIU2_OSD2_BLK3_CFG_W1 4287658272 #define P_VIU2_OSD2_BLK3_CFG_W2 4287658276 #define P_VIU2_OSD2_BLK3_CFG_W3 4287658280 #define P_VIU2_OSD2_BLK3_CFG_W4 4287658396 #define P_DBLK_CB_BFILT 4284622184 #define P_HCODEC_DBLK_Y_HFILT 4284638576 #define VPP_VSC_REGION3_PHASE_SLOPE 7435 #define P_D2D3_DBLD_CG_PARAM 4287671364 #define P_HCODEC_M4_CONTROL_REG 4284641444 #define LTI_CTI_DF_GAIN 12844 #define HCODEC_VLC_DC_BUF_STATUS 7492 #define HEVC_CABAC_LEFT_INFO 12574 #define P_VDIN_MATRIX_PROBE_POS 4287645864 #define VLC_DELTA_QP 7485 #define P_AUD_RESAMPLE_COEF0 4291875596 #define P_HEVC_PSCALE_FILT0_COEF0 4284671076 #define P_AUD_RESAMPLE_COEF2 4291875604 #define P_HEVC_PSCALE_FILT0_COEF1 4284671080 #define P_AUD_RESAMPLE_COEF1 4291875600 #define P_AUD_RESAMPLE_COEF4 4291875612 #define P_AUD_RESAMPLE_COEF3 4291875608 #define P_VDEC2_DBLK_CR_FILT 4284654976 #define P_VDEC2_INTRA_QUANT_MATRIX 4284659720 #define VPP_OFIFO_URG_CTRL 7640 #define P_GAMMA_VCOM_HSWITCH_ADDR 4287648268 #define HEVCD_IPP_TOP_FRMCTL 13319 #define SANA_STREAM_START_ADDR 12321 #define P_VD2_AFBC_VD_CFMT_H 4287678020 #define HEVC_CSFTINT1 13119 #define HEVC_CSFTINT0 13118 #define P_MCDI_REL_BADW_THD_MIN_MAX 4287675536 #define P_CURR_CANVAS_CTRL 4284622540 #define VDEC2_ANC25_CANVAS_ADDR 10665 #define DNR_DM_COR_DIF 11621 #define SRSHARP1_PK_ALP2_ERR2CURV_LIMIT 13344 #define HEVC_SAO_PIC_SIZE_LCU 13830 #define ENCP_VIDEO_HSPULS_SWITCH 7066 #define P_VD2_AFBC_VD_CFMT_W 4287678000 #define LCD_PWM0_LO_ADDR 5308 #define VIU_OSD2_MATRIX_HL_COLOR 6843 #define VPP2_MISC 7718 #define HCODEC_VLD_DBG_DATA 7231 #define P_HEVCD_MCRCC_CTL3 4284666824 #define P_HCODEC_ASSIST_MBOX0_MASK 4284629448 #define P_HEVCD_MCRCC_CTL2 4284666820 #define P_HEVCD_MCRCC_CTL1 4284666816 #define VDIN_SCALE_COEF 4609 #define ENCI_SYNC_VOFFST 6929 #define ENCL_TST_Y 7322 #define SRSHARP1_SHARP_SR2_YBIC_VCOEF1 13405 #define SRSHARP1_PK_ALP2_MIERR_CORING 13342 #define VPU_MCVEC_MMC_CTRL 10029 #define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 13404 #define VENC_DVI_SETTING_MORE 7249 #define DCAC_CPU_DATA 3605 #define VDIN0_MEAS_HS_COUNT 4702 #define VPP_OSD_VSC_PHASE_STEP 7616 #define VDEC2_AV_SCRATCH_A 10698 #define ENCT_VFIFO2VD_LINE_BOT_START 7205 #define SRSHARP1_SATPRT_CTRL 13428 #define VDEC2_AV_SCRATCH_6 10694 #define VDEC2_AV_SCRATCH_7 10695 #define VDEC2_AV_SCRATCH_8 10696 #define VDEC2_AV_SCRATCH_9 10697 #define VDEC2_AV_SCRATCH_2 10690 #define VDEC2_AV_SCRATCH_3 10691 #define VDEC2_AV_SCRATCH_4 10692 #define VDEC2_AV_SCRATCH_5 10693 #define VDEC2_AV_SCRATCH_N 10711 #define VDEC2_AV_SCRATCH_J 10707 #define VDEC2_AV_SCRATCH_K 10708 #define VDEC2_AV_SCRATCH_L 10709 #define VDEC2_AV_SCRATCH_M 10710 #define VDEC2_AV_SCRATCH_F 10703 #define VDEC2_AV_SCRATCH_G 10704 #define VDEC2_AV_SCRATCH_H 10705 #define P_HCODEC_MB_SKIP_RUN 4284642636 #define VDEC2_AV_SCRATCH_I 10706 #define VDEC2_AV_SCRATCH_B 10699 #define VDEC2_AV_SCRATCH_C 10700 #define VDEC2_AV_SCRATCH_D 10701 #define VDEC2_AV_SCRATCH_E 10702 #define P_VPU_MCINF_MMC_CTRL 4287667384 #define P_HEVC_MPRED_L0_REF02_POC 4284663944 #define P_HCODEC_MFDIN_REGC_MBLP 4284629072 #define VDIN1_SC_MISC_CTRL 5131 #define I2C_M_2_TOKEN_LIST0 29698 #define I2C_M_2_TOKEN_LIST1 29699 #define I2C_M_ERROR 3 #define VDEC2_AV_SCRATCH_0 10688 #define VDEC2_AV_SCRATCH_1 10689 #define P_VPP_BLEND_VD2_V_START_END 4287657084 #define P_NR4_MCNR_LUMACUR_CAL_PRAM 4287674100 #define P_VDEC2_PSCALE_CTRL 4284654660 #define CIPLUS_ENDIAN 6398 #define HEVC_ASSIST_TIMER0_LO 12384 #define HEVC_RV_AI_MB_COUNT 15884 #define P_SPICC1_LD_CNTL0 4291907624 #define ABUF_WR_CUR_FF_CNT_LSB 16 #define P_SPICC1_LD_CNTL1 4291907628 #define P_DOS_VDEC_INT_EN 4284677140 #define P_IE_CUR_REF_SEL 4284644640 #define P_LDIM_STTS_HIST_READ_REGION 4287654728 #define AFBC_DEC_DEF_COLOR 6883 #define P_DI_IF1_FMT_CTRL 4287651788 #define P_VDEC2_CINDEX3_REG 4284648628 #define NR2_MET_NM_CTRL 5957 #define VDEC2_MDEC_DOUBLEW_STATUS 10723 #define XVYCC_LUT_G_DATA_PORT 12641 #define ABUF_RD_AHB_RST_PLS 3 #define P_LDIM_STTS_MATRIX_PROBE_POS 4287654708 #define HEVC_ASSIST_TIMER0_HI 12385 #define P_ENCP_MACV_TS_CNT_MAX_L 4287655716 #define P_VPP_VSC_REGION12_STARTP 4287656980 #define P_ENCP_MACV_TS_CNT_MAX_H 4287655720 #define LTI_CTI_DIR_AC_DBG 12845 #define P_VLD_TIME_STAMP_0 4284625200 #define P_VLD_TIME_STAMP_1 4284625204 #define P_HCODEC_LAST_MVY 4284641480 #define P_VLD_TIME_STAMP_2 4284625208 #define P_HCODEC_LAST_MVX 4284641476 #define P_VLD_TIME_STAMP_3 4284625212 #define P_MCDI_RO_GMV_LOCK_FLG 4287676080 #define P_VPU_VLOCK_RO_VS_O_DIST 4287676488 #define VDEC2_VLD_MEM_SWAP_CTL 11350 #define P_L_GAMMA_PROBE_COLOR_H 4287647788 #define HEVC_STREAM_SWAP_ADDR 12596 #define AIU_AIFIFO_GBIT 5250 #define ENCT_VIDEO_MODE 7271 #define mLVDS2_PORT_SWAP 3 #define ENCT_TST_VDCNT_STSET 7215 #define HEVC_SHIFT_EMULATECODE 12554 #define P_VPU_VLOCK_LOOP1_PHSDIF_TGT 4287676468 #define MCDI_MOTION_PARADOX_THD 12114 #define P_VDEC2_PSCALE_SRCKEY_CTRL1 4284654764 #define P_VDEC2_PSCALE_SRCKEY_CTRL0 4284654760 #define P_MCDI_LMV_LOCK_ABS_DIF_THD 4287675688 #define P_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR 4284666240 #define HCODEC_VLC_INT_CONTROL_INTER 7471 #define ASSIST_SPARE16_REG2 8279 #define P_L_GAMMA_PROBE_COLOR_L 4287647784 #define ASSIST_SPARE16_REG1 8278 #define NR2_MATNR_MTN_CRTL 5994 #define SPICC0_TESTREG 19463 #define VPU_PROT2_RPT_PAT 10086 #define P_VD2_IF0_CANVAS1 4287654344 #define P_VD2_IF0_CANVAS0 4287654340 #define P_D2D3_MBDG_PARAM_6 4287671420 #define P_D2D3_MBDG_PARAM_7 4287671424 #define P_VD2_IF0_LUMA0_RPT_PAT 4287654384 #define P_VDEC2_MCRCC_CTL1 4284655104 #define P_D2D3_MBDG_PARAM_2 4287671404 #define P_D2D3_MBDG_PARAM_3 4287671408 #define GE2D_SRC1_RANGE_MAP_Y_CTRL 227 #define P_VDEC2_MCRCC_CTL3 4284655112 #define P_D2D3_MBDG_PARAM_4 4287671412 #define P_VDEC2_MCRCC_CTL2 4284655108 #define P_D2D3_MBDG_PARAM_5 4287671416 #define P_D2D3_MBDG_PARAM_0 4287671396 #define P_D2D3_MBDG_PARAM_1 4287671400 #define SPICC1_ENHANCE_CNTL 21518 #define P_HEVC_MC_MBBOT_ST_EVEN_ADDR 4284671248 #define P_VPU_VLOCK_MISC_CTRL 4287676420 #define P_HEVC_ANC15_CANVAS_ADDR 4284671612 #define P_CBREAK0_REG 4284615888 #define MBREAK3_REG 791 #define CURR_CANVAS_CTRL 2483 #define P_PARSER_INT_STATUS 4291879344 #define P_HEVCD_MPP_DECOMP_PERFMON_DATA 4284666648 #define P_VPP_VD2_CLIP_MISC0 4287657868 #define P_VPP_VD2_CLIP_MISC1 4287657872 #define P_HEVC_DC_SCALER 4284676112 #define VPP_GCLK_CTRL0 7538 #define VPP_GCLK_CTRL1 7539 #define NR_ALP1_MIN_MAX 12829 #define VPP_GCLK_CTRL2 7666 #define FRM_PIC 256 #define P_VLD_MEM_VIFIFO_MEM_CTL 4284625224 #define HEVC_IQIT_IF_WAIT_CNT 12598 #define P_HCODEC_QDCT_JPEG_QUANT_ADDR 4284644512 #define VP9_DECODING_INFO 12623 #define P_NR4_MCNR_LUMA_ENH_CTRL 4287674080 #define VDEC2_WRRSP_VLD 10714 #define SRSHARP0_SR3_PK_CTRL0 12898 #define SRSHARP0_SR3_PK_CTRL1 12899 #define P_AIU_CRC_IREG 4291842332 #define ENCP_MACV_TIME_LO 7116 #define P_VDEC2_IMEM_DMA_ADR 4284648708 #define P_VPP_VE_DITHER_LUT_3 4287677580 #define P_VPP_VE_DITHER_LUT_4 4287677584 #define P_VPP_VE_DITHER_LUT_1 4287677572 #define P_VPP_VE_DITHER_LUT_2 4287677576 #define P_VPP_VE_DITHER_LUT_7 4287677596 #define P_HCODEC_MBREAK_TYPE 4284632160 #define P_VPP_VE_DITHER_LUT_8 4287677600 #define P_VPP_VE_DITHER_LUT_5 4287677588 #define P_VPP_VE_DITHER_LUT_6 4287677592 #define P_HEVC_MPRED_L1_REF01_POC 4284664004 #define VIU_OSD1_OETF_CTL 6876 #define P_VPP_VE_DITHER_LUT_9 4287677604 #define SRSHARP1_PK_CIRFB_BLEND_GAIN 13331 #define DOS_APB_ERR_CTRL 16131 #define ENCI_VIDEO_MODE 6912 #define HCODEC_DCAC_CPU_DATA 7701 #define VPU_PROT1_RPT_LOOP 10069 #define VPP_VDO_MEAS_VS_COUNT_LO 7594 #define P_VIU2_VD1_IF0_GEN_REG 4287658304 #define HEVC_MPRED_ABV_START_ADDR 12818 #define SRSHARP1_NR_ALP1_ERR2CURV_LIMIT 13340 #define P_VDIN_LDIM_STTS_HIST_SET_REGION 4287646048 #define P_VDEC2_ASSIST_MBOX0_IRQ_REG 4284645824 #define P_EE_ASSIST_MBOX1_MASK 4291854808 #define P_HEVC_QP_WRITE 4284668964 #define VD2_AFBC_CONV_CTRL 12676 #define HCODEC_MPSR 4865 #define VENC_VDAC_DAC3_OFFSET 7159 #define P_IQ_QUANT 4284627036 #define P_STV1_VE_ADDR 4287648424 #define P_DI_POST_CTRL 4287650820 #define LMEM_DMA_CTRL 848 #define HCODEC_QDCT_ADV_CONFIG 7988 #define SRSHARP0_OFFSET 0 #define P_HCODEC_MC_CTRL_GCLK_CTRL 4284638516 #define P_HCODEC_FST_BAK_MV_X 4284641360 #define P_HCODEC_FST_BAK_MV_Y 4284641364 #define P_NR2_POLAR3_CTRL 4287673968 #define AIU_MEM_AIFIFO2_MAN_WP 5231 #define V3_F_ZERO_CTL_0 8052 #define P_DI_CANVAS_URGENT1 4287650860 #define V3_F_ZERO_CTL_1 8053 #define P_DI_CANVAS_URGENT2 4287650872 #define P_DI_CANVAS_URGENT0 4287650856 #define ENCP_MACV_TIME_UP 7117 #define P_HCODEC_SAD_CONTROL 4284644620 #define VDEC2_DBLK_MB_WID_HEIGHT 10578 #define HEVC_IQIT_CLK_RST_CTRL 14080 #define P_ENCP_DACSEL_1 4287655992 #define P_ENCP_DACSEL_0 4287655988 #define P_HEVC_VLD_STATUS 4284674280 #define ENCP_DVI_VSO_END_ODD 7225 #define VPP_EOTF_COEF22_RS 12757 #define HEVC_QP_WRITE 14089 #define P_DEVICE_MMCP_CNTL 4291883308 #define VDEC2_ASSIST_MBOX2_IRQ_REG 8312 #define P_HCODEC_MB_WIDTH 4284641316 #define HCODEC_ANC13_CANVAS_ADDR 6557 #define VIU_OSD_BLEND_DUMMY_ALPHA 14778 #define P_VPU_PROT3_Y_LEN_STEP 4287667664 #define NR4_NM_Y_CFG 14100 #define GE2D_SRC2_KEY_MASK 209 #define P_AIFIFO_TIME_STAMP_CNTL 4291842624 #define AIU_MEM_AIFIFO2_MAN_RP 5232 #define XVYCC_INV_LUT_U_DATA_PORT 12635 #define VLC_PIC_POSITION 7475 #define AUDOUT_CTRL1 13441 #define ENCL_VIDEO_HAVON_BEGIN 7346 #define P_HEVC_CM_COLOR 4284668072 #define DI_MEM_CHROMA0_RPT_PAT 6115 #define ENCI_VIDEO_FSC_ADJ 6914 #define INV_CNT_ADDR 5312 #define HEVC_PARSER_CMD_SKIP_2 12586 #define HEVC_PARSER_CMD_SKIP_1 12585 #define HEVC_PARSER_CMD_SKIP_0 12584 #define P_DC_AC_SCALE_DIV 4284626972 #define MCDI_MCINFOWR_CTRL 12186 #define P_HCODEC_MDEC_PICW_BUF2_STATUS 4284638964 #define AUDOUT_BUF0_STA 13442 #define I2C_M_0_WDATA_REG0 31748 #define VPP_WRAP_OSD1_MATRIX_COEF02_10 15713 #define VPU_VLOCK_OUTPUT0_CAPT_LMT 12297 #define I2C_M_0_WDATA_REG1 31749 #define NR4_DRT_CTRL 11684 #define AUDIN_FIFO2_START 13381 #define P_HCODEC_CSP 4284632192 #define DBLK_CTRL1 2431 #define IE_CONTROL 8000 #define P_SLICE_START_BYTE_01 4284624944 #define P_ENCL_VIDEO_HAVON_BEGIN 4287656648 #define VPU_PROT2_Y_START_END 10083 #define P_PSCALE_CANVAS_RD_ADDR 4284622000 #define P_AIU_CODEC_ADC_LRCLK_CTRL 4291842212 #define P_VDEC2_MC_HALF_PEL_ONE 4284654604 #define PARSER_INSERT_DATA 14448 #define P_SLICE_START_BYTE_23 4284624948 #define SAT_SRC_NODE_REG 515 #define P_AIU_AIFIFO_CLB 4291842572 #define P_ENCP_VIDEO_HAVON_END 4287655564 #define HCODEC_MDEC_PIC_DC_STATUS 6543 #define QDCT_MB_RD_PTR 7955 #define HCODEC_ASSIST_MBOX0_CLR_REG 4209 #define VENC_VDAC_DAC2_FILT_CTRL0 7260 #define VENC_VDAC_DAC2_FILT_CTRL1 7261 #define QUANT_TABLE_DATA 7993 #define P_VDEC_ASSIST_MBX_SSEL 4284612884 #define P_VLC_VB_WR_PTR 4284642376 #define SANA_SHIFT_EMULATECODE 12329 #define P_VBO_CTRL_H 4287648132 #define P_VBO_CTRL_L 4287648128 #define P_QUANT_TABLE_DATA 4284644580 #define VBO_INTR_STATE 5368 #define PFIFO_RD_PTR 14439 #define P_PK_CIRFB_LPF_MODE 4287678516 #define P_HEVC_GCLK_EN 4284671500 #define P_STV1_VS_ADDR 4287648420 #define P_DI_MEM_FMT_CTRL 4287651736 #define P_ENCT_SYNC_TO_LINE_EN 4287656232 #define I2C_M_2_RDATA_REG0 29702 #define HEVCD_IPP_DYNCLKGATE_CONFIG 13344 #define P_L_STH2_HS_ADDR 4287647824 #define I2C_M_2_RDATA_REG1 29703 #define MCDI_REL_DET_COL_CFD_THD 12098 #define P_HCODEC_IE_SAD_1 4284644760 #define VPP_BLUE_STRETCH_2 7581 #define P_HCODEC_IE_SAD_0 4284644756 #define VPP_BLUE_STRETCH_3 7582 #define P_HCODEC_IE_SAD_3 4284644768 #define P_HCODEC_IE_SAD_2 4284644764 #define VPP2_MATRIX_OFFSET0_1 6501 #define HCODEC_WRRSP_FIFO_PICW_MC 6591 #define GE2D_SRC1_RANGE_MAP_CR_CTRL 229 #define P_VPU_DI_NRWR_MMC_CTRL 4287667244 #define P_CINDEX0_REG 4284615848 #define P_ENCI_SYNC_HSO_END 4287654956 #define VDEC2_VLD_MEM_VBUF_RD_PTR 11347 #define P_VENC_INTCTRL 4287655352 #define I2C_M_2_CONTROL_REG 29696 #define P_DC_CAV_LUT_ADDR 4284710992 #define HEVC_WRRSP_LMEM 13139 #define AUDIN_FIFO0_REQID 13360 #define VPP_BLUE_STRETCH_1 7580 #define VLD_MEM_VBUF_RD_PTR 3155 #define SPDIF_CLKNUM_96K 18 #define P_HCODEC_VLC_VB_PRE_BUFF_HI 4284642416 #define HCODEC_MC_WT_PRED_CTRL 6466 #define VDIN_BLKBAR_ROW_TH1_TH2 4708 #define P_HCODEC_VLC_HCMD_CUR_INFO 4284642448 #define P_MCDI_QME_LPF_MSK 4287675512 #define VIU2_VD1_IF0_LUMA_Y0 7764 #define VIU2_VD1_IF0_LUMA_Y1 7768 #define P_MCDI_REL_DET_RPT_CHK_GAIN_QMV 4287675600 #define P_ME_SUB_ACT_CTL 4284644732 #define HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR 13504 #define P_MCDI_RO_HIGH_VERT_FRQ_FLG 4287676076 #define VIU2_VD1_IF0_LUMA_X0 7763 #define P_ASYNC_FIFO2_REG0 4291858432 #define VIU2_VD1_IF0_LUMA_X1 7767 #define P_ASYNC_FIFO2_REG1 4291858436 #define P_ASYNC_FIFO2_REG2 4291858440 #define P_ASYNC_FIFO2_REG3 4291858444 #define P_ASYNC_FIFO2_REG4 4291858448 #define P_ASYNC_FIFO2_REG5 4291858452 #define P_ENCI_VIDEO_EN 4287655260 #define P_AIU_MEM_AIFIFO_CONTROL 4291842592 #define SRSHARP0_LTI_DIR_CORE_ALPHA 12842 #define MC_RESET 8 #define HEVC_MINDEX3_REG 13069 #define HCODEC_VLD_SHIFT_STATUS 7227 #define VIU_OSD2_BLK2_CFG_W3 6726 #define VIU_OSD2_BLK2_CFG_W2 6725 #define VIU_OSD2_BLK2_CFG_W4 6758 #define VIU_OSD2_BLK2_CFG_W1 6724 #define VIU_OSD2_BLK2_CFG_W0 6723 #define VDEC2_VLD_C3D 11325 #define VDEC2_VLD_C39 11321 #define P_VPU_HDMI_DITH_CNTL 4287668208 #define VDEC2_VLD_C38 11320 #define P_DI_CHAN2_RANGE_MAP_CB 4287651540 #define P_VBO_FSM_HOLDER_L 4287648232 #define P_VBO_FSM_HOLDER_H 4287648236 #define P_ENCP_VIDEO_SYNC_OFFST 4287655468 #define DECOMB_BLND_CON1 11654 #define P_HEVC_BLOCK_NUM 4284674216 #define DECOMB_BLND_CON0 11653 #define P_DI_CHAN2_RANGE_MAP_CR 4287651544 #define VPU_HDMI_SETTING 10011 #define NR4_MCNR_RO_V_SUM 11763 #define P_NR4_ALP1Y_ERR2CURV_LIMIT1 4287674064 #define P_NR4_ALP1Y_ERR2CURV_LIMIT0 4287674060 #define P_HEVC_DBLK_STRONG 4284671444 #define LCD_PWM1_HI_ADDR 5311 #define P_HCODEC_ASSIST_TIMER0_LO 4284629376 #define MB_WIDTH 3081 #define VPP_POSTBLEND_VD1_H_START_END 7452 #define VDEC2_VLD_TIME_STAMP_2 11342 #define VDEC2_VLD_TIME_STAMP_3 11343 #define VDEC2_VLD_TIME_STAMP_0 11340 #define VDEC2_VLD_TIME_STAMP_1 11341 #define P_LVDS_GEN_CNTL 4287648640 #define NR4_MCNR_SAD2BET2_LUT2 11760 #define NR4_MCNR_SAD2BET2_LUT1 11759 #define NR4_MCNR_SAD2BET2_LUT0 11758 #define NR4_MCNR_SAD2BET2_LUT3 11761 #define MCDI_PD_22_CHK_FLG_CNT 12126 #define CINDEX2_REG 812 #define P_AUDIN_HDMIRX_AFIFO_STAT 4291875480 #define P_VPP_VADJ1_Y 4287657220 #define VPU_VLOCK_RO_VS_O_DIST 12306 #define P_ENCT_SYNC_TO_PIXEL 4287656236 #define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 5262 #define VPP2_OSD_VSC_PHASE_STEP 6592 #define P_AIU_MEM_IEC958_WRAP_COUNT 4291842536 #define P_AUDIN_FIFO2_START 4291875092 #define RESYNC_MARKER_LENGTH 3086 #define VPU_PROT3_REQ_ONOFF 10108 #define AIU_RST_SOFT 5141 #define P_VDEC2_MC_HCMD_L 4284654892 #define P_VDEC2_MC_HCMD_H 4284654888 #define GE2D_SRC2_Y_START_END 179 #define HCODEC_MFDIN_REG6_DCFG 4110 #define P_HEVC_MBREAK2_REG 4284664920 #define P_AIU_MEM_IEC958_MEM_CTL 4291842532 #define DNR_DB_YEDGE_THD 11531 #define COMM_DESC_2_CTL 6399 #define P_MC_DPDN_MB_XY 4284622104 #define P_HEVC_DC_AC_CTRL 4284676116 #define AIU_MEM_IEC958_MAN_WP 5244 #define VDEC2_DBLK_CTRL1 10623 #define P_HEVC_ASSIST_AMR1_INT6 4284661932 #define P_HEVC_ASSIST_AMR1_INT5 4284661928 #define P_HEVC_ASSIST_AMR1_INT4 4284661924 #define ANC18_CANVAS_ADDR 2466 #define P_HEVC_ASSIST_AMR1_INT3 4284661920 #define P_HEVC_ASSIST_AMR1_INT2 4284661916 #define P_HEVC_ASSIST_AMR1_INT1 4284661912 #define P_HEVC_ASSIST_AMR1_INT0 4284661908 #define P_HEVC_ASSIST_AMR1_INT9 4284661944 #define P_HEVC_ASSIST_AMR1_INT8 4284661940 #define L_DUAL_PORT_CNTL_ADDR 5186 #define P_HEVC_ASSIST_AMR1_INT7 4284661936 #define P_HEVC_ASSIST_AMR1_INTF 4284661968 #define P_HEVC_ASSIST_AMR1_INTE 4284661964 #define P_HEVC_ASSIST_AMR1_INTD 4284661960 #define VPU_VLOCK_RO_M_INT_FRAC 12320 #define P_HEVC_ASSIST_AMR1_INTC 4284661956 #define P_HEVC_ASSIST_AMR1_INTB 4284661952 #define P_HEVC_ASSIST_AMR1_INTA 4284661948 #define AIU_MEM_IEC958_MAN_RP 5245 #define P_HCODEC_F_CODE_REG 4284641288 #define VIU_OSD1_COLOR_ADDR 6673 #define EE_ASSIST_MBOX0_FIQ_SEL 8307 #define P_ENCI_TST_VDCNT_STSET 4287656028 #define P_AUDIN_FIFO0_RDPTR 4291874960 #define P_L_LCD_MCU_CTL 4287648116 #define ANC29_CANVAS_ADDR 2477 #define P_ENCI_VBI_TTXDT2 4287655096 #define P_ENCI_VBI_TTXDT1 4287655092 #define P_ENCI_VBI_TTXDT3 4287655100 #define P_HEVC_MC_MIX_RATIO1 4284671028 #define P_ENCI_VBI_TTXDT0 4287655088 #define P_VPU_VDISP_PRE_ARB_CTRL 4287667284 #define VDIN1_MATRIX_COEF20_21 5140 #define MCDI_CHAR_DET_DIF_THD 12119 #define P_HEVC_MC_MIX_RATIO0 4284671024 #define P_VPP_SRSHARP0_CTRL 4287657540 #define VIU2_OSD1_MATRIX_COEF00_01 7792 #define HEVC_DBLK_VHMVD 14708 #define ANC21_CANVAS_ADDR 2469 #define SRSHARP1_PK_OS_STATIC 13350 #define AUDIN_DECODE_CONTROL_STATUS 13331 #define VDEC2_INTRA_QUANT_MATRIX 11778 #define P_HCODEC_ASSIST_TIMER0_HI 4284629380 #define P_VDEC2_VLD_MEM_VIFIFO_CURR_PTR 4284657924 #define LVDS_blank_data_r 20 #define P_HCODEC_VLC_HUFFMAN_DATA 4284642668 #define VD2_IF0_DUMMY_PIXEL 6786 #define VDIN1_WIN_H_START_END 5229 #define P_ISA_TIMER_MUX 4291883328 #define UART1_RFIFO 35841 #define OEV3_VS_ADDR 5305 #define P_VDIN_ASFIFO_CTRL3 4287646140 #define HEVC_IQIT_AVS2_WQP_45 14094 #define P_HCODEC_PSCALE_RST 4284638272 #define MCDI_MOTINEN 12035 #define P_MCDI_HIGH_VERT_FRQ_RT_GAIN 4287675716 #define MDB_CTRL 797 #define P_HEVC_ASSIST_AXI_CTRL 4284662256 #define LVDS_blank_data_g 10 #define LVDS_blank_data_b 0 #define L_OEV2_VE_ADDR 5174 #define P_VDIN_ASFIFO_CTRL0 4287645728 #define P_VDIN_ASFIFO_CTRL1 4287645732 #define P_VDIN_ASFIFO_CTRL2 4287645756 #define P_AIU_MEM_I2S_MASKS 4291842444 #define VENC_VDAC_DAC1_GAINCTRL 7154 #define SRSHARP1_SR3_DERING_PARAM0 13426 #define ENCP_VIDEO_SYNC_MODE 7041 #define P_VPP2_HSC_PHASE_CTRL1 4287653072 #define P_D2D3_DRMIF_VPOS 4287671464 #define AIU_MEM_IEC958_IRQ_LEVEL 5243 #define VPP_EOTF_LUT_DATA_PORT 12759 #define mLVDS_data_latch_1_ini 15 #define I2SIN_LRCLK_SEL 2 #define MCDI_REL_DET_LPF_MSK_04_12 12089 #define RESET1_LEVEL 1057 #define P_GE2D_HSC_ADV_CTRL 4287890172 #define P_VENC_VIDEO_TST_MDSEL 4287655364 #define SAT_ADJ_LIMT_REG 534 #define P_VPU_PROT3_STAT_0 4287667684 #define SPDIF_DATA_TYPE_SEL 18 #define P_DI_CONTPRD_Y 4287651472 #define P_DI_CONTPRD_X 4287651468 #define HCODEC_LMEM_DMA_CTRL 4944 #define VPP_VDO_MEAS_VS_COUNT_HI 7593 #define P_VPU_PROT3_STAT_1 4287667688 #define P_VPU_PROT3_STAT_2 4287667692 #define D2D3_MBDG_PARAM_7 11040 #define D2D3_MBDG_PARAM_3 11036 #define D2D3_MBDG_PARAM_4 11037 #define D2D3_MBDG_PARAM_5 11038 #define D2D3_MBDG_PARAM_6 11039 #define D2D3_MBDG_PARAM_0 11033 #define D2D3_MBDG_PARAM_1 11034 #define D2D3_MBDG_PARAM_2 11035 #define P_HEVC_DBLK_AVSFLAGS 4284671416 #define P_VPU_PROT2_RPT_LOOP 4287667604 #define HEVC_PARSER_HEADER_INFO2 12581 #define HCODEC_VLC_STATUS_CTRL 7424 #define AUDIN_FIFO0_LVL2 13353 #define AUDIN_FIFO0_LVL1 13352 #define P_VD2_IF0_GEN_REG 4287654336 #define AUDIN_FIFO0_LVL0 13351 #define VPP2_SMOKE2_H_START_END 6447 #define ASYNC_FIFO_FLUSH_STATUS 31 #define AUDIN_FIFO2_END 13382 #define P_ENCP_VIDEO_EQPULS_ELINE 4287655560 #define HEVC_ANC26_CANVAS_ADDR 14762 #define UART2_MISC 34820 #define AUDIN_HDMI_REF_CYCLES_STAT_1 13477 #define AUDIN_HDMI_REF_CYCLES_STAT_0 13476 #define P_HEVC_MPRED_LT_REF 4284663848 #define P_VPP_XVYCC_GCLK_CTRL 4287657444 #define AUDOUT_CTRL 13440 #define VDEC2_SLICE_START_BYTE_01 11276 #define VOFF_STATUS 3132 #define DI_MC_CTRL 5935 #define VDIN_MATRIX_COEF02_10 4626 #define HCODEC_DBLK_Y_HFILT 6492 #define ME_CONTROL 8009 #define P_VIU_OSD2_BLK2_CFG_W4 4287654296 #define P_VIU_OSD2_BLK2_CFG_W3 4287654168 #define P_HEVC_ASSIST_SW_RESET 4284661776 #define P_VIU_OSD2_BLK2_CFG_W0 4287654156 #define P_VIU_OSD2_BLK2_CFG_W2 4287654164 #define P_VIU_OSD2_BLK2_CFG_W1 4287654160 #define P_DNR_DM_AVG_VAR_DIF_THD 4287673768 #define P_VDEC2_VLD_MEM_SWAP_CTL 4284658008 #define P_VDEC2_MC_DPDN_MB_XY 4284654872 #define VDEC2_CBREAK0_REG 9012 #define P_VDEC2_MC_WT_PRED_CTRL 4284654856 #define P_VPP_MATRIX_CLIP 4287657848 #define P_SHARP_SR3_DRTLPF_THETA 4287678924 #define P_VDEC2_RV_AI_U_X 4284659752 #define POI_RPL_MODE_REG 528 #define VDEC2_SLICE_START_BYTE_23 11277 #define SRSHARP0_HCTI_BST_GAIN 12847 #define P_HEVC_MPRED_ABV_RPTR 4284663916 #define P_ANC29_CANVAS_ADDR 4284622516 #define P_HCODEC_MC_DP_MB_XY 4284638264 #define P_MLVDS_DUAL_GATE_CTL_HI 4287648748 #define AUDIN_DECODE_FORMAT 13330 #define VDEC2_AVSP_IQ_CTL 11804 #define HEVC_STREAM_START_ADDR 12546 #define P_VDEC2_RV_AI_V_X 4284659756 #define VIU_OSD2_TCOLOR_AG3 6714 #define VIU_OSD2_TCOLOR_AG2 6713 #define VIU_OSD2_TCOLOR_AG1 6712 #define VIU_OSD2_TCOLOR_AG0 6711 #define P_VDIN_DUMMY_DATA 4287645848 #define P_AIU_MEM_IEC958_START_PTR 4291842452 #define P_D2D3_DWMIF_CTRL 4287671440 #define P_HCODEC_VLD_MEM_SWAP_CTL 4284641624 #define AIU_CLK_CTRL_MORE 5145 #define VIU_OSD2_MATRIX_PROBE_COLOR 6842 #define VPU_RDARB_WEIGH0_SLV_L2C1 10143 #define P_OSD1_AFBCD_CHROMA_PTR 4287678100 #define NR2_MATNR_SNR_EDGE2B 5975 #define P_VPU_VDIN_PRE_ARB_CTRL 4287667280 #define P_ANC15_CANVAS_ADDR 4284622460 #define VDEC2_ASSIST_MMC_CTRL0 8193 #define VDEC2_ASSIST_MMC_CTRL1 8194 #define VDEC2_DEBLK_CMD 11792 #define MCDI_REL_SAD_THD_GAIN_OFFST 12071 #define P_AUDIN_FIFO0_INTR 4291874956 #define P_MLVDS_DUAL_GATE_CTL_LO 4287648752 #define P_HEVC_MPRED_L0_REF14_POC 4284663992 #define P_VPP_VADJ2_Y 4287657232 #define IGNORE_CONFIG_2 7939 #define P_DET3D_RO_DET_CB_VER 4287651064 #define VDEC2_VLD_MEM_VIFIFO_BUF_CNTL 11336 #define P_VPP_HSHARP_LUMA_GAIN 4287657300 #define VIU2_VD1_IF0_GEN_REG2 7789 #define P_DI_IF1_DUMMY_PIXEL 4287651780 #define P_HCODEC_CDB_CTRL 4284632308 #define MC_OM_MB_XY 2319 #define P_SCD_FOR_MV_X 4284624968 #define P_SCD_FOR_MV_Y 4284624972 #define VPP2_MATRIX_COEF02_10 6497 #define P_ANC26_CANVAS_ADDR 4284622504 #define P_MINDEX6_REG 4284615744 #define HEVC_WRRSP_FIFO_PICW_MC 14783 #define VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL 11331 #define HEVC_DBLK_CR_BFILT 14683 #define P_GE2D_ARB_BURST_NUM 4287890328 #define SRSHARP1_PK_CON_2DRTBPGAIN_LIMIT 13324 #define P_VDEC2_ANC1_CANVAS_ADDR 4284655172 #define HCODEC_VLD_TIME_STAMP_LENGTH 7248 #define P_HCODEC_ASSIST_DMA_INT_MSK2 4284629404 #define MIPI_DSI_TOP_MEM_PD 7421 #define SRSHARP0_HLTI_BST_CORE 12854 #define P_HEVC_MC_HCMD_L 4284671276 #define HEVC_MBREAK3_REG 13079 #define DBKR_CANVAS_ADDR 2480 #define P_V3_SKIP_WEIGHT 4284644800 #define P_HEVC_MC_HCMD_H 4284671272 #define VENC_VDAC_DAC4_FILT_CTRL1 7253 #define VENC_VDAC_DAC4_FILT_CTRL0 7252 #define VDEC2_CPSR 8993 #define P_STH2_VS_ADDR 4287648344 #define ENCI_SYNC_HOFFST 6928 #define VDEC2_MINDEX4_REG 8974 #define DI_PRE_SIZE 5891 #define VPP_WRAP_OSD3_MATRIX_COEF13_14 15797 #define P_VENC_VIDEO_EXSRC 4287655300 #define HEVC_MPRED_ABV_RPTR 12827 #define VD2_AFBC_DEC_DEF_COLOR 12675 #define AUDOUT_INTR_PTR 13449 #define VDIN1_SCALE_COEF_IDX 5120 #define HEVC_CBREAK_TYPE 13112 #define ENCI_VBI_CCDT_ODD 6946 #define VDIN1_HIST_CTRL 5168 #define P_HCODEC_VLC_STREAM_BUFF 4284642424 #define P_VP9D_MPP_INTERPOL_CFG0 4284666112 #define ENCT_TST_EN 7208 #define P_VDEC2_DC_AC_SCALE_MUL 4284659736 #define GE2D_MATRIX_COEF22_CTRL 202 #define P_ENCT_VIDEO_PR_OFFST 4287656344 #define VDIN1_COM_GCLK_CTRL2 5232 #define P_VPU_VLOCK_OUTPUT1_CAPT_LMT 4287676460 #define VDEC2_PRE_START_CODE 11275 #define P_OSD_DB_FLT_PXI_THRD 4287677716 #define ENCT_TST_CR 7212 #define ENCT_TST_CB 7211 #define P_VIU_OSD2_CTRL_STAT 4287654080 #define P_VPP2_MATRIX_PROBE_POS 4287653240 #define GAMMA_DATA_PORT 5249 #define HEVC_AVSP_IQ_WQ_PARAM_23 15898 #define I2C_M_2_SLAVE_ADDR 29697 #define SRSHARP0_SHARP_3DLIMIT 12868 #define VDEC2_ANC8_CANVAS_ADDR 10648 #define MIPI_DSI_DWC_DPI_VCID_OS 7171 #define HEVC_AVSP_IQ_WQ_PARAM_45 15899 #define HEVC_MDEC_SW_RESET 14724 #define LDIM_STTS_HIST_REGION_IDX 6864 #define SPICC1_LD_RADDR 21516 #define AIU_AIFIFO2_STATUS 5185 #define AUDIN_FIFO0_PTR 13346 #define P_ENCL_VIDEO_VSO_BEGIN 4287656668 #define P_L_DE_VS_ADDR 4287648076 #define MCDI_RPTMV_FLG 12050 #define OSDSR_CBIC_VCOEF 12599 #define HEVC_MPRED_L1_REF00_POC 12848 #define P_HEVC_ASSIST_AMR2_INTD 4284662024 #define HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL 15427 #define P_HEVC_ASSIST_AMR2_INTE 4284662028 #define P_HEVC_ASSIST_AMR2_INTF 4284662032 #define P_HEVC_ASSIST_AMR2_INTA 4284662012 #define P_HEVC_ASSIST_AMR2_INTB 4284662016 #define P_HEVC_ASSIST_AMR2_INTC 4284662020 #define VD1_IF0_LUMA1_RPT_PAT 6750 #define P_HEVC_ASSIST_AMR2_INT8 4284662004 #define P_HEVC_ASSIST_AMR2_INT9 4284662008 #define P_HEVC_ASSIST_AMR2_INT4 4284661988 #define P_HEVC_ASSIST_AMR2_INT5 4284661992 #define P_HEVC_ASSIST_AMR2_INT6 4284661996 #define P_HEVC_ASSIST_AMR2_INT7 4284662000 #define P_HEVC_ASSIST_AMR2_INT0 4284661972 #define P_HEVC_ASSIST_AMR2_INT1 4284661976 #define P_HEVC_ASSIST_AMR2_INT2 4284661980 #define P_HEVC_ASSIST_AMR2_INT3 4284661984 #define UART0_STATUS 36867 #define HEVC_AVSP_IQ_WQ_PARAM_01 15897 #define MIPI_DSI_DWC_INT_MSK1_OS 7218 #define P_VPP_OSD_SC_CTRL0 4287657760 #define VPP_POST2_MATRIX_COEF20_21 14755 #define VPP2_VADJ1_MC_MD 6467 #define HEVC_MSP 13056 #define VPU_RDMA_MMC_CTRL 10020 #define HCODEC_VLD_ERROR_MASK 7214 #define P_VLC_JPEG_CTRL 4284642656 #define P_VPU_HDMI_FMT_CTRL 4287667468 #define P_VDIN_LFIFO_CTRL 4287645800 #define P_LDIM_BL_DATA_PORT 4287648060 #define HEVC_PARSER_RESULT_0 12568 #define HEVC_PARSER_RESULT_2 12570 #define HEVC_PARSER_RESULT_1 12569 #define VDEC_ASSIST_MBOX1_CLR_REG 117 #define HCODEC_DC_AC_CTRL 7685 #define HEVC_PARSER_RESULT_3 12571 #define VIU_OSD2_HL2_H_START_END 6709 #define P_HCODEC_V5_SIMPLE_MB_ME_WEIGHT 4284644864 #define P_ENCL_VIDEO_PB_OFFST 4287656596 #define P_NR_DB_FLT_RANDLUT 4287683816 #define P_ENCP_DVI_HSO_END 4287656132 #define P_ENCT_TST_VDCNT_STSET 4287656124 #define ENCI_DVI_VSO_END_EVN 7176 #define P_LVDS_PHY_CNTL6 4287648708 #define P_LVDS_PHY_CNTL7 4287648712 #define P_VLC_PUSH_STREAM 4284642428 #define P_LVDS_PHY_CNTL4 4287648660 #define P_LVDS_PHY_CNTL5 4287648664 #define CBREAK2_REG 822 #define ENCP_DBG_PX_INT 7058 #define P_LVDS_PHY_CNTL8 4287648716 #define P_VDEC2_MC_CTRL1 4284654636 #define P_VDEC2_MC_CTRL0 4284654620 #define VPP_WRAP_OSD2_MATRIX_OFFSET2 15738 #define P_VDEC2_MC_CTRL2 4284654908 #define P_VDIN_HIST_CTRL 4287645888 #define HEVC_CINDEX5_REG 13103 #define HEVC_CPC_W 13097 #define P_XVYCC_LUT_R_DATA_PORT 4287677820 #define VDIN1_MEAS_HS_RANGE 5213 #define HEVCD_IPP_SWMPREDIF_CONFIG 13328 #define HEVC_CPC_P 13094 #define REG_BASE_AOBUS 4286578688 #define HCODEC_CMAX_REG 4915 #define ENCP_VIDEO_VSO_END 7082 #define P_HEVC_ACC0REG2 4284665284 #define P_HEVC_ACC0REG1 4284665220 #define DBLK_BETAX_QP_SEL 2401 #define HEVC_CPC_D 13095 #define P_LVDS_PHY_CNTL2 4287648652 #define HEVC_CPC_E 13096 #define P_LVDS_PHY_CNTL3 4287648656 #define P_LVDS_PHY_CNTL0 4287648644 #define P_LVDS_PHY_CNTL1 4287648648 #define P_DOLBY_CORE3_CLKGATE_CTRL 4287683520 #define AIU_I2S_CBUS_DDR_WDATA 5290 #define NR2_MATNR_SNR_NRM_CFG 5971 #define P_HEVC_PARSER_INT_STATUS 4284662916 #define SPDIF_CLKNUM_48K 12 #define P_HEVC_IMEM_DMA_COUNT 4284665096 #define HCODEC_ASSIST_MBOX2_CLR_REG 4217 #define VDEC2_WRRSP_FIFO_PICW_MC 10687 #define HS_POL 0 #define IMEM_DMA_COUNT 834 #define NR4_ALP0Y_ERR2CURV_LIMIT0 11693 #define NR4_ALP0Y_ERR2CURV_LIMIT1 11694 #define P_HEVC_ANC28_CANVAS_ADDR 4284671664 #define P_HEVC_DBLK_CMD_CTRL 4284671312 #define P_DET3D_MAT_STA_P1TH 4287651044 #define DBLK_Y_BHFILT_HIGH 2392 #define VLC_COEFF_INFO 7491 #define HEVC_DC_SCALER 15876 #define ME_F_SKIP_SAD 8019 #define ASYNC_FIFO_FLUSH_CNT_MSB 14 #define P_PARSER_SEARCH_PATTERN 4291879332 #define HCODEC_CDB_ADDR_REG 4923 #define UART0_RFIFO 36865 #define PK_CON_2CIRBPGAIN_TH_RATE 12807 #define HCODEC_QP_VALUE_REG 7173 #define ENCL_VFIFO2VD_LINE_BOT_END 7318 #define P_NR2_RO_POLAR3_NUMOFPIX 4287673972 #define VD1_IF0_LUMA_FIFO_SIZE 6755 #define SPDIF_CLKNUM_44K 6 #define VDEC2_SLICE_VER_POS_PIC_TYPE 11268 #define SPI_FLASH_RDSR 27 #define P_VIUB_SW_RESET0 4287660040 #define VDIN_GO_LINE_CTRL 4655 #define HEVC_AVSP_IQ_CTL 15900 #define P_NR4_NM_X_CFG 4287683660 #define ENCI_DVI_VSO_BEGIN_EVN 7174 #define P_VDEC2_MBREAK_TYPE 4284648544 #define VPP_WRAP_OSD1_MATRIX_CLIP 15720 #define P_QP_CTRL_REG 4284626948 #define P_OEV2_HS_ADDR 4287648460 #define DET3D_MAT_STA_M1TH 5946 #define P_HCODEC_QDCT_MB_START_PTR 4284644416 #define P_VDEC2_ASSIST_DMA_INT2 4284645784 #define L_INV_CNT_ADDR 5184 #define SANA_STREAM_END_ADDR 12322 #define DI_CHAN2_LUMA_Y0 6136 #define SRSHARP0_SR3_DRTLPF_ALPHA_OFST 12906 #define DBLK_CBUS_HCMD2 2423 #define HCODEC_MC_STATUS1 6410 #define DBLK_CBUS_HCMD1 2424 #define HCODEC_MC_STATUS0 6409 #define DBLK_CBUS_HCMD0 2425 #define P_POWER_CTL_VLD 4284624928 #define P_VIU_OSD2_MATRIX_OFFSET2 4287654620 #define P_NR4_MCNR_SAD2BET0_LUT3 4287674276 #define P_NR4_MCNR_SAD2BET0_LUT2 4287674272 #define CTI_DIR_ALPHA 12843 #define P_HCODEC_CINDEX7_REG 4284632260 #define P_HCODEC_VLC_PUSH_STREAM 4284642428 #define P_NR4_MCNR_SAD2BET0_LUT1 4287674268 #define P_NR4_MCNR_SAD2BET0_LUT0 4287674264 #define P_MCDI_UNI_MVDST 4287675412 #define P_VD1_IF0_GEN_REG 4287654208 #define P_ISA_TIMERA 4291883332 #define P_ISA_TIMERG 4291883416 #define P_ISA_TIMERF 4291883412 #define P_ISA_TIMERI 4291883424 #define P_HCODEC_MC_MBBOT_ST_ODD_ADDR 4284638484 #define P_ISA_TIMERH 4291883420 #define P_ISA_TIMERC 4291883340 #define P_ISA_TIMERB 4291883336 #define P_ISA_TIMERE 4291883400 #define P_ISA_TIMERD 4291883344 #define QDCT_DBG_IDX 7971 #define FBUF_ADDR 15446 #define HCODEC_RV_AI_Y_X 7689 #define DI_CHAN2_LUMA_X0 6135 #define DNR_STAT_X_START_END 11528 #define P_NR2_MATNR_SNR_OS 4287651144 #define NR2_FRM_SIZE 5968 #define P_AUDIN_FIFO2_CTRL 4291875112 #define P_GE2D_SCALE_COEF 4287890260 #define HEVC_MINDEX2_REG 13068 #define P_HEVC_ASSIST_AFIFO_CTRL 4284661764 #define NR4_DRT_CSAD_GAIN 11686 #define GE2D_DST_CLIPY_START_END 181 #define P_VDEC2_VLD_TIME_STAMP_SYNC_1 4284657964 #define P_VDEC2_VLD_TIME_STAMP_SYNC_0 4284657960 #define P_AUDIN_SPDIF_MODE 4291874816 #define P_VLC_PIC_SIZE 4284642500 #define SRSHARP1_HLTI_FLT_CLP_DC 13364 #define ENCL_VIDEO_HSO_BEGIN 7349 #define P_D2D3_DRMIF_STATUS 4287671528 #define PSCALE_PICO_SHIFT_XY 2344 #define HEVC_MC_MBBOT_ST_ODD_ADDR 14661 #define P_HEVC_ASSIST_MBOX0_CLR_REG 4284662212 #define P_DI_CONTP2RD_X 4287651476 #define P_DI_CONTP2RD_Y 4287651480 #define P_VDEC2_ASSIST_AMR1_INTB 4284645568 #define P_VDEC2_ASSIST_AMR1_INTA 4284645564 #define P_VDEC2_ASSIST_AMR1_INTD 4284645576 #define P_VDEC2_ASSIST_AMR1_INTC 4284645572 #define P_VDEC2_ASSIST_AMR1_INT6 4284645548 #define P_VDEC2_ASSIST_AMR1_INT5 4284645544 #define P_VDEC2_ASSIST_AMR1_INT8 4284645556 #define HCODEC_QDCT_JPEG_DCT_COEFF23 7982 #define P_VDEC2_ASSIST_AMR1_INT7 4284645552 #define P_VDEC2_ASSIST_AMR1_INT9 4284645560 #define MCDI_PD_22_CHK_WND1_Y 12124 #define MCDI_PD_22_CHK_WND1_X 12123 #define P_VDEC2_ASSIST_AMR1_INT0 4284645524 #define SPI_FLASH_RES 20 #define P_VDEC2_ASSIST_AMR1_INT2 4284645532 #define P_VDEC2_ASSIST_AMR1_INT1 4284645528 #define P_VDEC2_ASSIST_AMR1_INT4 4284645540 #define P_VDEC2_ASSIST_AMR1_INT3 4284645536 #define P_LAST_MVX 4284625092 #define P_LAST_MVY 4284625096 #define EE_ASSIST_MBOX2_MASK 8314 #define VDEC2_ANC9_CANVAS_ADDR 10649 #define P_VDIN_BLKBAR_STATUS0 4287646124 #define P_VDIN_BLKBAR_STATUS1 4287646128 #define P_AIU_958_SYNWORD1 4291842160 #define EE_ASSIST_MBOX2_FIQ_SEL 8315 #define P_AIU_958_SYNWORD3 4291842168 #define P_AIU_958_SYNWORD2 4291842164 #define P_VDEC2_DBLK_CBPY_ADJ 4284655044 #define P_MDEC_EXTIF_CFG1 4284622740 #define P_MDEC_EXTIF_CFG0 4284622736 #define HCODEC_QDCT_JPEG_DCT_COEFF01 7981 #define DNR_DM_RNG_GAIN_OFST 11619 #define P_VPP_DUMMY_DATA 4287656960 #define HEVC_FST_BAK_MV_X 15380 #define HEVC_FST_BAK_MV_Y 15381 #define SRSHARP1_SHARP_HVSIZE 13312 #define P_HEVCD_IPP_SWMPREDIF_PUINFO0 4284665932 #define VDIN0_OFFSET 0 #define DI_MTNWR_X 6083 #define P_VDEC2_MC_HALF_PEL_TWO 4284654608 #define DI_MTNWR_Y 6084 #define P_HEVCD_IPP_SWMPREDIF_PUINFO5 4284665952 #define P_HEVCD_IPP_SWMPREDIF_PUINFO3 4284665944 #define P_HEVCD_IPP_SWMPREDIF_PUINFO4 4284665948 #define P_HEVCD_IPP_SWMPREDIF_PUINFO1 4284665936 #define P_HEVCD_IPP_SWMPREDIF_PUINFO2 4284665940 #define P_HCODEC_PSCALE_CTRL 4284638276 #define P_HEVC_ASSIST_TIMER1_HI 4284662156 #define P_VLC_HUFFMAN_ADDR 4284642664 #define HCODEC_QDCT_JPEG_DCT_COEFF67 7984 #define MC_CTRL_REG 2304 #define P_HEVC_MBREAK3_REG 4284664924 #define P_HEVC_VLD_MEM_VIFIFO_START_PTR 4284674304 #define VPP2_CHROMA_ADDR_PORT 6512 #define P_GE2D_GCLK_CTRL1 4287890368 #define P_GE2D_GCLK_CTRL0 4287890364 #define P_DBLK_MB_XY 4284622164 #define SRSHARP0_LTI_CTI_DF_GAIN 12844 #define NR4_MCNR_LUMA_DIF_CALC 11707 #define P_HEVC_CABAC_LEFT_INFO 4284662904 #define P_ENCP_DVI_HSO_BEGIN 4287656128 #define P_DI_INP_GEN_REG2 4287651396 #define P_DI_INP_GEN_REG3 4287660704 #define HCODEC_QDCT_JPEG_DCT_COEFF45 7983 #define P_VIU_OSD2_HL2_V_START_END 4287654104 #define P_HEVC_MPRED_MV_WR_START_ADDR 4284663884 #define OEV1_SEL 0 #define ENCI_VFIFO2VD_PIXEL_END 7194 #define P_VIU2_SW_RESET0 4287657992 #define P_HEVC_ASSIST_TIMER1_LO 4284662152 #define P_VDEC2_ASSIST_AMR1_INTF 4284645584 #define P_VDEC2_ASSIST_AMR1_INTE 4284645580 #define P_VBO_SOFT_RST 4287648136 #define PARSER_SCR_CTL 14445 #define P_VDEC2_DBLK_Y_BVFILT 4284654948 #define VLC_VB_START_PTR 7440 #define GE2D_SRC1_Y_START_END 171 #define P_HCODEC_ME_MV_MERGE_CTL 4284644692 #define HCODEC_MBREAK_STAUTS 4890 #define LVDS_SER_EN 5360 #define P_ENCI_DVI_VSO_END_EVN 4287655968 #define P_AUDIO_MMCP_CNTL 4291883312 #define VPU_VLOCK_STBDET_ABS_WIN1 12314 #define ENCP_VIDEO_HAVON_END 7075 #define VPU_VLOCK_STBDET_ABS_WIN0 12313 #define TCON_HS_SEL 3 #define HCODEC_QDCT_JPEG_DCT_COEFF89 7985 #define P_MC_MBBOT_WRRSP_CNT 4284622576 #define P_VIU_OSD1_MATRIX_OFFSET0_1 4287654488 #define P_DET3D_MAT_STA_P1M1 4287651040 #define OSDSR_UK_GRAD2DADJA_TH_RATE 12605 #define P_MCDI_RO_PD_22_FLG 4287676092 #define SPI_FLASH_RDID 28 #define P_HCODEC_CBREAK_CTRL 4284632292 #define VDIN0_BLKBAR_IND_LEFT_START_END 4709 #define WM_FREQ_DIST_RIGHT 12725 #define P_ENCP_DVI_VSO_BEGIN_EVN 4287656152 #define P_QDCT_DCT_STATUS 4284644452 #define P_ENCI_SYNC_PIXEL_EN 4287656196 #define LCD_VBL 4 #define P_HEVCD_MCRCC_PERFMON_DATA 4284666832 #define P_SPICC0_TESTREG 4291899420 #define P_HEVC_CINDEX1_REG 4284665004 #define P_AUDOUT_FIFO_STS 4291875368 #define AUDIN_FIFO1_END 13364 #define HCODEC_MC_MIX_RATIO1 6413 #define HCODEC_MC_MIX_RATIO0 6412 #define LCD_VDD 5 #define P_ENCI_SYNC_VSO_EVNLN 4287654968 #define HEVC_MPRED_COL_POC 12897 #define VDEC2_CINDEX6_REG 9008 #define P_CIPLUS_CONFIG 4291847156 #define P_D2D3_DBLD_LPF_HCOEFF 4287671376 #define P_ANC27_CANVAS_ADDR 4284622508 #define VDIN1_WR_CTRL 5152 #define GPIO_INTR_GPIO_SEL0 15393 #define GPIO_INTR_GPIO_SEL1 15394 #define B_PIC 3 #define P_DOS_MEM_PD_VDEC 4284677312 #define VDEC2_HDEC_MC_MBRIGHT_RD 10546 #define MDEC_DOUBLEW_STATUS 2531 #define VIU2_OSD1_MATRIX_OFFSET0_1 7801 #define HCODEC_ANC3_CANVAS_ADDR 6547 #define HCODEC_CSFTINT0 4926 #define HCODEC_CSFTINT1 4927 #define P_MINDEX7_REG 4284615748 #define P_AIU_958_VALID_CTRL 4291842248 #define VDIN_CHROMA_ADDR_PORT 4651 #define P_VPP2_VSC_REGION3_PHASE_SLOPE 4287652908 #define HCODEC_CDB_DATA_REG 4924 #define HCODEC_MB_INFO 7212 #define DOLBY_CORE3_REG_START 13824 #define HCODEC_CMIN_REG 4914 #define P_GE2D_MATRIX_COEF22_CTRL 4287890216 #define VDEC2_WRRSP_FIFO_PICW_DBK 10686 #define P_VKS_PARA_DATA_PORT 4287677500 #define VI_DNLP_HIST08 11791 #define VI_DNLP_HIST07 11790 #define VI_DNLP_HIST06 11789 #define VI_DNLP_HIST05 11788 #define VI_DNLP_HIST09 11792 #define VI_DNLP_HIST00 11783 #define P_HEVC_IQIDCT_DEBUG_IDCT 4284676164 #define P_HCODEC_MSFTINT1 4284632188 #define VI_DNLP_HIST04 11787 #define VI_DNLP_HIST03 11786 #define P_HCODEC_MSFTINT0 4284632184 #define VI_DNLP_HIST02 11785 #define VI_DNLP_HIST01 11784 #define MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS 7174 #define P_HCODEC_QDCT_I_PRED_REF_WR_DATA 4284644556 #define VC1_BITPLANE_CTL 3608 #define SPDIF_CLKNUM_54U 0 #define P_HEVC_DBKW_CANVAS_ADDR 4284671684 #define HEVC_MPRED_CTRL8 12890 #define HEVC_MPRED_CTRL7 12889 #define HEVC_MPRED_CTRL6 12888 #define VPP2_SC_GCLK_CTRL 6516 #define LVDS_BLANK_DATA_LO 5327 #define HEVC_MPRED_CTRL5 12877 #define I2C_M_MANUAL_SDA_I 26 #define DBLK_MB_XY 2389 #define HEVC_MPRED_CTRL9 12891 #define HEVC_MPRED_CTRL0 12801 #define HEVC_MPRED_CTRL4 12876 #define MCDI_REL_DET_LPF_MSK_31_34 12092 #define HEVC_MPRED_CTRL3 12829 #define HEVC_MPRED_CTRL2 12828 #define HEVC_MPRED_CTRL1 12802 #define I2C_M_MANUAL_SDA_O 24 #define P_DNR_DM_COR_DIF 4287673748 #define HEVC_MBREAK2_REG 13078 #define P_POWER_CTL_IQIDCT 4284626976 #define P_ENCT_VFIFO2VD_PIXEL_END 4287656072 #define VPP_SMOKE1_VAL 7466 #define VDEC2_PSCALE_FILT0_COEF1 10522 #define VDEC2_PSCALE_FILT0_COEF0 10521 #define VPU_OSD1_MMC_CTRL 9985 #define ENCL_VIDEO_PB_SCL 7330 #define P_GAMMA_PROBE_CTRL 4287648292 #define P_NR4_ALP1C_ERR2CURV_LIMIT1 4287674056 #define VIU_OSD1_MATRIX_PRE_OFFSET2 6809 #define P_NR4_ALP1C_ERR2CURV_LIMIT0 4287674052 #define P_GE2D_VSC_NRND_POINT 4287890180 #define P_HEVC_CBREAK1_REG 4284665044 #define P_VDIN_WR_H_START_END 4287645828 #define NR2_MATNR_BETA_BRT 5977 #define VIU_OSD2_HL1_H_START_END 6707 #define VPU_RDARB_REQEN_SLV_L2C1 10142 #define HCODEC_SLICE_VER_POS_PIC_TYPE 7172 #define SRSHARP0_PK_CIRFB_BLEND_GAIN 12819 #define MCDI_MCVECWR_CTRL 12180 #define HEVC_ACC1REG2 13170 #define HEVC_ACC1REG1 13154 #define LVDS_BLANK_DATA_HI 5326 #define P_VPP_BLACKEXT_CTRL 4287657472 #define AIU_MEM_IEC958_WRAP_COUNT 5242 #define MC_MIX_RATIO0 2316 #define MC_MIX_RATIO1 2317 #define VPP_MATRIX_CTRL 7519 #define VPP2_SMOKE1_H_START_END 6445 #define VPP2_VADJ2_MA_MB 6469 #define P_HEVC_PARSER_MEM_WR_ADDR 4284662964 #define P_VIU_VD2_FMT_W 4287654436 #define P_V3_LEFT_INTRA_INFO 4284644828 #define P_VPP_EOTF_COEF02_10 4287678280 #define P_OSD1_AFBCD_PIXEL_VSCOPE 4287678120 #define VPP2_VADJ1_MA_MB 6466 #define VDEC2_MINDEX3_REG 8973 #define PK_ALP2_ERR2CURV_TH_RATE 12831 #define P_HEVC_MC_OMDN_MB_XY 4284671260 #define P_VDEC2_DBLK_CBPC_ADJ 4284655052 #define P_LVDS_PACK_CNTL_ADDR 4287648576 #define HEVC_MPRED_L0_REF08_POC 12840 #define PK_CON_2DRTHPGAIN_TH_RATE 12809 #define VIU_OSD1_CTRL_STAT 6672 #define P_D2D3_D2P_PARAM_1 4287671344 #define P_D2D3_D2P_PARAM_3 4287671352 #define P_D2D3_D2P_PARAM_2 4287671348 #define DI_IF2_LUMA_FIFO_SIZE 8218 #define NON_I_QUANT_MATRIX 3587 #define PARSER_SUB_RP 14477 #define VPP2_HSC_PHASE_CTRL1 6452 #define P_TCON_INVERT_CTL 4287655324 #define P_HCODEC_WRRSP_FIFO_PICW_MC 4284638972 #define P_VPP2_OSD_SCO_H_START_END 4287653672 #define HCODEC_MDEC_PIC_DC_MUX_CTRL 6541 #define P_VDEC_ASSIST_MBOX1_IRQ_REG 4284613072 #define ENCT_TST_CLRBAR_WIDTH 7214 #define VD2_AFBC_OUT_YSCOPE 12681 #define I2C_M_0_TOKEN_LIST0 31746 #define I2C_M_0_TOKEN_LIST1 31747 #define ABUF_WR_FF_CLR_PLS 2 #define MPC_P 774 #define P_NR_ALP0C_ERR2CURV_TH_RATE 4287678556 #define HEVC_ANC6_CANVAS_ADDR 14742 #define MPC_D 775 #define MCDI_REF_ERR_FRQ_CHK 12061 #define MPC_E 776 #define MCDI_RO_HIGH_VERT_FRQ_FLG 12203 #define MCDI_PD_22_CHK_WND0_Y 12122 #define MCDI_PD_22_CHK_WND0_X 12121 #define HCODEC_PSCALE_DUMMY 6424 #define MPC_W 777 #define P_VDEC2_PSCALE_PICO_START_Y 4284654684 #define P_VDEC2_PSCALE_PICO_START_X 4284654680 #define SHARP_DB_FLT_PXI_THRD 12922 #define MCDI_YCBCR_BLEND_CRTL 12132 #define IQIDCT_DEBUG_IDCT 3601 #define P_SPICC1_TESTREG 4291907612 #define DET3D_RAMRD_DATA_PORT 6043 #define VENC_ENCI_PIXEL 7018 #define P_ENCI_DBG_PX_RST 4287655200 #define P_DBLK_CTRL 4284622148 #define LCD_ANALOG_3PHI_CLK_SEL 7 #define P_HCODEC_MDEC_PIC_DC_STATUS 4284638780 #define P_VDEC2_ASSIST_DMA_INT_MSK2 4284645788 #define PARSER_SUB_WP 14476 #define DBLK_CMD_CTRL 2388 #define MDEC_PIC_DC_CTRL 2446 #define AUDIN_FIFO1_REQID 13379 #define P_DOS_HCODEC_INT_EN 4284677144 #define MC_HALF_PEL_TWO 2308 #define HEVC_MC_HCMDBUF_H 14664 #define P_HEVC_MSP 4284664832 #define HEVC_MC_HCMDBUF_L 14665 #define P_RESET4_REGISTER 4291825684 #define VDIN1_MATRIX_OFFSET0_1 5142 #define NR4_MTN_CTRL 11701 #define P_ENCI_DVI_VSO_BLINE_EVN 4287655944 #define P_VIU2_MISC_CTRL0 4287658008 #define P_CVBS_IRQ1_CNTL 4291883156 #define P_VIU_OSD2_BLK3_CFG_W4 4287654300 #define SPDIF_XTDCLK_UPD_ITVL 14 #define P_VIU_OSD2_BLK3_CFG_W3 4287654184 #define P_VIU_OSD2_BLK3_CFG_W2 4287654180 #define P_VIU_OSD2_BLK3_CFG_W1 4287654176 #define P_VIU_OSD2_BLK3_CFG_W0 4287654172 #define MCDI_REL_DET_PD22_CHK 12082 #define ANC20_CANVAS_ADDR 2468 #define RESET3_MASK 1043 #define P_ENCI_SYNC_TO_LINE_EN 4287656200 #define VI_DNLP_HIST32 11815 #define VI_DNLP_HIST31 11814 #define VI_DNLP_HIST30 11813 #define VS_POL 1 #define P_VI_HIST_MAX_MIN 4287674380 #define MCDI_FLT_MODESEL 12041 #define P_VDIN_MATRIX_PRE_OFFSET2 4287645796 #define P_MCDI_REF_BADW_SUM_GAIN 4287675492 #define HCODEC_MDEC_DOUBLEW_STATUS 6627 #define P_VKS_START_CTRL 4287677480 #define P_VDEC2_CINT_VEC_BASE 4284648584 #define HCODEC_VLD_STATUS_CTRL 7168 #define VI_DNLP_HIST19 11802 #define VI_DNLP_HIST18 11801 #define VI_DNLP_HIST17 11800 #define VI_DNLP_HIST16 11799 #define P_VDIN_MATRIX_COEF11_12 4287645772 #define VI_DNLP_HIST11 11794 #define VI_DNLP_HIST10 11793 #define VI_DNLP_HIST15 11798 #define OEH_VE_ADDR 5275 #define VI_DNLP_HIST14 11797 #define VI_DNLP_HIST13 11796 #define VI_DNLP_HIST12 11795 #define P_VLD_MEM_VBUF2_RD_PTR 4284625232 #define P_RESET5_MASK 4291825748 #define VI_DNLP_HIST29 11812 #define P_D2D3_DGEN_WIN_VER 4287671312 #define VI_DNLP_HIST28 11811 #define VI_DNLP_HIST27 11810 #define P_VPP_SHARP_DEMO_WIN_CTRL1 4287657700 #define P_VPP_SHARP_DEMO_WIN_CTRL2 4287657704 #define VI_DNLP_HIST22 11805 #define P_HEVC_SAO_CTRL7 4284668052 #define VI_DNLP_HIST21 11804 #define P_HEVC_SAO_CTRL8 4284668080 #define VI_DNLP_HIST20 11803 #define P_HEVC_SAO_CTRL9 4284668084 #define ENCI_DE_H_BEGIN 6934 #define VI_DNLP_HIST26 11809 #define P_HEVC_SAO_CTRL3 4284668036 #define POWER_CTL_IQIDCT 3592 #define VI_DNLP_HIST25 11808 #define P_HEVC_SAO_CTRL4 4284668040 #define VI_DNLP_HIST24 11807 #define P_HEVC_SAO_CTRL5 4284668044 #define VI_DNLP_HIST23 11806 #define AIU_MIX_ADCCFG 5143 #define P_HEVC_SAO_CTRL6 4284668048 #define P_HCODEC_PSCALE_CANVAS_WR_ADDR 4284638388 #define P_HEVC_SAO_CTRL0 4284667908 #define P_HEVC_SAO_CTRL1 4284667912 #define RESET7_REGISTER 1032 #define P_HEVC_SAO_CTRL2 4284668032 #define VDEC2_MDEC_DOUBLEW_CFG6 10721 #define VDEC2_MDEC_DOUBLEW_CFG7 10722 #define VPP_POSTBLEND_VD1_V_START_END 7453 #define P_HEVC_MPRED_L1_REF12_POC 4284664048 #define VDEC2_MDEC_DOUBLEW_CFG0 10715 #define VDEC2_MDEC_DOUBLEW_CFG1 10716 #define VDEC2_MDEC_DOUBLEW_CFG4 10719 #define VDEC2_MDEC_DOUBLEW_CFG5 10720 #define VDEC2_MDEC_DOUBLEW_CFG2 10717 #define VDEC2_MDEC_DOUBLEW_CFG3 10718 #define P_DI_MEM_CHROMA_Y0 4287651712 #define HCODEC_VLD_MEM_SWAP_ADDR 7253 #define HCODEC_QDCT_JPEG_Y_START_END 7975 #define WM_STATUS_RO 12745 #define SPI_FREAD_DUAL 14 #define HEVC_CCPU_INTR_GRP 13091 #define WRRSP_IMEM 835 #define P_DI_MEM_CHROMA_X0 4287651708 #define P_DI_CHAN2_LUMA_X0 4287651804 #define VDIN_MISC_CTRL 10114 #define P_PSCALE_CMD_BLK_Y 4284621940 #define P_PSCALE_CMD_BLK_X 4284621936 #define SRSHARP1_VCTI_CON_2_GAIN_1 13379 #define P_VLC_PIC_POSITION 4284642508 #define SRSHARP1_VCTI_CON_2_GAIN_0 13378 #define MCDI_RO_GMV_LOCK_FLG 12204 #define DVIN_CTRL_STAT 2277 #define MC_MBBOT_ST_EVEN_ADDR 2372 #define P_DI_CHAN2_LUMA_Y0 4287651808 #define HEVCD_IPP_SWMPREDIF_CTBINFO 13330 #define HCODEC_DBLK_CBUS_HCMD1 6520 #define HCODEC_DBLK_CBUS_HCMD2 6519 #define HCODEC_DBLK_CBUS_HCMD0 6521 #define HEVC_SAO_C_START_ADDR 13837 #define P_L_LCD_PWM1_HI_ADDR 4287647996 #define VIU2_OSD1_BLK2_CFG_W2 7717 #define VIU2_OSD1_BLK2_CFG_W1 7716 #define HCODEC_MBREAK0_REG 4884 #define VIU2_OSD1_BLK2_CFG_W4 7782 #define P_VDEC2_MINDEX5_REG 4284648508 #define VIU2_OSD1_BLK2_CFG_W3 7718 #define P_NR2_MATNR_SNR_EDGE2B 4287651164 #define P_HEVC_ANC29_CANVAS_ADDR 4284671668 #define P_DNR_DM_NR_BLND 4287673732 #define DC_AC_SCALE_MUL 3590 #define HCODEC_DBLK_CMD_CTRL 6484 #define P_DNR_DB_HACT 4287673404 #define XVYCC_INV_LUT_V_ADDR_PORT 12636 #define AIU_MEM_I2S_CONTROL 5220 #define VDIN_BLKBAR_IND_RIGHT_START_END 4710 #define P_VLC_MV_INDEX 4284642592 #define VPU_MEM_PD_REG0 10021 #define VPU_MEM_PD_REG1 10022 #define P_MCPU_INTR_GRP 4284615692 #define VDIN0_ACTIVE_MAX_PIX_CNT_STATUS 4611 #define P_HEVC_SAO_MMU_WR 4284668128 #define mLVDS2_reset_offset 29 #define HCODEC_MC_IDCT_DAT 6476 #define P_C_DATA 4291866636 #define MB_MOTION_MODE 3079 #define P_HEVC_ANC16_CANVAS_ADDR 4284671616 #define POL_CNTL_ADDR 5255 #define HCODEC_ASSIST_TIMER0_HI 4193 #define I2SIN_SIZE 8 #define VLD_MEM_VIFIFO_START_PTR 3136 #define HEVC_MDEC_PICR_BUF_STATUS 14777 #define P_AIU_CRC_BIT_SIZE1 4291842352 #define HCODEC_VLC_COEFF 7490 #define P_AIU_CRC_BIT_SIZE0 4291842356 #define P_VDEC2_M4_CONTROL_REG 4284657828 #define P_VDEC2_MDEC_EXTIF_CFG1 4284655508 #define P_VDEC2_MDEC_EXTIF_CFG0 4284655504 #define VDIN0_WR_V_START_END 4642 #define P_HEVC_RV_AI_MB_COUNT 4284676144 #define P_SPICC0_RXDATA 4291899392 #define P_HEVC_DBLK_RV8_QUANT 4284671448 #define DI_INTR_CTRL 5936 #define RV_AI_MB_COUNT 3596 #define SHARP_SR2_YBIC_HCOEF1 12889 #define SHARP_SR2_YBIC_HCOEF0 12888 #define HCODEC_ASSIST_TIMER0_LO 4192 #define P_HCODEC_VLC_SPECIAL_CTL 4284642440 #define LSB_FIRST 4 #define P_MCDI_MCINFORD_X 4287676012 #define P_MCDI_MCINFORD_Y 4287676016 #define P_HEVC_SAO_MMU_RPTR 4284668148 #define DC_CAV_LUT_RDATAH 88 #define DC_CAV_LUT_RDATAL 84 #define P_I2C_M_2_WDATA_REG1 4291940372 #define HCODEC_ASSIST_MBOX2_MASK 4218 #define P_I2C_M_2_WDATA_REG0 4291940368 #define P_AHB_BRIDGE_CNTL_REG1 4291883540 #define P_AHB_BRIDGE_CNTL_REG2 4291883544 #define VDIN_WR_V_START_END 4642 #define SRSHARP0_HLTI_CON_2_GAIN_1 12856 #define SRSHARP0_HLTI_CON_2_GAIN_0 12855 #define VDIN1_HSC_INI_CTRL 5133 #define P_HEVC_IQIT_SCALELUT_IDX_8 4284668952 #define P_HEVC_PARSER_CMD_FETCH 4284662864 #define P_HEVC_HDEC_MC_MBRIGHT_RD 4284671176 #define VPP_WRAP_OSD2_MATRIX_CLIP 15736 #define LDIM_STTS_MATRIX_OFFSET0_1 6856 #define P_IE_RESULT_BUFFER 4284644624 #define P_HEVC_MB_MOTION_MODE 4284674076 #define P_HEVC_HDEC_MC_OMEM_AUTO 4284671168 #define P_WRRSP_IMEM 4284615948 #define P_VIU2_OSD1_BLK3_CFG_W0 4287658140 #define IE_SAD_3 8040 #define IE_SAD_2 8039 #define IE_SAD_1 8038 #define IE_SAD_0 8037 #define P_VIU2_OSD1_BLK3_CFG_W2 4287658148 #define P_VIU2_OSD1_BLK3_CFG_W1 4287658144 #define P_VIU2_OSD1_BLK3_CFG_W4 4287658072 #define P_VIU2_OSD1_BLK3_CFG_W3 4287658152 #define P_HEVC_MC_PIC_W_H 4284671008 #define ASYNC_FIFO2_REG1 9217 #define ASYNC_FIFO2_REG0 9216 #define ASYNC_FIFO2_REG3 9219 #define P_VIU_OSD1_MATRIX_COEF11_12 4287654476 #define ASYNC_FIFO2_REG2 9218 #define VIU2_SW_RESET0 7682 #define P_VPP_OSD_SCALE_COEF_IDX 4287657776 #define P_DI_IF1_CHROMA_X0 4287651760 #define HEVCD_MPP_L1_WEIGHT_FLAG_ADDR 13437 #define P_HEVC_MPRED_DBG_DATA_2 4284664136 #define P_HEVC_MPRED_DBG_DATA_3 4284664140 #define P_HEVC_MPRED_DBG_DATA_0 4284664128 #define P_HEVC_MPRED_DBG_DATA_1 4284664132 #define P_QDCT_JPEG_DCT_COEFF67 4284644544 #define HCODEC_RV_AI_V_X 7691 #define NR_ALP1_ERR2CURV_LIMIT 12828 #define P_HEVC_MPRED_DBG_DATA_6 4284664152 #define P_DI_IF1_CHROMA_Y0 4287651764 #define P_HEVC_MPRED_DBG_DATA_7 4284664156 #define P_HEVC_MPRED_DBG_DATA_4 4284664144 #define P_HEVC_MPRED_DBG_DATA_5 4284664148 #define P_VDEC2_PSCALE_RBUF_START_BLKX 4284654740 #define P_VDEC2_PSCALE_RBUF_START_BLKY 4284654744 #define P_SPICC1_ENHANCE_CNTL 4291907640 #define P_AIFIFO_TIME_STAMP_SYNC_1 4291842632 #define P_AIFIFO_TIME_STAMP_SYNC_0 4291842628 #define I2C_M_1_TOKEN_LIST1 30723 #define I2C_M_1_TOKEN_LIST0 30722 #define HCODEC_MC_PIC_W_H 6408 #define DOLBY_CORE2A_DMA_PORT 13375 #define AUDIN_FIFO_INT 13394 #define SRSHARP0_LTI_CTI_DIR_AC_DBG 12845 #define DNR_DB_YVDELTA_GAIN 11542 #define P_HCODEC_QDCT_MB_MEM_CTL 4284644440 #define ENCT_VFIFO2VD_LINE_TOP_START 7203 #define VPP_XVYCC_MISC 7631 #define P_HCODEC_MDEC_PICR_BUF_STATUS 4284638948 #define P_HEVC_DBLK_Y_BHFILT 4284671324 #define P_QDCT_JPEG_DCT_COEFF45 4284644540 #define NR4_ALP0C_ERR2CURV_LIMIT1 11692 #define NR4_ALP0C_ERR2CURV_LIMIT0 11691 #define ENCI_VBI_CC625_LN 6948 #define IE_I4_PRED_MODE_HI 8005 #define ASYNC_FIFO2_REG5 9221 #define HEVCD_MPP_DECOMP_AXIURG_CTL 13511 #define ASYNC_FIFO2_REG4 9220 #define VLC_HUFFMAN_ADDR 7514 #define VDEC2_VLD_MEM_VIFIFO_END_PTR 11330 #define MCDI_LMV_RT 12044 #define P_HEVC_INTRA_QUANT_MATRIX 4284676104 #define P_VPU_VLOCK_RO_M_INT_FRAC 4287676544 #define HCODEC_QDCT_STATUS_CTRL 7936 #define ENCL_VIDEO_MODE 7335 #define P_HEVC_ASSIST_MBOX1_CLR_REG 4284662228 #define DI_IF2_CHROMA0_RPT_PAT 8216 #define P_VDEC2_SLICE_QP 4284657704 #define SRSHARP0_PK_OS_VERT_CORE_GAIN 12836 #define P_VENC_SYNC_ROUTE 4287655296 #define P_QDCT_JPEG_DCT_COEFF89 4284644548 #define VDEC2_PSCALE_CTRL1 10537 #define VDEC2_PSCALE_CTRL2 10542 #define P_AUDIN_FIFO0_END 4291874948 #define VDIN0_CHROMA_DATA_PORT 4652 #define MBREAK_STAUTS 794 #define P_HEVC_SAO_VB_RPTR 4284667996 #define GE2D_DST_X_START_END 182 #define VPP_VSC_REGION4_PHASE_SLOPE 7436 #define P_HEVC_DBLK_MB_WID_HEIGHT 4284671304 #define P_HCODEC_VLD_SHIFT_STATUS 4284641516 #define P_VDEC2_DBLK_CTRL1 4284655100 #define P_DI_CHAN2_DUMMY_PIXEL 4287651528 #define HEVC_SAO_TILE_START 13831 #define HCODEC_VLD_STATUS 7226 #define P_HCODEC_WRRSP_VLD 4284639080 #define HCODEC_ASSIST_MBOX1_CLR_REG 4213 #define P_LVDS_BIST_CNTL0 4287648692 #define VDEC2_ANC24_CANVAS_ADDR 10664 #define VPP2_INT_LINE_NUM 7712 #define P_NR_DB_FLT_YC_THRD 4287683812 #define DBLK_CB_FILT 2399 #define HEVC_SAO_IF_STATUS 12592 #define P_QDCT_JPEG_DCT_STATUS0 4284644524 #define P_QDCT_JPEG_DCT_STATUS1 4284644528 #define P_HEVC_VOFF_STATUS 4284674288 #define HEVC_DECODER_BUFFER_INFO 15375 #define VDEC2_MC_DP_MB_XY 10510 #define mLVDS2_data_write_toggle 18 #define ABUF_ARB_CTL0 15480 #define HEVC_DBLK_STRONG 14709 #define P_AFBC_LBUF_DEPTH 4287654804 #define VPU_PROT1_GEN_CNTL 10065 #define P_ENCL_TST_Y 4287656552 #define P_SPICC1_DMAREG 4291907600 #define AIU_AMCLK_MSR 5202 #define P_HCODEC_FST_FOR_MV_X 4284641344 #define P_HCODEC_FST_FOR_MV_Y 4284641348 #define P_NR2_RO_POLAR3_32 4287673996 #define P_ENCT_DACSEL_1 4287656488 #define VPP_OSD_HSC_INI_PAT_CTRL 7622 #define P_ENCT_DACSEL_0 4287656484 #define VBO_ACT_VSIZE 5221 #define P_HEVC_VIFF_BIT_CNT 4284674152 #define VPP_HSC_PHASE_CTRL1 7476 #define P_CDB_CTRL 4284615924 #define P_LCD_PWM1_HI_ADDR 4287648508 #define ASYNC_FIFO_FLUSH_CNT_LSB 0 #define HCODEC_CBREAK3_REG 4919 #define MCDI_LMV_LOCK_RT_MODE 12108 #define HEVC_MPRED_L1_REF11_POC 12859 #define SRSHARP0_VLTI_FLT_CON_CLP 12858 #define ENCI_YC_DELAY 6998 #define VDEC2_CDB_DATA_REG 9020 #define ASYNC_FIFO_RESIDUAL_LSB 15 #define P_STH2_VE_ADDR 4287648348 #define OSD_PATH_MISC_CTRL 6670 #define VIUB_SW_RESET0 8194 #define HCODEC_ANC4_CANVAS_ADDR 6548 #define MCDI_GMV_GAIN 12053 #define P_ANC30_CANVAS_ADDR 4284622520 #define ADAPTIVE_SCALE_DATA 12630 #define P_HCODEC_PSCALE_BMEM_DAT 4284638336 #define VKS_START_CTRL 12554 #define P_ENCL_DBG_PX_RST 4287656612 #define P_HCODEC_ANC21_CANVAS_ADDR 4284638868 #define AIU_MEM_IEC958_RD_PTR 5222 #define SPDIF_CLKNUM_32K 0 #define P_VDIN_MISC_CTRL 4287667720 #define ENCI_TST_VDCNT_STSET 7191 #define HEVC_MC_MB_INFO 14593 #define P_AIU_958_CTRL 4291842088 #define HEVC_MDEC_DOUBLEW_CFG3 14814 #define HEVC_MDEC_DOUBLEW_CFG2 14813 #define P_HCODEC_VLD_TIME_STAMP_SYNC_0 4284641576 #define HEVC_MDEC_DOUBLEW_CFG5 14816 #define HEVC_MDEC_DOUBLEW_CFG4 14815 #define HEVC_MDEC_DOUBLEW_CFG7 14818 #define P_HCODEC_VLD_TIME_STAMP_SYNC_1 4284641580 #define HEVC_MDEC_DOUBLEW_CFG6 14817 #define P_MCDI_PD_22_CHK_FRC_LMV 4287675764 #define HEVC_MDEC_DOUBLEW_CFG1 14812 #define HEVC_MDEC_DOUBLEW_CFG0 14811 #define P_VPP2_MATRIX_COEF11_12 4287653256 #define CPV2_SEL 7 #define P_DBLK_RV8_QUANT 4284622296 #define P_VIU_OSD1_BLK2_CFG_W4 4287653972 #define P_VIU_OSD1_BLK2_CFG_W2 4287654036 #define P_VIU_OSD1_BLK2_CFG_W3 4287654040 #define P_VIU_OSD1_BLK2_CFG_W0 4287654028 #define P_VIU_OSD1_BLK2_CFG_W1 4287654032 #define P_AIFIFO2_TIME_STAMP_SYNC_0 4291842660 #define P_AIFIFO2_TIME_STAMP_SYNC_1 4291842664 #define P_HEVCD_IPP_TOP_FRMCTL 4284665884 #define DBLK_Y_HFILT_HIGH 2397 #define P_VPU_HDMI_SETTING 4287667308 #define P_ENCP_VFIFO2VD_CTL 4287655264 #define DNR_DM_NR_BLND 11617 #define DI_IF1_LUMA0_RPT_PAT 6127 #define AUDIN_FIFO1_HOLD1_SEL 24 #define SPI_FLASH_USR 18 #define VIUB_ADDR_START 8192 #define HEVC_CMAX_REG 13107 #define HCODEC_VLC_DBG_READ 7511 #define NR4_MCNR_ALP1_MVX_LUT1 14105 #define VI_HIST_CTRL 11776 #define NR4_MCNR_ALP1_MVX_LUT3 14107 #define P_DECOMB_FRM_SIZE 4287673916 #define NR4_MCNR_ALP1_MVX_LUT2 14106 #define ENCP_DE_V_END_EVEN 7229 #define P_HEVC_MPRED_L0_REF03_POC 4284663948 #define P_GAMMA_CNTL_PORT 4287648256 #define P_HCODEC_VLD_REVERVED_19 4284641380 #define VDIN1_HIST_SPL_PIX_CNT 5173 #define P_MCDI_REL_DET_LMV_DIF_CHK 4287675584 #define P_VPP_XVYCC_MISC 4287657788 #define HEVC_PARSER_IF_CONTROL 12578 #define P_HCODEC_DBLK_MB_WID_HEIGHT 4284638536 #define HCODEC_MINDEX0_REG 4874 #define HEVC_SHIFT_STATUS 12555 #define P_NR_DB_FLT_SEED3 4287683836 #define VDEC2_MPEG1_2_REG 11265 #define P_VBO_TMCHK_VSYNC_STATE_L 4287648720 #define P_VBO_TMCHK_VSYNC_STATE_H 4287648724 #define D2D3_PRE_SCD_H 11013 #define P_VPU_VLOCK_RO_VS_I_DIST 4287676484 #define P_ENCT_VIDEO_BLANKY_VAL 4287656432 #define D2D3_PRE_SCD_V 11019 #define HCODEC_ME_F_SKIP_SAD 8019 #define P_MLVDS_RESET_PATTERN_EXT 4287648536 #define P_VDEC2_DCAC_CPU_ADDRESS 4284659792 #define P_HEVC_MPRED_L1_REF00_POC 4284664000 #define P_HEVC_CPU_TRACE 4284665344 #define VDEC2_DBLK_MB_XY 10581 #define P_HCODEC_MC_HCMDBUF_L 4284638500 #define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 13400 #define P_MBA_INC 4284624920 #define SRSHARP1_SHARP_SR2_YBIC_HCOEF1 13401 #define VENC_VIDEO_TST_MDSEL 7025 #define HEVC_SHIFT_STARTCODE 12553 #define P_ENCI_VFIFO2VD_CTL2 4287656060 #define VPU_PROT1_RBUF_ROOM 10072 #define ME_WEIGHT 8032 #define P_HEVC_WRRSP_FIFO_PICW_MC 4284671740 #define P_VLD_MEM_VBUF_RD_PTR 4284625228 #define AIU_AUDAC_CTRL0 5203 #define P_AIU_I2S_FF_CTRL 4291842128 #define P_VI_HIST_BLACK_WHITE_VALUE 4287674532 #define IE_I4_PRED_MODE_LO 8006 #define P_VPP2_HSC_INI_PAT_CTRL 4287653076 #define P_HCODEC_MC_HCMDBUF_H 4284638496 #define P_VBO_REGION_03 4287648164 #define P_VBO_REGION_02 4287648160 #define P_VBO_REGION_01 4287648156 #define P_VBO_REGION_00 4287648152 #define P_HCODEC_HDEC_MC_MBRIGHT_RD 4284638408 #define VKS_PRELPF_YCOEF0 12546 #define VKS_PRELPF_YCOEF1 12547 #define P_DI_CONTRD_CTRL 4287651484 #define DVIN_DISPLAY_SIZE 2276 #define P_HCODEC_AVSP_IQ_WQ_PARAM_23 4284643432 #define P_SHARP_DEJ_ALPHA 4287678868 #define VPU_PROT1_RPT_PAT 10070 #define VPU_DI_MTNRD_MMC_CTRL 9992 #define VDIN_MEAS_CTRL0 4698 #define P_MBREAK1_REG 4284615764 #define PFIFO_MONITOR 14456 #define AIU_MIX_CTRL 5144 #define HCODEC_RV_AI_U_X 7690 #define P_HCODEC_AVSP_IQ_WQ_PARAM_01 4284643428 #define P_ENCP_VIDEO_PB_SCL 4287655440 #define P_AUDIN_FIFO1_START 4291875020 #define HEVC_ANC25_CANVAS_ADDR 14761 #define DITH8_CNTL_MSB 3 #define P_VIU2_OSD1_COLOR 4287658056 #define P_NR4_RO_NR4_BLDVS2_SUM 4287683732 #define P_HEVC_VLD_TIME_STAMP_CNTL 4284674340 #define ANC17_CANVAS_ADDR 2465 #define P_ENCP_VIDEO_VSPULS_ELINE 4287655544 #define NR2_IIR_CTRL 5966 #define AUDIN_FIFO0_HOLD2_EN 21 #define AIU_958_DISCARD_NUM 5126 #define VDIN1_INTF_WIDTHM1 5148 #define P_ENCL_VIDEO_VAVON_ELINE 4287656652 #define P_HCODEC_ME_START_POSITION 4284644648 #define P_HCODEC_AVSP_IQ_WQ_PARAM_45 4284643436 #define AUDIN_MEM_PD 13482 #define HCODEC_V3_F_ZERO_CTL_1 8053 #define HCODEC_V3_F_ZERO_CTL_0 8052 #define PARSER_VIDEO2_START_PTR 14483 #define SRSHARP1_PK_CON_2DRTHPGAIN_LIMIT 13322 #define HEVC_IQIT_DEQUANT_CTRL 14081 #define P_NR4_MCNR_SKIN_CLIP0 4287674196 #define P_NR4_MCNR_SKIN_CLIP1 4287674200 #define VIU_OSD1_BLK1_CFG_W3 6690 #define VIU_OSD1_BLK1_CFG_W2 6689 #define VIU_OSD1_BLK1_CFG_W4 6676 #define VIU_OSD1_BLK1_CFG_W1 6688 #define VIU_OSD1_BLK1_CFG_W0 6687 #define VPP2_MATRIX_OFFSET2 6502 #define P_QDCT_MB_WR_PTR 4284644424 #define P_RESYNC_MARKER_LENGTH 4284624952 #define HCODEC_MFDIN_REG3_CANV 4107 #define NR4_MCNR_DC2NORM_LUT2 11738 #define NR4_MCNR_DC2NORM_LUT1 11737 #define P_HCODEC_QDCT_Q_QUANT_I 4284644464 #define NR4_MCNR_DC2NORM_LUT0 11736 #define P_HCODEC_QDCT_Q_QUANT_P 4284644468 #define P_PARSER_CONTROL 4291879296 #define P_HEVC_DBLK_OST_CBCRDIFF 4284671480 #define P_AUDIN_DECODE_CHANNEL_STATUS_A_1 4291874900 #define VCTI_BST_CORE 12865 #define P_AUDIN_DECODE_CHANNEL_STATUS_A_2 4291874904 #define P_AUDIN_DECODE_CHANNEL_STATUS_A_0 4291874896 #define P_AUDIN_DECODE_CHANNEL_STATUS_A_5 4291874916 #define P_AUDIN_DECODE_CHANNEL_STATUS_A_3 4291874908 #define P_AUDIN_DECODE_CHANNEL_STATUS_A_4 4291874912 #define HCODEC_ANC14_CANVAS_ADDR 6558 #define AUDOUT_BUF1_STA 13445 #define VDEC_ASSIST_DMA_INT 100 #define P_NR4_MCNR_GREEN_CENT 4287674164 #define P_DI_DIWR_Y 4287651612 #define P_DI_DIWR_X 4287651608 #define P_VDEC2_DBLK_GCLK_FREE 4284655024 #define VIFF_BIT_CNT 3098 #define P_HCODEC_MINDEX4_REG 4284632120 #define HCODEC_VLC_CONFIG 7425 #define ABUF_WR_CUR_FF_CNT_MSB 21 #define DEMO_CRTL 12886 #define P_VDEC2_PSCALE_PICO_SHIFT_XY 4284654752 #define P_PWM_PWM_C 4291928064 #define P_PWM_PWM_D 4291928068 #define P_PWM_PWM_A 4291932160 #define P_PWM_PWM_B 4291932164 #define MCDI_RO_FLD_PD_22_FLT_CNT1 12236 #define MCDI_RO_FLD_PD_22_FLT_CNT2 12239 #define VIU2_OSD1_BLK2_CFG_W0 7715 #define P_L_RGB_COEFF_ADDR 4287647768 #define P_IE_C_PRED_MODE 4284644636 #define VPP2_HSC_REGION12_STARTP 6416 #define P_MB_MOTION_MODE 4284624924 #define P_HEVC_MDEC_PIC_DC_MUX_CTRL 4284671540 #define P_RESET3_LEVEL 4291825804 #define P_ENCP_VIDEO_VSO_BLINE 4287655596 #define P_PWM_PWM_E 4291923968 #define P_PWM_PWM_F 4291923972 #define P_HCODEC_VLC_DC_RD_REQ 4284642580 #define P_VLC_MB_HEADER_INFO 4284642552 #define HCODEC_IE_CONTROL 8000 #define P_NR_ALP1_ERR2CURV_TH_RATE 4287678572 #define P_HEVC_MC_HCMDBUF_L 4284671268 #define P_HEVC_MC_HCMDBUF_H 4284671264 #define MBREAK_TYPE 792 #define VIUB_MISC_CTRL0 8198 #define H_RD 12 #define HCODEC_DBLK_CTRL1 6527 #define HEVC_VLD_ERROR_MASK 15406 #define P_ME_SUB_SNAP_GLITCH 4284644728 #define VPP2_HSC_REGION1_PHASE_SLOPE 6421 #define P_ENCI_MACV_N14 4287655160 #define P_ENCI_MACV_N15 4287655164 #define P_ENCI_MACV_N12 4287655152 #define SRSHARP0_PK_NR_ENABLE 12839 #define VDIN1_HIST_MAX_MIN 5171 #define P_ENCI_MACV_N13 4287655156 #define P_ENCI_MACV_N10 4287655144 #define P_ENCI_MACV_N11 4287655148 #define HEVC_MB_INFO 15404 #define P_ENCI_MACV_N18 4287655176 #define P_ENCI_MACV_N19 4287655180 #define P_ENCI_MACV_N16 4287655168 #define P_HEVC_ASSIST_DMA_INT_MSK 4284662164 #define P_ENCI_MACV_N17 4287655172 #define P_D2D3_PRE_SCD_H 4287671316 #define P_GE2D_TID_TOKEN 4287890332 #define P_VPP_EOTF_3X3_OFST_0 4287678304 #define P_VPP_EOTF_3X3_OFST_1 4287678308 #define P_VLC_COEFF 4284642568 #define HEVC_DBLK_VLD_HCMD2 14714 #define HEVC_DBLK_VLD_HCMD1 14715 #define HEVC_DBLK_VLD_HCMD0 14716 #define P_AUDIN_HDMI_MEAS_INTR_MASKN 4291875464 #define P_D2D3_PRE_SCD_V 4287671340 #define P_WM_CTRL 4287678144 #define MDEC_EXTIF_STS0 2534 #define GAMMA_TR 2 #define VPP_EOTF_COEF00_01 12753 #define P_VD1_IF0_CHROMA1_RPT_PAT 4287654268 #define HEVC_FST_FOR_MV_Y 15377 #define HEVC_FST_FOR_MV_X 15376 #define DITH8_CNTL 0 #define P_AUDIN_FIFO0_CTRL 4291874964 #define MIPI_DSI_DWC_VID_MODE_CFG_OS 7182 #define P_VPP_VSC_REGION4_PHASE_SLOPE 4287657008 #define GE2D_HSC_NRND_POINT 195 #define HEVC_RV_AI_V_X 15883 #define GE2D_SCALE_COEF 213 #define HCODEC_PSCALE_MCMD_CTRL 6434 #define HCODEC_V3_SKIP_WEIGHT 8048 #define L_VCOM_HSWITCH_ADDR 5148 #define P_HEVC_IQIT_STAT_GEN2 4284668976 #define P_HEVC_IQIT_STAT_GEN1 4284668968 #define P_HEVC_IQIT_STAT_GEN0 4284668960 #define P_HCODEC_QP_CTRL_REG 4284643332 #define P_DI_IF1_RANGE_MAP_Y 4287651824 #define P_HEVC_ASSIST_MBOX2_FIQ_SEL 4284662252 #define P_VDEC2_WRRSP_IMEM 4284648716 #define P_VP9D_MPP_REF_SCALE_ENBL 4284666116 #define P_ME_MV_WEIGHT_23 4284644700 #define P_HEVC_CMIN_REG 4284665032 #define OEV3_HS_ADDR 5303 #define P_DE_HE_ADDR 4287648584 #define P_HEVC_SAO_MMU_VH1_ADDR 4284668140 #define HCODEC_CBREAK_STAUTS 4922 #define I2SIN_CLK_SEL 1 #define ANC11_CANVAS_ADDR 2459 #define P_HCODEC_VLD_MEM_VIFIFO_LEVEL 4284641564 #define ENCP_VFIFO2VD_LINE_TOP_END 7004 #define P_MCDI_MOTION_PARADOX_THD 4287675720 #define VDEC2_ANC29_CANVAS_ADDR 10669 #define P_ENCI_MACV_N21 4287655188 #define P_ENCI_MACV_N22 4287655192 #define P_ENCI_MACV_N20 4287655184 #define MCDI_REL_DET_RPT_CHK_ROW 12083 #define P_VPU_RDWR_ARB_STATUS_L1C2 4287667824 #define AIU_958_BPF 5120 #define HEVCD_IPP_CONFIG 13320 #define P_HCODEC_VLD_MEM_VBUF_RD_PTR 4284641612 #define VLC_PUSH_ELEMENT 7456 #define P_VPU_RDWR_ARB_STATUS_L1C1 4287667808 #define ENCP_MACV_ENDLINE 7112 #define HEVC_SAO_MMU_RPTR 13885 #define P_HEVC_SAO_VB_WR_START_ADDR 4284667976 #define P_DNR_LUMA 4287673384 #define VLD_MEM_VIFIFO_BUF_CNTL 3144 #define EE_ASSIST_MBOX0_MASK 8306 #define ENCP_DVI_VSO_BEGIN_ODD 7223 #define P_VDEC2_ASSIST_MBOX1_IRQ_REG 4284645840 #define P_VDEC2_ANC14_CANVAS_ADDR 4284655224 #define ASYNC_FIFO_RESIDUAL_MSB 19 #define AIU_CODEC_DAC_LRCLK_CTRL 5160 #define HENC_TOP_INFO_1 7481 #define HENC_TOP_INFO_0 7479 #define P_VSYNC_HE_ADDR 4287648616 #define P_ENCP_DE_V_END_ODD 4287656188 #define DNR_DM_VAR_EDGE_DIF_THD2 11627 #define MIPI_DSI_DWC_LPCLK_CTRL_OS 7205 #define P_VLC_STATUS_CTRL 4284642304 #define P_HEVC_DBLK_MB_XY 4284671316 #define P_ENCP_SYNC_LINE_LENGTH 4287656208 #define VENC_VDAC_TST_VAL 7039 #define VDEC2_CBREAK_CTRL 9017 #define ENCL_TST_CLRBAR_WIDTH 7326 #define P_PWM_BLINK_EF 4291923996 #define P_WRRSP_FIFO_PICW_DBK 4284622584 #define P_ME_MV_MERGE_CTL 4284644692 #define LCD_GPIO 0 #define MSR_CLK_DUTY 24576 #define P_DI_EI_CTRL7 4287650932 #define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 15737 #define P_DI_EI_CTRL8 4287650936 #define P_DI_EI_CTRL9 4287650940 #define P_DI_EI_CTRL0 4287650832 #define P_DI_EI_CTRL1 4287650836 #define P_DI_EI_CTRL2 4287650840 #define P_DI_EI_CTRL3 4287650916 #define P_DI_EI_CTRL4 4287650920 #define P_DI_EI_CTRL5 4287650924 #define P_DI_EI_CTRL6 4287650928 #define P_DI_CHAN2_RPT_LOOP 4287651820 #define P_DI_INP_RPT_LOOP 4287651664 #define P_VPP_MISC 4287657112 #define MEDIA_CPU_INTR_MASK 15402 #define SRSHARP0_SR3_DERING_PARAM0 12914 #define VPU_DI_INP_MMC_CTRL 9991 #define VDEC2_DBLK_GCLK_FREE 10604 #define VPP_MATRIX_COEF20_21 7523 #define P_VPP2_OSD_SCALE_COEF 4287653684 #define P_ENCP_VIDEO_HSPULS_BEGIN 4287655520 #define P_AIU_MEM_I2S_CONTROL 4291842448 #define L_VSYNC_HS_ADDR 5209 #define NR4_SNR_CTRL_REG 11689 #define HEVC_LAST_MVX 15409 #define HEVC_LAST_MVY 15410 #define VDIN1_MATRIX_PRE_OFFSET2 5145 #define P_HEVC_NEXT_INTRA_DMA_ADDRESS 4284676148 #define P_HEVC_DBLK_OST_YBASE 4284671476 #define P_ME_MV_WEIGHT_01 4284644696 #define P_HEVC_SAO_Y_LENGTH 4284667952 #define P_L_GAMMA_PROBE_CTRL 4287647780 #define P_CINDEX7_REG 4284615876 #define P_AIU_I2S_MED_THRESH 4291842108 #define P_HCODEC_VLC_PIC_POSITION 4284642508 #define ENCP_SYNC_PIXEL_EN 7237 #define MCDI_PD22_CHK_THD_RT 12118 #define AIU_MEM_AIFIFO2_END_PTR 5228 #define VPP_DNLP_CTRL_10 7563 #define VPP_DNLP_CTRL_12 7565 #define VPP_DNLP_CTRL_11 7564 #define VPP_DNLP_CTRL_14 7567 #define VPP_DNLP_CTRL_13 7566 #define VPP_DNLP_CTRL_15 7568 #define VDIN_WIDTHM1I_WIDTHM1O 4618 #define MCDI_MCINFORD_CTRL 12189 #define HEVC_MPRED_PIC_SIZE 12805 #define HCODEC_IE_CUR_REF_SEL 8008 #define P_VDEC2_DBLK_Y_HFILT_HIGH 4284654964 #define DI_EI_CTRL10 6035 #define DI_EI_CTRL11 6046 #define DI_EI_CTRL12 6047 #define DI_EI_CTRL13 6056 #define P_AUDIN_FIFO1_END 4291875024 #define DI_INP_FMT_W 6106 #define AIU_958_PAUSE_PD_LENGTH 5159 #define mLVDS2_ins_reset 8 #define RDMA_ACCESS_AUTO 4368 #define P_VDEC2_MB_WIDTH 4284657700 #define VDEC2_MDEC_PICW_BUF_STATUS 10682 #define P_L_OEV2_HS_ADDR 4287647948 #define GE2D_SRC_OUTSIDE_ALPHA 214 #define VPP_DNLP_CTRL_01 7554 #define VPP_DNLP_CTRL_00 7553 #define VPP_DNLP_CTRL_03 7556 #define VPP_DNLP_CTRL_02 7555 #define VPP_DNLP_CTRL_05 7558 #define VPP_DNLP_CTRL_04 7557 #define VPP_DNLP_CTRL_07 7560 #define P_HEVC_MPEG1_2_REG 4284674052 #define VPP_DNLP_CTRL_06 7559 #define RESET1_MASK 1041 #define VPP_DNLP_CTRL_09 7562 #define VPP_DNLP_CTRL_08 7561 #define P_HEVC_F_CODE_REG 4284674056 #define AFBC_MODE 6881 #define P_ENCT_VIDEO_VSO_BEGIN 4287656412 #define P_AIU_MEM_AIFIFO_LEVEL 4291842604 #define MEDIA_CPU_INTR_STAT 15400 #define P_DBLK_CTRL1 4284622332 #define VPP_HSHARP_LUMA_THRESH23 7506 #define P_ANC25_CANVAS_ADDR 4284622500 #define NR4_MCNR_BLD_VS2LUT0 14085 #define HCODEC_PSCALE_DRAM_BUF_CTRL 6433 #define NR4_MCNR_BLD_VS2LUT1 14086 #define P_NR_ALP1_MIERR_CORING 4287678568 #define VI_HIST_H_START_END 11777 #define VPP_MATRIX_PROBE_COLOR1 7639 #define HEVC_ASSIST_MBOX0_IRQ_REG 12400 #define AIU_I2S_MISC 5138 #define HEVC_DCAC_DMA_CTRL 15890 #define VPP_HSHARP_LUMA_THRESH01 7505 #define PSCALE_BMEM_ADDR 2335 #define P_ANC14_CANVAS_ADDR 4284622456 #define P_VIU_OSD2_MATRIX_CTRL 4287654592 #define VDEC2_IQ_QUANT 11799 #define P_HEVC_DC_AC_SCALE_MUL 4284676120 #define HEVC_CINDEX6_REG 13104 #define DNR_DB_HACT 11535 #define P_VPP2_SMOKE1_VAL 4287653032 #define P_NR4_MCNR_CM_BLUE_CLIP0 4287674156 #define P_NR4_MCNR_CM_BLUE_CLIP1 4287674160 #define P_ENCT_MAX_LINE_SWITCH_POINT 4287656480 #define AFBC_ENABLE 6880 #define MDB_DATA_REG 796 #define P_HCODEC_CINDEX2_REG 4284632240 #define P_HCODEC_MDEC_SW_RESET 4284638736 #define P_VPP2_SC_MISC 4287652964 #define P_AIU_958_PAUSE_PAYLOAD 4291842196 #define HCODEC_SLICE_START_BYTE_23 7181 #define MDEC_PIC_DC_THRESH 2488 #define SPICC0_DRADDR 19464 #define VPP_HLTI_PARA 7634 #define AHB_MP4_MC_CTL 15455 #define P_ACC0REG2 4284616132 #define I2C_M_1_SLAVE_ADDR 30721 #define VPP2_OSD_VSC_CTRL0 6594 #define HCODEC_SLICE_START_BYTE_01 7180 #define P_VPP_VADJ2_MC_MD 4287657240 #define P_ACC0REG1 4284616068 #define P_DET3D_RAMRD_ADDR_PORT 4287651432 #define ENCT_VFIFO2VD_CTL 7200 #define P_SHARP_HVBLANK_NUM 4287678468 #define HCODEC_ANC20_CANVAS_ADDR 6564 #define ISA_TIMER_MUX1 15460 #define DI_DIWR_X 6086 #define DI_DIWR_Y 6087 #define VPP2_MATRIX_PROBE_COLOR 6492 #define P_VLD_MEM_VIFIFO_WP 4284625172 #define P_MCDI_REF_ERR_GAIN1 4287675504 #define P_HEVC_MPRED_L0_REF15_POC 4284663996 #define P_MCDI_REF_ERR_GAIN0 4287675500 #define DC_AC_CTRL 3589 #define ENCP_MACV_AGC_END 7109 #define P_AIU_MEM_AIFIFO_MAN_RP 4291842600 #define P_VDIN_MEAS_VS_COUNT_LO 4287646064 #define P_L_OEV1_VS_ADDR 4287647940 #define P_PK_CIRFB_HP_CORING 4287678524 #define VIU_OSD1_BLK3_CFG_W4 6678 #define VBO_LANE_SKEW_H 5231 #define VBO_LANE_SKEW_L 5230 #define VIU_OSD1_BLK3_CFG_W3 6698 #define VIU_OSD1_BLK3_CFG_W2 6697 #define VIU_OSD1_BLK3_CFG_W1 6696 #define VIU_OSD1_BLK3_CFG_W0 6695 #define P_ENCL_VFIFO2VD_PIXEL_END 4287656520 #define OSD_DB_FLT_CTRL 12608 #define P_HEVC_M4_CONTROL_REG 4284674212 #define DBLK_CR_BFILT 2395 #define P_VDIN_BLKBAR_ROW_TH1_TH2 4287646096 #define VDEC2_LMEM_DMA_CTRL 9040 #define HEVC_DBLK_CBPC_ADJ 14707 #define STH2_SEL 12 #define HCODEC_VLC_HUFFMAN_DATA 7515 #define P_HEVC_CDB_DATA_REG 4284665072 #define P_HEVC_MPRED_VERSION 4284663808 #define VCOM_VE_ADDR 5278 #define ENCP_VFIFO2VD_LINE_BOT_START 7005 #define SRSHARP0_SR3_DRTLPF_EN 12902 #define P_OSD_BLEND_CURRENT_XY 4287654584 #define AIU_MIX_GAIN 5147 #define tcon_pclk_div 24 #define ABUF_WR_PLY_RPT_LVL 1 #define VPP_SCALE_COEF 7428 #define P_PARSER_VIDEO2_RP 4291879512 #define AFBC_MIF_VER_SCOPE 6894 #define SRSHARP0_VCTI_BST_GAIN 12864 #define P_PWM_BLINK_CD 4291928092 #define PSCALE_MCMD_CTRL 2338 #define VPP2_MISC1 6518 #define P_PARSER_VIDEO2_WP 4291879508 #define P_VDEC2_ASSIST_DMA_INT_MSK 4284645780 #define VDIN_WR_CTRL2 4639 #define P_HEVC_IQIT_SCALELUT_WR_ADDR 4284668936 #define STV1_HS_ADDR 5287 #define VPU_VLOCK_LOOP0_CTRL0 12291 #define P_HCODEC_MCPU_INTR_MSK 4284632080 #define P_VPU_PROT2_GEN_CNTL 4287667588 #define VDIN0_HIST_CTRL 4656 #define VLC_COEFF_RD_REQ 7489 #define VLC_HUFFMAN_DATA 7515 #define P_HCODEC_SLICE_START_BYTE_23 4284641332 #define P_HCODEC_VLC_VB_PRE_BUFF_LOW 4284642420 #define VENC_VDAC_DAC1_FILT_CTRL0 7258 #define P_AHB_ARBITER_REG 4291883272 #define VENC_VDAC_DAC1_FILT_CTRL1 7259 #define HCODEC_ME_SUB_ANY_WEIGHT_SAD 8027 #define P_PWM_BLINK_AB 4291932188 #define HEVC_BYTE_ALIGN_PEAK_LO 15388 #define P_DI_MC_CTRL 4287651004 #define P_AIU_MEM_AIFIFO_MAN_WP 4291842596 #define P_VPU_RDWR_ARB_STATUS_L2C1 4287667844 #define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 7803 #define ENCT_VIDEO_MAX_PXCNT 7280 #define P_HCODEC_ME_PIC_INFO 4284644668 #define VIU2_OSD1_BLK0_CFG_W2 7741 #define VIU2_OSD1_BLK0_CFG_W1 7740 #define VIU2_OSD1_BLK0_CFG_W0 7739 #define DI_IF2_RANGE_MAP_CB 8220 #define VIU2_OSD1_BLK0_CFG_W4 7780 #define VIU2_OSD1_BLK0_CFG_W3 7742 #define NR4_MCNR_AC2NORM_LUT2 11741 #define NR4_MCNR_AC2NORM_LUT0 11739 #define NR4_MCNR_AC2NORM_LUT1 11740 #define P_NR2_FRM_SIZE 4287651136 #define XVYCC_INV_LUT_U_ADDR_PORT 12634 #define P_HCODEC_NON_I_QUANT_MATRIX 4284643340 #define DI_IF2_RANGE_MAP_CR 8221 #define P_VKS_OUT_WIN_SIZE 4287677444 #define HEVC_MC_HCMD_H 14666 #define P_HEVC_VLD_DECODE_CONTROL 4284674144 #define VDIN1_BLKBAR_IND_LEFT2_CNT 5224 #define HEVC_MC_HCMD_L 14667 #define P_DNR_DM_DIR_MISC 4287673744 #define IEC958_TIME_STAMP_SYNC_0 5281 #define IEC958_TIME_STAMP_SYNC_1 5282 #define HEVC_BYTE_ALIGN_PEAK_HI 15387 #define P_ENCL_TST_EN 4287656544 #define P_NR2_RO_POLAR3_P2 4287673992 #define P_NR2_RO_POLAR3_P1 4287673984 #define P_NR3_YMOT_PARA 4287676364 #define P_SPICC0_DRADDR 4291899424 #define HEVCD_MPP_WEIGHT_DATA 13441 #define P_HCODEC_SLICE_START_BYTE_01 4284641328 #define P_VDIN_MEAS_VS_COUNT_HI 4287646060 #define HCODEC_MBREAK3_REG 4887 #define P_ENCI_MACV_PULSE_LO 4287655236 #define P_DBLK_AVSFLAGS 4284622264 #define P_HEVC_MB_WIDTH 4284674084 #define P_VIU_MISC_CTRL1 4287653916 #define P_VIU_MISC_CTRL0 4287653912 #define DI_EI_DRT_PIXTH 6009 #define HEVC_IQIT_BITDEPTH 14091 #define P_MCDI_RO_FLD_PD_22_FOR_CNT 4287676068 #define P_VLC_TOTAL_BYTES 4284642408 #define VDIN_WIN_H_START_END 4717 #define P_ENCL_TST_CB 4287656556 #define P_HCODEC_CBREAK_TYPE 4284632288 #define I2SIN_LRCLK_SKEW 4 #define P_HEVC_MPRED_L1_REF14_POC 4284664056 #define P_VLD_MEM_VIFIFO_RP 4284625176 #define HEVC_MPRED_L0_REF02_POC 12834 #define P_ENCL_TST_CR 4287656560 #define HEVC_RV_AI_U_X 15882 #define L_STV1_VS_ADDR 5161 #define P_VPU_VLOCK_LOOP1_CTRL0 4287676432 #define P_NR2_RO_POLAR3_M2 4287673988 #define P_NR2_RO_POLAR3_M1 4287673980 #define P_DBLK_Y_HFILT_HIGH 4284622196 #define P_STH1_HS_ADDR 4287648320 #define HEVC_MC_HALF_PEL_TWO 14596 #define P_VDIN_WR_CTRL2 4287645820 #define DI_CONTRD_CTRL 6055 #define GAMMA_EN 0 #define P_AUDIN_FIFO0_PIO_STS 4291875520 #define MCDI_RO_FLD_BAD_BADW_CNT 12196 #define P_ENCI_MACV_PULSE_HI 4287655240 #define VENC_ENCP_PIXEL 7020 #define P_HEVC_MC_CMD 4284671000 #define PSCALE_DRAM_BUF_CTRL 2337 #define VDEC_ASSIST_MBOX1_IRQ_REG 116 #define P_PARSER_VIDEO_END_PTR 4291879428 #define HENC_TOP_MV_0 7498 #define HENC_TOP_MV_2 7500 #define HENC_TOP_MV_1 7499 #define HENC_TOP_MV_3 7501 #define P_VIU2_VD1_FMT_CTRL 4287658400 #define ABUF_RD_FF_CLR_PLS 2 #define ENCI_VBI_CGMSDT_L 6951 #define P_HEVC_PSCALE_CMD_BLK_X 4284671088 #define P_HEVC_PSCALE_CMD_BLK_Y 4284671092 #define ENCI_VBI_CGMSDT_H 6952 #define P_AUDOUT_BUF1_WPTR 4291875356 #define D2D3_DPF_LPF_CTRL 11024 #define HCODEC_ME_SUB_FIX_SAD 8028 #define GE2D_SRC2_CLIPX_START_END 176 #define P_VLC_STREAM_BUFF 4284642424 #define OEV2_VS_ADDR 5301 #define DOS_CFG_CMPIF_BRIDGE 16196 #define P_SHARP_SR2_CBIC_HCOEF0 4287678824 #define P_HEVCD_MPP_WEIGHT_DATA 4284666372 #define P_SHARP_SR2_CBIC_HCOEF1 4287678828 #define VDEC_ASSIST_DMA_INT2 102 #define L_OEV3_VS_ADDR 5177 #define P_VPU_CLK_GATE 4287667340 #define HCODEC_PSCALE_CANVAS_RD_ADDR 6444 #define SPICC0_CONREG 19458 #define DOS_VDIN_LCNT 16139 #define P_HEVC_ANC19_CANVAS_ADDR 4284671628 #define P_HEVC_STREAM_WR_PTR 4284662800 #define P_DNR_DB_YHDELTA_GAIN 4287673408 #define HEVC_CMIN_REG 13106 #define VPP_VSC_REGION12_STARTP 7429 #define P_HLTI_BST_GAIN 4287678676 #define P_HCODEC_ANC31_CANVAS_ADDR 4284638908 #define P_MCDI_PD22_CHK_THD 4287675672 #define P_VDEC2_ANC19_CANVAS_ADDR 4284655244 #define P_VPU_RDARB_WEIGH1_SLV_L1C2 4287667912 #define P_VPU_RDARB_WEIGH1_SLV_L1C1 4287667788 #define ENCI_DACSEL_1 7180 #define P_HEVC_ANC30_CANVAS_ADDR 4284671672 #define ENCI_DACSEL_0 7179 #define DCAC_DMA_ADDRESS 3603 #define P_AFBC_BODY_BADDR 4287654812 #define LVDS_USE_TCON 7 #define VDEC2_PSCALE_RST 10512 #define QP_VALUE_REG 3077 #define SPICC0_ENHANCE_CNTL 19470 #define P_HEVC_ANC25_CANVAS_ADDR 4284671652 #define MCDI_CHK_EDGE_THD 12042 #define NR_ALP1_MIERR_CORING 12826 #define HEVC_PARSER_PICTURE_SIZE 12579 #define MINDEX7_REG 785 #define P_VDIN_CHROMA_ADDR_PORT 4287645868 #define P_NR4_MCNR_BLD_VS2LUT0 4287683604 #define P_NR4_MCNR_BLD_VS2LUT1 4287683608 #define WM_STATUS_RAM_RO 12746 #define AUDIN_FIFO2_LVL2 13390 #define AUDIN_FIFO2_LVL1 13389 #define AUDIN_FIFO2_LVL0 13388 #define DNR_DM_DIF_FLT_MISC 11628 #define V3_L1_SKIP_MAX_SAD 8049 #define HCODEC_VLC_COEFF_RD_REQ 7489 #define P_VDEC_ASSIST_MBOX0_CLR_REG 4284613060 #define IE_ME_MB_INFO 8002 #define AUDIN_DECODE_CHANNEL_STATUS_A_1 13333 #define AUDIN_DECODE_CHANNEL_STATUS_A_0 13332 #define AUDIN_DECODE_CHANNEL_STATUS_A_3 13335 #define AUDIN_DECODE_CHANNEL_STATUS_A_2 13334 #define AUDIN_DECODE_CHANNEL_STATUS_A_5 13337 #define AUDIN_DECODE_CHANNEL_STATUS_A_4 13336 #define P_VBO_ACT_VSIZE 4287648148 #define I2C_M_1_WDATA_REG0 30724 #define I2C_M_1_WDATA_REG1 30725 #define P_HEVC_VLD_MEM_VIFIFO_WP 4284674324 #define P_HCODEC_MC_OTHER_GCLK_CTRL 4284638520 #define VPU_VENCL_DITH_EN 10057 #define VPU_RDARB_REQEN_SLV_L1C2 10138 #define VPU_RDARB_REQEN_SLV_L1C1 10129 #define HCODEC_VLD_DC_PRED 7213 #define P_VDEC2_FST_BAK_MV_X 4284657744 #define P_VDEC2_FST_BAK_MV_Y 4284657748 #define VD2_IF0_URGENT_CTRL 6799 #define HCODEC_IMEM_DMA_ADR 4929 #define VD2_AFBC_PIXEL_HOR_SCOPE 12687 #define GE2D_SRC2_X_START_END 178 #define SRSHARP0_PK_DRTFB_BP_CORING 12818 #define HCODEC_ME_SAD_ENOUGH_23 8017 #define ENCP_VIDEO_EQPULS_BEGIN 7071 #define P_VIU2_SW_RESET 4287657988 #define P_VIU_OSD2_MATRIX_PRE_OFFSET0_1 4287654624 #define HEVC_STREAM_RD_PTR 12549 #define P_HEVC_VLD_MEM_VIFIFO_RP 4284674328 #define AUDIN_HDMIRX_AFIFO_STAT 13478 #define L_STV2_HS_ADDR 5163 #define P_IE_WEIGHT 4284644564 #define VBO_INSGN_CTRL 5370 #define HCODEC_ME_SAD_ENOUGH_01 8016 #define P_VKS_PRELPF_CCOEF0 4287677456 #define P_VKS_PRELPF_CCOEF1 4287677460 #define P_VIU_OSD1_CTRL_STAT 4287653952 #define P_TOP_LEFT_READY 4284642632 #define SRSHARP1_HLTI_OS_MARGIN 13369 #define WATCHDOG_TCNT 15414 #define UART2_CONTROL 34818 #define P_DI_EI_DRT_CORRPIXTH 4287651304 #define P_VIU_OSD2_HL1_V_START_END 4287654096 #define NR2_3DEN_MODE 5965 #define XVYCC_INV_LUT_V_DATA_PORT 12637 #define P_POWER_CTL_MC 4284621844 #define SRSHARP1_LTI_DIR_CORE_ALPHA 13354 #define VDEC2_DBLK_Y_HFILT 10588 #define P_IE_DATA_FEED_BUFF_INFO 4284640096 #define ENCI_DE_V_END_ODD 6939 #define SPI_RES_RID 15 #define REG_BASE_HIU 4284727296 #define VDEC2_PSCALE_CMD_BLK_Y 10525 #define HEVC_VLD_C3D 15421 #define VDEC2_PSCALE_CMD_BLK_X 10524 #define VDIN0_HIST_V_START_END 4658 #define HEVC_VLD_C38 15416 #define HEVC_VLD_C39 15417 #define DCU_RESET 16 #define P_VDEC2_VLD_DECODE_CONTROL 4284657760 #define VPP2_VE_ENABLE_CTRL 6561 #define P_GE2D_SRC2_DST_CANVAS 4287890144 #define DBLK_CLIP_CTRL0 2402 #define ISA_DEBUG_REG3 15363 #define DBLK_CLIP_CTRL1 2403 #define ISA_DEBUG_REG2 15362 #define DBLK_CLIP_CTRL2 2404 #define ISA_DEBUG_REG1 15361 #define DBLK_CLIP_CTRL3 2405 #define ISA_DEBUG_REG0 15360 #define P_UART2_REG5 4291960852 #define SRSHARP0_HLTI_OS_MARGIN 12857 #define HEVC_ANC2_CANVAS_ADDR 14738 #define DBLK_CLIP_CTRL8 2410 #define VDEC2_CCPU_INTR_MSK 8996 #define ASYNC_FIFO_FIFO_FULL 26 #define DBLK_CLIP_CTRL4 2406 #define DBLK_CLIP_CTRL5 2407 #define DBLK_CLIP_CTRL6 2408 #define DBLK_CLIP_CTRL7 2409 #define HCODEC_VLC_COEFF_BUF_STATUS 7488 #define DI_IF1_LUMA_FIFO_SIZE 6130 #define HEVC_PARSER_DEBUG_DAT 12607 #define P_NR_ALP0C_ERR2CURV_LIMIT 4287678560 #define HEVC_MDB_CTRL 13085 #define P_AUDIN_FIFO_INT 4291875144 #define VDEC2_ASSIST_MBOX0_MASK 8306 #define P_HEVC_MBA_INC 4284674072 #define P_ENCI_VIDEO_BRIGHT 4287654924 #define VDEC2_DCAC_CPU_ADDRESS 11796 #define P_VPP_MATRIX_CTRL 4287657340 #define NR2_POLAR3_CTRL 11676 #define DET3D_MOTN_CFG 5940 #define VDEC2_MDEC_EXTIF_STS0 10726 #define HEVC_VLD_MEM_VIFIFO_END_PTR 15426 #define P_XVYCC_POST_RGB_BRGHT 4287677912 #define VPP_BLEND_VD2_V_START_END 7455 #define P_WATCHDOG_CNTL 4291883216 #define P_CBREAK_TYPE 4284615904 #define P_VDEC2_DC_AC_SCALE_DIV 4284659740 #define P_MCDI_GMV_RT 4287675472 #define TCON_DOUBLE_CTL 5321 #define P_ENCP_VIDEO_SY2_VAL 4287655620 #define VLC_INT_CONTROL 7472 #define P_HEVC_MPRED_CURR_LCU 4284663908 #define D2D3_SCU18_STEP 11023 #define P_OSD_DB_FLT_RANDLUT 4287677712 #define P_VPU_PROT3_GEN_CNTL 4287667652 #define QDCT_I_PRED_REF_WR_DATA 7987 #define P_TCON_DOUBLE_CTL 4287648548 #define P_LCD_MCU_CTL 4287648628 #define P_VDEC2_ANC7_CANVAS_ADDR 4284655196 #define P_SHARP_SATPRT_DIVM 4287678932 #define P_VPP_POSTBLEND_VD1_H_START_END 4287657072 #define HEVC_MDEC_DOUBLEW_STATUS 14819 #define P_HEVC_DBLK_Y_HFILT_HIGH 4284671348 #define HCODEC_VLC_JPEG_COEFF_BUF_STAT 7513 #define P_DOS_VDEC_MCRCC_STALL2_CTRL 4284677384 #define P_DI_MEM_RPT_LOOP 4287651716 #define MIPI_DSI_DWC_GEN_PLD_DATA_OS 7196 #define P_VDEC2_PSCALE_MCMD_CTRL 4284654728 #define P_VDIN_SYNC_MASK 4287646160 #define ANC16_CANVAS_ADDR 2464 #define HEVC_PSCALE_DUMMY 14616 #define HCODEC_CDB_CTRL 4925 #define VDIN1_MATRIX_PROBE_COLOR 5160 #define P_VDEC2_DBLK_CBUS_HCMD2 4284655068 #define P_QDCT_DBG_IDX 4284644492 #define P_VDEC2_DBLK_CBUS_HCMD0 4284655076 #define P_VDEC2_DBLK_CBUS_HCMD1 4284655072 #define P_HCODEC_MPC_P 4284632088 #define DI_PRE_CTRL 5888 #define P_HCODEC_MPC_W 4284632100 #define P_HCODEC_VLC_INT_CONTROL_INTER 4284642492 #define P_HCODEC_MPC_D 4284632092 #define RD_RDY 3 #define P_HCODEC_MPC_E 4284632096 #define DI_MEM_RPT_LOOP 6113 #define HEVCD_IPP_DYNCLKGATE_STATUS 13345 #define P_RESET4_LEVEL 4291825808 #define VIU_OSD2_PROT_CTRL 6734 #define P_VPP_XVYCC_MISC1 4287657856 #define P_VPP_XVYCC_MISC0 4287657852 #define P_ANC20_CANVAS_ADDR 4284622480 #define D2D3_DRMIF_VPOS 11050 #define HCODEC_ANC8_CANVAS_ADDR 6552 #define DOS_VDEC2_MCRCC_STALL_CTRL 16193 #define P_DBLK_CLIP_CTRL5 4284622236 #define P_DBLK_CLIP_CTRL6 4284622240 #define P_DBLK_CLIP_CTRL3 4284622228 #define P_DBLK_CLIP_CTRL4 4284622232 #define P_AIU_DELTA_SIGMA_RCNTS 4291842424 #define P_DBLK_CLIP_CTRL7 4284622244 #define P_DBLK_CLIP_CTRL8 4284622248 #define VDEC2_DBLK_OST_YBASE 10621 #define P_DBLK_CLIP_CTRL1 4284622220 #define P_VDIN_MEAS_HS_RANGE 4287646068 #define P_DBLK_CLIP_CTRL2 4284622224 #define P_DBLK_CLIP_CTRL0 4284622216 #define P_VPU_RDARB_WEIGH1_SLV_L2C1 4287667840 #define VDEC_ASSIST_MBOX0_CLR_REG 113 #define ENCP_VIDEO_VSPULS_BLINE 7069 #define AIU_958_PAUSE_NUM 5156 #define P_HCODEC_ANC25_CANVAS_ADDR 4284638884 #define P_VDEC2_MC_MPORT_CTRL 4284654848 #define DIPD_RO_COMB_7 12253 #define P_VPP2_VSC_REGION1_PHASE_SLOPE 4287652904 #define VDEC2_VIFF_BIT_CNT 11290 #define DIPD_RO_COMB_6 12252 #define DIPD_RO_COMB_9 12255 #define DIPD_RO_COMB_8 12254 #define DIPD_RO_COMB_3 12249 #define DIPD_RO_COMB_2 12248 #define DIPD_RO_COMB_5 12251 #define DIPD_RO_COMB_4 12250 #define DIPD_RO_COMB_1 12247 #define DIPD_RO_COMB_0 12246 #define DNR_DM_LDIF_LUT3_5 11633 #define P_EE_ASSIST_MBOX0_MASK 4291854792 #define P_VDEC2_ASSIST_MBOX0_CLR_REG 4284645828 #define HEVC_SAO_PIC_SIZE 13829 #define VDIN_WR_H_START_END 4641 #define P_HEVC_MPRED_L1_REF02_POC 4284664008 #define AIU_DELTA_SIGMA_LCNTS 5213 #define P_HCODEC_MINDEX6_REG 4284632128 #define P_VDEC2_VLD_DBG_INDEX 4284657912 #define SRSHARP1_PK_CON_2DRTHPGAIN_TH_RATE 13321 #define P_HCODEC_V3_LEFT_MV 4284644796 #define P_HCODEC_VLD_DC_PRED 4284641460 #define mLVDS_reset_offset 29 #define P_PSCALE_MCMD_XSIZE 4284621964 #define OEV1_HE_ADDR 5296 #define P_VPP_PEAKING_GAIN_ADD2 4287657692 #define mLVDS_reset_start_bit12 19 #define P_VLC_ENC_COEFF_BITS 4284642676 #define P_VPP_PEAKING_GAIN_ADD1 4287657688 #define P_HEVC_LAST_MVY 4284674248 #define P_HEVC_LAST_MVX 4284674244 #define P_GAMMA_PROBE_COLOR_H 4287648300 #define P_NR2_POLAR3_PARA1 4287673964 #define P_NR2_POLAR3_PARA0 4287673960 #define P_GAMMA_PROBE_COLOR_L 4287648296 #define P_VIU_OSD2_MATRIX_OFFSET0_1 4287654616 #define P_HCODEC_LMEM_DMA_COUNT 4284632392 #define P_VLD_STATUS 4284625128 #define HCODEC_WRRSP_LMEM 4947 #define COI_S_SCOPE_REG 526 #define P_HCODEC_CBREAK_STAUTS 4284632296 #define P_VDEC2_CBREAK_TYPE 4284648672 #define P_L_STV2_HE_ADDR 4287647920 #define P_VLD_TIME_STAMP_CNTL 4284625188 #define P_XVYCC_LUT_G_ADDR_PORT 4287677824 #define P_VDIN_WIN_H_START_END 4287646132 #define VP9_SHADOW_DATA 12625 #define DI_ARB_CTRL 5903 #define P_VDEC2_VLD_MEM_SWAP_ADDR 4284658004 #define P_HEVC_CBREAK0_REG 4284665040 #define VDEC2_MC_CMD 10502 #define V3_TOP_LEFT_CTL 8045 #define P_PIC_HEAD_INFO 4284624908 #define P_HCODEC_ACC0REG1 4284632452 #define P_HCODEC_ACC0REG2 4284632516 #define HEVC_VOFF_STATUS 15420 #define VPU_DI_MEM_MMC_CTRL 9990 #define RESET7_MASK 1048 #define NR4_MCNR_LUMACUR_CAL_PRAM 11709 #define VPU_HDMI_DITH_10_15 10229 #define P_AC3_CTRL_REG4 4291854712 #define P_AC3_CTRL_REG3 4291854708 #define P_AC3_CTRL_REG2 4291854704 #define P_SHARP_DB_FLT_CTRL 4287678940 #define P_AC3_CTRL_REG1 4291854700 #define HEVC_MPRED_MV_WR_START_ADDR 12819 #define HCODEC_VLC_VB_MEM_CTL 7447 #define P_VPP2_CHROMA_ADDR_PORT 4287653312 #define SPDIF_SAMPLE_SEL 23 #define VPU_HDMI_DITH_10_26 10230 #define P_ME_F_SKIP_SAD 4284644684 #define P_AIU_958_RPT 4291842092 #define AFBC_SIZE_IN 6882 #define P_V3_TOP_LEFT_CTL 4284644788 #define AFBC_PIXEL_HOR_SCOPE 6895 #define P_VPP_EOTF_COEF00_01 4287678276 #define P_L_OEV3_VE_ADDR 4287647976 #define AHB_ARBDEC_REG 15427 #define P_VPP2_OSD_HSC_INI_PHASE 4287653648 #define AIU_I2S_SYNC 5137 #define VPU_HDMI_DITH_10_04 10228 #define P_V3_TOP_INTRA_INFO 4284644824 #define P_VPP2_HSC_REGION12_STARTP 4287652928 #define NR4_COEFBLT_LUT31 14094 #define NR4_COEFBLT_LUT32 14095 #define HEVCD_MPP_ANC2AXI_TBL_DATA 13412 #define NR4_COEFBLT_LUT30 14093 #define P_NEXT_INTRA_DMA_ADDRESS 4284626996 #define P_VPP_HLTI_DN_FLT 4287657792 #define HEVC_IQIT_SCALELUT_IDX_16_32 14087 #define DOLBY_CORE2A_DMA_STATUS 13370 #define P_MCDI_PD22_CHK_THD_RT 4287675736 #define P_L_STV1_VE_ADDR 4287647912 #define NR4_COEFBLT_LUT10 14087 #define NR4_COEFBLT_LUT11 14088 #define NR4_COEFBLT_LUT12 14089 #define HEVC_MPRED_MV_WLCUY 12830 #define VPU_HDMI_DITH_10_37 10231 #define HCODEC_CPU_TRACE 4992 #define NR4_COEFBLT_LUT20 14090 #define NR4_COEFBLT_LUT21 14091 #define NR4_COEFBLT_LUT22 14092 #define P_GE2D_SRC1_CLIPY_START_END 4287890080 #define VPU_VLOCK_RO_OUTPUT_10_11 12309 #define P_VDEC2_VLD_MEM_VBUF2_RD_PTR 4284658000 #define FST_FOR_MV_X 3088 #define FST_FOR_MV_Y 3089 #define VDIN1_OFFSET 128 #define P_ENCP_VFIFO2VD_LINE_TOP_END 4287655280 #define P_ENCL_VFIFO2VD_LINE_BOT_START 4287656532 #define P_HCODEC_VLD_MEM_VIFIFO_RP 4284641560 #define P_VPU_VLOCK_RO_OUTPUT_10_11 4287676500 #define HEVC_MPRED_MV_RD_START_ADDR 12820 #define P_HEVC_ANC7_CANVAS_ADDR 4284671580 #define P_HCODEC_MB_INFO 4284641456 #define L_GAMMA_PROBE_CTRL 5129 #define P_HEVC_MINDEX1_REG 4284664876 #define P_DI_CHAN2_CHROMA0_RPT_PAT 4287651524 #define P_MDEC_SW_RESET 4284622352 #define SPICC0_LD_CNTL0 19466 #define P_RDMA_AHB_END_ADDR_6 4287644724 #define P_RDMA_AHB_END_ADDR_7 4287644732 #define P_RDMA_AHB_END_ADDR_4 4287644708 #define SPICC0_LD_CNTL1 19467 #define P_RDMA_AHB_END_ADDR_5 4287644716 #define P_RDMA_AHB_END_ADDR_2 4287644692 #define P_RDMA_AHB_END_ADDR_3 4287644700 #define P_VP9_CONTROL 4284663040 #define P_RDMA_AHB_END_ADDR_1 4287644684 #define P_HEVC_ASSIST_DMA_INT_MSK2 4284662172 #define HDEC_MC_OMEM_AUTO 2352 #define P_VIU_OSD2_CTRL_STAT2 4287654196 #define HCODEC_MCPU_INTR_REQ 4869 #define P_HCODEC_SCD_BAK_MV_X 4284641368 #define P_HCODEC_SCD_BAK_MV_Y 4284641372 #define DVIN_ACTIVE_START_LINE 2275 #define DNR_RO_GBS_STAT_DIF 11547 #define VPP2_VSC_PHASE_CTRL 6413 #define SRSHARP0_VLTI_BST_GAIN 12859 #define P_CIPLUS_KEY0 4291847136 #define P_CIPLUS_KEY1 4291847140 #define P_CIPLUS_KEY2 4291847144 #define P_VPU_VPU_3D_SYNC1 4287667424 #define VPU_VENCL_DITH_LUT_10 10218 #define VPU_VENCL_DITH_LUT_11 10219 #define OSD1_AFBCD_ENABLE 12704 #define VPU_VENCL_DITH_LUT_12 10220 #define P_VPU_VPU_3D_SYNC2 4287667428 #define P_AIU_CRC_STATUS 4291842324 #define VDIN1_MEAS_VS_COUNT_LO 5212 #define HEVC_ASSIST_MBOX0_MASK 12402 #define P_SANA_STREAM_END_ADDR 4291870856 #define VDIN0_MATRIX_OFFSET0_1 4630 #define P_HCODEC_QDCT_JPEG_X_START_END 4284644504 #define P_AIU_958_SYNWORD3_MASK 4291842180 #define P_L_CPV1_HS_ADDR 4287647868 #define P_HEVC_CINT_VEC_BASE 4284664968 #define P_CIPLUS_KEY3 4291847148 #define P_HCODEC_VLD_MEM_VIFIFO_WP 4284641556 #define P_HEVCD_IPP_BITDEPTH_CONFIG 4284665904 #define P_DI_MTN_1_CTRL11 4287651512 #define P_DI_MTN_1_CTRL12 4287651516 #define P_HCODEC_MPEG1_2_REG 4284641284 #define P_DI_MTN_1_CTRL10 4287651508 #define P_ENCL_DACSEL_1 4287656744 #define OSD1_AFBCD_CHROMA_PTR 12709 #define VPP_CTI_CTRL2 7596 #define HENC_SCRATCH_N 6871 #define P_HEVC_DBLK_CR_FILT 4284671360 #define HENC_SCRATCH_L 6869 #define HENC_SCRATCH_M 6870 #define HENC_SCRATCH_J 6867 #define HENC_SCRATCH_K 6868 #define HENC_SCRATCH_H 6865 #define HENC_SCRATCH_I 6866 #define HENC_SCRATCH_F 6863 #define HENC_SCRATCH_G 6864 #define HENC_SCRATCH_D 6861 #define HENC_SCRATCH_E 6862 #define HENC_SCRATCH_B 6859 #define HENC_SCRATCH_C 6860 #define HENC_SCRATCH_A 6858 #define P_ENCL_DACSEL_0 4287656740 #define MCDI_HIGH_VERT_FRQ_RT_GAIN 12113 #define P_VENC_VDAC_DACSEL0 4287655392 #define P_VENC_VDAC_DACSEL1 4287655396 #define P_VENC_VDAC_DACSEL2 4287655400 #define P_VI_HIST_GCLK_CTRL 4287674536 #define HENC_SCRATCH_8 6856 #define HENC_SCRATCH_9 6857 #define HENC_SCRATCH_6 6854 #define VDIN1_MEAS_VS_COUNT_HI 5211 #define HENC_SCRATCH_7 6855 #define HENC_SCRATCH_4 6852 #define HENC_SCRATCH_5 6853 #define HENC_SCRATCH_2 6850 #define HENC_SCRATCH_3 6851 #define P_VENC_VDAC_DACSEL3 4287655404 #define HENC_SCRATCH_0 6848 #define P_VENC_VDAC_DACSEL4 4287655408 #define HENC_SCRATCH_1 6849 #define P_VENC_VDAC_DACSEL5 4287655412 #define ABUF_WR_BLK_SIZE_MSB 14 #define HCODEC_PMV4_Y 7207 #define HCODEC_PMV4_X 7206 #define P_VDEC2_DBLK_OST_YBASE 4284655092 #define P_HEVC_ANC20_CANVAS_ADDR 4284671632 #define D2D3_GLB_CTRL 11008 #define P_ENCI_DE_V_BEGIN_EVEN 4287655008 #define OSD_BLEND_CURRENT_XY 6830 #define VENC_ENCP_LINE 7019 #define P_VDEC2_CPSR 4284648580 #define VPP2_OSD_HSC_INI_PAT_CTRL 6598 #define P_SHARP_SR2_MISC 4287678848 #define P_HCODEC_HENC_LEFT_INFO_1 4284642536 #define P_HCODEC_HENC_LEFT_INFO_0 4284642528 #define HCODEC_DBLK_CB_FILT 6495 #define HEVC_DC_AC_SCALE_MUL 15878 #define P_VDEC2_PRE_START_CODE 4284657708 #define DBLK_QP 2390 #define SRSHARP0_SR3_DERING_LUMA2PKOS_0TO3 12910 #define HCODEC_GCLK_EN 6531 #define VDIN0_WR_CTRL2 4639 #define D2D3_DBLD_MG_PARAM 11026 #define ENCT_VIDEO_VSO_BEGIN 7287 #define ASYNC_FIFO_WRAP_EN 21 #define DI_CONTWR_Y 6049 #define DI_CONTWR_X 6048 #define MC_MPORT_DAT 2369 #define VDIN1_LCNT_SHADOW_STATUS 5127 #define P_DBLK_OST_YBASE 4284622324 #define P_HEVC_SAO_TILE_START 4284667932 #define P_PSCALE_DRAM_BUF_CTRL 4284621956 #define P_HEVC_DBLK_CTRL1 4284671484 #define P_HCODEC_QDCT_TOP_CONTROL 4284644476 #define MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS 7211 #define P_GE2D_MATRIX_COEF00_01 4287890200 #define HEVC_STREAM_LEVEL 12550 #define L_OEV2_HE_ADDR 5172 #define P_VLC_P_MB_HEADER_INFO 4284642556 #define P_VPU_VLOCK_LOOP0_ACCUM_LMT 4287676424 #define P_VD2_IF0_CHROMA0_RPT_PAT 4287654388 #define VLC_ENC_COEFF_BITS 7517 #define I2C_M_START 0 #define MCDI_REL_DET_LPF_MSK_22_30 12091 #define CINDEX3_REG 813 #define DOLBY_CORE2A_CLKGATE_CTRL 13362 #define P_L_VSYNC_HS_ADDR 4287648100 #define P_TS_FILE_CONFIG 4291847112 #define AUDIN_HDMI_MEAS_INTR_STAT 13475 #define AC3_CTRL_REG2 8284 #define ASYNC_FIFO_ENDIAN_LSB 21 #define AC3_CTRL_REG3 8285 #define AC3_CTRL_REG4 8286 #define DI_CHAN2_DUMMY_PIXEL 6066 #define P_SPI_FLASH_USER 4291903516 #define P_VLD_MEM_VIFIFO_CONTROL 4284625168 #define I2C_M_1_CONTROL_REG 30720 #define VDEC2_CSFTINT0 9022 #define VDEC2_CSFTINT1 9023 #define AC3_CTRL_REG1 8283 #define P_VDEC2_PSCALE_CANVAS_RD_ADDR 4284654768 #define P_ENCI_SYNC_MODE 4287654944 #define P_VBO_LANE_SKEW_H 4287648188 #define VPP_OSD_HSC_PHASE_STEP 7619 #define P_VBO_LANE_SKEW_L 4287648184 #define VENC_INTCTRL 7022 #define P_DI_IF2_RPT_LOOP 4287660120 #define XVYCC_INV_LUT_Y_ADDR_PORT 12632 #define VDIN_DOLBY_AXI_CTRL3 4732 #define VDIN_DOLBY_AXI_CTRL1 4730 #define VDIN_DOLBY_AXI_CTRL2 4731 #define VDIN_DOLBY_AXI_CTRL0 4729 #define AUDIN_FIFO0_RDPTR 13348 #define P_ENCI_CFILT7 4287655252 #define P_HENC_TOP_INFO_1 4284642532 #define NR2_MET_NM_TNR 5960 #define P_HENC_TOP_INFO_0 4284642524 #define P_VPP2_SCO_FIFO_CTRL 4287653068 #define P_VPU_VIU_VENC_MUX_CTRL 4287667304 #define HCODEC_VLC_DC_INFO 7495 #define SPICC0_STATREG 19461 #define MC_MBBOT_ST_ODD_ADDR 2373 #define SRSHARP1_PK_CIRFB_BP_CORING 13328 #define P_VD2_AFBC_MIF_HOR_SCOPE 4287678004 #define P_DOLBY_TV_ADAPTIVE_SCALE_LUTDATA 4287680396 #define ENCP_MACV_TIME_RST 7118 #define HCODEC_DBLK_MB_XY 6485 #define AIFIFO_TIME_STAMP_CNTL 5264 #define P_HEVC_MC_PIC_INFO 4284670984 #define VPU_PROT3_Y_START_END 10099 #define VDEC2_VLD_DECODE_CONTROL 11288 #define XVYCC_POST_RGB_BRGHT 12662 #define P_AUDIN_SPDIF_NPCM_PCPD 4291874836 #define HEVC_PARSER_MEM_WR_ADDR 12589 #define HCODEC_MC_HCMDBUF_H 6472 #define P_ME_PIC_INFO 4284644668 #define AIU_CRC_IREG 5191 #define ABUF_RD_BLK_SIZE_LSB 0 #define HCODEC_MC_HCMDBUF_L 6473 #define P_SHARP_SR3_DERING_CTRL 4287678892 #define AIU_MEM_AIFIFO_START_PTR 5252 #define DNR_RO_GBS_STAT_CNT 11548 #define ME_MV_WEIGHT_23 8023 #define HEVC_ANC29_CANVAS_ADDR 14765 #define P_HCODEC_ME_WEIGHT 4284644736 #define P_HCODEC_MFDIN_REG8_DMBL 4284629056 #define P_L_OEH_HS_ADDR 4287647840 #define P_HEVC_MPRED_TILE_START 4284663836 #define P_GE2D_SRC2_KEY 4287890240 #define VDEC2_PIC_HEAD_INFO 11267 #define P_DI_NRWR_X 4287651584 #define VPP2_SMOKE1_VAL 6442 #define P_DOS_CFG_CMPIF_BRIDGE 4284677392 #define HEVC_MC_HALF_PEL_ONE 14595 #define IQIDCT_CONTROL 3598 #define VPP_WRAP_OSD1_MATRIX_COEF13_14 15717 #define VDEC2_PSCALE_MCMD_CTRL 10530 #define P_DI_MC_22LVL1 4287650996 #define P_DI_MC_22LVL0 4287650992 #define P_DI_MC_22LVL2 4287651000 #define HCODEC_VLC_DC_RD_REQ 7493 #define NR4_ALP1Y_ERR2CURV_LIMIT0 11699 #define NR4_ALP1Y_ERR2CURV_LIMIT1 11700 #define HCODEC_DBLK_Y_HFILT_HIGH 6493 #define P_PRE_START_CODE 4284624940 #define P_MC_MB_INFO 4284621828 #define ENCT_VIDEO_MAX_LNCNT 7291 #define ENCI_VBI_CC525_LN 6947 #define MCDI_MC_REL_GAIN_OFFST_0 12150 #define MCDI_MC_REL_GAIN_OFFST_1 12151 #define P_STH2_HE_ADDR 4287648340 #define ENCT_VIDEO_BLANKPR_VAL 7294 #define PARSER_SUB_HOLE 14478 #define P_VPP2_INT_LINE_NUM 4287658112 #define P_AUDIN_FIFO0_CTRL1 4291874968 #define VPP_VSC_REGION1_PHASE_SLOPE 7434 #define P_AIU_MEM_AIFIFO_MEM_CTL 4291842620 #define P_PSCALE_RST 4284621888 #define P_HCODEC_PMV4_X 4284641432 #define P_HCODEC_PMV4_Y 4284641436 #define ME_MV_WEIGHT_01 8022 #define P_HCODEC_MBBOT_EVEN_ADDR 4284644572 #define MIPI_DSI_TOP_SUSPEND_PIX 7413 #define P_DI_NRWR_Y 4287651588 #define P_VDEC2_MC_OTHER_GCLK_CTRL 4284654904 #define HEVC_F_CODE_REG 15362 #define L_CPV2_VS_ADDR 5157 #define P_AFBC_PIXEL_HOR_SCOPE 4287654844 #define HEVC_DBLK_MB_XY 14677 #define P_ADAPTIVE_SCALE_ADDR 4287677780 #define VDEC2_PSCALE_BMEM_ADDR 10527 #define P_ENCT_VIDEO_BLANKPB_VAL 4287656436 #define P_VIU_OSD2_FIFO_CTRL_STAT 4287654188 #define DI_IF1_RANGE_MAP_CB 6141 #define CCPU_INTR_MSK 804 #define AIFIFO_TIME_STAMP_SYNC_0 5265 #define AIFIFO_TIME_STAMP_SYNC_1 5266 #define HEVC_POWER_CTL_VLD 15368 #define P_HEVC_ELEMENT_RESULT 4284662844 #define DI_IF1_RANGE_MAP_CR 6142 #define NR2_MATNR_MTN_GAIN 5997 #define REG_CM2_ENH_COEFF2_H10 338 #define P_VBO_PXL_CTRL 4287648180 #define REG_CM2_ENH_COEFF2_H11 346 #define REG_CM2_ENH_COEFF2_H12 354 #define REG_CM2_ENH_COEFF2_H13 362 #define P_HEVC_MC_HALF_PEL_TWO 4284670992 #define VDEC2_ANC30_CANVAS_ADDR 10670 #define MCDI_MC_LPF_MSK_0 12145 #define MCDI_MC_LPF_MSK_1 12146 #define MCDI_MC_LPF_MSK_2 12147 #define MCDI_MC_LPF_MSK_3 12148 #define MCDI_MC_LPF_MSK_4 12149 #define P_HCODEC_CINDEX3_REG 4284632244 #define REG_CM2_ENH_COEFF2_H04 290 #define REG_CM2_ENH_COEFF2_H05 298 #define REG_CM2_ENH_COEFF2_H06 306 #define REG_CM2_ENH_COEFF2_H07 314 #define REG_CM2_ENH_COEFF2_H00 258 #define P_ENCT_VFIFO2VD_LINE_TOP_START 4287656076 #define REG_CM2_ENH_COEFF2_H01 266 #define REG_CM2_ENH_COEFF2_H02 274 #define REG_CM2_ENH_COEFF2_H03 282 #define VPU_VLOCK_OROW_OCOL_MAX 12304 #define REG_CM2_ENH_COEFF2_H08 322 #define REG_CM2_ENH_COEFF2_H09 330 #define P_VIU_OSD1_BLK3_CFG_W1 4287654048 #define P_VIU_OSD1_BLK3_CFG_W2 4287654052 #define P_VDEC2_PSCALE_CMD_BLK_Y 4284654708 #define P_VIU_OSD1_BLK3_CFG_W3 4287654056 #define P_VDEC2_PSCALE_CMD_BLK_X 4284654704 #define P_VIU_OSD1_BLK3_CFG_W4 4287653976 #define P_VIU_OSD1_BLK3_CFG_W0 4287654044 #define P_AHB_BRIDGE_CNTL_WR 4291883520 #define P_VDEC2_QP_CTRL_REG 4284659716 #define ENCP_VIDEO_PB_SCL 7044 #define AUDIN_FIFO2_REQID 13391 #define DI_INP_RPT_LOOP 6100 #define P_HEVC_CABAC_TOP_INFO_3 4284663068 #define P_HEVC_CABAC_TOP_INFO_2 4284662900 #define P_HEVC_CABAC_TOP_INFO_5 4284663084 #define P_HEVC_CABAC_TOP_INFO_4 4284663076 #define ENCI_DBG_FLDLN_RST 6985 #define P_HEVC_PARSER_VERSION 4284662784 #define L_OEV3_HE_ADDR 5176 #define P_NR2_MATNR_XBETA_CFG 4287651176 #define L_CPV1_VE_ADDR 5154 #define HEVC_ASSIST_MBOX2_FIQ_SEL 12411 #define MBA_INC 3078 #define mLVDS2_data_latch_1_ini 15 #define MCDI_REL_DET_RPT_CHK_GAIN_QMV 12084 #define OSDSR_ABIC_VCOEF 12597 #define VDEC2_ASSIST_DMA_INT_MSK 8293 #define MCRCC_CTL1 2432 #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 15804 #define MCRCC_CTL3 2434 #define MCRCC_CTL2 2433 #define HEVC_MC_MBBOT_ST_EVEN_ADDR 14660 #define P_HCODEC_VLC_DBG_READ 4284642652 #define P_ENCL_VFIFO2VD_CTL 4287656512 #define VD1_IF0_CHROMA_PSEL 6753 #define P_VPP_HSHARP_LUMA_THRESH23 4287657288 #define P_PWM_B2 4291932184 #define P_VIU_OSD2_MATRIX_PROBE_POS 4287654640 #define P_HEVC_MPRED_L0_REF04_POC 4284663952 #define HCODEC_VLD_MEM_VIFIFO_CONTROL 7236 #define VPU_PROT3_DDR 10103 #define P_PWM_A2 4291932180 #define SRSHARP1_DNLP_08 13390 #define SRSHARP1_DNLP_09 13391 #define SRSHARP1_DNLP_06 13388 #define P_HEVC_PARSER_MEM_RD_ADDR 4284662960 #define SRSHARP1_DNLP_07 13389 #define P_VIU2_VD1_IF0_CHROMA1_RPT_PAT 4287658364 #define SRSHARP1_DNLP_04 13386 #define SRSHARP1_DNLP_05 13387 #define P_D2D3_RESEV_STATUS2 4287671548 #define P_D2D3_RESEV_STATUS1 4287671544 #define P_VIFF_BIT_CNT 4284625000 #define P_PWM_D2 4291928088 #define P_VPP_HSHARP_LUMA_THRESH01 4287657284 #define SRSHARP1_DNLP_13 13395 #define SRSHARP1_DNLP_14 13396 #define RDMA_STATUS 4373 #define VPP_MISC1 7542 #define SRSHARP1_DNLP_11 13393 #define SRSHARP1_DNLP_12 13394 #define HCODEC_MINDEX1_REG 4875 #define NR_ALP0C_ERR2CURV_TH_RATE 12823 #define SRSHARP1_DNLP_10 13392 #define MLVDS_RESET_PATTERN_EXT 5318 #define P_VLC_DELTA_QP 4284642548 #define HCODEC_DBLK_AVSFLAGS 6510 #define SRSHARP0_DB_FLT_CTRL 12919 #define P_PWM_C2 4291928084 #define P_VDIN_HIST_H_START_END 4287645892 #define SRSHARP1_DNLP_02 13384 #define SRSHARP1_DNLP_03 13385 #define SRSHARP1_DNLP_00 13382 #define SRSHARP1_DNLP_01 13383 #define HCODEC_DCAC_MB_COUNT 7702 #define HCODEC_ANC26_CANVAS_ADDR 6570 #define P_VD2_IF0_LUMA_FIFO_SIZE 4287654412 #define P_VDEC2_MC_PIC_W_H 4284654624 #define P_PWM_F2 4291923992 #define DC_AC_SCALE_DIV 3591 #define AUDIN_FIFO1_HOLD_LVL 28 #define CIPLUS_CONFIG 6397 #define HEVC_MPRED_L0_REF13_POC 12845 #define P_UART0_MISC 4291969040 #define WRRSP_PARSER 14482 #define P_PWM_E2 4291923988 #define VIU2_VD1_IF0_CANVAS1 7762 #define P_ENCI_RGB_SETTING 4287654988 #define VIU2_VD1_IF0_CANVAS0 7761 #define P_PK_DRTFB_LPF_MODE 4287678520 #define P_CPV1_VE_ADDR 4287648392 #define P_DNR_DM_GMS_THD 4287673816 #define REG_BASE_CBUS 4291821568 #define P_HCODEC_VLC_JPEG_COEFF_BUF_STAT 4284642660 #define DBLK_GCLK_OFF 2413 #define SAT_SAT_RANGE_REG02 17 #define XVYCC_LUT_B_ADDR_PORT 12642 #define SAT_SAT_RANGE_REG03 23 #define SAT_SAT_RANGE_REG00 5 #define SAT_SAT_RANGE_REG01 11 #define ENCI_DVI_VSO_BEGIN_ODD 7175 #define P_HCODEC_ACC1REG2 4284632520 #define P_HCODEC_ACC1REG1 4284632456 #define P_CPV2_VE_ADDR 4287648408 #define SAT_SAT_RANGE_REG06 41 #define SAT_SAT_RANGE_REG07 47 #define SAT_SAT_RANGE_REG04 29 #define SAT_SAT_RANGE_REG05 35 #define SRSHARP1_SHARP_SR2_CTRL 13399 #define DNR_DM_DIR_MISC 11620 #define P_SPICC1_STATREG 4291907604 #define VPU_PROT2_STAT_1 10090 #define VPU_PROT2_STAT_2 10091 #define VPU_PROT2_STAT_0 10089 #define P_AIU_958_POP 4291842152 #define SPI_HPM 19 #define P_VIUB_MISC_CTRL0 4287660056 #define HEVC_ASSIST_AXI_CTRL 12412 #define ENCI_VIDEO_HUE 6918 #define P_DOS_SCRATCH31 4284677308 #define P_DOS_SCRATCH30 4284677304 #define P_DOS_SCRATCH28 4284677296 #define P_DOS_SCRATCH29 4284677300 #define P_DOS_SCRATCH26 4284677288 #define P_DOS_SCRATCH27 4284677292 #define P_DOS_SCRATCH24 4284677280 #define P_DOS_SCRATCH25 4284677284 #define P_DOS_SCRATCH22 4284677272 #define P_DOS_SCRATCH23 4284677276 #define P_DOS_SCRATCH20 4284677264 #define P_DOS_SCRATCH21 4284677268 #define HCODEC_VLD_MEM_VIFIFO_BUF_CNTL 7240 #define P_MCDI_REL_DET_LPF_MSK_31_34 4287675632 #define P_VDEC2_CDB_DATA_REG 4284648688 #define P_WM_FREQ_DIST_RIGHT 4287678164 #define P_DI_CHAN2_GEN_REG 4287651796 #define INTRA_MODE 128 #define DNR_RO_DM_GMS_STAT_MS 11640 #define P_VIDEO_PTS 4291879372 #define P_SHARP_DB_FLT_PXI_THRD 4287678952 #define P_GE2D_SRC1_FMT_CTRL 4287890104 #define LVDS_blank_data_reserved 30 #define P_PK_CON_2DRTHPGAIN_TH_RATE 4287678500 #define P_VPP_PREBLEND_CURRENT_XY 4287657104 #define P_PARSER_VIDEO2_HOLE 4291879516 #define P_HEVC_SAO_Y_START_ADDR 4284667948 #define AUDIN_FIFO0_CHAN 11 #define ENCL_DBG_LN_INT 7340 #define P_ENCI_VFIFO2VD_LINE_TOP_START 4287656044 #define P_AUDIN_FIFO0_WRAP 4291875012 #define VD2_AFBC_HEAD_BADDR 12678 #define P_MBREAK_STAUTS 4284615784 #define P_VDEC2_PSCALE_MCMD_YSIZE 4284654736 #define VDEC2_PSCALE_CANVAS_WR_ADDR 10541 #define VPU_VLOCK_RO_OUTPUT_00_01 12308 #define P_VLC_VB_MEM_CTL 4284642396 #define DET3D_RO_DET_CB_HOR 5949 #define OSD1_AFBCD_PIXEL_VSCOPE 12714 #define SRSHARP0_SHARP_SR2_CTRL 12887 #define P_HCODEC_MC_MBBOT_ST_EVEN_ADDR 4284638480 #define MPSR 769 #define P_HCODEC_CDB_ADDR_REG 4284632300 #define HCODEC_IE_DATA_FEED_BUFF_INFO 6872 #define P_ENCP_DVI_VSO_BEGIN_ODD 4287656156 #define MALI_AFBCD_TOP_CTRL 6671 #define P_VAS_STREAM_ID 4291879364 #define AIU_MEM_AIFIFO_LEVEL 5259 #define MCDI_REL_BADW_THD_MIN_MAX 12068 #define P_PK_ALP2_ERR2CURV_LIMIT 4287678592 #define VBO_VBK_CTRL_1 5227 #define VBO_VBK_CTRL_0 5226 #define AIU_MEM_AIFIFO2_BYTES_AVAIL 5229 #define P_VPU_VLOCK_LOOP1_ACCUM_LMT 4287676540 #define P_DNR_DM_CTRL 4287673728 #define P_VENC_VDAC_DAC2_OFFSET 4287655892 #define P_OSD1_AFBCD_FRAME_PTR 4287678096 #define P_HCODEC_MINDEX5_REG 4284632124 #define P_ABUF_FIFO_CTL0 4291883492 #define VPU_HDMI_FMT_CTRL 10051 #define BIT_SWP 0 #define DI_IF2_GEN_REG 8208 #define P_HCODEC_QDCT_JPEG_Y_START_END 4284644508 #define SRSHARP0_NR_ALP0Y_ERR2CURV_TH_RATE 12821 #define ENCL_VIDEO_BLANKPB_VAL 7357 #define P_VDEC2_VLD_C3D 4284657908 #define P_VDEC2_VLD_C38 4284657888 #define P_VDEC2_VLD_C39 4284657892 #define DECOMB_HV_BLANK 11664 #define P_DI_MEM_LUMA_FIFO_SIZE 4287651732 #define AUDIN_SPDIF_END 13327 #define MC_MBBOT_WRRSP_CNT 2492 #define VPU_VLOCK_ADJ_EN_SYNC_CTRL 12317 #define P_VDEC2_MINDEX6_REG 4284648512 #define VPP_DAT_CONV_PARA0 7572 #define VPP_DAT_CONV_PARA1 7573 #define P_L_LCD_PWR_ADDR 4287647980 #define HEVC_SAO_CTRL10 13870 #define HEVC_SAO_CTRL11 13871 #define HEVC_CABAC_LEFT_INFO_2 12575 #define HEVC_CABAC_LEFT_INFO_4 12618 #define HEVC_CABAC_LEFT_INFO_3 12616 #define P_HEVC_MINDEX2_REG 4284664880 #define HEVC_CABAC_LEFT_INFO_5 12620 #define TCON_DE_SEL 5 #define SRSHARP1_PK_CON_2DRTBPGAIN_TH_RATE 13323 #define SRSHARP0_HCTI_BST_CORE 12848 #define PSCALE_DUMMY 2328 #define AIU_CODEC_ADC_LRCLK_CTRL 5161 #define HCODEC_LAST_SLICE_MV_ADDR 7216 #define VLC_TOTAL_BYTES 7450 #define P_HEVC_WRRSP_LMEM 4284665164 #define P_VDEC2_POWER_CTL_MC 4284654612 #define AIU_MEM_AIFIFO_CURR_PTR 5253 #define P_HENC_LEFT_INFO_0 4284642528 #define P_HENC_LEFT_INFO_1 4284642536 #define P_AUDIN_SPDIF_CHNL_STS_A 4291874824 #define P_AUDIN_SPDIF_CHNL_STS_B 4291874828 #define HCODEC_VLC_VB_BUFF 7451 #define P_VPP_OSD_SCO_H_START_END 4287657768 #define P_DOS_MEM_PD_VP9DEC 4284677348 #define P_AIU_AIFIFO_STATUS 4291842564 #define P_HCODEC_QDCT_MIX_I_PRED_STATUS 4284644604 #define P_VIU2_VD1_IF0_DUMMY_PIXEL 4287658376 #define P_HCODEC_QDCT_JPEG_DCT_COEFF45 4284644540 #define VPP2_HSC_REGION0_PHASE_SLOPE 6420 #define VPP_EOTF_LUT_ADDR_PORT 12758 #define P_ENCT_VIDEO_Y_OFFST 4287656336 #define HCODEC_VLC_PUSH_STREAM 7455 #define P_HEVC_MPRED_POC24_CTRL1 4284664124 #define ATOM_LOCK 12335 #define P_HEVC_MPRED_POC24_CTRL0 4284664120 #define VPU_PROT2_GEN_CNTL 10081 #define P_HEVC_FST_BAK_MV_Y 4284674132 #define P_VDEC2_ANC20_CANVAS_ADDR 4284655248 #define HCODEC_VLD_MEM_VBUF_RD_PTR 7251 #define P_HEVC_FST_BAK_MV_X 4284674128 #define P_VDEC2_VLD_DC_PRED_C 4284657852 #define P_HCODEC_QDCT_JPEG_DCT_COEFF67 4284644544 #define AUDIN_FIFO2_WRAP 13392 #define P_VLC_DC_BUF_STATUS 4284642576 #define P_GPIO_INTR_FILTER_SEL0 4291883148 #define VDEC2_ANC28_CANVAS_ADDR 10668 #define HCODEC_MCPU_INTR_MSK 4868 #define HCODEC_MMAX_REG 4883 #define MIPI_DSI_DWC_CMD_MODE_CFG_OS 7194 #define P_HCODEC_QDCT_JPEG_DCT_COEFF89 4284644548 #define P_HEVC_VLD_MEM_VIFIFO_CONTROL 4284674320 #define P_HEVC_ANC18_CANVAS_ADDR 4284671624 #define PARSER_ES_CONTROL 14455 #define P_HCODEC_DBLK_CBPC 4284638664 #define AUDIN_SOURCE_SEL 13329 #define SRSHARP1_SR3_DERING_LUMA2PKOS_0TO3 13422 #define VENC_VIDEO_TST_EN 7024 #define NR2_MATNR_CBETA_SCL 5980 #define P_ENCP_DE_V_END_EVEN 4287656180 #define P_HCODEC_DBLK_CBPY 4284638656 #define P_DOLBY_CORE2A_SWAP_CTRL4 4287680732 #define P_DOLBY_CORE2A_SWAP_CTRL5 4287680736 #define P_DOLBY_CORE2A_SWAP_CTRL2 4287680724 #define P_DOLBY_CORE2A_SWAP_CTRL3 4287680728 #define P_DOLBY_CORE2A_SWAP_CTRL0 4287680716 #define P_DOLBY_CORE2A_SWAP_CTRL1 4287680720 #define P_HEVC_VLD_MEM_VIFIFO_WRAP_COUNT 4284674372 #define LDIM_STTS_MATRIX_HL_COLOR 6860 #define P_LDIM_STTS_CTRL0 4287654660 #define HCODEC_NON_I_QUANT_MATRIX 7683 #define HCODEC_MC_MBBOT_ST_ODD_ADDR 6469 #define VDEC_ASSIST_MBOX0_FIQ_SEL 115 #define P_OSD1_AFBCD_HDR_PTR 4287678092 #define P_AIU_MEM_I2S_START_PTR 4291842432 #define HEVC_MPRED_L0_REF01_POC 12833 #define VPP_DOLBY_CTRL 7571 #define P_PSCALE_CTRL1 4284621988 #define P_PSCALE_CTRL2 4284622008 #define VIU2_OSD1_MATRIX_CLIP 7800 #define VPP_POST2_MATRIX_OFFSET2 14762 #define P_MCDI_RO_GMV_VLD_CNT 4287676036 #define VPP_VADJ2_MC_MD 7494 #define VDEC2_CCPU_INTR_REQ 8997 #define NR4_MCNR_SAD2ALP0_LUT0 11742 #define NR4_MCNR_SAD2ALP0_LUT2 11744 #define VPP2_VSC_REGION4_ENDP 6407 #define NR4_MCNR_SAD2ALP0_LUT1 11743 #define NR4_MCNR_SAD2ALP0_LUT3 11745 #define NR3_SUREMOT_YGAIN 12277 #define DNR_DM_LDIF_LUT0_2 11632 #define P_VENC_STATA 4287655348 #define VLC_HCMD_CONFIG 7508 #define VDEC2_MDEC_PICR_BUF_STATUS 10681 #define I2C_M_0_CONTROL_REG 31744 #define P_OEV2_VE_ADDR 4287648472 #define P_VDEC2_POWER_CTL_IQIDCT 4284659744 #define AIU_AIFIFO2_CTRL 5184 #define P_VDIN_BLKBAR_IND_LEFT_START_END 4287646100 #define VDEC2_LMEM_DMA_COUNT 9042 #define HEVC_MCPU_INTR_GRP 13059 #define P_ME_SUB_FIX_SAD 4284644720 #define ENCT_SYNC_TO_LINE_EN 7242 #define VLC_JPEG_COEFF_BUF_STAT 7513 #define P_HCODEC_QDCT_JPEG_DCT_COEFF01 4284644532 #define P_DOS_SCRATCH17 4284677252 #define P_DOS_SCRATCH18 4284677256 #define P_DOS_SCRATCH15 4284677244 #define P_DOS_SCRATCH16 4284677248 #define P_DOS_SCRATCH13 4284677236 #define P_AUDIN_FIFO0_PIO_RDH 4291875528 #define P_DOS_SCRATCH14 4284677240 #define P_DOS_SCRATCH11 4284677228 #define P_DOS_SCRATCH12 4284677232 #define P_AUDIN_FIFO0_PIO_RDL 4291875524 #define P_XVYCC_VD1_RGB_DLUT_8_11 4287677904 #define P_NR4_MCNR_ALP1_SGN_COR 4287683676 #define P_DOS_SCRATCH19 4284677260 #define HEVC_PSCALE_CMD_CTRL 14619 #define P_DOS_SCRATCH10 4284677224 #define VDIN1_BLKBAR_H_START_END 5217 #define P_ENCI_VFIFO2VD_PIXEL_START 4287656036 #define HEVCD_IPP_SWMPREDIF_PUINFO5 13336 #define HEVCD_IPP_SWMPREDIF_PUINFO4 13335 #define VENC_VDAC_DAC0_GAINCTRL 7152 #define HEVCD_IPP_SWMPREDIF_PUINFO3 13334 #define HEVCD_IPP_SWMPREDIF_PUINFO2 13333 #define HEVCD_IPP_SWMPREDIF_PUINFO1 13332 #define HEVCD_IPP_SWMPREDIF_PUINFO0 13331 #define HUE_CFG_PARA_REG 537 #define P_MCDI_FIELD_HVF_PRDX_CNT 4287675780 #define P_HCODEC_QDCT_JPEG_DCT_COEFF23 4284644536 #define VPP2_OSD_SC_DUMMY_DATA 6599 #define P_HCODEC_MDEC_PICW_BUF_STATUS 4284638952 #define P_SPICC0_CONREG 4291899400 #define MIPI_DSI_DWC_INT_ST0_OS 7215 #define P_VPP2_MATRIX_PRE_OFFSET2 4287653280 #define LAST_MVY 3122 #define LAST_MVX 3121 #define GAMMA_ADDR_PORT 5250 #define DNR_DB_HGAP 11533 #define P_VDEC2_ASSIST_MBOX0_FIQ_SEL 4284645836 #define DOS_HEVC_INT_EN 16182 #define VDIN0_MATRIX_CTRL 4624 #define HCODEC_QDCT_I_PRED_REF_WR_IDX 7986 #define MCDI_REL_BADW_THD_GAIN_OFFST 12067 #define P_HCODEC_QUANT_TABLE_DATA 4284644580 #define VDIN0_MATRIX_COEF02_10 4626 #define VPP_WRAP_OSD3_MATRIX_COEF15_25 15799 #define OSD_BLEND_DUMMY_DATA 6829 #define ASYNC_FIFO_FLUSH 23 #define VIU2_OSD2_TEST_RDDATA 7756 #define P_VPP2_PREBLEND_H_SIZE 4287652992 #define P_CINDEX6_REG 4284615872 #define P_EE_ASSIST_MBOX2_IRQ_REG 4291854816 #define CM_GLOBAL_GAIN_REG 519 #define HCODEC_ME_SUB_REF_MV_CTL 8026 #define P_VIU2_OSD1_FIFO_CTRL_STAT 4287658284 #define HEVC_IMEM_DMA_COUNT 13122 #define P_NR4_RO_NM_VAR_MIN_MAX 4287683724 #define P_DET3D_MAT_STA_RSFT 4287651052 #define P_VPP_VE_DITHER_LUT_12 4287677616 #define P_VPP_VE_DITHER_LUT_11 4287677612 #define P_VPP_VE_DITHER_LUT_10 4287677608 #define ENCI_SYNC_TO_LINE_EN 7234 #define P_DI_CONTWR_CTRL 4287651464 #define VPU_VLOCK_LOOP1_IMISSYNC_MAX 12293 #define P_VDEC2_PSCALE_STATUS 4284654712 #define HCODEC_VLC_MV_INDEX 7496 #define PIC_HEAD_INFO 3075 #define P_MDEC_PIC_DC_THRESH 4284622560 #define ENCT_VIDEO_YC_DLY 7279 #define P_DOLBY_CORE2A_REG_START 4287680512 #define VD2_AFBC_MIF_HOR_SCOPE 12685 #define P_VD2_IF0_CHROMA1_RPT_PAT 4287654396 #define MC_HALF_PEL_ONE 2307 #define P_HCODEC_MAC_CTRL1 4284632448 #define P_HCODEC_MAC_CTRL2 4284632512 #define P_ISA_TIMERE_HI 4291883404 #define VENC_VIDEO_TST_CR 7028 #define VPP_VCTI_PARA 7638 #define P_VIU2_VD1_IF0_URGENT_CTRL 4287658428 #define MC_STATUS0 2313 #define MC_STATUS1 2314 #define P_VPP_OSDSC_DITHER_CTRL 4287677632 #define VENC_VIDEO_TST_CB 7027 #define VDIN_HSC_INI_CTRL 4621 #define P_HEVC_VLD_DC_PRED_C 4284674236 #define VD2_IF0_LUMA0_RPT_PAT 6780 #define L_VCOM_VS_ADDR 5149 #define VDEC2_DCAC_DMA_ADDRESS 11795 #define P_L_CPV2_VE_ADDR 4287647896 #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 15740 #define P_HCODEC_MCPU_INTR_REQ 4284632084 #define P_HEVC_ANC8_CANVAS_ADDR 4284671584 #define P_HCODEC_MDB_CTRL 4284632180 #define P_VDIN_COM_GCLK_CTRL 4287645804 #define HEVC_PSCALE_DRAM_BUF_CTRL 14625 #define P_HEVC_MPRED_CUR_POC 4284664192 #define CPV1_VS_ADDR 5281 #define STV1_VE_ADDR 5290 #define HEVC_MPRED_PIC_SIZE_EXT 12864 #define VD1_IF0_URGENT_CTRL 6767 #define P_DNR_DM_VAR_EDGE_DIF_THD2 4287673772 #define P_VPP2_VSC_REGION0_PHASE_SLOPE 4287652900 #define VD2_AFBC_LBUF_DEPTH 12677 #define P_HCODEC_MSP 4284632064 #define P_MINDEX0_REG 4284615720 #define P_NR2_CONV_MODE 4287651324 #define GE2D_DST_BITMASK 210 #define P_NR4_ALP0C_ERR2CURV_LIMIT0 4287674028 #define P_NR4_ALP0C_ERR2CURV_LIMIT1 4287674032 #define HCODEC_PMV1_Y 7201 #define HCODEC_PMV1_X 7200 #define VDIN_COM_STATUS3 4723 #define VDIN_COM_STATUS2 4622 #define VDIN_COM_STATUS1 4614 #define VDIN_COM_STATUS0 4613 #define P_HCODEC_V5_SIMPLE_MB_DQUANT 4284644860 #define HCODEC_MFDIN_REG8_DMBL 4112 #define P_MPC_W 4284615716 #define P_MPC_P 4284615704 #define P_MPC_D 4284615708 #define P_MPC_E 4284615712 #define HCODEC_PSCALE_PICI_H 6419 #define VPU_VLOCK_CTRL 12288 #define L_POL_CNTL_ADDR 5127 #define HCODEC_PSCALE_PICI_W 6418 #define VDEC2_MINDEX2_REG 8972 #define P_DECODER_BUFFER_INFO 4284624956 #define P_IE_I4_PRED_MODE_HI 4284644628 #define HCODEC_PMV3_Y 7205 #define HCODEC_PMV3_X 7204 #define NR4_MCNR_SKIN_GAIN_PAR1 11732 #define OUTPUT_YUV 15 #define P_PFIFO_DATA 4291879328 #define P_DVIN_ACTIVE_START_LINE 4291830668 #define CPV2_VS_ADDR 5285 #define P_ENCL_VIDEO_HSO_BEGIN 4287656660 #define WM_SPACE_RESOLUTION 12721 #define CPC_W 809 #define P_HCODEC_PSCALE_CMD_CTRL 4284638316 #define CPC_P 806 #define HCODEC_ASSIST_AMR2_INT0 4149 #define P_L_VCOM_VS_ADDR 4287647860 #define CPC_E 808 #define HCODEC_ASSIST_AMR2_INT4 4153 #define HCODEC_ASSIST_AMR2_INT3 4152 #define AIU_MEM_AIFIFO_MEM_CTL 5263 #define HCODEC_ASSIST_AMR2_INT2 4151 #define HCODEC_ASSIST_AMR2_INT1 4150 #define P_AUDIO_PTS_WR_PTR 4291879384 #define CPC_D 807 #define SDRAM_CTL7 15453 #define SDRAM_CTL8 15454 #define ENCP_VIDEO_HAVON_BEGIN 7076 #define SDRAM_CTL5 15451 #define SDRAM_CTL6 15452 #define SDRAM_CTL4 15450 #define SDRAM_CTL2 15448 #define HCODEC_ASSIST_AMR2_INTD 4162 #define SDRAM_CTL0 15447 #define HCODEC_ASSIST_AMR2_INTC 4161 #define HCODEC_ASSIST_AMR2_INTB 4160 #define HCODEC_ASSIST_AMR2_INTA 4159 #define HCODEC_ASSIST_AMR2_INT8 4157 #define P_VD1_IF0_PROT_CNTL 4287654328 #define HCODEC_ASSIST_AMR2_INT7 4156 #define HCODEC_ANC7_CANVAS_ADDR 6551 #define HCODEC_VLD_MEM_VIFIFO_WP 7237 #define HCODEC_ASSIST_AMR2_INT6 4155 #define HCODEC_ASSIST_AMR2_INT5 4154 #define P_HCODEC_DBLK_BETAX_QP_SEL 4284638596 #define P_HEVC_PARSER_MANUAL_CMD 4284662956 #define HCODEC_ASSIST_AMR2_INT9 4158 #define P_VDEC2_CPU_TRACE 4284648960 #define HEVC_DBLK_Y_BHFILT_HIGH 14680 #define SRSHARP1_VCTI_BST_GAIN 13376 #define P_STREAM_DATA_IN_CONFIG 4291866644 #define HEVC_MBREAK1_REG 13077 #define P_DI_PRE_HOLD 4287651020 #define P_HCODEC_VLD_DECODE_CONTROL 4284641376 #define VIU_OSD1_EOTF_COEF02_10 6870 #define P_VDEC2_MC_MIX_RATIO0 4284654640 #define P_VDEC2_MC_MIX_RATIO1 4284654644 #define VLC_VB_INT_PTR 7448 #define ENCP_SYNC_TO_LINE_EN 7238 #define P_VDEC2_CINDEX7_REG 4284648644 #define GE2D_SRC2_DEF_COLOR 175 #define UART1_WFIFO 35840 #define HEVC_QP_VALUE_REG 15365 #define P_VDEC2_NON_I_QUANT_MATRIX 4284659724 #define HEVC_STREAM_SWAP_CTRL 12597 #define P_DOLBY_CORE2A_STATUS0 4287680748 #define P_VPU_VPU_PWM_V1 4287667396 #define P_VPU_VPU_PWM_V0 4287667392 #define VIU2_VD1_IF0_CHROMA_PSEL 7777 #define P_DOLBY_CORE2A_STATUS1 4287680752 #define P_DOLBY_CORE2A_STATUS2 4287680756 #define P_DOLBY_CORE2A_STATUS3 4287680760 #define RDMA_ACCESS_MAN 4371 #define P_VPU_VPU_PWM_V3 4287667404 #define P_VPU_VPU_PWM_V2 4287667400 #define P_LDIM_BL_ADDR_PORT 4287648056 #define P_ACC1REG1 4284616072 #define P_ACC1REG2 4284616136 #define P_VPP2_SMOKE2_VAL 4287653036 #define VDIN_BLKBAR_CTRL1 4703 #define VDIN_BLKBAR_CTRL0 4704 #define P_CSP 4284615808 #define P_HCODEC_PSCALE_DUMMY 4284638304 #define ENCL_VIDEO_VSO_ELINE 7354 #define P_AIU_I2S_CBUS_DDR_WDATA 4291842728 #define VDIN0_MATRIX_PRE_OFFSET2 4633 #define HCODEC_QDCT_JPEG_QUANT_ADDR 7976 #define P_PSCALE_BMEM_DAT 4284621952 #define L_LCD_PWM0_HI_ADDR 5181 #define P_EE_ASSIST_MBOX2_FIQ_SEL 4291854828 #define P_HEVC_PSCALE_BMEM_DAT 4284671104 #define VIU_OSD2_BLK3_CFG_W3 6730 #define VIU_OSD2_BLK3_CFG_W4 6759 #define VIU_OSD2_BLK3_CFG_W1 6728 #define VIU_OSD2_BLK3_CFG_W2 6729 #define VIU_OSD2_BLK3_CFG_W0 6727 #define ASYNC_FIFO_ENDIAN_MSB 22 #define P_VKS_CTRL 4287677440 #define P_NR4_MCNR_LUMA_STAT_LIMTX 4287674084 #define P_NR4_MCNR_LUMA_STAT_LIMTY 4287674088 #define NR2_EDGE2BETA_LUT0 5986 #define NR2_EDGE2BETA_LUT1 5987 #define NR2_EDGE2BETA_LUT2 5988 #define NR2_EDGE2BETA_LUT3 5989 #define HCODEC_VLD_MEM_VIFIFO_RP 7238 #define D2D3_DBR_OUTPIC_SIZE 11010 #define P_EE_ASSIST_MBOX3_IRQ_REG 4291854832 #define P_HCTI_BST_GAIN 4287678652 #define P_CDB_DATA_REG 4284615920 #define P_ENCL_VFIFO2VD_PIXEL_START 4287656516 #define VPP_FRONT_CTI_CTRL2 7613 #define P_VPU_VPU_PWM_H3 4287667420 #define P_VPU_VPU_PWM_H2 4287667416 #define P_VPU_VPU_PWM_H1 4287667412 #define P_VPU_VPU_PWM_H0 4287667408 #define HEVCD_MPP_L0_WEIGHT_FLAG_ADDR 13436 #define P_IE_I4_PRED_MODE_LO 4284644632 #define DBLK_OST_YBASE 2429 #define VENC_VDAC_DAC5_FILT_CTRL1 7255 #define VENC_VDAC_DAC5_FILT_CTRL0 7254 #define P_STREAM_EVENT_INFO 4291866624 #define VPU_VLOCK_STBDET_SGN_WIN1 12316 #define VPU_VLOCK_STBDET_SGN_WIN0 12315 #define P_QDCT_CONFIG 4284644356 #define VIU_OSD1_EOTF_LUT_ADDR_PORT 6874 #define RDMA_AHB_START_ADDR_MAN 4352 #define VDEC2_DECODER_BUFFER_INFO 11279 #define L_LCD_PWM1_HI_ADDR 5183 #define P_VLD_TIME_STAMP_LENGTH 4284625216 #define P_MMIN_REG 4284615752 #define P_ENCP_DBG_LN_RST 4287655492 #define NR4_MCNR_SKIN_GAIN_PAR0 11731 #define PARSER_VIDEO_END_PTR 14465 #define IE_MB_POSITION 8001 #define P_VDEC2_VLD_STATUS 4284657896 #define P_HCODEC_ASSIST_DMA_INT_MSK 4284629396 #define P_HEVC_MPRED_L1_REF13_POC 4284664052 #define P_DNR_DM_RNG_GAIN_OFST 4287673740 #define VDEC2_VLD_TIME_STAMP_SYNC_0 11338 #define VDEC2_VLD_TIME_STAMP_SYNC_1 11339 #define PARSER_SEARCH_MASK 14442 #define ENCI_DE_V_END_EVEN 6937 #define P_HEVC_PRE_START_CODE 4284674092 #define SRSHARP1_SR3_DRTLPF_ALPHA_OFST 13418 #define P_HEVC_DCAC_CPU_ADDRESS 4284676176 #define SPI_FLASH_USR_DOUT 12 #define P_VLD_STATUS_CTRL 4284624896 #define VDIN0_HIST_CHROMA_SUM 4662 #define P_LDIM_STTS_MATRIX_PRE_OFFSET2 4287654700 #define ABUF_RD_BLK_SIZE_MSB 14 #define P_AIU_958_DCU_FF_CTRL 4291842076 #define HEVC_MPRED_L1_REF06_POC 12854 #define P_EE_ASSIST_MBOX1_FIQ_SEL 4291854812 #define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 12888 #define SRSHARP0_SHARP_SR2_YBIC_HCOEF1 12889 #define ENCP_VBI_SETTING 7121 #define P_VLD_TIME_STAMP_SYNC_0 4284625192 #define P_VLD_TIME_STAMP_SYNC_1 4284625196 #define SRSHARP0_PK_CON_2DRTBPGAIN_LIMIT 12812 #define P_QDCT_I_PRED_REF_WR_IDX 4284644552 #define P_ENCI_DACSEL_1 4287655984 #define P_ENCI_DACSEL_0 4287655980 #define DOLBY_CORE3_CLKGATE_CTRL 14064 #define STV2_VE_ADDR 5294 #define MCDI_LMV_GAINTHD 12045 #define L_LCD_PWR_ADDR 5179 #define P_ENCL_VIDEO_YC_DLY 4287656636 #define HEVC_ANC30_CANVAS_ADDR 14766 #define P_DI_INP_CANVAS0 4287651644 #define P_HCODEC_DCAC_DMA_CTRL 4284643400 #define VIU2_OSD1_MATRIX_COEF02_10 7793 #define P_OSD_BLEND_GEN_CTRL1 4287654576 #define P_OSD_BLEND_GEN_CTRL0 4287654572 #define VDIN0_LDIM_STTS_HIST_SET_REGION 4696 #define MCDI_RO_RPT_MV 12205 #define VPP_PIC_IN_HEIGHT 7426 #define P_DECOMB_MODE 4287673912 #define P_L_VSYNC_VE_ADDR 4287648112 #define HEVC_CINDEX7_REG 13105 #define P_VIU_OSD1_MATRIX_COEF02_10 4287654472 #define D2D3_DGEN_WIN_VER 11012 #define HCODEC_QDCT_TOP_BASE_MEM 7968 #define P_RESET1_LEVEL 4291825796 #define P_DI_INP_LUMA_FIFO_SIZE 4287651680 #define HCODEC_ASSIST_MBX_SSEL 4165 #define P_VDEC2_ASSIST_MBOX1_FIQ_SEL 4284645852 #define HCODEC_MCW_DBLK_WRRSP_CNT 6587 #define HEVC_DBLK_CBPY_ADJ 14705 #define P_ME_SUB_REF_MV_CTL 4284644712 #define V3_L2_SKIP_WEIGHT 8050 #define ENCI_VBI_WSS_LN 6950 #define VDIN_BLKBAR_IND_RIGHT2_CNT 4714 #define P_HEVC_VLD_SHIFT_STATUS 4284674284 #define P_DNR_CTRL 4287673344 #define P_VDEC2_CSP 4284648576 #define VDEC_ASSIST_MBOX0_MASK 114 #define P_VIU_OSD2_HL2_H_START_END 4287654100 #define HCODEC_ASSIST_AMR2_INTF 4164 #define HCODEC_ASSIST_AMR2_INTE 4163 #define DCAC_CPU_ADDRESS 3604 #define HCODEC_CINDEX2_REG 4908 #define AIU_AIFIFO_CLB 5251 #define P_HCODEC_DBLK_OST_CBCRDIFF 4284638712 #define P_ENCI_VBI_SETTING 4287655040 #define SLICE_QP 3082 #define VDIN1_LFIFO_CTRL 5146 #define OSDSR_HV_SIZEIN 12592 #define P_HEVC_DBLK_QP 4284671320 #define HCODEC_PMV2_Y 7203 #define AO_CPU_IRQ_IN0_INTR_STAT_CLR 15377 #define DI_CHAN2_CHROMA0_RPT_PAT 6065 #define P_HCODEC_VLC_HUFFMAN_ADDR 4284642664 #define P_DNR_DM_EDGE_DIF_THD 4287673760 #define P_AFBC_OUT_YSCOPE 4287654820 #define P_VENC_VDAC_FIFO_CTRL 4287655920 #define HCODEC_PMV2_X 7202 #define HCODEC_ANC25_CANVAS_ADDR 6569 #define P_XVYCC_INV_LUT_V_ADDR_PORT 4287677808 #define P_HEVC_MPSR 4284664836 #define P_HCODEC_ASSIST_MBOX1_CLR_REG 4284629460 #define P_MCDI_MC_COL_CFD_12 4287675920 #define P_MCDI_MC_COL_CFD_13 4287675924 #define P_MCDI_MC_COL_CFD_10 4287675912 #define P_MCDI_MC_COL_CFD_11 4287675916 #define VDIN1_DOLBY_DSC_STATUS3 5149 #define VDIN1_DOLBY_DSC_STATUS1 5246 #define VDIN1_DOLBY_DSC_STATUS2 5247 #define VDIN1_DOLBY_DSC_STATUS0 5245 #define P_MCDI_MC_COL_CFD_18 4287675944 #define P_MCDI_MC_COL_CFD_19 4287675948 #define P_MCDI_MC_COL_CFD_16 4287675936 #define P_MCDI_MC_COL_CFD_17 4287675940 #define P_MCDI_MC_COL_CFD_14 4287675928 #define P_MCDI_MC_COL_CFD_15 4287675932 #define P_MCDI_MC_COL_CFD_23 4287675964 #define P_MCDI_MC_COL_CFD_24 4287675968 #define P_MCDI_MC_COL_CFD_21 4287675956 #define VDIN0_SCALE_COEF_IDX 4608 #define P_MCDI_MC_COL_CFD_22 4287675960 #define P_MCDI_MC_COL_CFD_20 4287675952 #define P_MPEG1_2_REG 4284624900 #define SHARP_3DLIMIT 12868 #define P_MCDI_MC_COL_CFD_25 4287675972 #define NR2_MET_NMFRM_TNR_CLEV 5963 #define P_HEVC_ANC26_CANVAS_ADDR 4284671656 #define GE2D_VSC_NRND_PHASE 194 #define P_HCODEC_MFDIN_REG3_CANV 4284629036 #define P_VDEC2_VLD_MEM_VIFIFO_END_PTR 4284657928 #define P_HEVC_MPRED_DBG2_DATA_1 4284664100 #define P_HEVC_MPRED_DBG2_DATA_0 4284664096 #define MCDI_MC_CRTL 12144 #define P_ENCI_VBI_CC625_LN 4287655056 #define VPP_HLTI_DN_FLT 7632 #define HCODEC_IE_WEIGHT 7989 #define VDEC2_DBLK_Y_BHFILT 10583 #define NR2_MET_NMFRM_TNR_YLEV 5961 #define P_VP9_TOP_Y_MODE_0 4284663048 #define HCODEC_ME_SUB_SNAP_GLITCH 8030 #define AUDIN_INT_CTRL 13393 #define P_VP9_TOP_Y_MODE_1 4284663052 #define VDEC2_DBLK_OST_CBCRDIFF 10622 #define P_MBBOT_EVEN_ADDR 4284644572 #define P_HCODEC_MFDIN_REG6_DCFG 4284629048 #define P_VPP_VSC_REGION0_PHASE_SLOPE 4287656996 #define P_PARSER_INSERT_DATA 4291879360 #define P_HEVC_MPRED_DBG2_DATA_3 4284664108 #define P_VIU_VD2_FMT_CTRL 4287654432 #define P_HEVC_MPRED_DBG2_DATA_2 4284664104 #define P_LDIM_STTS_MATRIX_PRE_OFFSET0_1 4287654696 #define P_ENCT_VIDEO_MAX_LNCNT 4287656428 #define P_HEVC_POWER_CTL_IQIDCT 4284676128 #define HEVC_LMEM_DMA_COUNT 13138 #define P_DITH_CNTL_ADDR 4287648288 #define P_VDEC2_VLD_MEM_VIFIFO_START_PTR 4284657920 #define P_AUDIN_FIFO2_CTRL1 4291875116 #define P_NR_ALP0Y_ERR2CURV_TH_RATE 4287678548 #define P_RESET0_MASK 4291825728 #define P_VPP_HSC_START_PHASE_STEP 4287657036 #define HCODEC_VLC_VB_WR_PTR 7442 #define AIU_CRC_BIT_CNT0 5199 #define AIU_CRC_BIT_CNT1 5198 #define P_VD2_AFBC_LBUF_DEPTH 4287677972 #define P_DOLBY_CORE3_SWAP_CTRL1 4287683528 #define P_DOLBY_CORE3_SWAP_CTRL0 4287683524 #define HCODEC_MB_MOTION_MODE 7175 #define P_NR4_MCNR_SAD2BET2_LUT3 4287674308 #define P_NR4_MCNR_SAD2BET2_LUT2 4287674304 #define P_VDEC2_MDEC_PICR_BUF_STATUS 4284655332 #define P_NR4_MCNR_SAD2BET2_LUT1 4287674300 #define P_NR4_MCNR_SAD2BET2_LUT0 4287674296 #define P_VDEC2_DBLK_STATUS 4284654924 #define VPU_VLOCK_RO_VS_I_DIST 12305 #define VDEC2_M4_TABLE_SELECT 11304 #define MIPI_DSI_DWC_DPI_COLOR_CODING_OS 7172 #define P_DOLBY_CORE3_SWAP_CTRL5 4287683544 #define P_HCODEC_PSCALE_RBUF_START_BLKX 4284638356 #define P_DOLBY_CORE3_SWAP_CTRL4 4287683540 #define P_DOLBY_CORE3_SWAP_CTRL3 4287683536 #define P_DOLBY_CORE3_SWAP_CTRL2 4287683532 #define PFIFO_WR_PTR 14438 #define P_DOLBY_CORE3_SWAP_CTRL9 4287683560 #define P_MCDI_REL_DET_LPF_MSK_04_12 4287675620 #define P_DOLBY_CORE3_SWAP_CTRL8 4287683556 #define P_HCODEC_PSCALE_RBUF_START_BLKY 4284638360 #define P_DOLBY_CORE3_SWAP_CTRL7 4287683552 #define P_DOLBY_CORE3_SWAP_CTRL6 4287683548 #define DNR_DM_SDIF_LUT6_8 11631 #define HEVC_VC1_BITPLANE_CTL 15896 #define P_DNR_DB_VBS_MISC 4287673428 #define P_ENCT_VIDEO_PB_SCL 4287656328 #define P_ENCT_VFIFO2VD_LINE_BOT_END 4287656088 #define P_VPP2_VADJ2_MC_MD 4287653144 #define D2D3_DBLD_CG_PARAM 11025 #define NR3_COOP_PARA 12273 #define HCODEC_ASSIST_DMA_INT 4196 #define HEVC_PSCALE_PICI_H 14611 #define AUDIN_FIFO0_HOLD0_SEL 22 #define VDIN0_INTF_WIDTHM1 4636 #define P_HCODEC_DCAC_MB_COUNT 4284643416 #define P_DOS_SECURE_REG_NULL 4284677640 #define DNR_DM_GMS_THD 11638 #define HEVC_PSCALE_RBUF_START_BLKX 14629 #define HEVC_PSCALE_RBUF_START_BLKY 14630 #define HEVC_MDEC_PIC_DC_THRESH 14776 #define P_DI_MTN_CTRL1 4287650864 #define HCODEC_MC_DP_MB_XY 6414 #define VIU_OSD2_MATRIX_PROBE_POS 6844 #define VIU_OSD2_MATRIX_OFFSET0_1 6838 #define HEVC_PSCALE_PICI_W 14610 #define P_VDEC2_MC_OMDN_MB_XY 4284654876 #define MINDEX6_REG 784 #define AIU_CRC_POLY_COEF1 5194 #define AIU_CRC_POLY_COEF0 5195 #define VENC_VDAC_DAC3_GAINCTRL 7158 #define VDIN0_BLKBAR_ROW_TH1_TH2 4708 #define HCODEC_VLD_DECODE_CONTROL 7192 #define VD1_IF0_GEN_REG 6736 #define P_HCODEC_QDCT_DCT_STATUS 4284644452 #define P_L_CPV1_VS_ADDR 4287647876 #define VPU_RDARB_WEIGH1_SLV_L2C1 10144 #define P_ENCI_SYNC_VOFFST 4287654980 #define AIU_MEM_IEC958_MASKS 5224 #define QDCT_MB_CONTROL 7957 #define P_AIU_MEM_IEC958_IRQ_LEVEL 4291842540 #define HEVC_SAO_C_LENGTH 13838 #define OSD_DB_FLT_CTRL1 12609 #define P_VENC_VIDEO_PROG_MODE 4287655328 #define P_HEVC_AVSP_IQ_WQ_PARAM_45 4284676204 #define P_VPU_VDIN1_MMC_CTRL 4287667256 #define P_L_CPV2_HE_ADDR 4287647888 #define HEVC_ANC3_CANVAS_ADDR 14739 #define P_HCODEC_DBLK_CBPC_ADJ 4284638668 #define HEVC_DBLK_CTRL1 14719 #define P_VDEC2_CSFTINT1 4284648700 #define P_VDEC2_CSFTINT0 4284648696 #define P_VENC_VDAC_DAC5_OFFSET 4287655916 #define IQ_OMEM_PT1 32 #define IQ_OMEM_PT0 16 #define P_HCODEC_PSCALE_PICO_W 4284638288 #define DI_CONTWR_CTRL 6050 #define OSD1_BLEND_SRC_CTRL 7677 #define HEVC_WRRSP_VLD 14810 #define P_HEVCD_IPP_DYNCLKGATE_CONFIG 4284665984 #define P_NR4_MCNR_RO_V_SUM 4287674316 #define PCMOUT_CTRL1 13425 #define PCMOUT_CTRL0 13424 #define SRSHARP1_SHARP_3DLIMIT 13380 #define P_VPP_VDO_MEAS_VS_COUNT_HI 4287657636 #define P_HCODEC_PSCALE_PICO_H 4284638292 #define P_HCODEC_MFDIN_REGA_CAV1 4284629064 #define P_PARSER_AUDIO_HOLE 4291879460 #define OSD_DB_FLT_PXI_THRD 12613 #define MIPI_DSI_DWC_PHY_TST_CTRL0_OS 7213 #define P_HCODEC_ASSIST_MMC_CTRL1 4284629000 #define GE2D_ALU_OP_CTRL 204 #define P_HCODEC_ASSIST_MMC_CTRL2 4284629004 #define MCDI_CHAR_DET_CNT_THD 12120 #define P_HCODEC_ASSIST_MMC_CTRL0 4284628996 #define P_HCODEC_ASSIST_MMC_CTRL3 4284629008 #define PCMOUT_CTRL3 13427 #define ENCT_VFIFO2VD_CTL2 7207 #define PCMOUT_CTRL2 13426 #define PCMOUT_CTRL4 13428 #define ASSIST_SPARE8_REG2 8281 #define ASSIST_SPARE8_REG3 8282 #define ASSIST_SPARE8_REG1 8280 #define P_ENCP_DVI_VSO_BLINE_EVN 4287656136 #define STV2_HS_ADDR 5291 #define VIU2_OSD2_HL2_V_START_END 7734 #define AUDOUT_FIFO_PIO_WRL 13498 #define QDCT_Q_STATUS 7962 #define P_GE2D_SC_MISC_CTRL 4287890176 #define VI_HIST_V_START_END 11778 #define VDEC2_MC_MIX_RATIO0 10508 #define VDEC2_MC_MIX_RATIO1 10509 #define AUDOUT_FIFO_PIO_WRH 13499 #define ENCT_DBG_PX_INT 7275 #define NR2_SW_EN 5967 #define P_L_CPV2_HS_ADDR 4287647884 #define P_MCDI_MCVECWR_X 4287675976 #define P_MCDI_MCVECWR_Y 4287675980 #define P_HCODEC_PSCALE_BMEM_ADDR 4284638332 #define P_DNR_STAT_X_START_END 4287673376 #define P_HEVC_IQIT_SCALELUT_RD_ADDR 4284668940 #define NR3_CNOOP_GAIN 12274 #define DI_INP_GEN_REG3 8360 #define DI_INP_GEN_REG2 6033 #define P_HCODEC_VLC_PUSH_ELEMENT 4284642432 #define P_ABUF_RD_CTL3 4291883484 #define P_ABUF_RD_CTL2 4291883480 #define P_ABUF_RD_CTL1 4291883476 #define P_ABUF_RD_CTL0 4291883472 #define VPU_VDIN0_MMC_CTRL 9997 #define DBLK_RST 2384 #define VIU_VD2_FMT_CTRL 6792 #define L_STV2_VE_ADDR 5166 #define L_STV2_VS_ADDR 5165 #define P_OSD_DB_FLT_SEED_U 4287677724 #define VDIN1_HSC_PHASE_STEP 5132 #define OSDSR_YBIC_HCOEF 12595 #define ME_SUB_FIX_MIN_SAD 8029 #define P_MC_CTRL_GCLK_CTRL 4284622132 #define P_HEVCD_IPP_TOP_LCUCONFIG 4284665880 #define P_OSD_DB_FLT_SEED_V 4287677728 #define P_OSD_DB_FLT_SEED_Y 4287677720 #define VDEC2_DBLK_AVSFLAGS 10606 #define HEVC_IQIDCT_DEBUG_IDCT 15889 #define HEVC_MPRED_IF_WAIT_CNT 12599 #define VPP_POST2_MATRIX_OFFSET0_1 14761 #define DBLK_CB_BFILT 2394 #define VIU2_VD1_IF0_URGENT_CTRL 7791 #define P_MCDI_HIGH_VERT_FRQ_DIF_DIF_THD 4287675712 #define P_VPP_SYNC_SEL0 4287657560 #define OEV3_SEL 2 #define P_I2C_M_0_WDATA_REG1 4291948564 #define P_I2C_M_0_WDATA_REG0 4291948560 #define P_VPP_BLUE_STRETCH_1 4287657584 #define HCODEC_REC_CANVAS_ADDR 6578 #define P_VPP_BLUE_STRETCH_2 4287657588 #define NR3_SUREMOT_CGAIN 12278 #define VDEC2_VLD_STATUS 11322 #define VDEC2_PMV1_Y 11297 #define VDEC2_PMV1_X 11296 #define VPP_OSD_VSC_INI_PHASE 7617 #define P_VPP_BLUE_STRETCH_3 4287657592 #define MCDI_MOTION_PARADOX_RT 12115 #define P_VDIN_VSC_PHASE_STEP 4287645836 #define P_HEVCD_MPP_DECOMP_PERFMON_CTL 4284666644 #define VDEC2_MBREAK_STAUTS 8986 #define P_PARSER_SUB_HOLE 4291879480 #define P_AIU_MEM_AIFIFO2_BYTES_AVAIL 4291842484 #define SRSHARP0_PK_CIRFB_BP_CORING 12816 #define MSR_CLK_REG3 24580 #define MSR_CLK_REG2 24579 #define MSR_CLK_REG1 24578 #define MSR_CLK_REG0 24577 #define P_HCODEC_QDCT_CONFIG 4284644356 #define MSR_CLK_REG5 24582 #define MSR_CLK_REG4 24581 #define P_DET3D_RO_MAT_HEDG_LR 4287651364 #define P_ANC24_CANVAS_ADDR 4284622496 #define P_ANC21_CANVAS_ADDR 4284622484 #define VDIN0_HIST_H_START_END 4657 #define AUDOUT_BUF0_WPTR 13444 #define P_VPP_FRONT_CTI_CTRL2 4287657716 #define VDEC2_REC_CANVAS_ADDR 10674 #define VP9_TOP_Y_MODE_0 12610 #define VP9_TOP_Y_MODE_1 12611 #define TCON_VSYNC_SEL_DVI 11 #define HCODEC_ANC9_CANVAS_ADDR 6553 #define P_OEV3_VE_ADDR 4287648488 #define P_QDCT_TOP_BASE_MEM 4284644480 #define P_AIU_958_SYNWORD2_MASK 4291842176 #define VPU_VLOCK_OUTPUT1_PLL_LMT 12300 #define PARSER_INT_ENABLE 14443 #define P_HEVC_MDEC_EXTIF_STS0 4284671896 #define P_LVDS_PHY_CLK_CNTL 4287648700 #define ISA_CNTL_REG0 15369 #define P_HCODEC_ANC29_CANVAS_ADDR 4284638900 #define CMIN_REG 818 #define P_VDEC2_PSCALE_BMEM_DAT 4284654720 #define P_HCODEC_ANC24_CANVAS_ADDR 4284638880 #define P_L_OEV1_HS_ADDR 4287647932 #define L_CPV1_HS_ADDR 5151 #define UART2_RFIFO 34817 #define P_DNR_DBLK_BLANK_NUM 4287673352 #define TS_FILE_CONFIG 6386 #define P_AIU_MEM_AIFIFO2_CURR_PTR 4291842476 #define VPP_VADJ2_BLACK_VAL 7576 #define VDEC2_MINDEX1_REG 8971 #define HCODEC_VLC_P_MB_HEADER_INFO 7487 #define P_VDIN_MEAS_HS_COUNT 4287646072 #define P_HCODEC_WRRSP_IMEM 4284632332 #define HCODEC_PSCALE_CANVAS_WR_ADDR 6445 #define P_HCODEC_MINDEX7_REG 4284632132 #define VPP_VSC_INI_PHASE 7438 #define P_VDIN_DOLBY_AXI_CTRL2 4287646188 #define P_VDIN_DOLBY_AXI_CTRL3 4287646192 #define P_VDIN_DOLBY_AXI_CTRL0 4287646180 #define P_VDIN_DOLBY_AXI_CTRL1 4287646184 #define P_HEVC_MPRED_COLREF_EN_L1 4284663868 #define P_HEVC_MPRED_COLREF_EN_L0 4284663864 #define P_XVYCC_INV_LUT_Y_ADDR_PORT 4287677792 #define HCODEC_ANC24_CANVAS_ADDR 6568 #define P_AUDOUT_CTRL1 4291875332 #define VDEC2_RESYNC_MARKER_LENGTH 11278 #define HEVC_ASSIST_AMR1_INTA 12335 #define HEVC_ASSIST_AMR1_INTC 12337 #define HEVC_ASSIST_AMR1_INTB 12336 #define M4_CONTROL_REG 3113 #define HEVC_ASSIST_AMR1_INTE 12339 #define P_VPP_VDO_MEAS_VS_COUNT_LO 4287657640 #define HEVC_ASSIST_AMR1_INTD 12338 #define P_HCODEC_ME_SUB_REF_MV_CTL 4284644712 #define HEVC_ASSIST_AMR1_INTF 12340 #define HCODEC_SAD_CONTROL 8003 #define P_ENCP_VFIFO2VD_PIXEL_START 4287655268 #define P_VDIN_LCNT_SHADOW_STATUS 4287645724 #define P_LDIM_STTS_WIDTHM1_HEIGHTM1 4287654664 #define P_DET3D_RO_MAT_HEDG_TB 4287651368 #define ENCP_VFIFO2VD_CTL2 7248 #define HEVC_ASSIST_AMR1_INT9 12334 #define HEVC_ASSIST_AMR1_INT8 12333 #define HEVC_ASSIST_AMR1_INT1 12326 #define HEVC_ASSIST_AMR1_INT0 12325 #define HEVC_ASSIST_AMR1_INT3 12328 #define HEVC_ASSIST_AMR1_INT2 12327 #define HEVC_ASSIST_AMR1_INT5 12330 #define HEVC_ASSIST_AMR1_INT4 12329 #define HEVC_ASSIST_AMR1_INT7 12332 #define HEVC_ASSIST_AMR1_INT6 12331 #define NR_DB_FLT_SEED_U 14141 #define NR_DB_FLT_SEED_V 14142 #define NR_DB_FLT_SEED_Y 14140 #define P_VDEC2_ANC9_CANVAS_ADDR 4284655204 #define mLVDS2_PN_SWAP 1 #define P_VDEC2_DBKW_CANVAS_ADDR 4284655300 #define HCODEC_MC_CTRL_GCLK_CTRL 6477 #define AIU_958_MISC 5124 #define HEVC_PRE_START_CODE 15371 #define HEVC_VLD_MEM_SWAP_CTL 15446 #define L_CPV1_HE_ADDR 5152 #define D2D3_DWMIF_HPOS 11045 #define ENCT_VIDEO_VAVON_ELINE 7283 #define HCODEC_MMIN_REG 4882 #define P_VDEC2_PSCALE_FILT0_COEF1 4284654696 #define AIU_MEM_I2S_BUF_CNTL 5238 #define P_VDEC2_PSCALE_FILT0_COEF0 4284654692 #define DI_MTN_1_CTRL11 6062 #define DI_MTN_1_CTRL10 6061 #define DI_MTN_1_CTRL12 6063 #define DNR_DM_DIF2NORM_LUT3_5 11636 #define DNR_DB_CEDGE_THD 11532 #define P_SMARTCARD_STATUS 4291973132 #define NR4_DRT_YSAD_GAIN 11685 #define P_HCODEC_QDCT_MB_WR_PTR 4284644424 #define P_HCODEC_DBLK_CBPY_ADJ 4284638660 #define HEVC_CM_HEADER_OFFSET 13867 #define VDEC2_ASSIST_TIMER0_LO 8288 #define VIU_OSD2_MATRIX_COEF02_10 6834 #define VPU_VLOCK_LOOP1_IMISSYNC_MIN 12294 #define ENCL_VFIFO2VD_CTL2 7319 #define P_VDEC2_MPEG1_2_REG 4284657668 #define NR4_MCNR_ALP1_GLB_CTRL 11735 #define P_HEVC_DBLK_CR_BFILT 4284671340 #define VDEC2_MSFTINT0 8990 #define VDEC2_MSFTINT1 8991 #define ROI_Y_SCOPE_REG 522 #define VPU_PROT1_X_START_END 10066 #define P_DVIN_DISPLAY_SIZE 4291830672 #define CVBS_IRQ0_CNTL 15396 #define P_DET3D_MAT_SYMTC_TH 4287651056 #define MCDI_RO_FLD_PD_22_FOR_CNT 12201 #define VPU_HDMI_DITH_CNTL 10236 #define VPP2_VE_DEMO_CENTER_BAR 6563 #define P_DNR_DM_AVG_THD 4287673764 #define ENCP_DACSEL_0 7181 #define ENCP_DACSEL_1 7182 #define VDEC2_ASSIST_TIMER0_HI 8289 #define P_HEVCD_IPP_DBG_SEL 4284666048 #define P_AUDIN_HDMI_MEAS_INTR_STAT 4291875468 #define SCD_FOR_MV_Y 3091 #define SCD_FOR_MV_X 3090 #define HCODEC_CINDEX1_REG 4907 #define VPU_VLOCK_RO_LINE_PIX_ADJ 12307 #define XVYCC_POST_RGB_DLUT_0_3 12663 #define P_VIU_SECURE_REG 4287653904 #define P_ENCP_VBI_CTRL 4287655744 #define VDEC2_VC1_CONTROL_REG 11294 #define P_ENCP_VIDEO_MODE 4287655476 #define VDIN0_BLKBAR_IND_RIGHT_START_END 4710 #define P_VCTI_CON_2_GAIN_1 4287678732 #define P_VCTI_CON_2_GAIN_0 4287678728 #define HEVC_SHIFT_COMMAND 12558 #define P_NR4_RO_NM_VAR_SCNT 4287683720 #define VLC_HCMD_CUR_INFO 7460 #define P_LMEM_DMA_CTRL 4284616000 #define P_VIU_OSD2_TCOLOR_AG0 4287654108 #define P_AHB_ARBDEC_REG 4291883276 #define P_VIU_OSD2_TCOLOR_AG3 4287654120 #define P_VIU_OSD2_TCOLOR_AG2 4287654116 #define P_VIU_OSD2_TCOLOR_AG1 4287654112 #define IQIDCT_DEBUG_INFO_0 3599 #define P_MC_MBBOT_ST_ODD_ADDR 4284622100 #define HEVC_MINDEX0_REG 13066 #define P_ENCI_VIDEO_SAT 4287654932 #define ASYNC_FIFO_FILL_EN 20 #define HEVC_PARSER_CMD_STATUS 12565 #define mLVDS2_data_latch_1_toggle 16 #define P_HEVC_MINDEX0_REG 4284664872 #define VPP_WRAP_OSD2_MATRIX_COEF00_01 15728 #define MCDI_REL_DET_RPT_CHK_THD_1 12086 #define MCDI_REL_DET_RPT_CHK_THD_0 12085 #define P_ENCI_VIDEO_SCH 4287654940 #define VDEC2_PMV2_Y 11299 #define P_AIU_CRC_BIT_CNT1 4291842360 #define P_AIU_MEM_AIFIFO_BYTES_AVAIL 4291842588 #define P_MCDI_RO_FLD_PD_22_PRE_CNT1 4287676200 #define P_MCDI_RO_FLD_PD_22_PRE_CNT2 4287676212 #define P_AIU_CRC_BIT_CNT0 4291842364 #define P_VIU2_VD1_IF0_PROT_CNTL 4287658424 #define VDEC2_PMV2_X 11298 #define P_PSCALE_CMD_CTRL 4284621932 #define P_NR_DB_FLT_SEED_Y 4287683824 #define P_NR_DB_FLT_SEED_U 4287683828 #define P_NR_DB_FLT_SEED_V 4287683832 #define VIU2_VD1_IF0_CHROMA_Y1 7770 #define VIU2_VD1_IF0_CHROMA_Y0 7766 #define P_ENCP_VBI_BEGIN 4287655752 #define P_NR2_MATNR_MTN_CRTL 4287651240 #define HCODEC_MCPU_INTR_GRP 4867 #define P_VDEC2_DBLK_MB_WID_HEIGHT 4284654920 #define P_VDEC2_VLD_TIME_STAMP_0 4284657968 #define P_VDEC2_ANC6_CANVAS_ADDR 4284655192 #define VIU2_VD1_IF0_CHROMA_X0 7765 #define VIU2_VD1_IF0_CHROMA_X1 7769 #define P_VLD_C3D 4284625140 #define P_AIU_MEM_AIFIFO2_MEM_CTL 4291842720 #define VDEC2_MC_OMDN_MB_XY 10567 #define P_VLD_C39 4284625124 #define SRSHARP0_VCTI_CON_2_GAIN_1 12867 #define P_VLD_C38 4284625120 #define SRSHARP0_VCTI_CON_2_GAIN_0 12866 #define HEVCD_IPP_TOP_TILECONFIG3 13317 #define HEVCD_IPP_TOP_TILECONFIG1 13315 #define P_VDIN_GO_LINE_CTRL 4287645884 #define VDIN1_ACTIVE_MAX_PIX_CNT_STATUS 5123 #define HEVCD_IPP_TOP_TILECONFIG2 13316 #define P_DI_INP_RANGE_MAP_Y 4287651560 #define PARSER_VIDEO_START_PTR 14464 #define P_VPP2_OSD_HSC_INI_PAT_CTRL 4287653656 #define SLICE_VER_POS_PIC_TYPE 3076 #define P_VPU_OSD2_MMC_CTRL 4287667208 #define P_HEVC_VLD_DBG_INDEX 4284674296 #define P_XVYCC_POST_RGB_CTRST 4287677908 #define QP_CTRL_REG 3585 #define P_VDEC2_VLD_TIME_STAMP_3 4284657980 #define P_VDEC2_VLD_TIME_STAMP_1 4284657972 #define P_VDEC2_VLD_TIME_STAMP_2 4284657976 #define P_VPU_VLOCK_RO_OUTPUT_00_01 4287676496 #define P_L_OEV1_HE_ADDR 4287647936 #define ENCI_TST_CLRBAR_STRT 7189 #define P_VPP2_POSTBLEND_CURRENT_XY 4287653012 #define L_GAMMA_DATA_PORT 5121 #define ENCI_DVI_VSO_BLINE_EVN 7170 #define P_VPU_WRARB_WEIGH0_SLV_L1C1 4287667800 #define HEVC_DBLK_Y_BVFILT 14681 #define P_VPU_WRARB_WEIGH0_SLV_L1C2 4287667904 #define P_VIU_OSD2_MATRIX_PRE_OFFSET2 4287654628 #define HCTI_OS_MARGIN 12851 #define P_HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR 4284666364 #define VPP_POST2_MATRIX_COEF02_10 14753 #define ADAPTIVE_SCALE_ADDR 12629 #define HCODEC_PSCALE_CMD_BLK_X 6428 #define HCODEC_PSCALE_CMD_BLK_Y 6429 #define ENCL_VIDEO_HAVON_END 7345 #define P_AUDOUT_BUF0_WPTR 4291875344 #define P_VPP_OSD_VSC_CTRL0 4287657736 #define HCODEC_VLC_COEFF_INFO 7491 #define DNR_DM_DIF2NORM_LUT0_2 11635 #define MCDI_FIELD_LUMA_AVG_SUM_0 12130 #define P_VLD_MEM_VIFIFO_WRAP_COUNT 4284625220 #define MCDI_FIELD_LUMA_AVG_SUM_1 12131 #define P_ENCI_VBI_CCDT_ODD 4287655048 #define P_MCDI_REL_DET_COL_CFD_AVG_LUMA 4287675660 #define DOS_HCODEC_INT_EN 16134 #define P_VPU_PROT1_MMC_CTRL 4287667360 #define P_NR4_DRT_ALP_MINMAX 4287674016 #define P_D2D3_SCU18_STEP 4287671356 #define HLTI_BST_CORE 12854 #define P_MCDI_CTRL_MODE 4287675408 #define NR4_MCNR_ALP1_SGN_PRAM 14104 #define HCODEC_VLC_ADV_CONFIG 7461 #define P_HEVC_VLD_TIME_STAMP_3 4284674364 #define HCODEC_NEXT_ALIGN_PEAK 7197 #define P_AUDIN_FIFO1_PIO_STS 4291875532 #define WRRSP_LMEM 851 #define P_HEVC_VLD_TIME_STAMP_0 4284674352 #define P_HCODEC_MBREAK_CTRL 4284632164 #define P_HEVC_VLD_TIME_STAMP_1 4284674356 #define P_HEVC_VLD_TIME_STAMP_2 4284674360 #define LCD_ANALOG_SEL_CPH3 8 #define SRSHARP0_DB_FLT_RANDLUT 12921 #define VDEC2_ANC31_CANVAS_ADDR 10671 #define VDIN0_CHROMA_ADDR_PORT 4651 #define VPP_WRAP_OSD3_MATRIX_COEF20_21 15795 #define P_ENCI_VBI_CGMS_LN 4287655076 #define P_DECOMB_DET_EDGE_CON0 4287673864 #define P_DECOMB_DET_EDGE_CON1 4287673868 #define PARSER_SUB_END_PTR 14475 #define P_DVIN_ACTIVE_START_PIX 4291830664 #define P_VDEC2_ANC13_CANVAS_ADDR 4284655220 #define P_ENCP_VIDEO_HSPULS_SWITCH 4287655528 #define P_MB_INFO 4284625072 #define P_DI_IF1_RANGE_MAP_CR 4287651832 #define P_SMARTCARD_REG5 4291973140 #define CHROMA_GAIN_REG00 0 #define P_SMARTCARD_REG6 4291973144 #define P_HEVC_MDEC_PIC_DC_CTRL 4284671544 #define CHROMA_GAIN_REG02 12 #define CHROMA_GAIN_REG01 6 #define CHROMA_GAIN_REG04 24 #define SPICC1_STATREG 21509 #define CHROMA_GAIN_REG03 18 #define CHROMA_GAIN_REG06 36 #define P_SMARTCARD_REG8 4291973152 #define CHROMA_GAIN_REG05 30 #define P_SMARTCARD_REG1 4291973124 #define P_SMARTCARD_REG2 4291973128 #define P_SMARTCARD_REG0 4291973120 #define P_AIU_AMCLK_MSR 4291842376 #define P_HCODEC_ASSIST_DMA_INT2 4284629400 #define HEVC_SAO_AXI_RCTRL 13834 #define CHROMA_GAIN_REG07 42 #define P_HEVC_ASSIST_MBOX0_IRQ_REG 4284662208 #define XVYCC_POST_RGB_CTRST 12661 #define P_HEVC_MPRED_L1_REF15_POC 4284664060 #define P_HEVC_POWER_CTL_MC 4284670996 #define P_DI_IF1_RANGE_MAP_CB 4287651828 #define HCODEC_MBREAK2_REG 4886 #define HEVC_MPRED_L1_REF08_POC 12856 #define DNR_DM_FLT_THD 11622 #define P_VIU_OSD2_MATRIX_COEF20_21 4287654608 #define P_VENC_VDAC_DAC1_FILT_CTRL0 4287656296 #define SRSHARP1_PK_CON_2CIRHPGAIN_LIMIT 13318 #define P_VENC_VDAC_DAC1_FILT_CTRL1 4287656300 #define NR3_MODE 12272 #define HCODEC_NEXT_INTRA_DMA_ADDRESS 7693 #define P_L_OEV3_HE_ADDR 4287647968 #define P_PK_CON_2DRTBPGAIN_TH_RATE 4287678508 #define P_GE2D_STATUS2 4287890340 #define VPP_HSC_START_PHASE_STEP 7443 #define P_GE2D_STATUS0 4287890064 #define P_GE2D_STATUS1 4287890068 #define ANC10_CANVAS_ADDR 2458 #define SPI_FLASH_SLAVE3 20495 #define SPI_FLASH_SLAVE2 20494 #define SPI_FLASH_SLAVE1 20493 #define P_VIU2_VD1_IF0_CHROMA0_RPT_PAT 4287658356 #define VDIN_LDIM_STTS_HIST_SET_REGION 4696 #define NR4_MCNR_GREEN_CLIP2 11729 #define NR4_MCNR_GREEN_CLIP0 11728 #define P_HCODEC_IGNORE_CONFIG_2 4284644364 #define P_HEVC_DC_AC_SCALE_DIV 4284676124 #define P_HCODEC_DCAC_CPU_DATA 4284643412 #define VD2_AFBC_VD_CFMT_CTRL 12683 #define P_GE2D_DST_BITMASK 4287890248 #define P_QDCT_JPEG_QUANT_ADDR 4284644512 #define P_HCODEC_V3_LEFT_SMALL_MAX_SAD 4284644840 #define VDEC2_PSCALE_CANVAS_RD_ADDR 10540 #define HEVC_ANC31_CANVAS_ADDR 14767 #define VDIN1_HIST_CHROMA_SUM 5174 #define VPP_EOTF_COEF02_10 12754 #define P_HCODEC_MC_STATUS0 4284638244 #define P_HCODEC_MC_STATUS1 4284638248 #define P_VDEC_ASSIST_DMA_INT_MSK 4284613012 #define P_HEVCD_MPP_DECOMP_CTL3 4284666640 #define P_VPP_VSC_REGION3_PHASE_SLOPE 4287657004 #define P_HEVCD_MPP_DECOMP_CTL2 4284666636 #define P_HEVCD_MPP_DECOMP_CTL1 4284666632 #define DI_CHAN2_GEN_REG2 6071 #define DI_CHAN2_GEN_REG3 8362 #define P_AUDOUT_FIFO_PIO_STS 4291875556 #define P_NR4_RO_NM_SAD_SUM 4287683708 #define P_VPP2_PREBLEND_VD1_H_START_END 4287652968 #define P_VIU_OSD2_MATRIX_HL_COLOR 4287654636 #define VCOP_CTRL_REG 3584 #define VPP_OSD_SCALE_COEF 7629 #define VBO_INTR_STATE_CTRL 5244 #define RAM_TEST_DATAH 4 #define VIU2_OSD2_BLK0_CFG_W4 7780 #define VIU_OSD1_MATRIX_COEF31_32 6814 #define L_VCOM_VE_ADDR 5150 #define VIU2_OSD2_BLK0_CFG_W2 7741 #define VIU2_OSD2_BLK0_CFG_W3 7742 #define VIU2_OSD2_BLK0_CFG_W0 7739 #define VIU2_OSD2_BLK0_CFG_W1 7740 #define RAM_TEST_DATAL 5 #define V3_IPRED_TYPE_WEIGHT_1 8057 #define P_HCODEC_DBLK_VLD_HCMD0 4284638704 #define V3_IPRED_TYPE_WEIGHT_0 8056 #define P_HCODEC_DBLK_VLD_HCMD1 4284638700 #define P_HCODEC_DBLK_VLD_HCMD2 4284638696 #define P_AHB_ARBITER2_REG 4291883304 #define P_VKS_IWIN_HSIZE 4287677468 #define P_DECOMB_WIND01 4287673900 #define P_DECOMB_WIND00 4287673896 #define VIU_OSD2_MATRIX_PRE_OFFSET2 6841 #define VPU_PROT3_RPT_LOOP 10101 #define OEV2_HE_ADDR 5300 #define P_VDIN_MATRIX_CTRL 4287645760 #define DI_INP_URGENT_CTRL 8356 #define AUDIN_FIFO1_LOAD 2 #define P_DECOMB_WIND10 4287673904 #define P_DECOMB_WIND11 4287673908 #define P_SPICC1_PERIODREG 4291907608 #define VPP_BLACKEXT_CTRL 7552 #define GAMMA_PROBE_POS_X 5261 #define P_NR2_MATNR_YBETA_SCL 4287651180 #define MLVDS_CONTROL 5315 #define GAMMA_PROBE_POS_Y 5262 #define P_IGNORE_CONFIG_2 4284644364 #define OEV_UNITE 3 #define P_MDB_CTRL 4284615796 #define P_ENCL_VIDEO_PR_SCL 4287656588 #define HEVC_ANC0_CANVAS_ADDR 14736 #define ENCL_VIDEO_HOFFST 7359 #define AFBC_BODY_BADDR 6887 #define HEVC_MPRED_L0_REF12_POC 12844 #define P_VENC_DVI_SETTING_MORE 4287656260 #define P_VPP2_BLEND_ONECOLOR_CTRL 4287653004 #define P_CPU_TRACE 4284616192 #define P_VPP_MATRIX_COEF11_12 4287657352 #define SRSHARP1_NR_ALPY_SSD_GAIN_OFST 13332 #define P_VIU_OSD2_BLK0_CFG_W4 4287654288 #define P_VIU_OSD2_BLK0_CFG_W3 4287654136 #define P_VIU_OSD2_BLK0_CFG_W2 4287654132 #define P_VIU_OSD2_BLK0_CFG_W1 4287654128 #define P_HCODEC_RESYNC_MARKER_LENGTH 4284641336 #define VPP_XVYCC_MISC0 7647 #define HEVC_SAO_VB_WR_START_ADDR 13842 #define P_VPP_MATRIX_COEF23_24 4287657840 #define P_VIU_OSD2_BLK0_CFG_W0 4287654124 #define P_VIUB_ADDR_END 4287661052 #define P_HEVC_PARSER_HEADER_INFO 4284662876 #define VPP_XVYCC_MISC1 7648 #define P_COMM_DESC_2_CTL 4291847164 #define P_DI_MC_32LVL1 4287650988 #define P_DI_MC_32LVL0 4287650984 #define P_VPP_OFIFO_SIZE 4287657116 #define P_VDIN_BLKBAR_IND_RIGHT2_CNT 4287646120 #define P_QDCT_INT_STATUS 4284644600 #define HCODEC_Q_QUANT_CONTROL 7990 #define HEVC_DBLK_STS1 13582 #define SPICC0_RXDATA 19456 #define P_MC_PIC_W_H 4284621856 #define P_RESET6_MASK 4291825752 #define HEVC_DBLK_STS0 13581 #define SRSHARP1_VLTI_BST_GAIN 13371 #define VDIN_VSHRK_CTRL 4721 #define HCODEC_ANC18_CANVAS_ADDR 6562 #define P_VDEC2_CINDEX6_REG 4284648640 #define VDEC2_MC_OTHER_GCLK_CTRL 10574 #define HEVC_DBLK_BETAX_QP_SEL 14689 #define HEVC_CBREAK_STAUTS 13114 #define P_HEVC_CCPU_INTR_GRP 4284664972 #define PARSER_VIDEO_RP 14467 #define QDCT_STATUS_CTRL 7936 #define P_DI_PRE_SIZE 4287650828 #define P_EE_ASSIST_MBOX0_IRQ_REG 4291854784 #define P_VPP_MATRIX_PRE_OFFSET0_1 4287657372 #define P_SHARP_SR3_DRTLPF_ALPHA_OFST 4287678888 #define P_VPP_OSD_VSC_PHASE_STEP 4287657728 #define DI_MEM_GEN_REG3 8361 #define DI_MEM_GEN_REG2 6034 #define P_HCODEC_CINDEX4_REG 4284632248 #define REG_CM2_ENH_COEFF3_H12 355 #define HEVC_IMEM_DMA_ADR 13121 #define REG_CM2_ENH_COEFF3_H13 363 #define REG_CM2_ENH_COEFF3_H10 339 #define REG_CM2_ENH_COEFF3_H11 347 #define P_DOLBY_TV_ADAPTIVE_SCALE_REGDATA 4287680388 #define REG_CM2_ENH_COEFF3_H09 331 #define REG_CM2_ENH_COEFF3_H07 315 #define P_POL_CNTL_ADDR 4287648284 #define REG_CM2_ENH_COEFF3_H08 323 #define P_NR2_IIR_CTRL 4287651128 #define P_HEVCD_IPP_SWMPREDIF_CTBINFO 4284665928 #define VPU_ASYNC_RD_MODE0 10149 #define VPU_ASYNC_RD_MODE1 10150 #define VPU_ASYNC_RD_MODE2 10151 #define VPU_ASYNC_RD_MODE3 10152 #define VPU_ASYNC_RD_MODE4 10153 #define REG_CM2_ENH_COEFF3_H01 267 #define REG_CM2_ENH_COEFF3_H02 275 #define REG_CM2_ENH_COEFF3_H00 259 #define REG_CM2_ENH_COEFF3_H05 299 #define REG_CM2_ENH_COEFF3_H06 307 #define REG_CM2_ENH_COEFF3_H03 283 #define REG_CM2_ENH_COEFF3_H04 291 #define OSDSR_CONST_PARA 12601 #define P_HCODEC_DCAC_DMA_ADDRESS 4284643404 #define P_VIU2_VD1_IF0_RANGE_MAP_CR 4287658416 #define P_VDEC2_ACC1REG1 4284648840 #define P_VDIN_VSHRK_CTRL 4287646148 #define P_VDEC2_ACC1REG2 4284648904 #define DI_INP_LUMA_X0 6096 #define HEVC_MBREAK0_REG 13076 #define P_VIU2_VD1_IF0_RANGE_MAP_CB 4287658412 #define DI_INP_LUMA_Y0 6097 #define VLD_MEM_VIFIFO_MEM_CTL 3154 #define P_VPU_422TO444_RST 4287667496 #define SHARP_SR3_DRTLPF_EN 12902 #define VPP_MATRIX_COEF22 7524 #define PARSER_VIDEO_WP 14466 #define P_AUDIN_FIFO2_END 4291875096 #define HCODEC_VLC_VB_START_PTR 7440 #define AIU_CRC_CAL_REG1 5192 #define AIU_CRC_CAL_REG0 5193 #define VDEC2_VLD_SHIFT_STATUS 11323 #define P_PK_DRTFB_HP_CORING 4287678532 #define STV1_VS_ADDR 5289 #define HCODEC_ANC21_CANVAS_ADDR 6565 #define P_MCDI_FIELD_MV 4287675776 #define P_HEVC_PARSER_CMD_WRITE 4284662856 #define P_HEVCD_MPP_ANC_CANVAS_DATA_ADDR 4284666628 #define HEVC_ASSIST_MBOX1_IRQ_REG 12404 #define ENCP_VBI_BEGIN 7122 #define SRSHARP1_NR_ALP0_MIN_MAX 13337 #define SRSHARP1_PK_ALP2_MIN_MAX 13345 #define P_HCODEC_IMEM_DMA_COUNT 4284632328 #define VDEC2_NON_I_QUANT_MATRIX 11779 #define LCD_TTL_SEL 4 #define P_HEVC_MPRED_L0_REF05_POC 4284663956 #define HCODEC_AVSP_IQ_WQ_PARAM_23 7706 #define P_I2C_M_0_RDATA_REG1 4291948572 #define P_I2C_M_0_RDATA_REG0 4291948568 #define P_HCODEC_HENC_SCRATCH_E 4284640056 #define P_HCODEC_HENC_SCRATCH_D 4284640052 #define P_HCODEC_HENC_SCRATCH_G 4284640064 #define P_HCODEC_HENC_SCRATCH_F 4284640060 #define P_HCODEC_HENC_SCRATCH_I 4284640072 #define P_HCODEC_HENC_SCRATCH_H 4284640068 #define P_HCODEC_HENC_SCRATCH_K 4284640080 #define P_HCODEC_HENC_SCRATCH_J 4284640076 #define P_HCODEC_HENC_SCRATCH_M 4284640088 #define P_HCODEC_HENC_SCRATCH_L 4284640084 #define VDIN1_BLKBAR_V_START_END 5218 #define P_SPICC1_LD_RADDR 4291907632 #define P_HCODEC_HENC_SCRATCH_N 4284640092 #define P_STH2_HS_ADDR 4287648336 #define VKS_PPS_YCOEF31 74 #define P_HCODEC_HENC_SCRATCH_5 4284640020 #define VKS_PPS_YCOEF30 73 #define P_HCODEC_HENC_SCRATCH_4 4284640016 #define P_HCODEC_HENC_SCRATCH_7 4284640028 #define P_HCODEC_HENC_SCRATCH_6 4284640024 #define P_HCODEC_HENC_SCRATCH_9 4284640036 #define P_HCODEC_HENC_SCRATCH_8 4284640032 #define VKS_PPS_YCOEF32 75 #define P_HCODEC_HENC_SCRATCH_A 4284640040 #define P_MC_PIC_INFO 4284621832 #define P_HCODEC_HENC_SCRATCH_C 4284640048 #define P_HCODEC_HENC_SCRATCH_B 4284640044 #define VDIN_VSC_PHASE_STEP 4643 #define P_ANC18_CANVAS_ADDR 4284622472 #define HCODEC_MINDEX2_REG 4876 #define AUD_RESAMPLE_CTRL2 13506 #define P_VPP_MATRIX_OFFSET2 4287657368 #define AUD_RESAMPLE_CTRL0 13503 #define AUD_RESAMPLE_CTRL1 13504 #define VKS_PPS_YCOEF20 63 #define VKS_PPS_YCOEF24 67 #define VKS_PPS_YCOEF23 66 #define VKS_PPS_YCOEF22 65 #define P_VPP_HSC_INI_PAT_CTRL 4287657172 #define VKS_PPS_YCOEF21 64 #define VKS_PPS_YCOEF28 71 #define VKS_PPS_YCOEF27 70 #define VKS_PPS_YCOEF26 69 #define HCODEC_MC_OTHER_GCLK_CTRL 6478 #define VKS_PPS_YCOEF25 68 #define P_ENCP_MACV_AGC_STRT 4287655696 #define HCODEC_AVSP_IQ_WQ_PARAM_45 7707 #define VKS_PPS_YCOEF29 72 #define HEVC_IQIDCT_CONTROL 15886 #define P_XVYCC_INV_LUT_V_DATA_PORT 4287677812 #define HEVC_SAO_IF_DATA_V 12595 #define HEVC_SAO_IF_DATA_Y 12593 #define VKS_PPS_YCOEF13 56 #define P_HEVC_MPRED_AXI_WCTRL 4284663872 #define VKS_PPS_YCOEF12 55 #define VKS_PPS_YCOEF11 54 #define HEVC_SAO_IF_DATA_U 12594 #define VKS_PPS_YCOEF10 53 #define P_DI_NR_CTRL2 4287650852 #define VKS_PPS_YCOEF17 60 #define MCDI_HIGH_VERT_FRQ_DIF_DIF_THD 12112 #define P_DI_NR_CTRL1 4287650848 #define P_PSCALE_PICO_START_Y 4284621916 #define VKS_PPS_YCOEF16 59 #define P_DI_NR_CTRL0 4287650844 #define VKS_PPS_YCOEF15 58 #define VKS_PPS_YCOEF14 57 #define P_PSCALE_PICO_START_X 4284621912 #define VKS_PPS_YCOEF19 62 #define VKS_PPS_YCOEF18 61 #define ABUF_WR_BLK_SIZE_LSB 0 #define DIPD_RO_COMB_20 12266 #define DIPD_RO_COMB_13 12259 #define DIPD_RO_COMB_14 12260 #define DIPD_RO_COMB_15 12261 #define DIPD_RO_COMB_16 12262 #define VKS_PPS_YCOEF02 45 #define DIPD_RO_COMB_17 12263 #define P_AUDIN_FIFO1_REQID 4291875084 #define VKS_PPS_YCOEF01 44 #define SRSHARP0_NR_ALPY_SSD_GAIN_OFST 12820 #define DIPD_RO_COMB_18 12264 #define VKS_PPS_YCOEF00 43 #define DIPD_RO_COMB_19 12265 #define PK_CIRFB_LPF_MODE 12813 #define VKS_PPS_YCOEF06 49 #define VKS_PPS_YCOEF05 48 #define VKS_PPS_YCOEF04 47 #define VKS_PPS_YCOEF03 46 #define VKS_PPS_YCOEF09 52 #define VKS_PPS_YCOEF08 51 #define VKS_PPS_YCOEF07 50 #define MIPI_DSI_DWC_BTA_TO_CNT_OS 7203 #define DIPD_RO_COMB_10 12256 #define DIPD_RO_COMB_11 12257 #define DIPD_RO_COMB_12 12258 #define HEVC_MPRED_PIC_SIZE_LCU 12806 #define HCODEC_VLD_REVERVED_19 7193 #define VPU_PROT2_CLK_GATE 10080 #define AUDIN_FIFO1_CTRL 13368 #define P_HCODEC_ANC30_CANVAS_ADDR 4284638904 #define P_HEVC_ASSIST_MBOX1_FIQ_SEL 4284662236 #define P_MCDI_REL_DET_LUT_12_15 4287675652 #define VDIN0_COM_STATUS1 4614 #define VDIN0_COM_STATUS0 4613 #define VDIN0_COM_STATUS3 4723 #define VDIN0_COM_STATUS2 4622 #define VLTI_BST_GAIN 12859 #define P_AUDIN_FIFO0_PTR 4291874952 #define HEVC_ASSIST_AFIFO_CTRL1 12290 #define P_ENCL_VIDEO_BLANKPR_VAL 4287656696 #define P_VDEC2_ASSIST_AMR2_INTF 4284645648 #define P_ENCP_VIDEO_SYNC_SCL 4287655448 #define P_DI_IF1_GEN_REG 4287651744 #define P_DI_MEM_RANGE_MAP_CR 4287651580 #define P_VDEC2_ASSIST_AMR2_INT4 4284645604 #define P_VDEC2_ASSIST_AMR2_INT5 4284645608 #define P_VDEC2_ASSIST_AMR2_INT2 4284645596 #define P_VDEC2_ASSIST_AMR2_INT3 4284645600 #define P_VDEC2_ASSIST_AMR2_INT0 4284645588 #define P_VDEC2_ASSIST_AMR2_INT1 4284645592 #define P_HEVC_PSCALE_SRCKEY_CTRL0 4284671144 #define P_HEVC_PSCALE_SRCKEY_CTRL1 4284671148 #define PSCALE_MCMD_YSIZE 2340 #define P_VDEC2_ASSIST_AMR2_INTD 4284645640 #define HCODEC_MFDIN_REG0_CRST 4104 #define P_VDEC2_ASSIST_AMR2_INTE 4284645644 #define P_VDEC2_ASSIST_AMR2_INTB 4284645632 #define P_VDEC2_ASSIST_AMR2_INTC 4284645636 #define ENCI_TST_CLRBAR_WIDTH 7190 #define P_VDEC2_ASSIST_AMR2_INTA 4284645628 #define VPU_RDARB_WEIGH1_SLV_L1C1 10131 #define VPU_RDARB_WEIGH1_SLV_L1C2 10162 #define P_VDEC2_ASSIST_AMR2_INT8 4284645620 #define P_VDEC2_ASSIST_AMR2_INT9 4284645624 #define P_VDEC2_ASSIST_AMR2_INT6 4284645612 #define P_VDEC2_ASSIST_AMR2_INT7 4284645616 #define HCODEC_CBREAK1_REG 4917 #define VP9D_MPP_REFINFO_DATA 13379 #define HCODEC_VLC_PIC_INFO 7474 #define NR4_MCNR_LUMA_STAT_LIMTY 11706 #define NR4_MCNR_LUMA_STAT_LIMTX 11705 #define P_L_DE_HS_ADDR 4287648068 #define P_DCAC_CPU_ADDRESS 4284627024 #define UART1_CONTROL 35842 #define LDIM_STTS_MATRIX_COEF02_10 6852 #define P_VDEC2_MBREAK_CTRL 4284648548 #define P_DIPD_COMB_CTRL4 4287676240 #define P_DIPD_COMB_CTRL5 4287676244 #define P_DIPD_COMB_CTRL2 4287676232 #define P_DIPD_COMB_CTRL3 4287676236 #define P_DIPD_COMB_CTRL0 4287676224 #define P_DIPD_COMB_CTRL1 4287676228 #define VDIN_WIN_V_START_END 4718 #define P_HCODEC_VLC_VB_WR_PTR 4284642376 #define MIPI_DSI_DWC_PHY_IF_CFG_OS 7209 #define P_VPP_VADJ2_MA_MB 4287657236 #define P_VPP_EOTF_COEF22_RS 4287678292 #define P_VDEC2_DBLK_CMD_CTRL 4284654928 #define P_VDEC2_CURR_CANVAS_CTRL 4284655308 #define VDIN0_HIST_SPL_VAL 4660 #define HCODEC_AVSP_IQ_WQ_PARAM_01 7705 #define SRSHARP1_HLTI_BST_CORE 13366 #define ENCP_DE_V_BEGIN_ODD 7230 #define P_DI_MEM_RANGE_MAP_CB 4287651576 #define VDIN_MATRIX_HL_COLOR 4649 #define DI_NRWR_CTRL 6082 #define P_VDEC_ASSIST_MBOX1_CLR_REG 4284613076 #define HCODEC_MFDIN_REG2_STAT 4106 #define P_DC_CAV_LUT_DATAH 4284710988 #define DBLK_VLD_HCMD0 2428 #define P_UART1_STATUS 4291964940 #define P_DC_CAV_LUT_DATAL 4284710984 #define VPP_VADJ2_MA_MB 7493 #define P_VIU_OSD1_EOTF_COEF11_12 4287654748 #define DBLK_VLD_HCMD2 2426 #define DBLK_VLD_HCMD1 2427 #define P_HEVC_SHIFT_CONTROL 4284662816 #define P_MCDI_REL_DET_MIN 4287675636 #define L_VSYNC_VS_ADDR 5211 #define P_HEVC_RV_AI_U_X 4284676136 #define DI_INP_RANGE_MAP_CB 6075 #define P_VP9_SHADOW_DATA 4284663108 #define P_CVBS_IRQ0_CNTL 4291883152 #define DET3D_RO_MAT_CHRU_LR 6021 #define CINDEX5_REG 815 #define DI_INP_RANGE_MAP_CR 6076 #define P_HCODEC_MFDIN_REG5_LNR1 4284629044 #define P_VPU_422TO444_CTRL0 4287667500 #define P_VPU_422TO444_CTRL1 4287667504 #define P_DI_EI_XWIN1 4287651428 #define P_DI_EI_XWIN0 4287651424 #define P_AIU_MEM_IEC958_MASKS 4291842464 #define RDMA_AHB_END_ADDR_MAN 4353 #define VDIN0_SYNC_MASK 4724 #define BYTE_ALIGN_PEAK_HI 3099 #define VPP2_MATRIX_CTRL 6495 #define WM_STORAGE_SETTING 12729 #define HEVC_MC_WT_PRED_CTRL 14658 #define P_VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT 4284657988 #define P_VIU2_OSD2_BLK1_CFG_W4 4287658388 #define P_VIU2_OSD2_BLK1_CFG_W2 4287658244 #define P_VIU2_OSD2_BLK1_CFG_W3 4287658248 #define P_VIU2_OSD2_BLK1_CFG_W0 4287658236 #define P_VIU2_OSD2_BLK1_CFG_W1 4287658240 #define RESET2_MASK 1042 #define P_QDCT_MB_BUFF 4284644444 #define NR_ALPY_SSD_GAIN_OFST 12820 #define ENCT_VIDEO_PR_SCL 7267 #define HCODEC_DBLK_CBPY_ADJ 6513 #define LVDS_SRG_TEST 5352 #define P_HEVC_SLICE_QP 4284674088 #define SRSHARP1_NR_ALP1_MIERR_CORING 13338 #define P_AUDIN_FIFO1_WRAP 4291875088 #define P_VLD_SHIFT_STATUS 4284625132 #define P_OSD_BLEND_DUMMY_DATA 4287654580 #define P_HCODEC_MDEC_DOUBLEW_CFG7 4284639112 #define BYTE_ALIGN_PEAK_LO 3100 #define P_HCODEC_MDEC_DOUBLEW_CFG0 4284639084 #define P_L_STV1_HE_ADDR 4287647904 #define P_HCODEC_MDEC_DOUBLEW_CFG2 4284639092 #define P_ABUF_ARB_CTL0 4291883488 #define P_HCODEC_MDEC_DOUBLEW_CFG1 4284639088 #define P_HCODEC_MDEC_DOUBLEW_CFG4 4284639100 #define P_HCODEC_MDEC_DOUBLEW_CFG3 4284639096 #define P_HCODEC_MDEC_DOUBLEW_CFG6 4284639108 #define DOS_VDIN_CCTL 16141 #define P_HCODEC_MDEC_DOUBLEW_CFG5 4284639104 #define HEVC_MCPU_INTR_MSK 13060 #define HEVC_ASSIST_MBOX0_FIQ_SEL 12403 #define P_MCDI_FIELD_LUMA_AVG_SUM_0 4287675784 #define P_MCDI_FIELD_LUMA_AVG_SUM_1 4287675788 #define VIU2_ADDR_END 7935 #define P_HCODEC_VLC_COEFF_BUF_STATUS 4284642560 #define P_VOFF_STATUS 4284625136 #define AIU_958_FORCE_LEFT 5125 #define DNR_DM_AVG_THD 11625 #define P_VDEC2_MINDEX7_REG 4284648516 #define P_CVBS_IRQ0_COUNTER 4291883160 #define P_VSYNC_VE_ADDR 4287648624 #define P_LVDS_SER_EN 4287648704 #define DET3D_RO_MAT_CHRU_TB 6022 #define VPP_VSC_REGION0_PHASE_SLOPE 7433 #define P_ISA_BIST_REG0 4291883200 #define P_ISA_BIST_REG1 4291883204 #define P_VPU_VLOCK_OVWRITE_ACCUM1 4287676448 #define VPU_PROT3_Y_LEN_STEP 10100 #define P_VPU_VLOCK_OVWRITE_ACCUM0 4287676444 #define P_VLC_CONFIG 4284642308 #define P_VDIN_INTF_WIDTHM1 4287645808 #define HEVC_MMAX_REG 13075 #define GE2D_SRC1_CLIPY_START_END 168 #define P_AHB_MP4_MC_CTL 4291883388 #define P_RESET6_LEVEL 4291825816 #define HEVCD_IPP_BITDEPTH_CONFIG 13324 #define ABUF_RD_INT_POS_MSB 30 #define HEVC_DBLK_CB_FILT 14687 #define QDCT_MB_END_PTR 7953 #define P_HEVC_ASSIST_MBOX2_IRQ_REG 4284662240 #define VDEC2_MBREAK1_REG 8981 #define ENCT_VIDEO_VSO_BLINE 7289 #define P_DOS_GEN_CTRL0 4284677128 #define P_HCODEC_HENC_SCRATCH_1 4284640004 #define P_HCODEC_HENC_SCRATCH_0 4284640000 #define P_HCODEC_HENC_SCRATCH_3 4284640012 #define P_HCODEC_HENC_SCRATCH_2 4284640008 #define P_ENCL_SYNC_TO_PIXEL 4287656252 #define HCODEC_FST_BAK_MV_X 7188 #define HCODEC_FST_BAK_MV_Y 7189 #define CBREAK_TYPE 824 #define RDMA_CTRL 4372 #define P_VBO_VBK_CTRL_0 4287648168 #define P_VBO_VBK_CTRL_1 4287648172 #define VPP2_HSC_REGION3_PHASE_SLOPE 6422 #define P_VDEC2_ANC16_CANVAS_ADDR 4284655232 #define P_INV_CNT_ADDR 4287648512 #define HCODEC_MDEC_SW_RESET 6532 #define ENCL_SYNC_LINE_LENGTH 7244 #define VPP_WRAP_OSD3_MATRIX_OFFSET2 15802 #define HCODEC_V5_SIMPLE_MB_DQUANT 8063 #define VDEC2_MBREAK0_REG 8980 #define RDMA_SRAM_REGDATA 4386 #define HCODEC_QDCT_JPEG_CTRL 7973 #define mLVDS_reset_pattern_ext 0 #define P_VPU_CONT_MMC_CTRL 4287667336 #define CPV1_HS_ADDR 5279 #define VPP_MATRIX_COEF15_25 7645 #define P_GE2D_SRC2_CLIPY_START_END 4287890116 #define P_HEVC_ANC24_CANVAS_ADDR 4284671648 #define P_VDEC2_SCD_BAK_MV_X 4284657752 #define P_VDEC2_SCD_BAK_MV_Y 4284657756 #define P_SHARP_SR3_DRTLPF_EN 4287678872 #define P_ENCP_SYNC_TO_LINE_EN 4287656216 #define PK_FINALGAIN_HP_BP 12834 #define P_ENCP_VIDEO_VOFFST 4287655640 #define NR2_MATNR_MTN_COR 5996 #define P_VDEC2_MB_INFO 4284657840 #define HEVC_DBLK_OST_CBCRDIFF 14718 #define P_HEVC_CCPU_INTR_MSK 4284664976 #define P_HCODEC_VLC_VB_INT_PTR 4284642400 #define P_VDEC2_NEXT_INTRA_DMA_ADDRESS 4284659764 #define DBLK_STATUS 2387 #define P_HEVC_SAO_AXI_WCTRL 4284667940 #define VDIN1_DUMMY_DATA 5158 #define DNR_VBOFFST_STAT 11526 #define P_PWM_TIME_CD 4291928080 #define HEVC_SAO_VERSION 13824 #define P_ASSIST_POR_CONFIG 4291854676 #define SRSHARP0_SR3_DERING_GAINVS_VR2MAX 12913 #define HEVC_SAO_DBG_MODE1 13855 #define HEVC_SAO_DBG_MODE0 13854 #define AHB_ARBITER_REG 15426 #define VDIN1_LDIM_STTS_HIST_REGION_IDX 5207 #define P_MAC_CTRL1 4284616064 #define P_MAC_CTRL2 4284616128 #define P_VPP_EOTF_COEF20_21 4287678288 #define DET3D_RO_MAT_HEDG_TB 6026 #define P_NR3_CNOOP_GAIN 4287676360 #define P_PWM_TIME_EF 4291923984 #define ENCI_RGB_SETTING 6931 #define NR_GAUSSIAN_MODE 12802 #define P_DNLP_13 4287678796 #define P_DNLP_14 4287678800 #define P_DNLP_15 4287678804 #define VENC_VDAC_FIFO_CTRL 7164 #define HCODEC_SAD_CONTROL_1 7995 #define HCODEC_SAD_CONTROL_0 7994 #define C656_FS_LNED 7143 #define P_DI_EI_DRT_PIXTH 4287651300 #define VDIN_MATRIX_COEF20_21 4628 #define P_VPU_VD2_MMC_CTRL 4287667216 #define L_TCON_PATTERN_HI 5194 #define P_AIU_MEM_AIFIFO2_MAN_RP 4291842496 #define DNR_DM_EDGE_DIF_THD 11624 #define P_HEVC_MC_CTRL_GCLK_CTRL 4284671284 #define VPU_OSD3_MMC_CTRL 10007 #define P_VIU2_OSD2_HL1_H_START_END 4287658188 #define HCODEC_F_CODE_REG 7170 #define P_VPU_ISP_GCLK_CTRL1 4287667464 #define SPI_FLASH_B10 20506 #define P_VPU_ISP_GCLK_CTRL0 4287667460 #define P_VDIN_MATRIX_PROBE_COLOR 4287645856 #define SPI_FLASH_B12 20508 #define SPI_FLASH_B11 20507 #define SPI_FLASH_B14 20510 #define SPI_FLASH_B13 20509 #define P_VDIN_BLKBAR_V_START_END 4287646088 #define MIPI_DSI_DWC_VID_HSA_TIME_OS 7186 #define VLC_COEFF_BUF_STATUS 7488 #define ENCI_DBG_FLDLN_INT 6987 #define P_VPU_ARB_DBG_CTRL_L1C2 4287667924 #define P_VPU_ARB_DBG_CTRL_L1C1 4287667916 #define SPI_FLASH_B15 20511 #define P_VDIN_LCNT_STATUS 4287645712 #define HEVC_MPRED_CURR_LCU 12825 #define HEVC_MPRED_L0_REF00_POC 12832 #define AUDOUT_FIFO_PIO_STS 13497 #define DOLBY_CORE2A_STATUS3 13374 #define CPV1_HE_ADDR 5280 #define DOLBY_CORE2A_STATUS2 13373 #define DOLBY_CORE2A_STATUS1 13372 #define DOLBY_CORE2A_STATUS0 13371 #define HEVC_MPRED_L1_REF07_POC 12855 #define P_ENCP_VIDEO_EN 4287655424 #define NR2_MATNR_SNR_LPF_CFG 5973 #define MIPI_DSI_TOP_STAT 7415 #define HEVC_PSCALE_PICO_SHIFT_XY 14632 #define DET3D_RO_MAT_HEDG_LR 6025 #define L_TCON_PATTERN_LO 5195 #define ENCP_VIDEO_HSO_END 7080 #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 15723 #define HEVC_MCPU_INTR_REQ 13061 #define VDEC2_VLD_DC_PRED_C 11311 #define P_VDEC2_MC_HCMDBUF_H 4284654880 #define HCODEC_QDCT_TOP_WRRSP 7970 #define GE2D_MATRIX_OFFSET 203 #define P_VDEC2_MC_HCMDBUF_L 4284654884 #define MIPI_DSI_TOP_MEAS_STAT_VS0 7418 #define MIPI_DSI_TOP_MEAS_STAT_VS1 7419 #define P_NR4_MCNR_BANDSPLIT_PRAM 4287683672 #define P_DI_CHAN2_URGENT_CTRL 4287660696 #define HCTI_CON_2_GAIN_0 12849 #define HCTI_CON_2_GAIN_1 12850 #define P_D2D3_DBLD_LG_PARAM 4287671372 #define L_LCD_PWM0_LO_ADDR 5180 #define P_VDIN_SCIN_HEIGHTM1 4287645844 #define VDEC2_MCW_DBLK_WRRSP_CNT 10683 #define EE_ASSIST_MBOX3_CLR_REG 8317 #define DITH10_CNTL 4 #define VDIN1_SCALE_COEF 5121 #define HCODEC_MC_CMD 6406 #define DVIN_FRONT_END_CTRL 2272 #define P_SANA_SHIFT_CONTROL 4291870876 #define P_HEVC_RV_AI_V_X 4284676140 #define P_CRT_MASK 4291825756 #define P_ENCP_DE_H_END 4287656172 #define P_ENCP_DBG_LN_INT 4287655500 #define HEVC_IQIT_SCALELUT_WR_ADDR 14082 #define P_PARSER_FETCH_ADDR 4291879300 #define P_HCODEC_CPU_TRACE 4284632576 #define P_ENCT_DBG_PX_INT 4287656364 #define P_VDEC2_ASSIST_MBOX2_MASK 4284645864 #define RGB_BASE_ADDR 5253 #define P_DBLK_CBPC 4284622280 #define HEVC_CPSR 13089 #define HEVC_LMEM_DMA_ADR 13137 #define HEVC_MC_PIC_INFO 14594 #define P_L_STV2_VS_ADDR 4287647924 #define P_DBLK_CBPY 4284622272 #define P_DNLP_00 4287678744 #define P_DNLP_01 4287678748 #define P_DNLP_02 4287678752 #define P_VIU2_VD1_IF0_LUMA0_RPT_PAT 4287658352 #define VPU_VD2_MMC_CTRL 9988 #define P_DNLP_03 4287678756 #define P_DNLP_04 4287678760 #define P_DNLP_05 4287678764 #define L_OEV2_HS_ADDR 5171 #define P_DNLP_06 4287678768 #define L_DITH_CNTL_ADDR 5128 #define P_DNLP_07 4287678772 #define P_DNLP_08 4287678776 #define P_DNLP_09 4287678780 #define P_ADV_MV_CTL2 4284644780 #define P_ADV_MV_CTL0 4284644772 #define P_ADV_MV_CTL1 4284644776 #define P_L_VSYNC_HE_ADDR 4287648104 #define DI_IF2_GEN_REG2 8222 #define DI_IF2_GEN_REG3 8226 #define P_DNLP_10 4287678784 #define P_DNLP_11 4287678788 #define P_RDMA_SRAM_REGADDR 4287644804 #define P_DNLP_12 4287678792 #define P_HCODEC_MCPU_INTR_GRP 4284632076 #define VPP2_MATRIX_COEF20_21 6499 #define HEVC_IQIT_AVS2_QP_DELTA 14095 #define VDIN0_MATRIX_COEF00_01 4625 #define P_DBLK_CMD_CTRL 4284622160 #define P_HEVC_MPRED_L1_REF03_POC 4284664012 #define VDEC2_DBLK_VHMVD 10612 #define P_HEVC_SHIFTED_DATA 4284662832 #define P_VDEC2_ACC0REG2 4284648900 #define P_VDEC2_ACC0REG1 4284648836 #define VDIN0_MATRIX_PROBE_POS 4650 #define VDEC2_MINDEX0_REG 8970 #define P_NR_GAUSSIAN_MODE 4287678472 #define GE2D_SRC1_X_START_END 170 #define P_HEVC_SAO_TILE_SIZE_LCU 4284667936 #define P_NR_ALP1_ERR2CURV_LIMIT 4287678576 #define VDEC2_MC_PIC_W_H 10504 #define P_VDEC2_MC_MB_INFO 4284654596 #define NR4_RO_NR4_DBGPIX_NUM 14116 #define P_SANA_STREAM_WR_PTR 4291870860 #define AUDIN_FIFO0_PIO_RDH 13490 #define P_NR_ALP1_MIN_MAX 4287678580 #define P_PK_CON_2CIRBPGAIN_LIMIT 4287678496 #define AUDIN_FIFO1_PIO_STS 13491 #define AUDIN_FIFO0_PIO_RDL 13489 #define VPP_VSC_PHASE_CTRL 7437 #define P_HEVC_PARSER_IF_CONTROL 4284662920 #define P_VDIN_BLKBAR_IND_RIGHT1_CNT 4287646116 #define P_PWM_TIME_AB 4291932176 #define ASSIST_HW_REV 8275 #define HCODEC_ME_F_SKIP_WEIGHT 8020 #define P_HCODEC_VLC_STATUS_CTRL 4284642304 #define P_HEVC_SAO_INT_EN 4284667916 #define P_VDEC2_CINDEX5_REG 4284648636 #define P_HEVC_MDEC_PICW_BUF2_STATUS 4284671732 #define VPP2_DUMMY_DATA1 6505 #define NR4_MCNR_BLUE_GAIN_PAR1 11722 #define NR4_MCNR_BLUE_GAIN_PAR0 11721 #define GE2D_TID_TOKEN 231 #define ABUF_RD_INT_POS_LSB 16 #define HEVC_PSCALE_BMEM_DAT 14624 #define HEVC_PARSER_VERSION 12544 #define P_MEDIA_CPU_PCR 4291883392 #define VDIN1_COM_STATUS3 5235 #define P_MC_OMDN_MB_XY 4284622108 #define VDIN1_COM_STATUS1 5126 #define VDIN1_COM_STATUS2 5134 #define VDIN1_COM_STATUS0 5125 #define P_PFIFO_RD_PTR 4291879324 #define SRSHARP1_DB_FLT_CTRL 13431 #define P_DET3D_MOTN_CFG 4287651024 #define P_HCODEC_POWER_CTL_VLD 4284641312 #define P_HEVC_MPRED_MV_WLCUY 4284663928 #define P_ANC22_CANVAS_ADDR 4284622488 #define VPU_DI_CHAN2_MMC_CTRL 9993 #define MCDI_MCVECWR_X 12178 #define MCDI_MCVECWR_Y 12179 #define AUDIN_FIFO2_PIO_STS 13494 #define HENC_LEFT_INFO_0 7480 #define HENC_LEFT_INFO_1 7482 #define AFBC_STAT 6890 #define P_AIU_958_CHSTAT_L1 4291842084 #define P_AIU_958_CHSTAT_L0 4291842080 #define HCODEC_VLC_MB_HEADER_INFO 7486 #define P_HCODEC_DBLK_STATUS 4284638540 #define VPU_ARB_PATH_CTRL 10169 #define P_ENCT_VIDEO_VSO_BLINE 4287656420 #define VDEC2_MC_MBBOT_ST_EVEN_ADDR 10564 #define P_VDEC2_VLD_TIME_STAMP_CNTL 4284657956 #define P_HEVC_SAO_VERSION 4284667904 #define P_HCODEC_ANC27_CANVAS_ADDR 4284638892 #define P_HCODEC_ANC26_CANVAS_ADDR 4284638888 #define DNR_RO_GBS_STAT_RR 11546 #define HEVC_DC_AC_SCALE_DIV 15879 #define P_MCDI_RO_MOTION_PARADOX_FLG 4287676088 #define P_VENC_ENCP_PIXEL 4287655344 #define P_AIU_958_CHSTAT_R1 4291842244 #define P_AIU_958_CHSTAT_R0 4291842240 #define HCODEC_VLC_VB_PRE_BUFF_HI 7452 #define VD1_BLEND_SRC_CTRL 7675 #define ENCP_VIDEO_VAVON_BLINE 7078 #define WM_MARK_RESOLUTION 12723 #define P_XVYCC_VD1_RGB_BRGHT 4287677892 #define DI_CONTPRD_Y 6052 #define DI_CONTPRD_X 6051 #define P_SANA_STREAM_LEVEL 4291870868 #define NR4_NM_SAD_THD 14101 #define P_AUDIN_INT_CTRL 4291875140 #define D2D3_DBG_CTRL 11043 #define P_VDEC2_LMEM_DMA_COUNT 4284648776 #define DNR_RO_GBS_STAT_LR 11544 #define P_VLD_MEM_VIFIFO_LEVEL 4284625180 #define EE_ASSIST_MBOX2_CLR_REG 8313 #define ENCP_VIDEO_MODE 7053 #define P_HCODEC_QDCT_INT_STATUS 4284644600 #define DNR_DB_VBS_MISC 11541 #define P_VPU_PROT3_CLK_GATE 4287667648 #define L_STV1_HE_ADDR 5160 #define VBO_STATUS_H 5236 #define P_PK_NR_ENABLE 4287678620 #define VBO_STATUS_L 5235 #define TCON_CONTROL_HI 5324 #define P_HEVC_MC_OTHER_GCLK_CTRL 4284671288 #define DNR_RO_GBS_STAT_LL 11545 #define XVYCC_POST_RGB_DLUT_4_7 12664 #define P_SANA_SHIFT_EMULATECODE 4291870884 #define P_HCODEC_CPSR 4284632196 #define P_QDCT_STATUS_CTRL 4284644352 #define P_AUDIN_FIFO1_PTR 4291875028 #define OSD_BLEND_GEN_CTRL0 6827 #define OSD_BLEND_GEN_CTRL1 6828 #define VDIN_LDIM_STTS_HIST_READ_REGION 4697 #define PARSER_VIDEO_HOLE 14468 #define LDIM_STTS_HIST_READ_REGION 6866 #define P_DBLK_Y_VFILT 4284622200 #define HEVC_MPRED_MV_RD_ROW_JUMP 12824 #define HCODEC_CBREAK0_REG 4916 #define P_D2D3_DRMIF_HPOS 4287671460 #define ENCT_VFIFO2VD_PIXEL_START 7201 #define HCODEC_VLC_INPUT_STATUS 7476 #define P_VPU_VLOCK_OUTPUT0_PLL_LMT 4287676456 #define P_PWM_DELTA_SIGMA_EF 4291923980 #define NR4_SNR_ALPHA1_MAX_MIN 11696 #define L_CPV2_HE_ADDR 5156 #define TCON_CONTROL_LO 5325 #define L_OEV3_HS_ADDR 5175 #define VDEC2_MDB_DATA_REG 8988 #define HEVC_RV_AI_Y_X 15881 #define P_PARSER_AV_WRAP_COUNT 4291879492 #define VPP_BLEND_VD2_H_START_END 7454 #define P_D2D3_DWMIF_HPOS 4287671444 #define P_HEVCD_MPP_YLOG2WGHTDENOM_ADDR 4284666360 #define P_AIU_AUDIO_AMP_REG3 4291842300 #define P_AIU_AUDIO_AMP_REG2 4291842296 #define P_AIU_AUDIO_AMP_REG1 4291842292 #define P_AIU_AUDIO_AMP_REG0 4291842288 #define P_PWM_DELTA_SIGMA_CD 4291928076 #define P_DNR_DB_HBS 4287673400 #define AIU_MEM_I2S_RD_PTR 5217 #define P_AUDIN_FIFO2_RDPTR 4291875108 #define DI_CHAN2_GEN_REG 6133 #define HCODEC_IE_C_PRED_MODE 8007 #define P_HCODEC_DBLK_CB_FILT 4284638588 #define VDEC2_DBLK_CMD_CTRL 10580 #define P_HEVC_PSCALE_MCMD_CTRL 4284671112 #define DI_IF2_FMT_W 8224 #define AIU_HDMI_CLK_DATA_CTRL 5162 #define HCODEC_VLC_SPECIAL_CTL 7458 #define VDEC2_RV_AI_MB_COUNT 11788 #define VPP2_PREBLEND_H_SIZE 6432 #define AIU_I2S_MUTE_SWAP 5132 #define P_AIU_MEM_AIFIFO2_MAN_WP 4291842492 #define P_AUDIN_SPDIF_END 4291874876 #define HCODEC_VLD_C3D 7229 #define P_XVYCC_VADJ1_CURV_0 4287677848 #define HEVC_MMIN_REG 13074 #define P_XVYCC_VADJ1_CURV_2 4287677856 #define P_XVYCC_VADJ1_CURV_1 4287677852 #define HCODEC_VLD_C38 7224 #define HCODEC_VLD_C39 7225 #define AC3_RESET 256 #define P_VDEC_ASSIST_TIMER0_HI 4284612996 #define P_MCDI_REL_DET_COL_CFD_THD 4287675656 #define P_HCODEC_TOP_LEFT_READY 4284642632 #define P_XVYCC_INV_LUT_CTL 4287677840 #define HCODEC_DBLK_CBPC_ADJ 6515 #define P_NR4_TOP_CTRL 4287674364 #define P_AUDOUT_CTRL 4291875328 #define P_HCODEC_VLD_STATUS_CTRL 4284641280 #define P_NR_ALP0_MIN_MAX 4287678564 #define VLC_STREAM_BUFF 7454 #define P_MCDI_RPTMV_SAD 4287675460 #define AUDIN_FIFO0_START 13344 #define P_ENCI_TST_EN 4287656000 #define P_VPU_VLOCK_STBDET_WIN0_WIN1 4287676508 #define VDEC_ASSIST_AMR2_INT0 53 #define VDEC_ASSIST_AMR2_INT1 54 #define NR4_MCNR_LUMA_ENH_CTRL 11704 #define VDEC_ASSIST_AMR2_INT2 55 #define P_DECOMB_HV_BLANK 4287673920 #define VDEC_ASSIST_AMR2_INTA 63 #define VDEC_ASSIST_AMR2_INTB 64 #define VDEC_ASSIST_AMR2_INT3 56 #define VDEC_ASSIST_AMR2_INT4 57 #define VDEC_ASSIST_AMR2_INT5 58 #define VDEC_ASSIST_AMR2_INT6 59 #define HCODEC_VLC_VB_PRE_BUFF_LOW 7453 #define VDEC_ASSIST_AMR2_INT7 60 #define VDEC_ASSIST_AMR2_INT8 61 #define VDEC_ASSIST_AMR2_INT9 62 #define P_HCODEC_DBLK_CBUS_HCMD2 4284638684 #define P_HCODEC_DBLK_CBUS_HCMD0 4284638692 #define P_VPP2_OSD_SC_CTRL0 4287653664 #define P_HCODEC_DBLK_CBUS_HCMD1 4284638688 #define P_AIU_MEM_IEC958_BUF_CNTL 4291842556 #define P_VLC_DC_RD_REQ 4284642580 #define HCODEC_MFDIN_REG7_SCMD 4111 #define VDEC_ASSIST_AMR2_INTC 65 #define VDEC_ASSIST_AMR2_INTD 66 #define VDEC_ASSIST_AMR2_INTE 67 #define VDEC_ASSIST_AMR2_INTF 68 #define P_ENCI_TST_CB 4287656012 #define PSCALE_PICO_START_X 2326 #define PSCALE_PICO_START_Y 2327 #define MIPI_DSI_TOP_CLK_CNTL 7409 #define NR4_SNR_ALPHA0_MAX_MIN 11690 #define P_ENCI_TST_CR 4287656016 #define VPP2_VADJ_CTRL 6464 #define RDMA_SRAM_CNTL 4384 #define P_MC_MPORT_CTRL 4284622080 #define HCODEC_ANC19_CANVAS_ADDR 6563 #define P_ENCP_VIDEO_SY_VAL 4287655616 #define AV_SCRATCH_M 2518 #define AV_SCRATCH_N 2519 #define AV_SCRATCH_K 2516 #define AV_SCRATCH_L 2517 #define AV_SCRATCH_I 2514 #define AV_SCRATCH_J 2515 #define AV_SCRATCH_G 2512 #define AV_SCRATCH_H 2513 #define AV_SCRATCH_E 2510 #define AV_SCRATCH_F 2511 #define P_VIU2_VD1_IF0_LUMA1_RPT_PAT 4287658360 #define AV_SCRATCH_C 2508 #define AV_SCRATCH_D 2509 #define AV_SCRATCH_A 2506 #define AV_SCRATCH_B 2507 #define AV_SCRATCH_9 2505 #define AV_SCRATCH_7 2503 #define AV_SCRATCH_8 2504 #define AV_SCRATCH_5 2501 #define AV_SCRATCH_6 2502 #define AV_SCRATCH_3 2499 #define AV_SCRATCH_4 2500 #define AV_SCRATCH_1 2497 #define AV_SCRATCH_2 2498 #define AV_SCRATCH_0 2496 #define P_HCODEC_WRRSP_CO_MB 4284639072 #define VDIN_LCNT_STATUS 4612 #define ISA_TIMER_MUX 15440 #define P_VD2_IF0_RPT_LOOP 4287654380 #define P_HCODEC_CPC_P 4284632216 #define VIU_OSD1_EOTF_COEF00_01 6869 #define SPICC0_INTREG 19459 #define P_OSD_DB_FLT_CTRL 4287677696 #define P_HCODEC_CPC_W 4284632228 #define QDCT_DBG_READ 7972 #define VI_HIST_SPL_VAL 11780 #define P_GE2D_DST_Y_START_END 4287890140 #define C656_FS_LNST 7142 #define P_ENCL_VIDEO_Y_OFFST 4287656592 #define P_ENCL_VIDEO_VAVON_BLINE 4287656656 #define ANC12_CANVAS_ADDR 2460 #define P_VIU2_OSD2_HL1_V_START_END 4287658192 #define P_DI_INP_RANGE_MAP_CB 4287651564 #define HCODEC_POWER_CTL_IQIDCT 7688 #define VPP2_OSD_SCALE_COEF_IDX 6604 #define UART2_STATUS 34819 #define P_XVYCC_VADJ1_CURV_3 4287677860 #define P_DI_INP_RANGE_MAP_CR 4287651568 #define P_HCODEC_CPC_D 4284632220 #define P_IMEM_DMA_CTRL 4284615936 #define P_HCODEC_CPC_E 4284632224 #define P_ENCP_VIDEO_Y_OFFST 4287655456 #define HCODEC_MC_CTRL_REG 6400 #define DNR_DM_LDIF_LUT6_8 11634 #define P_VPP_MATRIX_HL_COLOR 4287657332 #define P_VDEC_ASSIST_TIMER0_LO 4284612992 #define SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 12908 #define P_MCDI_RO_FLD_BAD_BADW_CNT 4287676048 #define DC_CAV_LUT_ADDR 80 #define VDEC2_DBLK_BETAX_QP_SEL 10593 #define P_VPP2_PREBLEND_VD1_V_START_END 4287652972 #define HEVC_MPRED_AXI_WCTRL 12816 #define HCODEC_QDCT_I_PRED_REF_WR_DATA 7987 #define P_HCODEC_MFDIN_REG0E 4284629080 #define P_HCODEC_MFDIN_REG0F 4284629084 #define P_M4_CONTROL_REG 4284625060 #define P_MCDI_REL_DET_RPT_CHK_ROW 4287675596 #define MCDI_REF_BADW_SUM_GAIN 12057 #define P_HCODEC_MFDIN_REG0D 4284629076 #define VDEC2_ASSIST_MBX_SSEL 8261 #define P_LCD_MCU_DATA_0 4287648632 #define P_LCD_MCU_DATA_1 4287648636 #define P_GE2D_SRC1_LUT_ADDR 4287890096 #define P_VDEC2_DBLK_AVSFLAGS 4284655032 #define P_NR4_MCNR_MV_GAIN0 4287674108 #define VLD_RESET 2 #define P_HEVC_ANC23_CANVAS_ADDR 4284671644 #define L_STV2_HE_ADDR 5164 #define AO_CPU_IRQ_IN0_INTR_STAT 15376 #define P_VIU_OSD1_OETF_3X3_OFST_0 4287654528 #define V4_FORCE_SKIP_CFG 8059 #define P_VIU_OSD1_OETF_3X3_OFST_1 4287654532 #define NR2_MATNR_SNR_USF_GAIN 5974 #define SRSHARP0_SR3_DERING_GAINVS_MADSAD 12912 #define RV_AI_V_X 3595 #define VPP_WRAP_OSD2_MATRIX_EN_CTRL 15741 #define AO_CPU_IRQ_IN0_INTR_MASK 15378 #define P_L_VCOM_HSWITCH_ADDR 4287647856 #define VKS_LBUF_SIZE 12555 #define P_VPU_BT656_MMC_CTRL 4287667260 #define P_HEVC_SAO_MMU_VH0_ADDR 4284668136 #define P_VPU_VLOCK_OUTPUT1_PLL_LMT 4287676464 #define HCODEC_MDB_ADDR_REG 4891 #define P_VDIN_WIN_V_START_END 4287646136 #define DOLBY_TV_REG_START 13056 #define P_ENCI_SYNC_VSO_ODD 4287654964 #define C_D_BUS_CONTROL 11266 #define P_L_CPV1_HE_ADDR 4287647872 #define P_VDIN_MATRIX_COEF22 4287645780 #define P_ENCT_VIDEO_MAX_PXCNT 4287656384 #define AIU_958_DCU_FF_CTRL 5127 #define HCODEC_MDEC_PIC_DC_CTRL 6542 #define HEVC_DBKR_CANVAS_ADDR 14768 #define HCODEC_VC1_CONTROL_REG 7198 #define P_ME_SAD_0 4284644740 #define P_ME_SAD_3 4284644752 #define P_DET3D_RO_MAT_CHRU_TB 4287651352 #define P_ME_SAD_1 4284644744 #define P_ME_SAD_2 4284644748 #define HCODEC_DBLK_STRONG 6517 #define P_VDEC2_ANC15_CANVAS_ADDR 4284655228 #define RESET5_REGISTER 1030 #define P_HCODEC_PSCALE_PICI_H 4284638284 #define P_HCODEC_ME_CONTROL 4284644644 #define P_HCODEC_PSCALE_PICI_W 4284638280 #define AUDIN_FIFO0_HOLD1_SEL 24 #define VP9_LEFT_Y_MODE_1 12613 #define VP9_LEFT_Y_MODE_0 12612 #define P_HEVC_RV_AI_Y_X 4284676132 #define MIPI_DSI_TOP_SW_RESET 7408 #define P_GE2D_VSC_NRND_PHASE 4287890184 #define P_DI_IF2_RANGE_MAP_Y 4287660140 #define P_HCODEC_VLD_TIME_STAMP_CNTL 4284641572 #define ENCI_VIDEO_SCH 6919 #define P_HEVCD_IPP_TOP_FRMCONFIG 4284665864 #define MCDI_REL_DET_LPF_MSK_00_03 12088 #define RESET0_REGISTER 1025 #define L_VSYNC_VE_ADDR 5212 #define P_VIU2_OSD2_HL2_H_START_END 4287658196 #define SRSHARP0_SHARP_HVBLANK_NUM 12801 #define P_VDEC2_IQ_QUANT 4284659804 #define OEV2_HS_ADDR 5299 #define VDIN_MATRIX_CTRL 4624 #define P_DET3D_RO_MAT_CHRU_LR 4287651348 #define I2C_M_1_RDATA_REG1 30727 #define I2C_M_1_RDATA_REG0 30726 #define PSCALE_BMEM_DAT 2336 #define P_VPP2_DUMMY_DATA1 4287653284 #define HCODEC_VLD_TIME_STAMP_0 7244 #define HCODEC_VLD_TIME_STAMP_1 7245 #define HCODEC_VLD_TIME_STAMP_2 7246 #define HCODEC_VLD_TIME_STAMP_3 7247 #define VDEC2_CPU_TRACE 9088 #define CINDEX4_REG 814 #define P_HEVC_MBREAK0_REG 4284664912 #define P_HCODEC_MFDIN_REG16 4284629112 #define P_HCODEC_MFDIN_REG12 4284629096 #define AUDIN_FIFO2_PIO_RDL 13495 #define P_HCODEC_MFDIN_REG13 4284629100 #define P_HCODEC_MFDIN_REG14 4284629104 #define P_HCODEC_MFDIN_REG15 4284629108 #define P_VDEC2_DBLK_Y_BHFILT 4284654940 #define AUDIN_FIFO2_PIO_RDH 13496 #define P_VENC_VDAC_DAC0_OFFSET 4287655876 #define P_HCODEC_MFDIN_REG10 4284629088 #define P_HCODEC_MFDIN_REG11 4284629092 #define P_ENCL_VFIFO2VD_LINE_BOT_END 4287656536 #define P_HCODEC_IQIDCT_CONTROL 4284643384 #define ENCI_VIDEO_SAT 6917 #define P_VPU_VLOCK_RO_LINE_PIX_ADJ 4287676492 #define VPU_VLOCK_GCLK_EN 12318 #define VPP2_VDO_MEAS_CTRL 6568 #define LDIM_STTS_CTRL0 6849 #define MCDI_BI_MVDST 12038 #define P_VPP_HSHARP_CHROMA_THRESH01 4287657292 #define P_UART1_MISC 4291964944 #define ENCP_VFIFO2VD_PIXEL_START 7001 #define P_VD1_IF0_CHROMA_PSEL 4287654276 #define SPICC1_PERIODREG 21510 #define CSP 800 #define DITH10_EN 10 #define P_HCODEC_PRE_START_CODE 4284641324 #define HEVC_SAO_ABV_RPTR 13845 #define P_PWM_DELTA_SIGMA_AB 4291932172 #define P_VLTI_BST_CORE 4287678704 #define P_VPU_WRARB_WEIGH0_SLV_L2C1 4287667856 #define MLVDS_DUAL_GATE_CTL_LO 5372 #define P_VIU_OSD1_EOTF_LUT_ADDR_PORT 4287654760 #define P_VPP_HSHARP_CHROMA_THRESH23 4287657296 #define P_MSP 4284615680 #define L_CPV2_HS_ADDR 5155 #define P_VENC_INTFLAG 4287655356 #define VPP2_SMOKE2_VAL 6443 #define P_SPICC1_TXDATA 4291907588 #define P_VPP2_GAINOFF_CTRL0 4287653288 #define P_VPP2_GAINOFF_CTRL1 4287653292 #define P_MCDI_RO_FLD_MTN_CNT 4287676056 #define HCODEC_CURR_CANVAS_CTRL 6579 #define P_VPP2_GAINOFF_CTRL2 4287653296 #define P_HEVC_MC_WT_PRED_CTRL 4284671240 #define P_VPP2_GAINOFF_CTRL3 4287653300 #define P_VPP2_GAINOFF_CTRL4 4287653304 #define RAM_TEST_RD_CMD 0 #define VDEC2_GCLK_EN 10627 #define VPU_ASYNC_WR_MODE1 10155 #define VPU_ASYNC_WR_MODE0 10154 #define VPU_ASYNC_WR_MODE2 10156 #define DITH8_EN 9 #define VDEC2_ASSIST_MBOX0_CLR_REG 8305 #define AIU_MEM_I2S_MAN_RP 5236 #define SRSHARP1_NR_ALP1_ERR2CURV_TH_RATE 13339 #define VPP_WRAP_OSD1_MATRIX_COEF23_24 15718 #define MC_DPDN_MB_XY 2374 #define P_VDEC2_DBLK_CLIP_CTRL5 4284655004 #define P_VDEC2_DBLK_CLIP_CTRL4 4284655000 #define P_HEVCD_IPP_SWMPREDIF_CONFIG 4284665920 #define P_VDEC2_DBLK_CLIP_CTRL7 4284655012 #define mLVDS_reset_start 0 #define P_MCDI_MCINFOWR_CANVAS_SIZE 4287675804 #define P_VDEC2_DBLK_CLIP_CTRL6 4284655008 #define P_VDEC2_DBLK_CLIP_CTRL8 4284655016 #define P_VIU_OSD1_COLOR 4287653960 #define ENCP_DBG_LN_RST 7057 #define VPP2_LINE_IN_LENGTH 6401 #define P_D2D3_DGEN_WIN_HOR 4287671308 #define P_VDEC2_DBLK_CLIP_CTRL1 4284654988 #define P_VDEC2_DBLK_CLIP_CTRL0 4284654984 #define P_ENCP_VIDEO_VAVON_ELINE 4287655612 #define P_VDEC2_DBLK_CLIP_CTRL3 4284654996 #define P_VDEC2_DBLK_CLIP_CTRL2 4284654992 #define SPI_FLASH_CMD 20480 #define HCODEC_ME_WEIGHT 8032 #define MLVDS_DUAL_GATE_CTL_HI 5371 #define CCPU_INTR_GRP 803 #define ENCP_DE_H_BEGIN 7226 #define SMARTCARD_INTR 37892 #define DECODER_BUFFER_INFO 3087 #define SRSHARP1_VLTI_CON_2_GAIN_1 13374 #define SRSHARP1_VLTI_CON_2_GAIN_0 13373 #define NR_ALP0Y_ERR2CURV_LIMIT 12822 #define P_CPSR 4284615812 #define VPP_WRAP_OSD1_MATRIX_COEF11_12 15714 #define MIPI_DSI_DWC_PHY_RSTZ_OS 7208 #define P_L_POL_CNTL_ADDR 4287647772 #define HEVC_PSCALE_PICO_W 14612 #define PARSER_VIDEO2_END_PTR 14484 #define OSD1_AFBCD_FRAME_PTR 12708 #define HEVC_PSCALE_PICO_H 14613 #define VDEC2_ASSIST_MBOX2_CLR_REG 8313 #define HCODEC_ASSIST_DMA_INT_MSK2 4199 #define VDEC2_PMV3_Y 11301 #define VDEC2_PMV3_X 11300 #define P_AUDOUT_FIFO_PIO_WRL 4291875560 #define P_VPP2_CHROMA_DATA_PORT 4287653316 #define P_HCODEC_MBBOT_ODD_ADDR 4284644576 #define P_HEVC_WRRSP_VLD 4284671848 #define P_VIU2_OSD1_CTRL_STAT 4287658176 #define HEVCD_IPP_AXIIF_CONFIG 13323 #define P_AUDOUT_FIFO_PIO_WRH 4291875564 #define P_HEVC_MC_CTRL2 4284671292 #define P_HEVC_MPRED_L0_REF06_POC 4284663960 #define VIU_OSD1_COLOR 6674 #define HUE_HUE_RANGE_REG06 37 #define HUE_HUE_RANGE_REG07 43 #define HUE_HUE_RANGE_REG04 25 #define ENCI_SYNC_ADJ 6930 #define HUE_HUE_RANGE_REG05 31 #define HUE_HUE_RANGE_REG02 13 #define HSYNC_VE_ADDR 5336 #define HUE_HUE_RANGE_REG03 19 #define HUE_HUE_RANGE_REG00 1 #define HUE_HUE_RANGE_REG01 7 #define P_SHARP_SR3_DERING_LUMA2PKOS_0TO3 4287678904 #define P_GAMMA_ADDR_PORT 4287648264 #define MDEC_PICW_BUF_STATUS 2490 #define HCODEC_MINDEX3_REG 4877 #define EE_ASSIST_MBOX1_CLR_REG 8309 #define ENCP_MACV_TS_CNT_MAX_L 7113 #define P_VDIN_CHROMA_DATA_PORT 4287645872 #define ENCP_MACV_TS_CNT_MAX_H 7114 #define VLC_VB_RD_PTR 7443 #define P_HCODEC_LMEM_DMA_ADR 4284632388 #define HCODEC_MDB_CTRL 4893 #define SRSHARP1_PK_CON_2CIRBPGAIN_LIMIT 13320 #define MCDI_CTRL_MODE 12036 #define P_ENCT_TST_CLRBAR_STRT 4287656116 #define P_AIU_MEM_AIFIFO_START_PTR 4291842576 #define P_MCDI_MCVECRD_CTRL 4287675996 #define VPP_OFIFO_SIZE 7463 #define MCDI_LMV_LOCK_ROW 12107 #define L_GAMMA_CNTL_PORT 5120 #define P_HEVC_MC_CTRL0 4284671004 #define P_HEVC_MC_CTRL1 4284671020 #define P_I2C_M_0_SLAVE_ADDR 4291948548 #define DI_IF1_FMT_CTRL 6131 #define VLC_HCMD_MBXY_AUTO 7462 #define VPU_VLOCK_LOOP0_ACCUM_LMT 12290 #define HEVC_WRRSP_DCAC 14809 #define VDIN1_WIDTHM1I_WIDTHM1O 5130 #define C656_VS_LNST_O 7139 #define COMM_DESC_KEY1 6390 #define COMM_DESC_KEY0 6389 #define P_VDIN_MATRIX_PRE_OFFSET0_1 4287645792 #define VD1_IF0_RANGE_MAP_CB 6763 #define C656_VS_LNST_E 7138 #define VPP_POST2_MATRIX_PRE_OFFSET0_1 14763 #define HEVC_MPRED_MV_RPTR 12822 #define P_ANC19_CANVAS_ADDR 4284622476 #define P_VSYNC_VS_ADDR 4287648620 #define VD2_AFBC_VD_CFMT_H 12689 #define P_SPICC0_LD_WADDR 4291899444 #define P_SHARP_SR3_PK_CTRL1 4287678860 #define P_SHARP_SR3_PK_CTRL0 4287678856 #define VD2_AFBC_VD_CFMT_W 12684 #define VD1_IF0_RANGE_MAP_CR 6764 #define P_VDEC2_PSCALE_CMD_CTRL 4284654700 #define P_HCODEC_MFDIN_REGB_AMPC 4284629068 #define P_ENCL_VIDEO_HAVON_END 4287656644 #define P_DOS_HEVC_INT_EN 4284677336 #define STV2_HE_ADDR 5292 #define VDEC2_ACC0REG2 9073 #define VDEC2_ACC0REG1 9057 #define VPP_OSDSC_DITHER_LUT_11 12603 #define VPP_OSDSC_DITHER_LUT_10 12602 #define VPP_OSDSC_DITHER_LUT_13 12605 #define VPP_OSDSC_DITHER_LUT_12 12604 #define VPP_OSDSC_DITHER_LUT_15 12607 #define VPP_OSDSC_DITHER_LUT_14 12606 #define HCODEC_AVSP_IQ_CTL 7708 #define AUDIN_FIFO1_PIO_RDL 13492 #define AUDIN_FIFO1_PIO_RDH 13493 #define P_RDMA_AHB_START_ADDR_7 4287644728 #define HCODEC_PSCALE_SRCKEY_CTRL0 6442 #define GE2D_SRC1_LUT_DAT 173 #define HCODEC_PSCALE_SRCKEY_CTRL1 6443 #define P_VLC_HCMD_CONFIG 4284642640 #define VP9D_MPP_INTERPOL_CFG0 13376 #define P_RDMA_AHB_START_ADDR_2 4287644688 #define P_RDMA_AHB_START_ADDR_1 4287644680 #define P_RDMA_AHB_START_ADDR_4 4287644704 #define P_RDMA_AHB_START_ADDR_3 4287644696 #define P_RDMA_AHB_START_ADDR_6 4287644720 #define P_RDMA_AHB_START_ADDR_5 4287644712 #define P_HCODEC_MCW_DBLK_WRRSP_CNT 4284638956 #define P_AIU_RST_SOFT 4291842132 #define OEV1_HS_ADDR 5295 #define mLVDS2_reset_1_select 12 #define VDEC2_IQIDCT_DEBUG_IDCT 11793 #define ENCP_MACV_STRTLINE 7111 #define P_VDEC2_VLD_MEM_VIFIFO_CONTROL 4284657936 #define HEVC_MC_MBBOT_WRRSP_CNT 14780 #define HCODEC_ANC22_CANVAS_ADDR 6566 #define P_VPP2_PREBLEND_CURRENT_XY 4287653008 #define P_LDIM_STTS_MATRIX_HL_COLOR 4287654704 #define DITH_CNTL_ADDR 5256 #define SRSHARP1_NR_ALP0C_ERR2CURV_LIMIT 13336 #define HCODEC_VLC_MB_INFO 7477 #define P_ENCI_TST_CLRBAR_STRT 4287656020 #define ENCP_DVI_VSO_BEGIN_EVN 7222 #define P_XVYCC_LUT_R_ADDR_PORT 4287677816 #define P_SMARTCARD_INTR 4291973136 #define P_NR2_MATNR_MTN_CRTL2 4287651244 #define HEVC_VLD_MEM_VBUF2_RD_PTR 15444 #define P_VDEC2_ANC8_CANVAS_ADDR 4284655200 #define AUDIN_FIFO2_PTR 13383 #define NR4_MCNR_CM_RSHFT_ALP0 11719 #define P_VDEC2_DBLK_VHMVD 4284655056 #define P_MCDI_REL_DET_LPF_DIF_THD 4287675612 #define VDIN1_WR_V_START_END 5154 #define VDIN_HIST_MAX_MIN 4659 #define CPV2_HS_ADDR 5283 #define P_VPP_MATRIX_COEF13_14 4287657836 #define VIU_OSD2_MATRIX_COEF00_01 6833 #define tcon_pattern_enable 0 #define ENCL_VIDEO_HSO_END 7350 #define SRSHARP1_DEMO_CRTL 13398 #define P_VPP2_MATRIX_CTRL 4287653244 #define P_CBREAK_CTRL 4284615908 #define P_VPP2_PIC_IN_HEIGHT 4287652872 #define P_L_STV1_VS_ADDR 4287647908 #define mLVDS2_MLSB_SWAP 2 #define VLC_JPEG_CTRL 7512 #define ENCL_VIDEO_VOFFST 7360 #define RV_AI_U_X 3594 #define P_HEVC_AVSP_IQ_WQ_PARAM_01 4284676196 #define mLVDS_reset_1_select 12 #define MCDI_RPTMV_SAD 12049 #define DOS_VDEC_MCRCC_STALL_CTRL 16192 #define ENCT_VIDEO_MATRIX_CB 7301 #define VENC_VIDEO_TST_CLRBAR_WIDTH 7030 #define ME_MV_MERGE_CTL 8021 #define I2SIN_POS_SYNC 3 #define P_VDEC2_IMEM_DMA_CTRL 4284648704 #define DET3D_RO_FRM_MOTN 6031 #define VPU_422TO444_RST 10058 #define P_PK_CON_2CIRHPGAIN_LIMIT 4287678488 #define HEVC_MINT_VEC_BASE 13058 #define AIFIFO2_TIME_STAMP_CNTL 5272 #define P_HEVC_AVSP_IQ_WQ_PARAM_23 4284676200 #define ENCT_VIDEO_MATRIX_CR 7302 #define AIU_MEM_I2S_MAN_WP 5235 #define HEVC_STREAM_CONTROL 12545 #define VDIN0_MATRIX_PRE_OFFSET0_1 4632 #define P_GE2D_MATRIX_COEF02_10 4287890204 #define ENCP_VIDEO_HSPULS_END 7065 #define P_RDMA_SRAM_CNTL 4287644800 #define P_DOS_VDEC2_MCRCC_STALL_CTRL 4284677380 #define VIU2_OSD1_MATRIX_OFFSET2 7802 #define HEVC_ANC1_CANVAS_ADDR 14737 #define EE_ASSIST_MBOX0_CLR_REG 8305 #define P_AUDIN_FIFO1_LVL0 4291875072 #define P_AUDIN_FIFO1_LVL2 4291875080 #define P_AUDIN_FIFO1_LVL1 4291875076 #define PWM_D2 26630 #define VDEC2_PMV4_Y 11303 #define VDEC2_PMV4_X 11302 #define P_HCODEC_DBLK_Y_BVFILT 4284638564 #define AUDIN_FIFO1_WRAP 13380 #define AUDIN_FIFO0_PIO_STS 13488 #define VLC_P_MB_HEADER_INFO 7487 #define P_VPU_VLOCK_STBDET_SGN_WIN1 4287676528 #define HEVC_PARSER_DEBUG_IDX 12606 #define P_VPU_VLOCK_STBDET_SGN_WIN0 4287676524 #define PWM_C2 26629 #define LVDS_REPACK 0 #define ENCL_VFIFO2VD_PIXEL_START 7313 #define PWM_F2 25606 #define P_DI_MEM_FMT_W 4287651740 #define DNR_DM_DIF2NORM_LUT6_8 11637 #define ME_SKIP_LINE 8013 #define MCDI_REL_DET_MIN 12093 #define VDIN_SC_MISC_CTRL 4619 #define PWM_E2 25605 #define P_HCODEC_DBLK_OST_YBASE 4284638708 #define P_L_OEV3_HS_ADDR 4287647964 #define QDCT_JPEG_X_START_END 7974 #define P_HCODEC_VLD_C38 4284641504 #define P_HCODEC_VLD_C39 4284641508 #define ADR_RDY 5 #define P_QDCT_MB_LEVEL 4284644432 #define P_VDEC2_PSCALE_MCMD_XSIZE 4284654732 #define HCODEC_ASSIST_DMA_INT_MSK 4197 #define WRRSP_CO_MB 2520 #define L_OEV1_HS_ADDR 5167 #define P_DBLK_Y_BHFILT 4284622172 #define PWM_B2 27654 #define CMAX_REG 819 #define L_LCD_MCU_CTL 5213 #define L_LCD_PWM1_LO_ADDR 5182 #define AIU_MEM_AIFIFO2_CONTROL 5230 #define VPP_POST2_MATRIX_COEF00_01 14752 #define P_GPIO_INTR_EDGE_POL 4291883136 #define PWM_A2 27653 #define QM_WEN 2 #define P_VIU2_VD1_IF0_RPT_LOOP 4287658348 #define P_HCODEC_VLD_C3D 4284641524 #define ME_DEBUG 8012 #define VPP_WRAP_OSD2_MATRIX_COEF02_10 15729 #define P_VPP_VE_DITHER_CTRL 4287677568 #define P_LDIM_STTS_HIST_START_RD_REGION 4287654732 #define P_DET3D_RO_DET_CB_HOR 4287651060 #define VDEC2_ASSIST_MBOX1_CLR_REG 8309 #define V3_LEFT_MV 8047 #define DVIN_HS_LEAD_VS_ODD 2273 #define P_HCODEC_HENC_TOP_INFO_0 4284642524 #define P_HCODEC_HENC_TOP_INFO_1 4284642532 #define P_VDIN_MATRIX_OFFSET2 4287645788 #define P_HEVC_NON_I_QUANT_MATRIX 4284676108 #define P_HEVC_MC_HALF_PEL_ONE 4284670988 #define mLVDS2_data_latch_0_ini 13 #define P_VPP2_VADJ_CTRL 4287653120 #define HDEC_MC_MBRIGHT_RD 2354 #define P_VENC_ENCI_PIXEL 4287655336 #define AIU_AMCLK_GATE_LO 5201 #define VIU2_VD1_IF0_LUMA_PSEL 7776 #define AUDIO_PTS_WR_PTR 14454 #define HCODEC_CINDEX5_REG 4911 #define P_LBUF_TOP_CTRL 4287676412 #define P_GE2D_MATRIX_COEF20_21 4287890212 #define P_ABUF_WR_CTL3 4291883468 #define P_ABUF_WR_CTL1 4291883460 #define P_ABUF_WR_CTL2 4291883464 #define SPDIF_BURST_PRE_INT_EN 29 #define P_VPP_BLEND_VD2_H_START_END 4287657080 #define P_ABUF_WR_CTL0 4291883456 #define P_HEVC_PSCALE_CTRL 4284671044 #define P_HEVC_ANC22_CANVAS_ADDR 4284671640 #define ME_STATUS 8011 #define DI_MTNWR_CTRL 6085 #define D2D3_DGEN_WIN_HOR 11011 #define P_VPP2_MATRIX_COEF00_01 4287653248 #define P_RESET7_MASK 4291825760 #define VD2_IF0_LUMA_X1 6775 #define P_HCODEC_IMEM_DMA_ADR 4284632324 #define VD2_IF0_LUMA_X0 6771 #define P_MCDI_REL_DET_LUT_0_3 4287675640 #define DI_INP_FMT_CTRL 6105 #define P_VIU2_VD1_FMT_W 4287658404 #define HCODEC_ME_SAD_RANGE_INC 8024 #define DI_IF2_CANVAS0 8209 #define HCODEC_V3_IPRED_TYPE_WEIGHT_0 8056 #define HCODEC_V3_IPRED_TYPE_WEIGHT_1 8057 #define P_RESET7_REGISTER 4291825696 #define MC_DP_MB_XY 2318 #define I2C_M_3_SLAVE_ADDR 28673 #define P_AIU_MEM_AIFIFO2_LEVEL 4291842500 #define P_D2D3_CBDG_STATUS_2 4287671536 #define P_MC_WT_PRED_CTRL 4284622088 #define VDEC2_ANC10_CANVAS_ADDR 10650 #define P_D2D3_CBDG_STATUS_1 4287671488 #define P_SPICC1_DWADDR 4291907620 #define P_VLC_IPRED_MODE_LO 4284642544 #define I2C_M_DATA_CNT_MSB 11 #define P_DI_MTNWR_CTRL 4287651604 #define P_PWM_MISC_REG_CD 4291928072 #define P_HCODEC_SCD_FOR_MV_Y 4284641356 #define MLVDS_CLK_CTL1_LO 5188 #define P_HCODEC_SCD_FOR_MV_X 4284641352 #define VPP_BLEND_ONECOLOR_CTRL 7459 #define VLD_MEM_SWAP_ADDR 3157 #define HEVC_DBLK_RST 14672 #define P_VPP_MATRIX_PROBE_COLOR 4287657328 #define P_PWM_MISC_REG_EF 4291923976 #define VD2_IF0_LUMA_Y1 6776 #define VD2_IF0_LUMA_Y0 6772 #define P_HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL 4284641548 #define P_HCODEC_CBREAK2_REG 4284632280 #define P_VPP_VE_ENABLE_CTRL 4287657604 #define HCODEC_AV_SCRATCH_4 6596 #define P_DI_IF2_GEN_REG3 4287660168 #define HCODEC_AV_SCRATCH_5 6597 #define P_DI_IF2_GEN_REG2 4287660152 #define HCODEC_AV_SCRATCH_2 6594 #define HCODEC_AV_SCRATCH_3 6595 #define HCODEC_AV_SCRATCH_8 6600 #define VDEC2_ANC21_CANVAS_ADDR 10661 #define HCODEC_V3_L2_SKIP_WEIGHT 8050 #define HCODEC_AV_SCRATCH_9 6601 #define HCODEC_AV_SCRATCH_6 6598 #define HCODEC_AV_SCRATCH_7 6599 #define HCODEC_AV_SCRATCH_A 6602 #define P_STREAM_WAIT_IRQ_CONFIG 4291866648 #define HCODEC_IQIDCT_DEBUG_IDCT 7697 #define MCDI_GMV_LOCK_CNT_THD_GAIN 12109 #define P_VLC_IPRED_MODE_HI 4284642540 #define P_HEVC_SCD_BAK_MV_X 4284674136 #define P_HEVC_SCD_BAK_MV_Y 4284674140 #define HCODEC_AV_SCRATCH_0 6592 #define HCODEC_AV_SCRATCH_1 6593 #define MCW_DBLK_WRRSP_CNT 2491 #define NR2_MET_NMFRM_TNR_CCNT 5964 #define P_HEVC_DBLK_RST 4284671296 #define P_HEVC_MPRED_MV_RD_ROW_JUMP 4284663904 #define HEVC_SLICE_START_BYTE_23 15373 #define P_HCODEC_V3_LEFT_INTRA_INFO 4284644828 #define ENCT_VIDEO_EN 7264 #define MLVDS_CLK_CTL1_HI 5187 #define P_ENCT_VIDEO_FILT_CTRL 4287656456 #define SPICC1_DWADDR 21513 #define P_MDEC_PICR_BUF_STATUS 4284622564 #define DE_VE_ADDR 5332 #define P_ENCL_TST_VDCNT_STSET 4287656572 #define NR2_MET_NMFRM_TNR_YCNT 5962 #define P_PWM_MISC_REG_AB 4291932168 #define HEVC_SLICE_START_BYTE_01 15372 #define VIU_OSD_BLEND_DIN2_SCOPE_V 14774 #define LBUF_TOP_CTRL 12287 #define VIU_OSD_BLEND_DIN2_SCOPE_H 14773 #define VD2_IF0_RANGE_MAP_Y 6794 #define P_VDEC2_ASSIST_MBOX2_CLR_REG 4284645860 #define P_V3_LEFT_MV 4284644796 #define P_ENCP_MACV_STRTLINE 4287655708 #define ENCP_VIDEO_VSPULS_END 7068 #define P_ENCI_VBI_WSSDT 4287655060 #define P_ENCT_VIDEO_EN 4287656320 #define UART0_CONTROL 36866 #define PRE_START_CODE 3083 #define HEVC_DCAC_CPU_DATA 15893 #define P_WM_STATUS_RO 4287678244 #define P_XVYCC_INV_LUT_Y_DATA_PORT 4287677796 #define P_VDEC2_MC_CTRL_REG 4284654592 #define P_VDEC2_LAST_SLICE_MV_ADDR 4284657856 #define P_ENCP_VIDEO_BLANKY_VAL 4287655624 #define P_VIU2_OSD1_BLK1_CFG_W2 4287658116 #define P_VIU2_OSD1_BLK1_CFG_W1 4287658112 #define P_VIU2_OSD1_BLK1_CFG_W0 4287658108 #define P_VIU2_OSD1_BLK1_CFG_W4 4287658388 #define P_VIU2_OSD1_BLK1_CFG_W3 4287658120 #define ASYNC_FIFO_FILL_STATUS 25 #define ENCT_VFIFO2VD_LINE_TOP_END 7204 #define P_HLTI_CON_2_GAIN_1 4287678688 #define DET3D_RO_SPLT_HB 6016 #define P_HLTI_CON_2_GAIN_0 4287678684 #define P_ENCP_VBI_SETTING 4287655748 #define DET3D_RO_SPLT_HT 5951 #define P_VPU_PROT1_Y_START_END 4287667532 #define P_DNR_DB_CHDELTA2_GAIN 4287673420 #define VDEC2_VLD_MEM_VIFIFO_MEM_CTL 11346 #define tcon_pattern_loop_start 12 #define VDIN_DUMMY_DATA 4646 #define VPU_WRARB_WEIGH0_SLV_L2C1 10148 #define P_LDIM_STTS_MATRIX_OFFSET2 4287654692 #define P_ME_SAD_ENOUGH_01 4284644672 #define VD2_AFBC_MIF_VER_SCOPE 12686 #define P_RGB_COEFF_ADDR 4287648280 #define P_WRRSP_FIFO_PICW_MC 4284622588 #define P_DI_CONTWR_Y 4287651460 #define P_DI_CONTWR_X 4287651456 #define DI_IF1_CHROMA0_RPT_PAT 6128 #define HCODEC_MFDIN_REG1_CTRL 4105 #define P_ME_SAD_ENOUGH_23 4284644676 #define SRSHARP0_VLTI_CON_2_GAIN_1 12862 #define SRSHARP0_VLTI_CON_2_GAIN_0 12861 #define mLVDS_config_reserved 20 #define P_VIDEO_DTS 4291879368 #define OSD1_AFBCD_CONV_CTRL 12710 #define ME_SAD_RANGE_INC 8024 #define P_VDIN_MATRIX_COEF00_01 4287645764 #define AUDOUT_FIFO_STS 13450 #define AIU_AMCLK_GATE_HI 5200 #define VIU2_VD1_IF0_RANGE_MAP_CR 7788 #define SRSHARP0_HCTI_FLT_CLP_DC 12846 #define P_DI_MTNPRD_X 4287651628 #define P_DI_MTNPRD_Y 4287651632 #define P_VDEC2_ASSIST_MBX_SSEL 4284645652 #define P_HEVC_CCPU_INTR_REQ 4284664980 #define P_MCDI_CHK_EDGE_THD 4287675432 #define GAMMA_PROBE_COLOR_L 5258 #define GAMMA_PROBE_COLOR_H 5259 #define P_UART1_WFIFO 4291964928 #define VIU2_VD1_IF0_RANGE_MAP_CB 7787 #define P_WM_FREQ_DIST_LEFT 4287678160 #define PARSER_STATUS 14480 #define MEDIA_CPU_INTR_STAT_CLR 15401 #define P_IQIDCT_CONTROL 4284627000 #define ENCL_SYNC_PIXEL_EN 7245 #define NR4_MCNR_SAD2ALP1_LUT3 11749 #define NR4_MCNR_SAD2ALP1_LUT2 11748 #define NR4_MCNR_SAD2ALP1_LUT1 11747 #define SPI_FLASH_USR_DUMMY 14 #define VD1_IF0_LUMA_PSEL 6752 #define NR4_MCNR_SAD2ALP1_LUT0 11746 #define AIFIFO2_TIME_STAMP_2 5277 #define AIFIFO2_TIME_STAMP_1 5276 #define P_HEVC_MPRED_L1_REF05_POC 4284664020 #define I2C_M_3_RDATA_REG0 28678 #define I2C_M_3_RDATA_REG1 28679 #define AIFIFO2_TIME_STAMP_3 5278 #define P_PK_DRT_SAD_MISC 4287678624 #define P_I2C_M_0_CONTROL_REG 4291948544 #define AIFIFO2_TIME_STAMP_0 5275 #define P_VLD_REVERVED_19 4284624996 #define AIU_MEM_AIFIFO2_MEM_CTL 5288 #define SRSHARP1_HCTI_CON_2_GAIN_1 13362 #define SRSHARP1_HCTI_CON_2_GAIN_0 13361 #define P_VPP_MATRIX_COEF15_25 4287657844 #define P_HEVC_SAO_DBG_DATA_4 4284668112 #define P_HEVC_SAO_DBG_DATA_3 4284668108 #define P_HEVC_SAO_DBG_DATA_6 4284668120 #define P_HEVC_SAO_DBG_DATA_5 4284668116 #define P_DCAC_DMA_ADDRESS 4284627020 #define P_HEVC_SAO_DBG_DATA_0 4284668096 #define P_HEVC_SAO_DBG_DATA_2 4284668104 #define P_HEVC_SAO_DBG_DATA_1 4284668100 #define HCODEC_ANC0_CANVAS_ADDR 6544 #define P_HEVC_SAO_DBG_DATA_7 4284668124 #define P_VPP_OSDSC_DITHER_LUT_13 4287677684 #define P_VPP_OSDSC_DITHER_LUT_14 4287677688 #define P_VPP_OSDSC_DITHER_LUT_15 4287677692 #define P_VDEC2_ASSIST_DMA_INT 4284645776 #define P_VPP_OSDSC_DITHER_LUT_10 4287677672 #define P_VPP_OSDSC_DITHER_LUT_11 4287677676 #define P_VPP_OSDSC_DITHER_LUT_12 4287677680 #define HEVC_SHIFT_BYTE_COUNT 12557 #define P_HEVC_ASSIST_MBOX1_MASK 4284662232 #define P_DOLBY_CORE2A_DMA_CTRL 4287680740 #define P_VENC_VDAC_DAC4_GAINCTRL 4287655904 #define P_NR2_RO_POLAR3_SMOOTHMV 4287673976 #define AIU_MEM_I2S_MEM_CTL 5240 #define P_WM_AM_LUT_ADDR_PORT 4287678240 #define DBLK_STATUS1 2411 #define DOS_SW_RESET4 16183 #define DOS_SW_RESET3 16180 #define DOS_SW_RESET0 16128 #define DOS_SW_RESET2 16136 #define DOS_SW_RESET1 16135 #define HCODEC_VLC_VB_END_PTR 7441 #define P_MCDI_REL_DET_GAIN_21 4287675576 #define P_MCDI_REL_DET_GAIN_20 4287675572 #define AIU_MEM_AIFIFO2_START_PTR 5226 #define P_AIU_MIX_CTRL 4291842144 #define VDEC2_ACC1REG2 9074 #define VDEC2_ACC1REG1 9058 #define DET3D_RO_SPLT_VL 6017 #define HEVC_LMEM_DMA_CTRL 13136 #define DET3D_RO_SPLT_VR 6018 #define P_MCDI_REL_DET_GAIN_11 4287675568 #define P_MCDI_REL_DET_GAIN_10 4287675564 #define P_VDEC2_CCPU_INTR_MSK 4284648592 #define P_VPP_LINE_IN_LENGTH 4287656964 #define P_MCDI_REL_DET_GAIN_01 4287675560 #define P_MCDI_REL_DET_GAIN_00 4287675556 #define LCD_MCU_DATA_1 5343 #define LCD_MCU_DATA_0 5342 #define VPP_POST2_MATRIX_EN_CTRL 14765 #define P_TCON_CONTROL_LO 4287648564 #define P_VDEC2_DBLK_CBPY 4284655040 #define P_HEVC_CDB_CTRL 4284665076 #define P_VDEC2_DBLK_CBPC 4284655048 #define VP9_CONTROL 12608 #define P_VPP2_VE_DEMO_CENTER_BAR 4287653516 #define MCDI_RO_RPT_FLG_CNT 12194 #define VDIN1_DOLBY_AXI_CTRL0 5241 #define VDIN1_DOLBY_AXI_CTRL1 5242 #define VDIN1_DOLBY_AXI_CTRL2 5243 #define VDIN1_DOLBY_AXI_CTRL3 5244 #define VIUB_SW_RESET 8193 #define ENCT_TST_MDSEL 7209 #define P_CINDEX4_REG 4284615864 #define P_ENCP_VIDEO_VSO_ELINE 4287655600 #define SRSHARP0_DNLP_EN 12869 #define LDIM_STTS_MATRIX_OFFSET2 6857 #define ENCT_DBG_PX_RST 7273 #define P_NR4_MCNR_SAD_GAIN 4287683584 #define P_TCON_CONTROL_HI 4287648560 #define VPU_PROT1_DDR 10071 #define STV2_SEL 5 #define AUDIN_FIFO1_HOLD2_EN 21 #define VPP_WRAP_OSD2_MATRIX_COEF22 15732 #define ME_SUB_FIX_SAD 8028 #define MCDI_RO_FLD_PD_22_FLT_CNT 12202 #define P_VIU_OSD1_BLK0_CFG_W2 4287654004 #define P_PK_ALP2_MIERR_CORING 4287678584 #define P_VIU_OSD1_BLK0_CFG_W3 4287654008 #define P_VIU_OSD1_BLK0_CFG_W4 4287653964 #define P_NR2_MATNR_SNR_NRM_GAIN 4287651152 #define VENC_SYNC_ROUTE 7008 #define P_VIU_OSD1_BLK0_CFG_W0 4287653996 #define P_VIU_OSD1_BLK0_CFG_W1 4287654000 #define P_HEVC_DBLK_CBPY 4284671424 #define ENCP_VIDEO_EQPULS_END 7072 #define P_ENCP_VIDEO_BLANKPB_VAL 4287655628 #define VPP_VE_H_V_SIZE 7588 #define P_HCODEC_MCRCC_CTL2 4284638724 #define P_HCODEC_MCRCC_CTL3 4284638728 #define P_C656_HS_ST 4287655808 #define P_HCODEC_MCRCC_CTL1 4284638720 #define P_L_OEV1_VE_ADDR 4287647944 #define VDIN1_ASFIFO_CTRL0 5128 #define P_WRRSP_DCAC 4284622692 #define VDIN1_ASFIFO_CTRL1 5129 #define VDIN1_ASFIFO_CTRL2 5135 #define VDIN1_ASFIFO_CTRL3 5231 #define P_HEVC_DBLK_CBPC 4284671432 #define SRSHARP0_DNLP_07 12877 #define SRSHARP0_DNLP_08 12878 #define SRSHARP0_DNLP_05 12875 #define SRSHARP0_DNLP_06 12876 #define HCODEC_VLD_MEM_VBUF2_RD_PTR 7252 #define SRSHARP0_DNLP_09 12879 #define P_HEVC_MCW_DBLK_WRRSP_CNT 4284671724 #define SRSHARP1_PKGAIN_VSLUMA_LUT_L 13438 #define STREAM_EVENT_INFO 11264 #define SRSHARP0_DNLP_10 12880 #define SRSHARP0_DNLP_11 12881 #define SRSHARP0_DNLP_14 12884 #define SRSHARP0_DNLP_15 12885 #define SRSHARP0_DNLP_12 12882 #define SRSHARP0_DNLP_13 12883 #define VDEC2_MB_MOTION_MODE 11271 #define P_ENCL_VIDEO_OFLD_VPEQ_OFST 4287656716 #define L_STV1_VE_ADDR 5162 #define SRSHARP0_DNLP_00 12870 #define SRSHARP0_DNLP_03 12873 #define SRSHARP0_DNLP_04 12874 #define SRSHARP0_DNLP_01 12871 #define SRSHARP0_DNLP_02 12872 #define P_MCDI_LMV_LOCK_CNT_THD_GAIN 4287675684 #define DECOMB_CMB_SEL_GAIN_OFST 11657 #define AIU_958_RPT 5131 #define VDIN0_BLKBAR_STATUS1 4716 #define P_HEVC_M4_TABLE_SELECT 4284674208 #define VDIN0_BLKBAR_STATUS0 4715 #define P_NR4_SNR_CTRL_REG 4287674020 #define SRSHARP1_PKGAIN_VSLUMA_LUT_H 13439 #define LDIM_STTS_MATRIX_PROBE_COLOR 6862 #define P_GE2D_HSC_NRND_POINT 4287890188 #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 7586 #define P_VDEC2_IMEM_DMA_COUNT 4284648712 #define ENCP_VIDEO_VSPULS_BEGIN 7067 #define HCODEC_AV_SCRATCH_D 6605 #define HCODEC_AV_SCRATCH_E 6606 #define HCODEC_AV_SCRATCH_B 6603 #define HCODEC_AV_SCRATCH_C 6604 #define HCODEC_AV_SCRATCH_H 6609 #define P_HCODEC_V3_TOP_LEFT_CTL 4284644788 #define HCODEC_AV_SCRATCH_I 6610 #define HCODEC_AV_SCRATCH_F 6607 #define HCODEC_AV_SCRATCH_G 6608 #define HCODEC_AV_SCRATCH_L 6613 #define HCODEC_AV_SCRATCH_M 6614 #define HCODEC_AV_SCRATCH_J 6611 #define HCODEC_AV_SCRATCH_K 6612 #define HCODEC_VLD_MEM_VIFIFO_START_PTR 7232 #define HCODEC_AV_SCRATCH_N 6615 #define P_HEVC_PSCALE_PICO_W 4284671056 #define P_L_STH2_VS_ADDR 4287647832 #define STV1_HE_ADDR 5288 #define HCODEC_V3_LEFT_MV 8047 #define P_WM_SPACE_RESOLUTION 4287678148 #define P_HCODEC_CSFTINT1 4284632316 #define P_VPP_FIFO_STATUS 4287657120 #define P_HCODEC_CSFTINT0 4284632312 #define VDIN0_LDIM_STTS_HIST_REGION_IDX 4695 #define P_ENCT_SYNC_PIXEL_EN 4287656228 #define SRSHARP1_NR_ALP1_MIN_MAX 13341 #define HEVC_DC_AC_CTRL 15877 #define ENCP_VIDEO_RGBIN_CTRL 7101 #define P_HCODEC_MBREAK0_REG 4284632144 #define VPU_WRARB_WEIGH0_SLV_L1C1 10134 #define P_ENCP_VIDEO_PR_SCL 4287655444 #define P_HCODEC_DBLK_CLIP_CTRL5 4284638620 #define P_HCODEC_DBLK_CLIP_CTRL4 4284638616 #define P_HCODEC_DBLK_CLIP_CTRL3 4284638612 #define P_HCODEC_DBLK_CLIP_CTRL2 4284638608 #define P_HCODEC_DBLK_CLIP_CTRL1 4284638604 #define P_HCODEC_DBLK_CLIP_CTRL0 4284638600 #define P_VPU_VDIN_ASYNC_HOLD_CTRL 4287667472 #define VPU_WRARB_WEIGH0_SLV_L1C2 10160 #define DNR_DB_YHDELTA2_GAIN 11537 #define VDIN0_DOLBY_DSC_CTRL3 4728 #define VDIN0_DOLBY_DSC_CTRL0 4725 #define P_NR2_MATNR_ALPHALP_LUT3 4287651272 #define VDIN0_DOLBY_DSC_CTRL2 4727 #define VDIN0_DOLBY_DSC_CTRL1 4726 #define P_NR2_MATNR_ALPHALP_LUT0 4287651260 #define P_NR2_MATNR_ALPHALP_LUT2 4287651268 #define P_NR2_MATNR_ALPHALP_LUT1 4287651264 #define NR_DB_FLT_PXI_THRD 14139 #define CVBS_IRQ0_COUNTER 15398 #define NR2_MOTION2BETA_LUT1 5991 #define PSCALE_CANVAS_WR_ADDR 2349 #define NR2_MOTION2BETA_LUT2 5992 #define NR2_MOTION2BETA_LUT0 5990 #define P_VLC_HUFFMAN_DATA 4284642668 #define P_HEVC_MINDEX4_REG 4284664888 #define VDEC2_MBREAK2_REG 8982 #define NR2_MOTION2BETA_LUT3 5993 #define P_HEVC_STREAM_CONTROL 4284662788 #define P_UART0_CONTROL 4291969032 #define P_HCODEC_DBLK_CLIP_CTRL8 4284638632 #define P_HCODEC_DBLK_CLIP_CTRL7 4284638628 #define P_HEVC_PSCALE_PICO_H 4284671060 #define P_HCODEC_DBLK_CLIP_CTRL6 4284638624 #define P_HCODEC_MDEC_EXTIF_CFG0 4284639120 #define P_HCODEC_MDEC_EXTIF_CFG1 4284639124 #define P_HEVC_MC_MPORT_DAT 4284671236 #define ENCI_VFIFO2VD_LINE_TOP_START 7195 #define HEVC_IQIT_STAT_GEN0 14088 #define HEVC_IQIT_STAT_GEN1 14090 #define HEVC_IQIT_STAT_GEN2 14092 #define mLVDS_dual_gate 7 #define P_VPU_DI_MEM_MMC_CTRL 4287667224 #define DI_MC_22LVL0 5932 #define DI_MC_22LVL2 5934 #define DI_MC_22LVL1 5933 #define P_C656_HS_ED 4287655812 #define P_SHARP_SR2_CBIC_VCOEF1 4287678844 #define HEVC_PARSER_LCU_START 12580 #define X_INT_ADR 1024 #define OEV2_VE_ADDR 5302 #define P_WM_SYMBOLS_XPOS 4287678172 #define P_PATTERN_CODE 4284625068 #define P_ENCP_VIDEO_MODE_ADV 4287655480 #define P_SHARP_SR2_CBIC_VCOEF0 4287678840 #define VPP_VSC_REGION34_STARTP 7430 #define LUMA_ADJ_LIMT_REG 533 #define P_ENCI_DVI_HSO_BEGIN 4287655936 #define VIU_OSD_BLEND_CTRL 14768 #define DIPD_COMB_CTRL5 12245 #define DIPD_COMB_CTRL4 12244 #define DIPD_COMB_CTRL3 12243 #define DIPD_COMB_CTRL2 12242 #define HEVC_WRRSP_IMEM 13123 #define DIPD_COMB_CTRL1 12241 #define DIPD_COMB_CTRL0 12240 #define AUDIN_FIFO1_ENDIAN 8 #define P_DBLK_VHMVD 4284622288 #define P_VD2_AFBC_ENABLE 4287677952 #define D2D3_DBR_DDD_DBG 11053 #define MCDI_REL_DET_GAIN_00 12073 #define MCDI_REL_DET_GAIN_01 12074 #define P_ENCP_VFIFO2VD_PIXEL_END 4287655272 #define HCODEC_MINT_VEC_BASE 4866 #define P_HEVCD_IPP_TOP_TILECONFIG3 4284665876 #define P_HEVCD_IPP_TOP_TILECONFIG2 4284665872 #define QDCT_INT_STATUS 7998 #define P_HEVCD_IPP_TOP_TILECONFIG1 4284665868 #define HEVC_ELEMENT_RESULT 12559 #define MCDI_REL_DET_GAIN_11 12076 #define LDIM_STTS_MATRIX_PRE_OFFSET2 6859 #define MCDI_REL_DET_GAIN_10 12075 #define MCDI_REL_DET_GAIN_20 12077 #define MCDI_REL_DET_GAIN_21 12078 #define P_DNR_HVSIZE 4287673348 #define mLVDS2_reset_start_bit12 19 #define P_QDCT_MB_MAGIC_WORD 4284644448 #define VLTI_BST_CORE 12860 #define P_MEDIA_CPU_INTR_STAT 4291883168 #define P_HEVC_DBLK_VHMVD 4284671440 #define VDEC2_MC_STATUS1 10506 #define VDEC2_MC_STATUS0 10505 #define P_VD1_IF0_RANGE_MAP_CR 4287654320 #define DNR_DB_YHDELTA_GAIN 11536 #define P_DI_IF2_GEN_REG 4287660096 #define VDEC2_BLOCK_NUM 11306 #define VKS_CTRL 12544 #define P_AIFIFO2_TIME_STAMP_3 4291842680 #define P_AIFIFO2_TIME_STAMP_2 4291842676 #define STH2_HE_ADDR 5269 #define AUDIN_FIFO1_INTR 13366 #define P_HEVCD_IPP_SWMPREDIF_STATUS 4284665924 #define P_VD1_IF0_RANGE_MAP_CB 4287654316 #define P_AIFIFO2_TIME_STAMP_1 4291842672 #define P_AIFIFO2_TIME_STAMP_0 4291842668 #define P_GE2D_DP_ONOFF_CTRL 4287890252 #define HCODEC_HENC_TOP_INFO_0 7479 #define HCODEC_HENC_TOP_INFO_1 7481 #define P_IEC958_TIME_STAMP_3 4291842712 #define P_IEC958_TIME_STAMP_2 4291842708 #define P_IEC958_TIME_STAMP_1 4291842704 #define P_IEC958_TIME_STAMP_0 4291842700 #define VIU2_OSD1_COLOR_ADDR 7697 #define ENCT_VIDEO_BLANKY_VAL 7292 #define P_VDEC2_MDB_DATA_REG 4284648560 #define P_HCODEC_V3_L2_SKIP_WEIGHT 4284644808 #define VIU_OSD1_MATRIX_COEF22_30 6813 #define VLD_DC_PRED_C 3119 #define VDIN0_WR_H_START_END 4641 #define VIU_OSD1_MATRIX_PRE_OFFSET0_1 6808 #define HEVC_ASSIST_MBOX1_FIQ_SEL 12407 #define AVSP_IQ_WQ_PARAM_23 3610 #define P_VENC_VDAC_DAC0_GAINCTRL 4287655872 #define VPP_MATRIX_COEF13_14 7643 #define VD1_IF0_CHROMA0_RPT_PAT 6749 #define VDEC2_PSCALE_MCMD_YSIZE 10532 #define LMEM_DMA_COUNT 850 #define P_FBUF_ADDR 4291883352 #define SRSHARP1_HLTI_BST_GAIN 13365 #define P_HEVC_PSCALE_CTRL2 4284671160 #define P_SHARP_SR3_DERING_GAINVS_MADSAD 4287678912 #define SHARP_SR3_DERING_LUMA2PKOS_4TO6 12911 #define P_HEVC_PSCALE_CTRL1 4284671140 #define P_VPP_DNLP_CTRL_15 4287657536 #define P_NR2_MATNR_MTNB_BRT 4287651292 #define MIPI_DSI_DWC_CMD_PKT_STATUS_OS 7197 #define P_VPP_DNLP_CTRL_14 4287657532 #define P_VPP_DNLP_CTRL_13 4287657528 #define P_VPP_DNLP_CTRL_12 4287657524 #define P_VPP2_VSC_INI_PHASE 4287652920 #define DI_CHAN2_RPT_LOOP 6139 #define SRSHARP0_HLTI_BST_GAIN 12853 #define HCODEC_VLD_MEM_VIFIFO_END_PTR 7234 #define P_DI_IF1_URGENT_CTRL 4287660684 #define AVSP_IQ_WQ_PARAM_45 3611 #define P_VPP_DNLP_CTRL_04 4287657492 #define P_VPP_DNLP_CTRL_03 4287657488 #define P_VPP_DNLP_CTRL_02 4287657484 #define P_VPP_DNLP_CTRL_01 4287657480 #define P_VPP_DNLP_CTRL_08 4287657508 #define P_VPP_DNLP_CTRL_07 4287657504 #define P_VPP_DNLP_CTRL_06 4287657500 #define P_VPP_DNLP_CTRL_05 4287657496 #define P_VPP_DNLP_CTRL_09 4287657512 #define P_C656_VS_LNST_O 4287655820 #define P_C656_VS_LNST_E 4287655816 #define P_HEVC_CM_HEADER_START_ADDR 4284668064 #define P_ENCL_VFIFO2VD_LINE_TOP_START 4287656524 #define P_VPP_DNLP_CTRL_11 4287657520 #define P_VPP_DNLP_CTRL_10 4287657516 #define P_HCODEC_IQIDCT_DEBUG_IDCT 4284643396 #define HCODEC_IE_SAD_2 8039 #define HCODEC_IE_SAD_1 8038 #define HCODEC_IE_SAD_0 8037 #define HCODEC_IE_SAD_3 8040 #define P_VPP_DNLP_CTRL_00 4287657476 #define HCODEC_VLC_VB_LEFT 7445 #define P_DIPD_RO_COMB_8 4287676280 #define P_DIPD_RO_COMB_7 4287676276 #define P_DIPD_RO_COMB_9 4287676284 #define P_V3_F_ZERO_CTL_0 4284644816 #define P_V3_F_ZERO_CTL_1 4284644820 #define P_DIPD_RO_COMB_0 4287676248 #define P_DIPD_RO_COMB_2 4287676256 #define P_DIPD_RO_COMB_1 4287676252 #define P_DIPD_RO_COMB_4 4287676264 #define P_DIPD_RO_COMB_3 4287676260 #define P_DIPD_RO_COMB_6 4287676272 #define P_DIPD_RO_COMB_5 4287676268 #define P_V3_LEFT_SMALL_MAX_SAD 4284644840 #define AVSP_IQ_WQ_PARAM_01 3609 #define DNR_RO_VBOF_STAT_CNT_9 11590 #define DNR_RO_VBOF_STAT_CNT_8 11589 #define DNR_RO_VBOF_STAT_CNT_5 11586 #define DNR_RO_VBOF_STAT_CNT_4 11585 #define DNR_RO_VBOF_STAT_CNT_7 11588 #define P_ENCI_DVI_VSO_ELINE_ODD 4287655956 #define P_VDIN_HIST_V_START_END 4287645896 #define DNR_RO_VBOF_STAT_CNT_6 11587 #define VDEC2_VLD_ERROR_MASK 11310 #define DNR_RO_VBOF_STAT_CNT_1 11582 #define DNR_RO_VBOF_STAT_CNT_0 11581 #define DNR_RO_VBOF_STAT_CNT_3 11584 #define DNR_RO_VBOF_STAT_CNT_2 11583 #define VIU_ADDR_START 6656 #define P_D2D3_MBDG_CTRL 4287671392 #define P_ENCL_INFO_READ 4287667324 #define VDIN1_SYNC_MASK 5236 #define P_SAD_CONTROL_1 4284644588 #define P_SAD_CONTROL_0 4284644584 #define MCDI_RO_COL_CFD_24 12232 #define VIU_OSD1_BLK0_CFG_W1 6684 #define MCDI_RO_COL_CFD_23 12231 #define VIU_OSD1_BLK0_CFG_W2 6685 #define VIU_OSD1_BLK0_CFG_W3 6686 #define MCDI_RO_COL_CFD_25 12233 #define VIU_OSD1_BLK0_CFG_W4 6675 #define VIU_OSD1_BLK0_CFG_W0 6683 #define MCDI_RO_COL_CFD_20 12228 #define MCDI_RO_COL_CFD_22 12230 #define P_HEVC_SLICE_START_BYTE_01 4284674096 #define MCDI_RO_COL_CFD_21 12229 #define MCDI_RO_COL_CFD_13 12221 #define P_VDEC2_CBREAK2_REG 4284648664 #define MCDI_RO_COL_CFD_12 12220 #define MCDI_RO_COL_CFD_15 12223 #define VDEC2_MDB_CTRL 8989 #define MCDI_RO_COL_CFD_14 12222 #define P_VPU_PROT2_Y_LEN_STEP 4287667600 #define MCDI_RO_COL_CFD_17 12225 #define VDEC_ASSIST_MBOX2_MASK 122 #define MCDI_RO_COL_CFD_16 12224 #define MCDI_RO_COL_CFD_19 12227 #define MCDI_RO_COL_CFD_18 12226 #define HEVC_MINDEX7_REG 13073 #define P_CVBS_IRQ1_COUNTER 4291883164 #define MCDI_RO_COL_CFD_11 12219 #define P_ENCP_VIDEO_YFP2_HTIME 4287655508 #define MCDI_RO_COL_CFD_10 12218 #define P_CPV1_HE_ADDR 4287648384 #define AUDIN_FIFO0_HOLD1_EN 20 #define P_AIU_958_BPF 4291842048 #define VPP_PREBLEND_CURRENT_XY 7460 #define P_HCODEC_VLC_HCMD_DBLK_INFO 4284642644 #define OSD_DB_FLT_CHRM_THRD 12611 #define P_VDEC2_RV_AI_MB_COUNT 4284659760 #define VDEC_ASSIST_TIMER1_HI 99 #define P_HCODEC_VOFF_STATUS 4284641520 #define AIU_MEM_AIFIFO_END_PTR 5254 #define P_MINDEX2_REG 4284615728 #define P_HCODEC_DBLK_RV8_QUANT 4284638680 #define VPU_TVD3D_MMC_CTRL 10000 #define P_ENCP_DBG_PX_RST 4287655488 #define mLVDS_msb_first 4 #define P_NR4_MCNR_SAD2ALP1_LUT3 4287674260 #define P_NR4_MCNR_SAD2ALP1_LUT0 4287674248 #define P_NR4_MCNR_SAD2ALP1_LUT2 4287674256 #define P_VDEC2_MCW_DBLK_WRRSP_CNT 4284655340 #define P_NR4_MCNR_SAD2ALP1_LUT1 4287674252 #define P_OEV2_VS_ADDR 4287648468 #define P_HEVC_SLICE_START_BYTE_23 4284674100 #define P_HEVC_FST_FOR_MV_Y 4284674116 #define P_HEVC_FST_FOR_MV_X 4284674112 #define P_HCODEC_DBKW_CANVAS_ADDR 4284638916 #define VD2_IF0_GEN_REG 6768 #define P_ENCT_VIDEO_MATRIX_CB 4287656468 #define P_ENCL_SYNC_TO_LINE_EN 4287656248 #define HCODEC_WRRSP_CO_MB 6616 #define P_ENCT_VIDEO_MATRIX_CR 4287656472 #define P_DOS_SW_RESET2 4284677152 #define P_MEDIA_CPU_INTR_MASK 4291883176 #define MCDI_REL_DET_BAD_THD_1 12101 #define P_DOS_SW_RESET3 4284677328 #define MCDI_REL_DET_BAD_THD_0 12100 #define P_DOS_SW_RESET4 4284677340 #define P_MCDI_HIGH_VERT_FRQ_DIF_THD 4287675708 #define P_DOS_SW_RESET0 4284677120 #define P_DOS_SW_RESET1 4284677148 #define VDEC2_RV_AI_U_X 11786 #define VDEC_ASSIST_TIMER1_LO 98 #define P_ENCT_INFO_READ 4287667320 #define D2D3_D2P_PARAM_3 11022 #define D2D3_D2P_PARAM_1 11020 #define VDEC2_MC_CTRL_GCLK_CTRL 10573 #define D2D3_D2P_PARAM_2 11021 #define P_DI_NR_1_CTRL1 4287651412 #define P_DI_NR_1_CTRL2 4287651416 #define HEVC_DBLK_STATUS1 14699 #define P_DI_NR_1_CTRL3 4287651420 #define P_DI_NR_1_CTRL0 4287651408 #define P_VPU_DI_IF1_MMC_CTRL 4287667220 #define SRSHARP1_SR3_DERING_LUMA2PKOS_4TO6 13423 #define MIPI_DSI_TOP_MEAS_STAT_TE0 7416 #define P_I2C_M_3_WDATA_REG1 4291936276 #define MIPI_DSI_TOP_MEAS_STAT_TE1 7417 #define P_I2C_M_3_WDATA_REG0 4291936272 #define P_ENCP_MAX_LINE_SWITCH_POINT 4287655996 #define P_UART0_WFIFO 4291969024 #define P_ASSIST_AMR_SCRATCH0 4291854652 #define P_ENCI_VFIFO2VD_LINE_BOT_END 4287656056 #define P_SAD_CONTROL 4284644620 #define P_ASSIST_AMR_SCRATCH1 4291854656 #define P_ASSIST_AMR_SCRATCH2 4291854660 #define P_ASSIST_AMR_SCRATCH3 4291854664 #define VPU_VLOCK_RO_LOOP0_ACCUM 12302 #define VPP_MATRIX_PROBE_COLOR 7516 #define ENCI_SYNC_LINE_LENGTH 7232 #define ENCP_MACV_PSSYNC_STRT 7107 #define P_VD2_AFBC_MIF_VER_SCOPE 4287678008 #define ENCL_VIDEO_PR_OFFST 7334 #define ENCP_VIDEO_VOFFST 7094 #define HCODEC_LAST_MVY 7218 #define HCODEC_LAST_MVX 7217 #define VIU_OSD1_EOTF_COEF22_RS 6873 #define MCDI_RO_MOTION_PARADOX_FLG 12206 #define P_VPP_MATRIX_PRE_OFFSET2 4287657376 #define CPV1_VE_ADDR 5282 #define P_VDEC2_PIC_HEAD_INFO 4284657676 #define AIU_958_CTRL 5130 #define P_VPU_VLOCK_STBDET_CLP 4287676512 #define P_UART2_WFIFO 4291960832 #define NR2_MATNR_BETA_EGAIN 5976 #define WM_SYMBOLS_YPOS 12728 #define P_VPP_SCO_FIFO_CTRL 4287657164 #define P_VIU_OSD1_EOTF_COEF20_21 4287654752 #define P_HEVC_CM_HEADER_LENGTH 4284668068 #define QDCT_TOP_CONTROL 7967 #define P_DNR_GBS 4287673360 #define PK_DRTFB_BP_CORING 12818 #define HEVC_VLD_DC_PRED 15405 #define P_VDEC2_CBREAK_STAUTS 4284648680 #define P_VDIN_COM_GCLK_CTRL2 4287646144 #define P_ANC23_CANVAS_ADDR 4284622492 #define P_HEVC_IQIDCT_DEBUG_INFO_0 4284676156 #define P_GE2D_ANTIFLICK_CTRL1 4287890276 #define L_GAMMA_PROBE_HL_COLOR 5132 #define P_GE2D_ANTIFLICK_CTRL0 4287890272 #define VIU2_OSD1_MATRIX_PRE_OFFSET2 7804 #define P_HEVCD_IPP_TOP_CNTL 4284665856 #define VBO_HBK_CTRL 5228 #define ENCP_DVI_VSO_ELINE_EVN 7220 #define D2D3_DWMIF_SIZE 11047 #define P_PIC 2 #define P_ANC12_CANVAS_ADDR 4284622448 #define P_VDEC2_ASSIST_MBOX1_MASK 4284645848 #define P_HCODEC_ANC28_CANVAS_ADDR 4284638896 #define VPP2_PREBLEND_CURRENT_XY 6436 #define VDEC2_MC_HCMD_H 10570 #define DNR_RO_VBOF_STAT_CNT_26 11607 #define ABUF_RD_FF_PAUSE_LVL 0 #define VDEC2_MC_HCMD_L 10571 #define DNR_RO_VBOF_STAT_CNT_27 11608 #define DNR_RO_VBOF_STAT_CNT_28 11609 #define DNR_RO_VBOF_STAT_CNT_29 11610 #define DNR_RO_VBOF_STAT_CNT_22 11603 #define DNR_RO_VBOF_STAT_CNT_23 11604 #define DNR_RO_VBOF_STAT_CNT_24 11605 #define P_D2D3_SCU18_INPIC_SIZE 4287671388 #define DNR_RO_VBOF_STAT_CNT_25 11606 #define DNR_RO_VBOF_STAT_CNT_20 11601 #define DNR_RO_VBOF_STAT_CNT_21 11602 #define ENCL_TST_VDCNT_STSET 7327 #define IFO_MODE_REG 527 #define RV_AI_Y_X 3593 #define DNR_RO_VBOF_STAT_CNT_30 11611 #define DNR_RO_VBOF_STAT_CNT_31 11612 #define P_HEVC_DCAC_MB_COUNT 4284676184 #define P_DI_MEM_LUMA_Y0 4287651704 #define VIU_OSD2_MATRIX_COEF22 6837 #define HCODEC_ME_SKIP_LINE 8013 #define INV_CNT 0 #define P_HCODEC_ANC17_CANVAS_ADDR 4284638852 #define P_DI_MEM_LUMA_X0 4287651700 #define PK_CON_2DRTBPGAIN_TH_RATE 12811 #define VPP2_HSC_REGION4_ENDP 6418 #define P_ENCP_VIDEO_MACV_OFFST 4287655472 #define HCODEC_VLD_DC_PRED_C 7215 #define ENCI_SYNC_CTRL 6921 #define D2D3_DBLD_LPF_VCOEFF 11029 #define P_VENC_ENCP_LINE 4287655340 #define VPU_DI_MTNWR_MMC_CTRL 9994 #define P_ENCI_VBI_TTX_LN 4287655084 #define P_VI_HIST_CTRL 4287674368 #define DOLBY_TV_ADAPTIVE_SCALE_REGADDR 13280 #define AUD_RESAMPLE_STATUS 13505 #define P_ENCI_VFIFO2VD_CTL 4287656032 #define P_EE_ASSIST_MBOX0_CLR_REG 4291854788 #define HCODEC_ASSIST_TIMER1_HI 4195 #define P_ISA_PLL_CLK_SIM0 4291883040 #define P_HCODEC_ANC1_CANVAS_ADDR 4284638788 #define AIFIFO_TIME_STAMP_LENGTH 5271 #define P_SPI_FLASH_USER4 4291903532 #define P_SPI_FLASH_USER1 4291903520 #define P_SPI_FLASH_USER2 4291903524 #define P_SPI_FLASH_USER3 4291903528 #define P_AUDIN_FIFO2_PIO_STS 4291875544 #define P_PARSER_SUB_START_PTR 4291879464 #define HEVC_DBLK_CMD_CTRL 14676 #define VLC_DBG_IDX 7510 #define VIU_OSD1_MATRIX_COLMOD_COEF42 6805 #define VIU_MISC_CTRL0 6662 #define VIU_MISC_CTRL1 6663 #define HEVC_PSCALE_PICO_START_X 14614 #define HEVC_PSCALE_PICO_START_Y 14615 #define P_RDMA_ACCESS_AUTO 4287644736 #define IEC958_TIME_STAMP_CNTL 5280 #define P_VPP2_MATRIX_COEF22 4287653264 #define DBLK_OST_CBCRDIFF 2430 #define VDEC2_LAST_SLICE_MV_ADDR 11312 #define VENC_VIDEO_TST_CLRBAR_STRT 7029 #define SPDIF_TIE_0 24 #define P_ENCT_VIDEO_HAVON_BEGIN 4287656392 #define HCODEC_ASSIST_TIMER1_LO 4194 #define HEVC_MPEG1_2_REG 15361 #define XVYCC_VD1_RGB_BRGHT 12657 #define VLC_PUSH_STREAM 7455 #define P_VPP_VD1_CLIP_MISC1 4287657864 #define P_HCTI_OS_MARGIN 4287678668 #define P_VPP_VD1_CLIP_MISC0 4287657860 #define MCDI_REL_DET_LPF_MSK_13_21 12090 #define STV2_VS_ADDR 5293 #define P_SPI_FLASH_CTRL2 4291903508 #define P_SPI_FLASH_CTRL1 4291903500 #define P_VDIN_CM_BRI_CON_CTRL 4287645876 #define P_HCODEC_DC_AC_SCALE_DIV 4284643356 #define VDEC2_ANC5_CANVAS_ADDR 10645 #define AIU_958_POP 5146 #define L_OEH_VS_ADDR 5146 #define ENCL_VIDEO_YFP1_HTIME 7341 #define HEVC_NEXT_INTRA_DMA_ADDRESS 15885 #define P_NR2_MET_NMFRM_TNR_YCNT 4287651112 #define NR4_MCNR_CM_CTRL0 11717 #define HCODEC_HDEC_MC_OMEM_AUTO 6448 #define VDEC2_VLD_MEM_VIFIFO_CURR_PTR 11329 #define P_DOLBY_TV_CLKGATE_CTRL 4287680452 #define P_HEVC_VLD_MEM_VBUF_RD_PTR 4284674380 #define P_HEVCD_MCRCC_PERFMON_CTL 4284666828 #define P_NR2_MET_NMFRM_TNR_CCNT 4287651120 #define P_DOLBY_TV_ADAPTIVE_SCALE_LUTADDR 4287680392 #define HEVC_VLD_MEM_VIFIFO_START_PTR 15424 #define PN_SWP 5 #define VIU_SECURE_REG 6660 #define P_L_DITH_CNTL_ADDR 4287647776 #define WM_EMBEDDING_STRENGTH_THRESHOLD0 12731 #define WM_EMBEDDING_STRENGTH_THRESHOLD1 12732 #define VDIN1_MATRIX_COEF11_12 5139 #define WM_EMBEDDING_STRENGTH_THRESHOLD2 12733 #define LMEM_DMA_ADR 849 #define WM_EMBEDDING_STRENGTH_THRESHOLD3 12734 #define WM_EMBEDDING_STRENGTH_THRESHOLD4 12735 #define WM_EMBEDDING_STRENGTH_THRESHOLD5 12736 #define P_ENCL_VIDEO_RGBIN_CTRL 4287656732 #define MCDI_REL_DET_LUT_4_7 12095 #define P_ENCI_CFILT_CTRL 4287655248 #define MMAX_REG 787 #define DMC_REG_BASE 4284710912 #define AUDIN_SPDIF_MISC 13316 #define AFBC_PIXEL_VER_SCOPE 6896 #define P_HEVC_REC_CANVAS_ADDR 4284671688 #define VDEC2_ASSIST_MBOX2_FIQ_SEL 8315 #define VDEC2_RV_AI_V_X 11787 #define IE_WEIGHT 7989 #define P_VPP_OSD_HSC_INI_PHASE 4287657744 #define P_ENCT_VFIFO2VD_CTL 4287656064 #define L_STH2_VE_ADDR 5143 #define P_HEVC_WRRSP_CO_MB 4284671840 #define I2C_M_CURR_TOKEN_MSB 7 #define P_HEVC_VLD_MEM_VIFIFO_END_PTR 4284674312 #define DNR_GBS_STAT 11527 #define VDEC2_MCPU_INTR_GRP 8963 #define NR2_MATNR_XBETA_CFG 5978 #define HCODEC_MAC_CTRL1 4960 #define HCODEC_MAC_CTRL2 4976 #define P_DI_INP_CHROMA_X0 4287651656 #define P_RESET1_MASK 4291825732 #define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 12892 #define HEVC_MC_DPDN_MB_XY 14662 #define SRSHARP0_SHARP_SR2_YBIC_VCOEF1 12893 #define P_ENCT_VIDEO_OFLD_VOAV_OFST 4287656464 #define AFBC_CONV_CTRL 6884 #define P_DBLK_CB_FILT 4284622204 #define P_NR4_MCNR_DC2NORM_LUT2 4287674216 #define P_NR4_MCNR_DC2NORM_LUT0 4287674208 #define HCTI_FLT_CLP_DC 12846 #define P_NR4_MCNR_DC2NORM_LUT1 4287674212 #define P_DI_INP_CHROMA_Y0 4287651660 #define VLC_DC_BUF_STATUS 7492 #define VDIN1_BLKBAR_IND_RIGHT_START_END 5222 #define P_NR2_SNR_MASK 4287651188 #define DI_EI_DRT_CORRPIXTH 6010 #define HEVC_DBLK_CB_BFILT 14682 #define P_HEVC_ANC4_CANVAS_ADDR 4284671568 #define DI_INP_CHROMA0_RPT_PAT 6102 #define ENCP_VIDEO_EN 7040 #define DNR_RO_VBOF_STAT_CNT_19 11600 #define DNR_RO_VBOF_STAT_CNT_15 11596 #define DNR_RO_VBOF_STAT_CNT_16 11597 #define DNR_RO_VBOF_STAT_CNT_17 11598 #define DNR_RO_VBOF_STAT_CNT_18 11599 #define DNR_RO_VBOF_STAT_CNT_11 11592 #define DNR_RO_VBOF_STAT_CNT_12 11593 #define DNR_RO_VBOF_STAT_CNT_13 11594 #define DNR_RO_VBOF_STAT_CNT_14 11595 #define DNR_RO_VBOF_STAT_CNT_10 11591 #define HEVC_MPRED_L1_REF04_POC 12852 #define MBREAK_CTRL 793 #define P_HEVC_DBLK_STATUS 4284671308 #define P_DNLP_EN 4287678740 #define HCODEC_ASSIST_MMC_CTRL0 4097 #define HCODEC_ASSIST_MMC_CTRL1 4098 #define P_ENCI_VBI_CGMSDT_H 4287655072 #define HCODEC_ASSIST_MMC_CTRL2 4099 #define HCODEC_ASSIST_MMC_CTRL3 4100 #define P_NR4_NM_SAD_THD 4287683668 #define P_ENCI_VBI_CGMSDT_L 4287655068 #define VPU_SW_RESET 10016 #define P_HEVC_ANC11_CANVAS_ADDR 4284671596 #define P_AFBC_MIF_HOR_SCOPE 4287654836 #define P_VDEC2_MBREAK0_REG 4284648528 #define D2D3_DBLD_LG_PARAM 11027 #define P_VPU_VPUARB2_ASYNC_HOLD_CTRL 4287667480 #define P_HEVC_ASSIST_MBOX0_FIQ_SEL 4284662220 #define P_ENCT_DBG_LN_INT 4287656368 #define P_L_VSYNC_VS_ADDR 4287648108 #define P_HCODEC_VC1_CONTROL_REG 4284641400 #define P_AIU_I2S_OUT_CFG 4291842124 #define DI_CHAN2_URGENT_CTRL 8358 #define HCODEC_VLD_TIME_STAMP_SYNC_0 7242 #define HCODEC_VLD_TIME_STAMP_SYNC_1 7243 #define MB_INFO 3116 #define P_VPU_PROT2_X_START_END 4287667592 #define HCODEC_IE_MB_POSITION 8001 #define MIPI_DSI_DWC_SDF_3D_OS 7204 #define VPP2_MATRIX_COEF11_12 6498 #define MCDI_PD22_CHK_THD 12102 #define P_ENCI_VIDEO_HUE 4287654936 #define P_VDEC2_MC_MBBOT_ST_ODD_ADDR 4284654868 #define P_HEVCD_IPP_CONFIG 4284665888 #define VPP2_HSC_REGION34_STARTP 6417 #define P_SPI_FLASH_CTRL 4291903496 #define P_MBBOT_ODD_ADDR 4284644576 #define P_VIUB_GCLK_CTRL3 4287660072 #define P_D2D3_MBDG_STATUS_3 4287671500 #define P_D2D3_MBDG_STATUS_4 4287671504 #define P_D2D3_MBDG_STATUS_1 4287671492 #define P_D2D3_MBDG_STATUS_2 4287671496 #define P_HEVC_CINDEX5_REG 4284665020 #define P_VIUB_GCLK_CTRL2 4287660068 #define P_VIUB_GCLK_CTRL1 4287660064 #define P_VIUB_GCLK_CTRL0 4287660060 #define VENC_ENCI_LINE 7017 #define DI_IF1_GEN_REG 6120 #define P_L_LCD_PWM0_LO_ADDR 4287647984 #define P_D2D3_MBDG_STATUS_7 4287671516 #define VDIN_SCIN_HEIGHTM1 4645 #define P_D2D3_MBDG_STATUS_5 4287671508 #define GE2D_MATRIX_PRE_OFFSET 197 #define P_D2D3_MBDG_STATUS_6 4287671512 #define P_AUDIN_HDMI_REF_CYCLES_STAT_0 4291875472 #define P_AUDIN_HDMI_REF_CYCLES_STAT_1 4291875476 #define P_HEVC_MPRED_INT_STATUS 4284663824 #define VPU_VD1_MMC_CTRL 9987 #define P_VDEC2_CMAX_REG 4284648652 #define PARSER_SUB_START_PTR 14474 #define P_HCODEC_QDCT_JPEG_QUANT_DATA 4284644516 #define ENCP_DVI_HSO_BEGIN 7216 #define VDIN_BLKBAR_H_START_END 4705 #define VDEC_ASSIST_MMC_CTRL3 4 #define VDEC_ASSIST_MMC_CTRL2 3 #define VDEC_ASSIST_MMC_CTRL1 2 #define P_HEVC_MCPU_INTR_REQ 4284664852 #define VDEC_ASSIST_MMC_CTRL0 1 #define EE_ASSIST_MBOX1_IRQ_REG 8308 #define PK_ALP2_MIERR_CORING 12830 #define VDIN0_VSC_INI_CTRL 4644 #define P_D2D3_DWMIF_VPOS 4287671448 #define P_PARSER_AV2_WRAP_COUNT 4291879520 #define P_AIU_I2S_SOURCE_DESC 4291842100 #define SRSHARP0_VCTI_FLT_CON_CLP 12863 #define P_MCDI_RO_FLD_PD_22_FLT_CNT 4287676072 #define P_AUDIN_SPDIF_FS_CLK_RLTN 4291874820 #define P_VDEC2_MDEC_PIC_DC_CTRL 4284655160 #define DOS_MEM_PD_HEVC 16179 #define MCDI_RO_COL_CFD_9 12217 #define MCDI_RO_COL_CFD_7 12215 #define MCDI_RO_COL_CFD_8 12216 #define MCDI_RO_COL_CFD_1 12209 #define HCODEC_PSCALE_CTRL 6417 #define MCDI_RO_COL_CFD_2 12210 #define MCDI_RO_COL_CFD_0 12208 #define MCDI_RO_COL_CFD_5 12213 #define MCDI_RO_COL_CFD_6 12214 #define MCDI_RO_COL_CFD_3 12211 #define MCDI_RO_COL_CFD_4 12212 #define SHARP_DEJ_ALPHA 12901 #define P_HCODEC_MBA_INC 4284641304 #define NR4_MCNR_LPF_CTRL 14081 #define P_AIU_CODEC_CLK_DATA_CTRL 4291842220 #define P_DIPD_RO_COMB_18 4287676320 #define P_DIPD_RO_COMB_19 4287676324 #define P_DIPD_RO_COMB_16 4287676312 #define P_DIPD_RO_COMB_17 4287676316 #define P_DIPD_RO_COMB_14 4287676304 #define P_DIPD_RO_COMB_15 4287676308 #define P_DIPD_RO_COMB_12 4287676296 #define P_DIPD_RO_COMB_13 4287676300 #define VPU_HDMI_DITH_01_15 10225 #define P_NR2_MET_NM_CTRL 4287651092 #define VDEC2_CBREAK_TYPE 9016 #define P_DIPD_RO_COMB_10 4287676288 #define P_DIPD_RO_COMB_11 4287676292 #define I2C_M_ACK_IGNORE 1 #define P_DI_INFO_ADDR 4287651012 #define VPP2_BLEND_ONECOLOR_CTRL 6435 #define P_VDEC2_ASSIST_TIMER0_HI 4284645764 #define P_LVDS_SRG_TEST 4287648672 #define P_SPI_FLASH_B13 4291903604 #define VPU_HDMI_DITH_01_04 10224 #define VIU_OSD_BLEND_DUMMY_DATA0 14777 #define P_SPI_FLASH_B12 4291903600 #define P_SPI_FLASH_B11 4291903596 #define P_SPI_FLASH_B10 4291903592 #define P_VDEC_ASSIST_DMA_INT 4284613008 #define P_SPI_FLASH_B15 4291903612 #define P_SPI_FLASH_B14 4291903608 #define P_WM_MARK_RESOLUTION 4287678156 #define P_HCODEC_VLD_DC_PRED_C 4284641468 #define VPU_HDMI_DITH_01_37 10227 #define VDIN_MATRIX_OFFSET2 4631 #define NR2_SNR_SAD_CFG 5969 #define P_VPU_PROT2_CLK_GATE 4287667584 #define VPU_HDMI_DITH_01_26 10226 #define P_VPP_OSD_SCI_WH_M1 4287657764 #define NR4_BLDVS3_SUM 14118 #define INTRA_MB 1 #define INTRA_QM 8 #define HCODEC_VLC_HCMD_DBLK_INFO 7509 #define DI_POST_CTRL 5889 #define AIU_CODEC_CLK_DATA_CTRL 5163 #define VPP_MATRIX_HL_COLOR 7517 #define VPP_POST2_MATRIX_COEF22 14756 #define ENCI_DVI_VSO_ELINE_EVN 7172 #define VDEC2_CINDEX2_REG 9004 #define P_DBLK_MB_WID_HEIGHT 4284622152 #define HCODEC_HENC_LEFT_INFO_1 7482 #define STH1_HS_ADDR 5264 #define D2D3_DBG_STATUS_1 11064 #define D2D3_DBG_STATUS_2 11065 #define HCODEC_HENC_LEFT_INFO_0 7480 #define HCODEC_ASSIST_MBOX1_FIQ_SEL 4215 #define AUDIN_FIFO0_DIN_SEL 3 #define VDIN1_MEAS_CTRL0 5210 #define VIU2_OSD1_COLOR 7698 #define PSCALE_CTRL 2321 #define P_DIPD_RO_COMB_20 4287676328 #define P_AUDIN_FIFO1_PIO_RDH 4291875540 #define MCDI_RO_FLD_PD_22_FOR_CNT1 12235 #define UART0_REG5 36869 #define MCDI_RO_FLD_PD_22_FOR_CNT2 12238 #define P_HCODEC_WRRSP_FIFO_PICW_DBK 4284638968 #define VPP_WRAP_OSD1_MATRIX_COEF22 15716 #define P_AUDIN_FIFO1_PIO_RDL 4291875536 #define HCODEC_LMEM_DMA_ADR 4945 #define P_VDEC2_DBLK_CR_BFILT 4284654956 #define ENCP_MACV_AGC_STRT 7108 #define P_MINDEX3_REG 4284615732 #define HCODEC_QDCT_MB_RD_PTR 7955 #define P_L_OEH_HE_ADDR 4287647844 #define VPP_PEAKING_SAT_THD1 7597 #define VPP_PEAKING_SAT_THD4 7600 #define VPP_PEAKING_SAT_THD5 7601 #define VPP_PEAKING_SAT_THD2 7598 #define VPP_PEAKING_SAT_THD3 7599 #define VPP_PEAKING_SAT_THD8 7604 #define VPP_PEAKING_SAT_THD9 7605 #define P_VBO_LANES 4287648140 #define VPP_PEAKING_SAT_THD6 7602 #define VPP_PEAKING_SAT_THD7 7603 #define ENCI_VBI_SETTING 6944 #define P_VKS_IWIN_VSIZE 4287677472 #define HEVCD_MPP_DECOMP_PERFMON_DATA 13510 #define HEVC_ANC21_CANVAS_ADDR 14757 #define SPICC0_LD_RADDR 19468 #define ANC13_CANVAS_ADDR 2461 #define P_HEVC_DBLK_Y_VFILT 4284671352 #define P_HCODEC_IE_RESULT_BUFFER 4284644624 #define MC_CTRL2 2383 #define MC_CTRL1 2315 #define MC_CTRL0 2311 #define P_VPP_HSC_REGION0_PHASE_SLOPE 4287657040 #define P_L_GAMMA_PROBE_POS_Y 4287647800 #define P_L_GAMMA_PROBE_POS_X 4287647796 #define P_VDEC2_ASSIST_TIMER0_LO 4284645760 #define P_AIU_958_SYNWORD1_MASK 4291842172 #define DNR_RO_DM_GMS_STAT_CNT 11639 #define P_VDEC2_CBREAK1_REG 4284648660 #define P_HEVC_VLD_MEM_VIFIFO_LEVEL 4284674332 #define P_VPP_VSC_REGION4_ENDP 4287656988 #define XVYCC_INV_LUT_Y_DATA_PORT 12633 #define SRSHARP0_PK_ALP2_ERR2CURV_LIMIT 12832 #define P_VD1_IF0_LUMA0_RPT_PAT 4287654256 #define ME_F_SKIP_WEIGHT 8020 #define ABUF_RD_CUR_FF_CNT_LSB 16 #define SPI_START_ADDR 4211081216 #define AHB_ARBITER2_REG 15434 #define AUDIN_FIFO1_EN 0 #define CM_ENH_SFT_MODE_REG 516 #define VLC_DC_INFO 7495 #define P_DNR_DM_DIF_FLT_MISC 4287673776 #define P_HEVC_MPRED_L0_REF07_POC 4284663964 #define HCODEC_IMEM_DMA_CTRL 4928 #define P_VPU_HDMI_DITH_11_04 4287668192 #define NR_DB_FLT_CTRL 14136 #define MCDI_RO_FLD_PD_22_PRE_CNT 12200 #define P_HEVC_MMIN_REG 4284664904 #define HCODEC_MINDEX4_REG 4878 #define D2D3_DWMIF_STATUS 11067 #define VDIN0_BLKBAR_V_START_END 4706 #define XVYCC_LUT_B_DATA_PORT 12643 #define P_DNR_DM_DIF2NORM_LUT0_2 4287673804 #define P_VDEC2_VLD_STATUS_CTRL 4284657664 #define P_D2D3_INTF_LENGTH 4287653920 #define I2C_M_CURR_TOKEN_LSB 4 #define P_VDIN_BLKBAR_H_START_END 4287646084 #define P_VPU_HDMI_DITH_11_26 4287668200 #define P_STV1_HS_ADDR 4287648412 #define P_RESET3_REGISTER 4291825680 #define DEMO_OWR_YHS_REG 529 #define P_VPU_HDMI_DITH_11_15 4287668196 #define VDEC2_PSCALE_RBUF_START_BLKX 10533 #define VDEC2_MC_HALF_PEL_TWO 10500 #define P_HEVC_SAO_ABV_WPTR 4284667984 #define VDEC2_PSCALE_RBUF_START_BLKY 10534 #define HEVC_REC_CANVAS_ADDR 14770 #define P_MCDI_REL_DET_GMV_DIF_CHK 4287675580 #define P_VPP2_GCLK_CTRL1 4287653324 #define P_L_STV2_VE_ADDR 4287647928 #define P_VPP2_GCLK_CTRL0 4287653320 #define P_AIU_AIFIFO_GBIT 4291842568 #define HCODEC_DBLK_STATUS 6483 #define P_ENCI_DVI_HSO_END 4287655940 #define LVDS_RESV 3 #define SPI_ENABLE_AHB 17 #define VLD_MEM_VIFIFO_WRAP_COUNT 3153 #define P_HEVC_PIC_HEAD_INFO 4284674060 #define AIU_958_VALID_CTRL 5170 #define P_HCODEC_MC_CTRL_REG 4284638208 #define P_VPU_HDMI_DITH_11_37 4287668204 #define VDEC2_IMEM_DMA_COUNT 9026 #define P_VPU_VLOCK_RO_LOOP1_ACCUM 4287676476 #define GE2D_VSC_NRND_POINT 193 #define P_NR4_MCNR_ALP1_AND_BET0_REG 4287674120 #define P_MCDI_REL_DET_LPF_MSK_00_03 4287675616 #define HEVC_MINDEX6_REG 13072 #define P_VDEC2_F_CODE_REG 4284657672 #define P_VDEC2_ANC12_CANVAS_ADDR 4284655216 #define VDEC2_ASSIST_MBOX0_IRQ_REG 8304 #define ASYNC_FIFO_FILL_CNT_MSB 19 #define VDEC2_AVSP_IQ_WQ_PARAM_01 11801 #define P_AIU_CRC_CAL_REG0 4291842340 #define P_AIU_CRC_CAL_REG1 4291842336 #define ENCL_TST_MDSEL 7321 #define P_HCODEC_HENC_LEFT_MV_2 4284642624 #define P_HCODEC_HENC_LEFT_MV_1 4284642620 #define P_HCODEC_HENC_LEFT_MV_3 4284642628 #define P_HCODEC_HENC_LEFT_MV_0 4284642616 #define AUDIN_FIFO1_UG 15 #define P_AIU_MEM_AIFIFO_END_PTR 4291842584 #define P_MCDI_REL_DET_BAD_THD_1 4287675668 #define P_MCDI_REL_DET_BAD_THD_0 4287675664 #define DUAL_IDF 12 #define P_MCDI_REL_DET_RPT_CHK_THD_0 4287675604 #define P_MCDI_REL_DET_RPT_CHK_THD_1 4287675608 #define P_QDCT_JPEG_CTRL 4284644500 #define DE_POL 2 #define DCLK_SEL 14 #define P_ANC11_CANVAS_ADDR 4284622444 #define P_VLC_VB_RD_PTR 4284642380 #define P_ENCI_DE_V_BEGIN_ODD 4287655016 #define DI_MEM_RANGE_MAP_CR 6079 #define MDEC_PICW_BUF2_STATUS 2493 #define P_MBREAK_TYPE 4284615776 #define DI_MEM_RANGE_MAP_CB 6078 #define VDEC2_AVSP_IQ_WQ_PARAM_45 11803 #define DET3D_MAT_STA_P1M1 5944 #define DUAL_PRM_MOT 768 #define VPU_OSD4_MMC_CTRL 10008 #define HCODEC_ME_SAD_3 8036 #define HCODEC_ME_SAD_2 8035 #define HCODEC_ME_SAD_1 8034 #define HCODEC_ME_SAD_0 8033 #define P_VDEC2_DBLK_VLD_HCMD0 4284655088 #define VDEC2_MB_WIDTH 11273 #define P_VDEC2_DBLK_VLD_HCMD1 4284655084 #define P_VDEC2_DBLK_VLD_HCMD2 4284655080 #define AUDIN_FIFO1_DIN_SEL 3 #define NR2_MATNR_ALPHALP_LUT3 6002 #define ENCT_TST_CLRBAR_STRT 7213 #define NR2_MATNR_ALPHALP_LUT2 6001 #define NR2_MATNR_ALPHALP_LUT1 6000 #define NR2_MATNR_ALPHALP_LUT0 5999 #define HEVC_MC_STATUS1 14602 #define HEVC_MC_STATUS0 14601 #define VDEC2_AVSP_IQ_WQ_PARAM_23 11802 #define P_VPP_OUT_H_V_SIZE 4287657620 #define DOS_VDEC_INT_EN 16133 #define MCDI_MCVECRD_CANVAS_SIZE 12134 #define P_MCDI_PD22_CHK_GAIN_OFFST_1 4287675680 #define P_MCDI_PD22_CHK_GAIN_OFFST_0 4287675676 #define P_DVIN_FRONT_END_CTRL 4291830656 #define P_OSD1_AFBCD_PIXEL_HSCOPE 4287678116 #define VIU2_OSD1_BLK3_CFG_W0 7719 #define VIU2_OSD1_BLK3_CFG_W1 7720 #define P_HCODEC_MINT_VEC_BASE 4284632072 #define VIU2_OSD1_BLK3_CFG_W4 7702 #define VIU2_OSD1_BLK3_CFG_W2 7721 #define VIU2_OSD1_BLK3_CFG_W3 7722 #define P_VDEC2_VLD_ERROR_MASK 4284657848 #define P_VPU_PROT1_REQ_ONOFF 4287667568 #define HEVC_DBLK_CTRL 14673 #define P_DI_INTR_CTRL 4287651008 #define MIPI_DSI_DWC_TO_CNT_CFG_OS 7198 #define P_ENCT_VIDEO_MODE_ADV 4287656352 #define P_VDEC2_CPC_W 4284648612 #define P_HCODEC_CINDEX0_REG 4284632232 #define NR2_MATNR_ALPHAHP_LUT2 6005 #define NR2_MATNR_ALPHAHP_LUT3 6006 #define VDIN0_BLKBAR_CNT_THRESHOLD 4707 #define P_NR2_MATNR_BETA_BRT 4287651172 #define P_VDEC2_PSCALE_DRAM_BUF_CTRL 4284654724 #define NR2_MATNR_ALPHAHP_LUT0 6003 #define NR2_MATNR_ALPHAHP_LUT1 6004 #define DECOMB_DET_EDGE_CON0 11650 #define MCDI_RO_FLD_PD_22_PRE_CNT1 12234 #define HCODEC_SCD_BAK_MV_X 7190 #define MCDI_RO_FLD_PD_22_PRE_CNT2 12237 #define DECOMB_DET_EDGE_CON1 11651 #define HCODEC_SCD_BAK_MV_Y 7191 #define HCODEC_ASSIST_MBOX0_FIQ_SEL 4211 #define HEVC_VLD_STATUS 15418 #define SRSHARP0_PK_ALP2_ERR2CURV_TH_RATE 12831 #define MCDI_RO_FLD_BAD_REL_CNT 12197 #define P_HEVC_CURR_CANVAS_CTRL 4284671692 #define VDIN1_WR_H_START_END 5153 #define VPP_WRAP_OSD3_MATRIX_COEF22 15796 #define DI_MEM_CANVAS0 6108 #define P_HCODEC_VLC_MB_INFO 4284642516 #define P_INTRA_QUANT_MATRIX 4284626952 #define P_VDEC2_CPC_D 4284648604 #define ENCT_VIDEO_PB_SCL 7266 #define P_VENC_VIDEO_TST_CLRBAR_WIDTH 4287655384 #define P_ANC8_CANVAS_ADDR 4284622432 #define VPP2_SMOKE2_V_START_END 6448 #define P_VDEC2_CPC_E 4284648608 #define VIU2_VD1_IF0_LUMA1_RPT_PAT 7774 #define P_VDEC2_CPC_P 4284648600 #define P_ENCT_VFIFO2VD_PIXEL_START 4287656068 #define P_VDIN_COM_STATUS0 4287645716 #define P_VDIN_COM_STATUS3 4287646156 #define P_VDIN_COM_STATUS1 4287645720 #define P_VDIN_COM_STATUS2 4287645752 #define P_VDEC2_MC_MPORT_DAT 4284654852 #define P_ENCL_VIDEO_MODE_ADV 4287656608 #define P_OSD1_AFBCD_STATUS 4287678112 #define VPU_VIU_ASYNC_MASK 10113 #define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 13402 #define SRSHARP1_SHARP_SR2_CBIC_HCOEF1 13403 #define P_ENCI_DBG_FLDLN_INT 4287655212 #define RAM_TEST_CMD 2 #define ENCP_VIDEO_PR_OFFST 7050 #define V3_LEFT_INTRA_INFO 8055 #define SPDIF_CLKNUM_192K 24 #define P_HCODEC_ANC16_CANVAS_ADDR 4284638848 #define IEC958_TIME_STAMP_LENGTH 5287 #define P_MCDI_REL_DET_PD22_CHK 4287675592 #define HEVC_QP_CTRL_REG 15873 #define P_VIU_OSD1_MATRIX_PRE_OFFSET2 4287654500 #define P_HEVC_IQIDCT_CONTROL 4284676152 #define VPP_MATRIX_PROBE_POS 7518 #define VDIN1_BLKBAR_STATUS1 5228 #define P_DBLK_Y_BHFILT_HIGH 4284622176 #define VDIN1_BLKBAR_STATUS0 5227 #define MBBOT_EVEN_ADDR 7991 #define VPU_VD3_MMC_CTRL 10009 #define INV_CNT_MSB 3 #define VPP_SRSHARP1_CTRL 7570 #define P_DI_CHAN2_LUMA_FIFO_SIZE 4287651532 #define ABUF_WR_FF_PAUSE_LVL 0 #define P_VDIN_DOLBY_DSC_CTRL0 4287646164 #define VIU_OSD1_EOTF_CTL 6868 #define P_VDIN_DOLBY_DSC_CTRL1 4287646168 #define P_VDIN_DOLBY_DSC_CTRL2 4287646172 #define P_VDIN_DOLBY_DSC_CTRL3 4287646176 #define P_HCODEC_IE_CONTROL 4284644608 #define HEVC_ANC9_CANVAS_ADDR 14745 #define P_AUDIN_DECODE_CONTROL_STATUS 4291874892 #define GE2D_SRC1_DEF_COLOR 166 #define P_PCMIN_CTRL2 4291875208 #define P_VDEC2_VOFF_STATUS 4284657904 #define P_PCMIN_CTRL0 4291875200 #define P_PCMIN_CTRL1 4291875204 #define OSD_DB_FLT_SEED3 12617 #define OSD_DB_FLT_SEED5 12619 #define OSD_DB_FLT_SEED4 12618 #define P_VLD_MEM_VIFIFO_BYTES_AVAIL 4284625164 #define P_MB_SKIP_RUN 4284642636 #define VDIN_MATRIX_COEF11_12 4627 #define P_VDEC2_WRRSP_VLD 4284655464 #define SRSHARP0_SR3_DRTLPF_THETA 12915 #define VPP_SMOKE3_V_START_END 7474 #define VPU_PROT3_CLK_GATE 10096 #define CINDEX6_REG 816 #define P_VPP2_VADJ2_MA_MB 4287653140 #define ENCT_VIDEO_YFP1_HTIME 7277 #define ENCL_SYNC_TO_LINE_EN 7246 #define HEVC_CBREAK1_REG 13109 #define VPP_POST2_MATRIX_CLIP 14760 #define DNR_DM_SDIF_LUT0_2 11629 #define P_HCODEC_VLD_TIME_STAMP_1 4284641588 #define L_HSYNC_HS_ADDR 5205 #define P_HCODEC_VLD_TIME_STAMP_2 4284641592 #define P_MDEC_PICW_BUF_STATUS 4284622568 #define P_HCODEC_VLD_TIME_STAMP_0 4284641584 #define P_HCODEC_VLD_TIME_STAMP_3 4284641596 #define AIU_CRC_BIT_SIZE1 5196 #define AIU_CRC_BIT_SIZE0 5197 #define HCODEC_DBLK_CBPY 6512 #define P_MCDI_MCVECWR_CANVAS_SIZE 4287675796 #define P_DET3D_RO_MAT_VEDG_LR 4287651372 #define P_DI_EI_CTRL11 4287651448 #define P_DI_EI_CTRL10 4287651404 #define ENCT_VIDEO_YFP2_HTIME 7278 #define HCODEC_DBLK_CBPC 6514 #define SPI_FLASH_USR_DUMMY_BLEN 10 #define P_HCODEC_MFDIN_REG7_SCMD 4284629052 #define P_DI_EI_CTRL13 4287651488 #define P_HCODEC_QDCT_PIC_INFO 4284644460 #define P_DI_EI_CTRL12 4287651452 #define P_AUDIN_FIFO2_PIO_RDL 4291875548 #define P_HCODEC_MC_CMD 4284638232 #define P_AUDIN_FIFO2_PIO_RDH 4291875552 #define VDEC2_VLD_DBG_INDEX 11326 #define MIPI_DSI_DWC_PWR_UP_OS 7169 #define ENCL_VIDEO_BLANKY_VAL 7356 #define P_HEVC_SAO_Y_WPTR 4284667964 #define NR4_RO_NM_SAD_CNT 14112 #define P_VDIN_HIST_SPL_PIX_CNT 4287645908 #define P_ME_DEBUG 4284644656 #define SRSHARP1_PK_OS_ADPT_MISC 13349 #define ENCT_VIDEO_FILT_CTRL 7298 #define P_VLD_MEM_SWAP_CTL 4284625240 #define P_HEVC_DBLK_CFG1 4284666884 #define OSD1_AFBCD_PIXEL_HSCOPE 12713 #define P_HEVC_DBLK_CFG0 4284666880 #define P_HEVC_DBLK_CFG3 4284666892 #define P_HEVC_DBLK_CFG2 4284666888 #define HCODEC_ME_SUB_MERGE_CTL 8025 #define P_VPU_PROT2_Y_START_END 4287667596 #define P_SHARP_PKOSHT_VSLUMA_LUT_H 4287678480 #define P_HEVC_DBLK_CFGA 4284666920 #define P_HEVC_DBLK_CFGC 4284666928 #define P_SHARP_PKOSHT_VSLUMA_LUT_L 4287678476 #define P_HEVC_DBLK_CFGB 4284666924 #define P_HEVC_DBLK_CFG5 4284666900 #define P_HEVC_DBLK_CFG4 4284666896 #define HEVC_MPRED_L0_REF04_POC 12836 #define P_HEVC_DBLK_CFG7 4284666908 #define P_HEVC_DBLK_CFG6 4284666904 #define HCODEC_CBREAK_CTRL 4921 #define P_HEVC_DBLK_CFG9 4284666916 #define P_HEVC_DBLK_CFG8 4284666912 #define DET3D_MAT_STA_P1TH 5945 #define ENCP_MACV_EN 7042 #define P_HCODEC_DBLK_QP 4284638552 #define P_MCDI_MCVECRD_CANVAS_SIZE 4287675800 #define ASYNC_FIFO_FILL_CNT_LSB 0 #define VDIN0_BLKBAR_IND_LEFT2_CNT 4712 #define RESET6_MASK 1046 #define P_ENCI_VFIFO2VD_LINE_TOP_END 4287656048 #define P_HCODEC_VLC_ENC_PEND_CMD 4284642520 #define P_DET3D_RO_MAT_VEDG_TB 4287651376 #define HCODEC_V3_TOP_LEFT_CTL 8045 #define VDEC2_ASSIST_DMA_INT2 8294 #define P_DECOMB_CMB_SEL_GAIN_OFST 4287673892 #define HEVC_MPRED_L1_REF03_POC 12851 #define P_RGB_BASE_ADDR 4287648276 #define P_EE_ASSIST_MBOX1_IRQ_REG 4291854800 #define PSCALE_CMD_CTRL 2331 #define HEVC_MC_CTRL_GCLK_CTRL 14669 #define P_VPU_PROT3_RPT_LOOP 4287667668 #define HEVC_SLICE_QP 15370 #define CDB_CTRL 829 #define PWM_DELTA_SIGMA_AB 27651 #define P_PSCALE_BMEM_ADDR 4284621948 #define P_VPU_MISC_CTRL 4287667456 #define P_VLC_VB_END_PTR 4284642372 #define STREAM_WAIT_IRQ_CONFIG 11270 #define P_VDEC2_PSCALE_CTRL2 4284654776 #define P_VDEC2_PSCALE_CTRL1 4284654756 #define P_HEVC_ANC21_CANVAS_ADDR 4284671636 #define P_AIU_958_DISCARD_NUM 4291842072 #define P_MCDI_RO_RPT_MV 4287676084 #define PWM_DELTA_SIGMA_CD 26627 #define VDEC2_DBLK_Y_BVFILT 10585 #define XVYCC_INV_LUT_CTL 12644 #define LDIM_STTS_MATRIX_PROBE_POS 6861 #define VPP2_DNLP_CTRL_08 6537 #define VPP2_DNLP_CTRL_09 6538 #define VPP2_DNLP_CTRL_06 6535 #define VPP2_DNLP_CTRL_07 6536 #define VPP2_DNLP_CTRL_04 6533 #define VPP2_DNLP_CTRL_05 6534 #define VPP2_DNLP_CTRL_02 6531 #define VPP2_DNLP_CTRL_03 6532 #define VPP2_DNLP_CTRL_00 6529 #define VPP2_DNLP_CTRL_01 6530 #define P_ENCP_DE_H_BEGIN 4287656168 #define P_DBKR_CANVAS_ADDR 4284622528 #define P_AIU_AIFIFO2_GBIT 4291842312 #define P_HEVC_ANC12_CANVAS_ADDR 4284671600 #define VPP2_DNLP_CTRL_15 6544 #define VPP2_DNLP_CTRL_13 6542 #define VPP2_DNLP_CTRL_14 6543 #define VPP2_DNLP_CTRL_11 6540 #define VPP2_DNLP_CTRL_12 6541 #define VLC_PIC_SIZE 7473 #define VPP2_DNLP_CTRL_10 6539 #define P_VDEC2_HDEC_MC_MBRIGHT_IDX 4284654788 #define P_UART0_REG5 4291969044 #define mLVDS_MLSB_SWAP 2 #define P_NR2_MATNR_BETA_EGAIN 4287651168 #define SRSHARP0_SR3_SAD_CTRL 12897 #define P_EE_ASSIST_MBOX3_FIQ_SEL 4291854844 #define AFBC_HEAD_BADDR 6886 #define HCODEC_MB_WIDTH 7177 #define P_D2D3_SCALER_CTRL 4287671320 #define VPU_ARB_DBG_CTRL_L2C1 10167 #define HCODEC_DBLK_VHMVD 6516 #define P_VDEC2_ANC11_CANVAS_ADDR 4284655212 #define ENCP_VFIFO2VD_PIXEL_END 7002 #define VPU_VENCX_CLK_CTRL 10117 #define ENCP_MACV_1ST_PSSYNC_STRT 7106 #define P_VENC_VDAC_DAC0_FILT_CTRL0 4287656288 #define P_VENC_VDAC_DAC0_FILT_CTRL1 4287656292 #define VPP2_OSD_SCALE_COEF 6605 #define P_LCD_PORT_SWAP 4287648216 #define P_VDEC2_ASSIST_MBOX2_IRQ_REG 4284645856 #define ENCT_VFIFO2VD_LINE_BOT_END 7206 #define WM_SYMBOLS_NUM 12722 #define MINDEX5_REG 783 #define P_C656_FS_LNED 4287655836 #define HCODEC_MDEC_DOUBLEW_CFG7 6626 #define HCODEC_MDEC_DOUBLEW_CFG6 6625 #define HCODEC_MDEC_DOUBLEW_CFG5 6624 #define HCODEC_MDEC_DOUBLEW_CFG4 6623 #define P_ENCP_MACV_AGC_END 4287655700 #define HCODEC_MDEC_DOUBLEW_CFG3 6622 #define HCODEC_MDEC_DOUBLEW_CFG2 6621 #define HCODEC_MDEC_DOUBLEW_CFG1 6620 #define P_VIU_OSD1_MATRIX_COEF20_21 4287654480 #define HCODEC_MDEC_DOUBLEW_CFG0 6619 #define P_DVIN_HS_LEAD_VS_ODD 4291830660 #define P_AIU_AUDAC_CTRL0 4291842380 #define GE2D_VSC_PHASE_SLOPE 186 #define HDEC_MC_MBRIGHT_IDX 2353 #define VDEC2_ANC22_CANVAS_ADDR 10662 #define P_DNR_RO_HBOF_STAT_CNT_30 4287673580 #define P_DNR_RO_HBOF_STAT_CNT_31 4287673584 #define DITH10_CNTL_MSB 7 #define P_OSD_BLENDO_H_START_END 4287654564 #define HEVC_SAO_TILE_SIZE_LCU 13832 #define HUE_SAT_RANGE_REG01 10 #define HUE_SAT_RANGE_REG00 4 #define P_RESET5_REGISTER 4291825688 #define ANC14_CANVAS_ADDR 2462 #define HCODEC_VLD_MEM_VIFIFO_LEVEL 7239 #define P_VD2_AFBC_STAT 4287677992 #define HUE_SAT_RANGE_REG07 46 #define ENCL_VIDEO_YFP2_HTIME 7342 #define HUE_SAT_RANGE_REG06 40 #define HUE_SAT_RANGE_REG03 22 #define HUE_SAT_RANGE_REG02 16 #define HUE_SAT_RANGE_REG05 34 #define MLVDS_RESET_PATTERN_LO 5317 #define VSYNC_VE_ADDR 5340 #define HUE_SAT_RANGE_REG04 28 #define NR4_MCNR_SKIN_CLIP0 11733 #define PWM_DELTA_SIGMA_EF 25603 #define NR4_MCNR_SKIN_CLIP1 11734 #define MC_IMEM_PT0 64 #define P_GE2D_HSC_INI_CTRL 4287890168 #define P_HEVC_VLD_MEM_VBUF2_RD_PTR 4284674384 #define P_ENCT_VFIFO2VD_LINE_BOT_START 4287656084 #define VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT 11345 #define HCODEC_CINT_VEC_BASE 4898 #define P_VIU_OSD2_MATRIX_COEF00_01 4287654596 #define PSCALE_RST 2320 #define P_VPP2_MATRIX_COEF02_10 4287653252 #define ENCL_DBG_PX_RST 7337 #define P_ENCI_VIDEO_MODE 4287654912 #define P_MCDI_MC_CRTL 4287675840 #define MLVDS_RESET_PATTERN_HI 5316 #define P_L_STH1_HE_ADDR 4287647812 #define P_OSD_DB_FLT_CTRL1 4287677700 #define P_MDB_DATA_REG 4284615792 #define VLC_MB_HEADER_INFO 7486 #define P_VDIN_MATRIX_COEF02_10 4287645768 #define P_AVSP_IQ_CTL 4284627056 #define P_HEVC_MPRED_DBG2_MODE 4284664076 #define DUAL_ISF 9 #define P_HEVC_RESYNC_MARKER_LENGTH 4284674104 #define P_HEVCD_MPP_L1_WEIGHT_FLAG_ADDR 4284666356 #define ENCP_VIDEO_BLANKPB_VAL 7091 #define HEVC_DBLK_GCLK_FREE 14700 #define P_DNR_RO_HBOF_STAT_CNT_27 4287673568 #define P_DNR_RO_HBOF_STAT_CNT_28 4287673572 #define P_DNR_RO_HBOF_STAT_CNT_29 4287673576 #define P_DNR_RO_HBOF_STAT_CNT_23 4287673552 #define P_DNR_RO_HBOF_STAT_CNT_24 4287673556 #define P_DNR_RO_HBOF_STAT_CNT_25 4287673560 #define P_DNR_RO_HBOF_STAT_CNT_26 4287673564 #define VPU_VPU_3D_SYNC1 10040 #define VPU_VPU_3D_SYNC2 10041 #define P_DNR_RO_HBOF_STAT_CNT_20 4287673540 #define P_DNR_RO_HBOF_STAT_CNT_21 4287673544 #define P_DNR_RO_HBOF_STAT_CNT_22 4287673548 #define P_VLD_DC_PRED_C 4284625084 #define HCODEC_WRRSP_DCAC 6617 #define P_DNR_RO_HBOF_STAT_CNT_16 4287673524 #define SRSHARP0_PK_DRTFB_HP_CORING 12817 #define P_DNR_RO_HBOF_STAT_CNT_17 4287673528 #define P_DNR_RO_HBOF_STAT_CNT_18 4287673532 #define P_DNR_RO_HBOF_STAT_CNT_19 4287673536 #define P_DNR_RO_HBOF_STAT_CNT_12 4287673508 #define P_DNR_RO_HBOF_STAT_CNT_13 4287673512 #define P_DNR_RO_HBOF_STAT_CNT_14 4287673516 #define P_DNR_RO_HBOF_STAT_CNT_15 4287673520 #define P_DNR_RO_HBOF_STAT_CNT_10 4287673500 #define P_DNR_RO_HBOF_STAT_CNT_11 4287673504 #define P_V3_TOP_MV 4284644792 #define P_VPP_SMOKE3_VAL 4287657136 #define RESET6_REGISTER 1031 #define P_HCODEC_MC_IDCT_DAT 4284638512 #define AUDIN_ADDR_END 13512 #define MDEC_PICR_BUF_STATUS 2489 #define P_VPU_PROT1_DDR 4287667548 #define P_C656_FS_LNST 4287655832 #define P_IEC958_TIME_STAMP_CNTL 4291842688 #define HCODEC_MBREAK_CTRL 4889 #define IMEM_DMA_CTRL 832 #define DI_IF1_LUMA_X0 6122 #define P_HCODEC_VLC_MB_HEADER_INFO 4284642552 #define ENCP_VIDEO_MAX_PXCNT 7063 #define P_C_D_BUS_CONTROL 4291866632 #define SPI_READ_READ_EN 13 #define HEVC_IQ_QUANT 15895 #define VCTI_BST_GAIN 12864 #define AFBC_LBUF_DEPTH 6885 #define P_HCODEC_PSCALE_CMD_BLK_X 4284638320 #define P_HCODEC_PSCALE_CMD_BLK_Y 4284638324 #define VD1_IF0_LUMA_Y1 6744 #define P_VPU_PROT1_RBUF_ROOM 4287667552 #define VD1_IF0_LUMA_Y0 6740 #define NR_DB_FLT_YC_THRD 14137 #define P_VPU_VIU2VDIN_HDN_CTRL 4287667712 #define VPP_OSD_SCO_V_START_END 7627 #define P_VIDEO_PTS_DTS_WR_PTR 4291879376 #define P_ENCI_SYNC_VSO_EVN 4287654960 #define DI_IF1_LUMA_Y0 6123 #define P_DOLBY_TV_REG_START 4287679488 #define MC_HCMD_L 2379 #define MC_HCMD_H 2378 #define P_GE2D_MATRIX_PRE_OFFSET 4287890196 #define P_LDIM_STTS_MATRIX_COEF00_01 4287654668 #define P_HEVC_MPRED_L1_REF04_POC 4284664016 #define MCDI_RO_PD_22_FLG 12207 #define PARSER_SEARCH_PATTERN 14441 #define VD1_IF0_LUMA_X0 6739 #define VD1_IF0_LUMA_X1 6743 #define P_MDEC_PIC_DC_STATUS 4284622396 #define ENCP_VIDEO_VSO_ELINE 7084 #define P_VDEC2_CCPU_INTR_GRP 4284648588 #define P_AIU_CRC_CTRL 4291842320 #define HEVC_SAO_MMU_WR 13880 #define IQIDCT_ENABLE 4 #define P_RDMA_STATUS 4287644756 #define VDEC2_NEXT_ALIGN_PEAK 11293 #define HEVC_MDEC_EXTIF_CFG1 14821 #define HEVC_MDEC_EXTIF_CFG0 14820 #define P_WM_THRES_ADDR_PORT 4287678252 #define P_QDCT_PIC_INFO 4284644460 #define MCDI_RO_FLD_BAD_SAD_CNT 12195 #define P_HCODEC_VLC_HCMD_CONFIG 4284642640 #define VIU2_OSD2_HL2_H_START_END 7733 #define HEVC_IQIT_SCALELUT_DATA 14084 #define P_ENCL_VIDEO_Y_SCL 4287656580 #define P_DI_MEM_GEN_REG 4287651692 #define VPP_WRAP_OSD1_MATRIX_COEF20_21 15715 #define HEVC_MC_PIC_W_H 14600 #define ENCP_VIDEO_SYNC_OFFST 7051 #define P_HCODEC_VLC_COEFF_INFO 4284642572 #define HCODEC_ANC1_CANVAS_ADDR 6545 #define SPI_FLASH_USER 20487 #define NR4_MCNR_LUMAPRE_CAL_PRAM 11708 #define HCODEC_FST_FOR_MV_X 7184 #define HCODEC_FST_FOR_MV_Y 7185 #define P_DNR_VBOFFST_STAT 4287673368 #define P_VPP_VDO_MEAS_CTRL 4287657632 #define P_VLC_PUSH_ELEMENT 4284642432 #define HCODEC_CPC_P 4902 #define HCODEC_CPC_E 4904 #define HCODEC_CPC_D 4903 #define P_VDEC2_MBREAK_STAUTS 4284648552 #define VPP2_PREBLEND_VD1_V_START_END 6427 #define P_RDMA_STATUS3 4287644764 #define P_RDMA_STATUS2 4287644760 #define ENCP_VIDEO_OFLD_VPEQ_OFST 7097 #define VDEC_ASSIST_AMR1_INTF 52 #define VDEC_ASSIST_AMR1_INTB 48 #define VDEC_ASSIST_AMR1_INTC 49 #define VDEC_ASSIST_AMR1_INTD 50 #define VDEC_ASSIST_AMR1_INTE 51 #define DI_CHAN2_RANGE_MAP_CB 6069 #define P_HCODEC_MFDIN_REG0_CRST 4284629024 #define MCDI_MCINFOWR_CANVAS_SIZE 12135 #define SPDIF_REVERSE_EN 22 #define VPU_VLOCK_LOOP1_PHSDIF_TGT 12301 #define VDEC_ASSIST_MBOX2_FIQ_SEL 123 #define DI_CHAN2_RANGE_MAP_CR 6070 #define HEVC_M4_CONTROL_REG 15401 #define GE2D_CMD_CTRL 163 #define HEVC_PARSER_INT_CONTROL 12576 #define DNR_DB_CVDELTA_GAIN 11543 #define P_HCODEC_RV_AI_MB_COUNT 4284643376 #define ENCT_VIDEO_HAVON_BEGIN 7282 #define GE2D_VSC_START_PHASE_STEP 185 #define P_HCODEC_VLC_TOTAL_BYTES 4284642408 #define SRSHARP0_PK_CON_2DRTHPGAIN_TH_RATE 12809 #define HCODEC_VLC_ENC_MV_BITS 7516 #define P_HCODEC_SAD_CONTROL_1 4284644588 #define P_HCODEC_SAD_CONTROL_0 4284644584 #define P_VDEC2_PSCALE_RST 4284654656 #define P_VBO_INSGN_CTRL 4287648744 #define P_VDIN_MEAS_CTRL0 4287646056 #define V5_SIMPLE_MB_ME_WEIGHT 8064 #define NR4_MCNR_LMV_PARM 11712 #define MCDI_MCINFORD_Y 12188 #define P_NR2_MOTION2BETA_LUT2 4287651232 #define P_NR2_MOTION2BETA_LUT3 4287651236 #define P_NR2_MOTION2BETA_LUT0 4287651224 #define P_NR2_MOTION2BETA_LUT1 4287651228 #define P_HCODEC_VLC_P_MB_HEADER_INFO 4284642556 #define P_ENCP_DVI_VSO_ELINE_EVN 4287656144 #define MCDI_MCINFORD_X 12187 #define ASSIST_POR_CONFIG 8277 #define P_ENCI_VBI_TTX_HTIME 4287655080 #define VPU_ARB_DBG_CTRL_L1C2 10165 #define P_DEBLK_CMD 4284627008 #define VPU_ARB_DBG_CTRL_L1C1 10163 #define P_VDEC2_ANC5_CANVAS_ADDR 4284655188 #define P_VBO_STATUS_H 4287648208 #define P_VBO_STATUS_L 4287648204 #define P_HCODEC_MFDIN_REG2_STAT 4284629032 #define L_DE_HS_ADDR 5201 #define VDEC_ASSIST_AMR1_INT6 43 #define VDEC_ASSIST_AMR1_INT7 44 #define VDEC_ASSIST_AMR1_INT8 45 #define VDEC_ASSIST_AMR1_INT9 46 #define P_GE2D_SRC2_Y_START_END 4287890124 #define VDEC_ASSIST_AMR1_INT2 39 #define VDEC_ASSIST_AMR1_INT3 40 #define VDEC_ASSIST_AMR1_INT4 41 #define VDEC_ASSIST_AMR1_INT5 42 #define VDEC_ASSIST_AMR1_INTA 47 #define VENC_VDAC_DAC1_OFFSET 7155 #define HCODEC_ANC17_CANVAS_ADDR 6561 #define P_HCODEC_DBLK_CR_FILT 4284638592 #define VDEC_ASSIST_AMR1_INT0 37 #define VDEC_ASSIST_AMR1_INT1 38 #define VPP2_SMOKE1_V_START_END 6446 #define P_VIUB_ADDR_START 4287660032 #define DNR_DM_SDIF_LUT3_5 11630 #define P_ENCL_VIDEO_MAX_LNCNT 4287656684 #define P_VIU2_OSD1_TEST_RDDATA 4287658288 #define HCODEC_CPC_W 4905 #define P_VENC_VDAC_DAC2_GAINCTRL 4287655888 #define HEVC_CDB_CTRL 13117 #define HCODEC_VLC_WRRSP 7449 #define P_HCODEC_DBLK_STATUS1 4284638636 #define P_HCODEC_MC_HALF_PEL_ONE 4284638220 #define P_HEVC_IQIT_AVS2_WQP_0123 4284668980 #define SRSHARP1_NR_ALP0C_ERR2CURV_TH_RATE 13335 #define LCD_PWR_ADDR 5307 #define P_VPP_DOLBY_CTRL 4287657548 #define GE2D_SRC1_RANGE_MAP_CB_CTRL 228 #define P_AUDIN_FIFO2_PTR 4291875100 #define P_CINDEX3_REG 4284615860 #define P_VDEC2_MCPU_INTR_REQ 4284648468 #define GAMMA_CNTL_PORT 5248 #define P_HCODEC_ME_SUB_ACT_CTL 4284644732 #define P_PK_FINALGAIN_HP_BP 4287678600 #define P_VDEC2_SLICE_VER_POS_PIC_TYPE 4284657680 #define P_VD1_IF0_CHROMA0_RPT_PAT 4287654260 #define VDEC2_POWER_CTL_VLD 11272 #define VIU_OSD2_BLK0_CFG_W3 6718 #define VIU_OSD2_BLK0_CFG_W2 6717 #define VIU_OSD2_BLK0_CFG_W1 6716 #define VIU_OSD2_BLK0_CFG_W0 6715 #define P_VPP2_HSC_REGION34_STARTP 4287652932 #define VPP_HSC_REGION3_PHASE_SLOPE 7446 #define VIU_OSD2_BLK0_CFG_W4 6756 #define P_VPP_FRONT_HLTI_CTRL 4287657708 #define ME_PIC_INFO 8015 #define CINT_VEC_BASE 802 #define P_VDEC2_PSCALE_PICO_H 4284654676 #define P_DUAL_PORT_CNTL_ADDR 4287648520 #define P_HCODEC_CBREAK3_REG 4284632284 #define P_MDB_ADDR_REG 4284615788 #define SANA_STREAM_LEVEL 12325 #define P_VDEC2_PSCALE_PICO_W 4284654672 #define AIFIFO2_TIME_STAMP_LENGTH 5279 #define VLC_VB_MEM_CTL 7447 #define HEVC_MPRED_L1_REF15_POC 12863 #define P_AUDIN_FIFO2_INTR 4291875104 #define VD2_IF0_LUMA1_RPT_PAT 6782 #define P_VIU_OSD2_TEST_RDDATA 4287654192 #define P_VPP_HCTI_DN_FLT 4287657804 #define P_NR3_CMOT_PARA 4287676368 #define P_HEVC_IQIT_AVS2_WQP_45 4284668984 #define P_NR2_MET_NM_TNR 4287651104 #define P_VPU_ARB4_V1_MMC_CTRL 4287667372 #define VIU2_VD1_FMT_CTRL 7784 #define P_DI_INP_CHROMA0_RPT_PAT 4287651672 #define HEVC_VLD_MEM_VBUF_RD_PTR 15443 #define P_LTI_CTI_DF_GAIN 4287678640 #define GE2D_SRC1_KEY 206 #define P_DBLK_CBUS_HCMD2 4284622300 #define P_DBLK_CBUS_HCMD1 4284622304 #define P_DBLK_CBUS_HCMD0 4284622308 #define P_VPP2_HSC_REGION1_PHASE_SLOPE 4287652948 #define P_VPP2_SC_GCLK_CTRL 4287653328 #define ABUF_RD_CUR_FF_CNT_MSB 21 #define P_VDEC2_M4_TABLE_SELECT 4284657824 #define PARSER_AUDIO_START_PTR 14469 #define DI_BLEND_CTRL 5901 #define P_VPP2_LINE_IN_LENGTH 4287652868 #define MCDI_REL_SAD_GAIN_OFFST_01 12069 #define NR2_POLAR3_PARA0 11674 #define C_DATA 11267 #define NR2_POLAR3_PARA1 11675 #define P_VDIN_BLKBAR_CNT_THRESHOLD 4287646092 #define VPU_VLOCK_MX4096 12310 #define XVYCC_LUT_R_DATA_PORT 12639 #define P_VCOM_VE_ADDR 4287648376 #define SRSHARP1_NR_TI_DNLP_BLEND 13353 #define P_HCODEC_HDEC_MC_OMEM_AUTO 4284638400 #define AIU_I2S_DAC_CFG 5136 #define F_CODE_REG 3074 #define P_HEVC_WRRSP_DCAC 4284671844 #define P_VD1_IF0_LUMA1_RPT_PAT 4287654264 #define MCDI_REL_SAD_GAIN_OFFST_23 12070 #define P_AUDOUT_BUF1_STA 4291875348 #define P_HEVC_MBREAK_CTRL 4284664932 #define P_OSD_DB_FLT_CHRM_THRD 4287677708 #define HCODEC_DC_AC_SCALE_DIV 7687 #define P_CSFTINT0 4284615928 #define P_CSFTINT1 4284615932 #define P_GE2D_ANTIFLICK_ALPHA_FILT1 4287890300 #define P_GE2D_ANTIFLICK_ALPHA_FILT0 4287890296 #define P_GE2D_ANTIFLICK_ALPHA_FILT3 4287890308 #define P_GE2D_ANTIFLICK_ALPHA_FILT2 4287890304 #define P_VD1_IF0_CHROMA_Y1 4287654248 #define P_DI_IF2_LUMA_Y0 4287660108 #define P_VD1_IF0_CHROMA_Y0 4287654232 #define P_HEVC_SAO_IF_STATUS 4284662976 #define AIU_ACODEC_CTRL 5164 #define P_DET3D_MAT_STA_M1TH 4287651048 #define P_DNR_DB_YEDGE_THD 4287673388 #define P_HCODEC_VLC_VB_RD_PTR 4284642380 #define ENCP_VIDEO_SY_VAL 7088 #define P_VD1_IF0_CHROMA_X1 4287654244 #define P_VD1_IF0_CHROMA_X0 4287654228 #define MBBOT_ODD_ADDR 7992 #define P_ANC7_CANVAS_ADDR 4284622428 #define P_DI_IF2_LUMA_X0 4287660104 #define P_MINT_VEC_BASE 4284615688 #define P_HCODEC_IE_WEIGHT 4284644564 #define VD2_IF0_LUMA_PSEL 6784 #define HEVC_ANC22_CANVAS_ADDR 14758 #define SRSHARP0_NR_ALP1_ERR2CURV_LIMIT 12828 #define P_VLC_SPECIAL_CTL 4284642440 #define P_VIU_OSD2_MATRIX_COEF22 4287654612 #define VDEC2_ASSIST_MBOX2_MASK 8314 #define VDEC2_ASSIST_DMA_INT 8292 #define P_XVYCC_VD1_RGB_CTRST 4287677888 #define VPP_OSD1_IN_SIZE 7665 #define HEVC_DBLK_CLIP_CTRL0 14690 #define HEVC_DBLK_CLIP_CTRL5 14695 #define HEVC_DBLK_CLIP_CTRL6 14696 #define HEVC_DBLK_CLIP_CTRL7 14697 #define HEVC_DBLK_CLIP_CTRL8 14698 #define HEVC_DBLK_CLIP_CTRL1 14691 #define HEVC_DBLK_CLIP_CTRL2 14692 #define HEVC_DBLK_CLIP_CTRL3 14693 #define HEVC_DBLK_CLIP_CTRL4 14694 #define C656_HS_ST 7136 #define DI_MEM_DUMMY_PIXEL 6116 #define HEVC_SHIFT_LENGTH_PROTECT 12602 #define HCODEC_QDCT_VLC_QUANT_CTL_0 7996 #define HCODEC_QDCT_VLC_QUANT_CTL_1 7997 #define VPU_OSD2_MMC_CTRL 9986 #define P_HCODEC_VLC_VB_SW_RD_PTR 4284642384 #define P_HCODEC_ME_SAD_RANGE_INC 4284644704 #define MCDI_REL_DET_LUT_8_11 12096 #define VIU_OSD1_MATRIX_CTRL 6800 #define P_CCPU_INTR_REQ 4284615828 #define SRSHARP1_HCTI_BST_CORE 13360 #define P_MCDI_MCINFOWR_CTRL 4287676008 #define ENCP_VBI_WIDTH 7123 #define VPP_HSC_INI_PAT_CTRL 7477 #define P_MEDIA_CPU_INTR_STAT_CLR 4291883172 #define VDIN0_WIDTHM1I_WIDTHM1O 4618 #define MC_PIC_INFO 2306 #define P_DI_IF2_FMT_W 4287660160 #define HCODEC_ME_AB_MEM_CTL 8014 #define VDIN1_SCIN_HEIGHTM1 5157 #define P_NR_DB_FLT_CTRL 4287683808 #define P_HEVC_DBLK_BETAX_QP_SEL 4284671364 #define P_DNR_DB_CEDGE_THD 4287673392 #define P_AFBC_CONV_CTRL 4287654800 #define VDEC2_VOFF_STATUS 11324 #define AFBC_OUT_YSCOPE 6889 #define P_VDEC2_ANC21_CANVAS_ADDR 4284655252 #define P_AO_CPU_IRQ_IN0_INTR_MASK 4291883080 #define VDEC2_POWER_CTL_IQIDCT 11784 #define P_VDIN_MATRIX_OFFSET0_1 4287645784 #define P_HEVC_IQIT_IF_WAIT_CNT 4284663000 #define P_L_CPV1_VE_ADDR 4287647880 #define P_AO_CPU_IRQ_IN0_INTR_STAT 4291883072 #define P_VDEC2_VLD_SHIFT_STATUS 4284657900 #define TCON_INVERT_CTL 7015 #define P_HCODEC_VLC_MV 4284642596 #define P_VPP_BLEND_ONECOLOR_CTRL 4287657100 #define SRSHARP0_DB_FLT_PXI_THRD 12922 #define P_VPU_MCVEC_MMC_CTRL 4287667380 #define VPU_VDIN1_MMC_CTRL 9998 #define P_VPU_PROT1_X_START_END 4287667528 #define QDCT_MB_WR_PTR 7954 #define P_PARSER_SCR 4291879352 #define P_VBO_INTR_STATE_CTRL 4287648240 #define P_UART1_REG5 4291964948 #define P_HCODEC_PSCALE_MCMD_CTRL 4284638344 #define VDEC2_MPSR 8961 #define VDEC2_VLD_MEM_VIFIFO_WP 11333 #define DEMO_POI_S_REG 532 #define P_DI_MTNRD_CTRL 4287651636 #define VDEC2_DC_AC_SCALE_MUL 11782 #define P_AFBC_DEC_DEF_COLOR 4287654796 #define C656_HS_ED 7137 #define VPP_WRAP_OSD3_MATRIX_COEF02_10 15793 #define P_DI_MC_REG2_X 4287650960 #define P_NR2_MET_NM_YCTRL 4287651096 #define P_DI_MC_REG2_Y 4287650964 #define P_VP9_LEFT_Y_MODE_1 4284663060 #define HCODEC_ACC1REG1 4962 #define D2D3_DRMIF_HPOS 11049 #define HCODEC_ACC1REG2 4978 #define VDEC2_CCPU_INTR_GRP 8995 #define CPH3_POL 8 #define SRSHARP0_SR3_DERING_LUMA2PKOS_4TO6 12911 #define VIU_OSD1_MATRIX_COEF00_01 6801 #define P_AIU_HDMI_CLK_DATA_CTRL 4291842216 #define AUDIN_FIFO0_INTR 13347 #define I2C_M_DELAY_LSB 12 #define P_VPU_OSD4_MMC_CTRL 4287667296 #define P_DBLK_CBPY_ADJ 4284622276 #define P_SCD_BAK_MV_Y 4284624988 #define P_SCD_BAK_MV_X 4284624984 #define P_GE2D_ALU_OP_CTRL 4287890224 #define P_VP9_LEFT_Y_MODE_0 4284663056 #define VIU2_RMIF_CTRL1 7809 #define VIU2_RMIF_CTRL0 7808 #define NR4_MCNR_GREEN_CENT 11725 #define P_HEVC_CINDEX7_REG 4284665028 #define P_AIU_AIFIFO2_STATUS 4291842308 #define L_GAMMA_PROBE_COLOR_H 5131 #define VPU_MCINF_MMC_CTRL 10030 #define P_CINT_VEC_BASE 4284615816 #define VPP_MATRIX_COEF23_24 7644 #define L_GAMMA_PROBE_COLOR_L 5130 #define P_PARSER_AUDIO_END_PTR 4291879448 #define P_VIU_OSD1_EOTF_CTL 4287654736 #define VDEC2_DBLK_CR_FILT 10592 #define P_VDEC2_CBREAK3_REG 4284648668 #define P_VLTI_FLT_CON_CLP 4287678696 #define PSCALE_CANVAS_RD_ADDR 2348 #define VIDEO_FRM_BUF_MSB_BIT 23 #define P_HCODEC_VLC_DC 4284642584 #define P_VPP_OSD_HSC_CTRL0 4287657748 #define VPP_MATRIX_COEF11_12 7522 #define P_VDEC2_ANC10_CANVAS_ADDR 4284655208 #define PK_CON_2CIRHPGAIN_TH_RATE 12805 #define P_HDEC_MC_MBRIGHT_IDX 4284622020 #define VDIN1_MATRIX_CTRL 5136 #define I2SIN_DIR 0 #define HCODEC_VLC_MV 7497 #define P_HCODEC_NEXT_ALIGN_PEAK 4284641396 #define QDCT_DCT_STATUS 7961 #define P_PARSER_SCR_CTL 4291879348 #define P_HEVC_VLD_MEM_VIFIFO_BUF_CNTL 4284674336 #define P_HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL 4284674316 #define P_HCODEC_ASSIST_MBOX0_CLR_REG 4284629444 #define P_VPU_PROT3_MMC_CTRL 4287667368 #define VDIN0_HSC_PHASE_STEP 4620 #define P_NR4_MCNR_BLUE_CENT 4287674144 #define DNR_RO_HBOF_STAT_CNT_7 11556 #define DNR_RO_HBOF_STAT_CNT_6 11555 #define DNR_RO_HBOF_STAT_CNT_9 11558 #define DNR_RO_HBOF_STAT_CNT_8 11557 #define DNR_RO_HBOF_STAT_CNT_3 11552 #define DNR_RO_HBOF_STAT_CNT_2 11551 #define DNR_RO_HBOF_STAT_CNT_5 11554 #define DNR_RO_HBOF_STAT_CNT_4 11553 #define DNR_RO_HBOF_STAT_CNT_1 11550 #define VDIN_DOLBY_DSC_CTRL0 4725 #define DNR_RO_HBOF_STAT_CNT_0 11549 #define OSD1_AFBCD_STATUS 12712 #define VDIN_DOLBY_DSC_CTRL1 4726 #define VDIN_DOLBY_DSC_CTRL2 4727 #define VDIN_DOLBY_DSC_CTRL3 4728 #define DET3D_MAT_SYMTC_TH 5948 #define VPP_VDO_MEAS_CTRL 7592 #define VD1_IF0_PROT_CNTL 6766 #define VDEC_ASSIST_MBOX1_FIQ_SEL 119 #define VPP_CLIP_MISC0 7641 #define VPP_CLIP_MISC1 7642 #define HCODEC_DC_AC_SCALE_MUL 7686 #define P_NR2_MATNR_CBETA_SCL 4287651184 #define QDCT_JPEG_DCT_STATUS1 7980 #define QDCT_JPEG_DCT_STATUS0 7979 #define VPP_DUMMY_DATA 7424 #define RESET2_REGISTER 1027 #define HEVC_ANC23_CANVAS_ADDR 14759 #define P_HEVC_SAO_IF_DATA_Y 4284662980 #define tcon_pclk_enable 26 #define CCPU_INTR_REQ 805 #define P_HEVC_SAO_IF_DATA_V 4284662988 #define P_HEVC_SAO_IF_DATA_U 4284662984 #define AUDIO_PTS 14453 #define LVDS_BIST_CNTL0 5357 #define VDEC2_DBLK_QP 10582 #define P_ENCT_VIDEO_RGB_CTRL 4287656452 #define P_GE2D_SRC1_LUT_DAT 4287890100 #define VPP_EOTF_CTL 12752 #define P_PK_CIRFB_BP_CORING 4287678528 #define REG_CM2_ENH_COEFF0_H01 264 #define P_VD2_AFBC_CONV_CTRL 4287677968 #define REG_CM2_ENH_COEFF0_H00 256 #define P_AIU_MEM_IEC958_END_PTR 4291842460 #define REG_CM2_ENH_COEFF0_H09 328 #define REG_CM2_ENH_COEFF0_H08 320 #define REG_CM2_ENH_COEFF0_H07 312 #define REG_CM2_ENH_COEFF0_H06 304 #define REG_CM2_ENH_COEFF0_H05 296 #define REG_CM2_ENH_COEFF0_H04 288 #define REG_CM2_ENH_COEFF0_H03 280 #define REG_CM2_ENH_COEFF0_H02 272 #define VIU2_OSD1_MATRIX_COEF13_14 7797 #define REG_CM2_ENH_COEFF0_H12 352 #define REG_CM2_ENH_COEFF0_H11 344 #define REG_CM2_ENH_COEFF0_H10 336 #define REG_CM2_ENH_COEFF0_H13 360 #define P_VDEC2_MBA_INC 4284657688 #define HCODEC_IQ_QUANT 7703 #define WFIFO_WORDSIZE 32 #define P_HDEC_MC_MBRIGHT_RD 4284622024 #define P_DBLK_CBPC_ADJ 4284622284 #define VPP_OSD_SC_CTRL0 7624 #define P_ENCI_SYNC_HOFFST 4287654976 #define P_HCODEC_ADV_MV_CTL2 4284644780 #define P_MINDEX1_REG 4284615724 #define P_HCODEC_ADV_MV_CTL1 4284644776 #define AUDIN_FIFO0_CTRL1 13350 #define P_HCODEC_ADV_MV_CTL0 4284644772 #define GE2D_GCLK_CTRL1 240 #define GE2D_GCLK_CTRL0 239 #define P_DOLBY_CORE2A_DMA_STATUS 4287680744 #define P_HEVC_ANC3_CANVAS_ADDR 4284671564 #define P_VLC_COEFF_BUF_STATUS 4284642560 #define P_AIU_MEM_IEC958_RD_PTR 4291842456 #define mLVDS_PORT_SWAP 3 #define P_VIU_ADDR_END 4287654908 #define HCODEC_V5_MB_DIFF_SUM 8060 #define VPP_POST_BLEND_DUMMY_ALPHA 14697 #define HEVC_AV_SCRATCH_F 14799 #define HEVC_AV_SCRATCH_G 14800 #define HCODEC_M4_CONTROL_REG 7209 #define HEVC_AV_SCRATCH_H 14801 #define HEVC_AV_SCRATCH_I 14802 #define HEVC_AV_SCRATCH_J 14803 #define HEVC_AV_SCRATCH_K 14804 #define HEVC_AV_SCRATCH_L 14805 #define HEVC_AV_SCRATCH_M 14806 #define HEVC_AV_SCRATCH_A 14794 #define HEVC_AV_SCRATCH_B 14795 #define HEVC_AV_SCRATCH_C 14796 #define HEVC_AV_SCRATCH_D 14797 #define HEVC_AV_SCRATCH_E 14798 #define P_VENC_VIDEO_TST_VDCNT_STSET 4287655388 #define VIU2_OSD1_TCOLOR_AG3 7738 #define HEVC_AV_SCRATCH_N 14807 #define MIPI_DSI_DWC_VID_VSA_LINES_OS 7189 #define P_V3_IPRED_TYPE_WEIGHT_1 4284644836 #define P_V3_IPRED_TYPE_WEIGHT_0 4284644832 #define VIU2_OSD1_TCOLOR_AG0 7735 #define VIU2_OSD1_TCOLOR_AG1 7736 #define VIU2_OSD1_TCOLOR_AG2 7737 #define HEVC_SHIFTED_DATA 12556 #define BLOCK_NUM 3114 #define P_HEVC_ASSIST_MBX_SSEL 4284662036 #define VPP_MATRIX_PRE_OFFSET0_1 7527 #define VDEC2_MDEC_SW_RESET 10628 #define V5_SMALL_DIFF_CNT 8061 #define OSDSR_VAR_PARA 12600 #define WRRSP_DCAC 2521 #define HEVC_ANC12_CANVAS_ADDR 14748 #define HEVC_VLD_MEM_VIFIFO_CURR_PTR 15425 #define P_ENCP_VIDEO_VSPULS_BEGIN 4287655532 #define P_XVYCC_LUT_G_DATA_PORT 4287677828 #define DEMO_POI_H_REG 531 #define P_DET3D_CB_CFG 4287651028 #define P_VIU2_OSD1_PROT_CTRL 4287658296 #define VPU_PROT2_MMC_CTRL 10025 #define P_HCODEC_ANC18_CANVAS_ADDR 4284638856 #define HEVC_AV_SCRATCH_6 14790 #define HEVC_AV_SCRATCH_7 14791 #define HEVC_AV_SCRATCH_8 14792 #define HEVC_AV_SCRATCH_9 14793 #define HEVC_AV_SCRATCH_0 14784 #define HEVC_AV_SCRATCH_1 14785 #define HEVC_AV_SCRATCH_2 14786 #define HEVC_AV_SCRATCH_3 14787 #define P_ENCI_VIDEO_MODE_ADV 4287654916 #define HEVC_AV_SCRATCH_4 14788 #define HEVC_AV_SCRATCH_5 14789 #define P_NR4_SNR_ALPHA1_MAX_MIN 4287674048 #define P_AIU_MEM_IEC958_MAN_RP 4291842548 #define HCODEC_DEBLK_CMD 7696 #define P_DI_BLEND_REG0_X 4287650880 #define P_DI_BLEND_REG0_Y 4287650884 #define P_DECOMB_BLND_CON0 4287673876 #define P_DECOMB_BLND_CON1 4287673880 #define P_HEVC_MPRED_PIC_SIZE_EXT 4284664064 #define P_VPP2_MATRIX_PROBE_COLOR 4287653232 #define P_HEVC_SAO_PIC_SIZE_LCU 4284667928 #define HEVC_MPRED_L0_REF15_POC 12847 #define P_ANC13_CANVAS_ADDR 4284622452 #define MC_ENABLE 1 #define P_DBLK_STATUS 4284622156 #define VDIN0_ASFIFO_CTRL0 4616 #define VDIN0_ASFIFO_CTRL1 4617 #define VDIN0_ASFIFO_CTRL2 4623 #define OEV1_VE_ADDR 5298 #define VDIN0_ASFIFO_CTRL3 4719 #define P_AIU_MEM_AIFIFO_BUF_CNTL 4291842608 #define QDCT_JPEG_QUANT_ADDR 7976 #define ABUF_WR_INT_EN 31 #define SRSHARP1_DB_FLT_RANDLUT 13433 #define VDEC2_ASSIST_MBOX1_MASK 8310 #define DCAC_DMA_CTRL 3602 #define P_ME_WEIGHT 4284644736 #define MCDI_MCVECWR_CANVAS_SIZE 12133 #define P_DCAC_MB_COUNT 4284627032 #define P_WATCHDOG_CNTL1 4291883220 #define P_LDIM_STTS_MATRIX_COEF02_10 4287654672 #define NR4_MCNR_ALP1_SGN_LUT1 14109 #define NR4_MCNR_ALP1_SGN_LUT2 14110 #define ENCL_INFO_READ 10015 #define P_MC_MBBOT_ST_EVEN_ADDR 4284622096 #define HCODEC_VLC_DC 7494 #define OEV1_VS_ADDR 5297 #define HEVC_ASSIST_MBOX2_MASK 12410 #define ENCP_DBG_LN_INT 7059 #define HEVC_PARSER_CMD_FETCH 12564 #define P_VPP_OFIFO_URG_CTRL 4287657824 #define P_HCODEC_QDCT_MB_END_PTR 4284644420 #define VBO_INTR_UNMASK 5245 #define P_ENCP_VFIFO2VD_LINE_BOT_START 4287655284 #define HCODEC_DBLK_GCLK_FREE 6508 #define ENCL_VIDEO_YC_DLY 7343 #define D2D3_MBDG_CTRL 11032 #define P_VPP_VSC_REGION34_STARTP 4287656984 #define AIU_MEM_AIFIFO2_CURR_PTR 5227 #define SRSHARP1_SHARP_HVBLANK_NUM 13313 #define P_HEVC_ASSIST_MBOX2_MASK 4284662248 #define MIPI_DSI_DWC_INT_MSK0_OS 7217 #define P_AIU_CRC_POLY_COEF0 4291842348 #define P_VDEC2_MDEC_SW_RESET 4284655120 #define P_AIU_CRC_POLY_COEF1 4291842344 #define VDEC2_VC1_BITPLANE_CTL 11800 #define AIU_MEM_AIFIFO_BYTES_AVAIL 5255 #define VDEC_ASSIST_MBOX1_MASK 118 #define P_HEVC_ANC6_CANVAS_ADDR 4284671576 #define P_DEMO_CRTL 4287678808 #define DNR_DB_YC_VEDGE_THD 11540 #define P_AIU_I2S_CBUS_DDR_CNTL 4291842724 #define SPI_FLASH_STATUS 20484 #define P_DET3D_RAMRD_DATA_PORT 4287651436 #define P_VI_HIST_V_START_END 4287674376 #define P_ANC9_CANVAS_ADDR 4284622436 #define P_VIU2_VD1_IF0_CHROMA_X1 4287658340 #define P_VPP2_MATRIX_OFFSET0_1 4287653268 #define P_VIU2_VD1_IF0_CHROMA_X0 4287658324 #define HCODEC_ANC16_CANVAS_ADDR 6560 #define P_WRRSP_CO_MB 4284622688 #define ENCP_MACV_TIME_DOWN 7115 #define P_STREAM_EVENT_CTL 4291866652 #define AIU_MEM_IEC958_LEVEL 5246 #define P_MDEC_PIC_DC_MUX_CTRL 4284622388 #define P_VIU2_VD1_IF0_CHROMA_Y0 4287658328 #define P_VIU2_VD1_IF0_CHROMA_Y1 4287658344 #define P_HEVC_PARSER_INT_CONTROL 4284662912 #define SPICC1_LD_WADDR 21517 #define P_OEV3_VS_ADDR 4287648484 #define P_ME_SUB_ANY_WEIGHT_SAD 4284644716 #define P_VIU2_OSD2_BLK2_CFG_W4 4287658392 #define P_VPP2_OSD_VSC_INI_PHASE 4287653636 #define VDIN0_COM_GCLK_CTRL 4635 #define P_VIU2_OSD2_BLK2_CFG_W3 4287658264 #define P_VIU2_OSD2_BLK2_CFG_W2 4287658260 #define SRSHARP1_SR3_DRTLPF_ALPHA_0 13415 #define P_NR4_MCNR_AC_DC_CRTL 4287674128 #define P_VIU2_OSD2_BLK2_CFG_W1 4287658256 #define SRSHARP1_SR3_DRTLPF_ALPHA_1 13416 #define P_VIU2_OSD2_BLK2_CFG_W0 4287658252 #define SRSHARP1_SR3_DRTLPF_ALPHA_2 13417 #define P_I2C_M_2_SLAVE_ADDR 4291940356 #define VDIN_ACTIVE_MAX_PIX_CNT_STATUS 4611 #define P_NR4_MCNR_ALP1_SGN_LUT1 4287683700 #define P_NR4_MCNR_ALP1_SGN_LUT2 4287683704 #define NR_TI_DNLP_BLEND 12841 #define P_VENC_ENCI_LINE 4287655332 #define P_HCTI_CON_2_GAIN_1 4287678664 #define P_HCTI_CON_2_GAIN_0 4287678660 #define P_DI_MC_REG3_Y 4287650972 #define VIU2_OSD2_BLK3_CFG_W0 7751 #define P_DI_MC_REG3_X 4287650968 #define XVYCC_YSCP_REG 540 #define ME_AB_MEM_CTL 8014 #define VIU2_OSD2_BLK3_CFG_W2 7753 #define VIU2_OSD2_BLK3_CFG_W1 7752 #define VIU2_OSD2_BLK3_CFG_W4 7783 #define VIU2_OSD2_BLK3_CFG_W3 7754 #define P_VPP_VE_DEMO_CENTER_BAR 4287657612 #define HCODEC_ANC27_CANVAS_ADDR 6571 #define HCODEC_WRRSP_VLD 6618 #define HEVC_PSCALE_CANVAS_RD_ADDR 14636 #define SRSHARP0_PK_CON_2CIRHPGAIN_LIMIT 12806 #define VIU_OSD2_TEST_RDDATA 6732 #define VIU_OSD_BLEND_DIN3_SCOPE_V 14776 #define VIU_OSD_BLEND_DIN3_SCOPE_H 14775 #define P_AIU_MEM_IEC958_CONTROL 4291842468 #define VPU_VLOCK_LOOP1_ACCUM_LMT 12319 #define VLC_VB_LEFT 7445 #define P_DNR_DM_DIF2NORM_LUT3_5 4287673808 #define P_DE_VE_ADDR 4287648592 #define P_HCODEC_PMV1_X 4284641408 #define MCDI_REF_BS_THD_GAIN 12058 #define VIU2_VD1_IF0_PROT_CNTL 7790 #define P_PARSER_VIDEO_START_PTR 4291879424 #define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 12909 #define QDCT_MB_START_PTR 7952 #define ENCP_VIDEO_RGB_CTRL 7095 #define HEVC_SAO_Y_START_ADDR 13835 #define P_HCODEC_PMV1_Y 4284641412 #define AIU_CRC_STATUS 5189 #define VDEC2_CINDEX0_REG 9002 #define HCTI_BST_CORE 12848 #define VLC_ENC_MV_BITS 7516 #define ANC15_CANVAS_ADDR 2463 #define VDIN_BLKBAR_IND_RIGHT1_CNT 4713 #define P_HEVC_BYTE_ALIGN_PEAK_LO 4284674160 #define SRSHARP1_PK_FINALGAIN_HP_BP 13346 #define TS_PL_PID_DATA 6388 #define P_VPP_PEAKING_SAT_THD2 4287657656 #define P_VPP_PEAKING_SAT_THD1 4287657652 #define P_VPP_PEAKING_SAT_THD6 4287657672 #define P_VPP_PEAKING_SAT_THD5 4287657668 #define P_VPP_PEAKING_SAT_THD4 4287657664 #define P_VPP_PEAKING_SAT_THD3 4287657660 #define P_VPP_PEAKING_SAT_THD9 4287657684 #define P_MCDI_RO_FLD_VLD_CNT 4287676060 #define P_VPP_PEAKING_SAT_THD8 4287657680 #define P_VPP_PEAKING_SAT_THD7 4287657676 #define P_NR4_MCNR_LMV_PARM 4287674112 #define HEVC_MPRED_L1_REF05_POC 12853 #define P_GE2D_GEN_CTRL0 4287890048 #define P_GE2D_GEN_CTRL1 4287890052 #define P_GE2D_GEN_CTRL2 4287890056 #define P_GE2D_GEN_CTRL3 4287890336 #define P_GE2D_GEN_CTRL4 4287890344 #define FRM_16x8_MOT 512 #define P_ENCT_TST_CLRBAR_WIDTH 4287656120 #define ENCI_SYNC_VSO_ODD 6925 #define P_LTI_CTI_DIR_AC_DBG 4287678644 #define P_AUDIN_FIFO0_LVL2 4291874980 #define VD2_IF0_RANGE_MAP_CB 6795 #define P_AUDIN_FIFO0_LVL0 4291874972 #define P_AUDIN_FIFO0_LVL1 4291874976 #define P_HEVC_SAO_CTRL10 4284668088 #define P_HEVC_SAO_CTRL11 4284668092 #define VPP_SYNC_SEL0 7574 #define VIU_OSD1_EOTF_COEF20_21 6872 #define P_DE_VS_ADDR 4287648588 #define VD2_IF0_RANGE_MAP_CR 6796 #define SHARP_SR3_DERING_GAINVS_VR2MAX 12913 #define SPI_FLASH_CTRL 20482 #define HCODEC_DBLK_STATUS1 6507 #define P_V3_MV_SAD_TABLE 4284644812 #define VDEC2_VLD_MEM_VIFIFO_RP 11334 #define VPP_OSDSR_GCLK_CTRL 7544 #define P_XVYCC_INV_LUT_U_ADDR_PORT 4287677800 #define DNR_RO_HBOF_STAT_CNT_10 11559 #define DNR_RO_HBOF_STAT_CNT_12 11561 #define DNR_RO_HBOF_STAT_CNT_11 11560 #define DNR_RO_HBOF_STAT_CNT_14 11563 #define VIU2_MISC_CTRL0 7686 #define DNR_RO_HBOF_STAT_CNT_13 11562 #define DNR_RO_HBOF_STAT_CNT_16 11565 #define DNR_RO_HBOF_STAT_CNT_15 11564 #define P_VPP_SMOKE3_V_START_END 4287657160 #define P_VDEC2_MDB_ADDR_REG 4284648556 #define SHARP_SR3_DRTLPF_ALPHA_OFST 12906 #define ANC9_CANVAS_ADDR 2457 #define P_ENCL_DBG_LN_INT 4287656624 #define DNR_RO_HBOF_STAT_CNT_29 11578 #define VDEC2_MC_OM_MB_XY 10511 #define DNR_RO_HBOF_STAT_CNT_28 11577 #define VDEC2_NEXT_INTRA_DMA_ADDRESS 11789 #define P_STV2_HE_ADDR 4287648432 #define DNR_RO_HBOF_STAT_CNT_30 11579 #define DNR_RO_HBOF_STAT_CNT_31 11580 #define DNR_RO_HBOF_STAT_CNT_18 11567 #define DNR_RO_HBOF_STAT_CNT_17 11566 #define P_AIU_MEM_IEC958_MAN_WP 4291842544 #define DNR_RO_HBOF_STAT_CNT_19 11568 #define P_QDCT_MB_MEM_CTL 4284644440 #define PK_DRTFB_HP_CORING 12817 #define P_HCODEC_CMIN_REG 4284632264 #define P_HCODEC_QDCT_MB_CONTROL 4284644436 #define P_VDIN_WR_CTRL 4287645824 #define MIPI_DSI_TOP_MEAS_CNTL 7414 #define P_HCODEC_ANC0_CANVAS_ADDR 4284638784 #define DNR_RO_HBOF_STAT_CNT_21 11570 #define DNR_RO_HBOF_STAT_CNT_20 11569 #define DNR_RO_HBOF_STAT_CNT_23 11572 #define DNR_RO_HBOF_STAT_CNT_22 11571 #define DNR_RO_HBOF_STAT_CNT_25 11574 #define DNR_RO_HBOF_STAT_CNT_24 11573 #define DNR_RO_HBOF_STAT_CNT_27 11576 #define LCD_PORT_SWAP 5238 #define DNR_RO_HBOF_STAT_CNT_26 11575 #define IMEM_DMA_ADR 833 #define SMARTCARD_STATUS 37891 #define P_VBO_TMCHK_HSYNC_STATE_H 4287648252 #define AVSP_IQ_CTL 3612 #define VDEC2_MC_HALF_PEL_ONE 10499 #define DI_IF1_CHROMA_Y0 6125 #define VBO_INFILTER_CTRL 5369 #define P_L_RGB_BASE_ADDR 4287647764 #define I2C_M_0_SLAVE_ADDR 31745 #define VPP_PREBLEND_VD1_V_START_END 7451 #define VD2_AFBC_MODE 12673 #define DI_IF1_CHROMA_X0 6124 #define P_HEVC_DBLK_CB_FILT 4284671356 #define VDEC2_VLD_TIME_STAMP_CNTL 11337 #define P_VDEC2_ASSIST_MBOX0_MASK 4284645832 #define P_NR4_MCNR_BLD_VS3LUT0 4287683592 #define P_NR4_MCNR_BLD_VS3LUT1 4287683596 #define P_VBO_TMCHK_HSYNC_STATE_L 4287648248 #define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS 4287645708 #define P_NR4_MCNR_BLD_VS3LUT2 4287683600 #define HCODEC_DBKW_CANVAS_ADDR 6577 #define VPP_HSC_REGION4_ENDP 7442 #define P_MC_HCMDBUF_H 4284622112 #define P_MC_HCMDBUF_L 4284622116 #define HCODEC_QDCT_DCT_STATUS 7961 #define P_AIU_MEM_I2S_RD_PTR 4291842436 #define P_XVYCC_VD1_RGB_DLUT_4_7 4287677900 #define P_HCODEC_REC_CANVAS_ADDR 4284638920 #define HEVC_PSCALE_MCMD_YSIZE 14628 #define SRSHARP1_OFFSET 512 #define P_PMV3_Y 4284625044 #define P_PMV3_X 4284625040 #define HEVC_MPRED_IMP_CMD1 12869 #define HEVC_MPRED_IMP_CMD2 12870 #define HEVC_MPRED_IMP_CMD3 12871 #define HEVC_MPRED_IMP_CMD0 12868 #define DI_EI_DRT_PIX_DIFFTH 6012 #define VIU2_VD1_IF0_LUMA0_RPT_PAT 7772 #define ENCL_VIDEO_MAX_LNCNT 7355 #define ABUF_WR_INT_POS_MSB 30 #define P_ENCP_DBG_PX_INT 4287655496 #define P_HCODEC_VC1_BITPLANE_CTL 4284643424 #define VDEC2_POWER_CTL_MC 10501 #define VPP_VSC_START_PHASE_STEP 7432 #define P_VPP_EOTF_CTL 4287678272 #define P_VDEC2_ANC24_CANVAS_ADDR 4284655264 #define NR4_MCNR_ALP0_REG 11713 #define P_VPU_ASYNC_STAT 4287667892 #define P_HEVC_MPRED_CTRL7 4284664164 #define P_HEVC_MPRED_CTRL6 4284664160 #define P_HEVC_MPRED_CTRL9 4284664172 #define P_HEVC_MPRED_CTRL8 4284664168 #define P_MCDI_LMV_LOCK_RT_MODE 4287675696 #define P_HEVC_MPRED_CTRL3 4284663924 #define P_HEVC_MPRED_CTRL2 4284663920 #define P_HEVC_MPRED_CTRL5 4284664116 #define P_HEVC_MPRED_CTRL4 4284664112 #define HCODEC_CINDEX4_REG 4910 #define P_HEVC_MPRED_CTRL1 4284663816 #define P_HEVC_MPRED_CTRL0 4284663812 #define DI_MC_REG3_Y 5927 #define P_DI_MC_REG0_Y 4287650948 #define DI_MC_REG3_X 5926 #define P_DI_MC_REG0_X 4287650944 #define P_PK_CON_2DRTBPGAIN_LIMIT 4287678512 #define P_I2C_M_2_RDATA_REG1 4291940380 #define P_I2C_M_2_RDATA_REG0 4291940376 #define HCODEC_CPSR 4897 #define P_IE_MB_POSITION 4284644612 #define HEVC_PSCALE_BMEM_ADDR 14623 #define GE2D_SC_MISC_CTRL 192 #define HEVC_MDEC_PICW_BUF2_STATUS 14781 #define P_HEVC_PATTERN_CODE 4284674220 #define GCLK_EN 2435 #define HEVC_LAST_SLICE_MV_ADDR 15408 #define P_VIU2_VD1_IF0_CANVAS1 4287658312 #define P_VIU2_VD1_IF0_CANVAS0 4287658308 #define HEVC_MC_CTRL0 14599 #define HEVC_MC_CTRL2 14671 #define HEVC_MC_CTRL1 14603 #define P_GAMMA_DATA_PORT 4287648260 #define P_HEVC_MBREAK_STAUTS 4284664936 #define P_L_OEV2_VE_ADDR 4287647960 #define P_MBREAK_CTRL 4284615780 #define P_HEVC_BYTE_ALIGN_PEAK_HI 4284674156 #define P_HCODEC_QP_VALUE_REG 4284641300 #define VLD_DC_PRED 3117 #define P_VPP_POSTBLEND_VD1_V_START_END 4287657076 #define VLD_TIME_STAMP_3 3151 #define VLD_TIME_STAMP_1 3149 #define VLD_TIME_STAMP_2 3150 #define VLD_TIME_STAMP_0 3148 #define P_HEVC_LMEM_DMA_COUNT 4284665160 #define BWD_PRED 4 #define P_HCODEC_PSCALE_SRCKEY_CTRL1 4284638380 #define P_HCODEC_PSCALE_SRCKEY_CTRL0 4284638376 #define P_VPP_PREBLEND_H_SIZE 4287657088 #define P_ENCP_VIDEO_EQPULS_BEGIN 4287655548 #define DI_MEM_FMT_W 6119 #define DOS_VDEC2_MCRCC_STALL2_CTRL 16195 #define P_HEVC_ASSIST_TIMER0_HI 4284662148 #define P_NR4_MCNR_CM_RSHFT_ALP0 4287674140 #define P_VIU_OSD1_PROT_CTRL 4287654072 #define SPICC1_TXDATA 21505 #define P_VLC_DBG_IDX 4284642648 #define SRSHARP1_DNLP_EN 13381 #define P_HCODEC_V5_SMALL_DIFF_CNT 4284644852 #define P_HEVC_STREAM_SWAP_ADDR 4284662992 #define VENC_VDAC_DAC2_OFFSET 7157 #define VDIN0_WR_CTRL 4640 #define P_ENCI_VIDEO_FSC_ADJ 4287654920 #define NR2_MET_NM_CCTRL 5959 #define P_HCODEC_CBREAK1_REG 4284632276 #define VDEC2_MDEC_PIC_DC_CTRL 10638 #define DC_SCALER 3588 #define P_SPI_FLASH_CMD 4291903488 #define DI_MEM_GEN_REG 6107 #define P_NR4_MCNR_BET1_AND_BET2_REG 4287674124 #define P_VPP_SMOKE1_VAL 4287657128 #define HCODEC_PSCALE_PICO_SHIFT_XY 6440 #define VPP_MATRIX_OFFSET2 7526 #define MMIN_REG 786 #define VPP_HSC_REGION4_PHASE_SLOPE 7447 #define P_VPU_HDMI_DITH_01_37 4287668172 #define P_PSCALE_FILT0_COEF1 4284621928 #define STV1_SEL 4 #define P_PSCALE_FILT0_COEF0 4284621924 #define P_PARSER_VIDEO2_START_PTR 4291879500 #define I2C_M_0_RDATA_REG1 31751 #define I2C_M_0_RDATA_REG0 31750 #define HEVC_WRRSP_FIFO_PICW_DBK 14782 #define P_AIU_AIFIFO2_CLB 4291842316 #define HEVCD_MPP_WEIGHTPRED_CNTL_ADDR 13435 #define SRSHARP1_SR3_DERING_GAINVS_MADSAD 13424 #define HEVC_MPRED_DBG_DATA_4 12884 #define HEVC_MPRED_DBG_DATA_3 12883 #define P_HEVC_DBLK_CLIP_CTRL1 4284671372 #define HEVC_MPRED_DBG_DATA_2 12882 #define PK_CON_2DRTHPGAIN_LIMIT 12810 #define P_HEVC_DBLK_CLIP_CTRL0 4284671368 #define HEVC_MPRED_DBG_DATA_1 12881 #define P_OEV1_HS_ADDR 4287648444 #define HEVC_MPRED_DBG_DATA_0 12880 #define P_VDEC2_ASSIST_MBOX1_CLR_REG 4284645844 #define P_HEVC_DBLK_CLIP_CTRL7 4284671396 #define P_HEVC_DBLK_CLIP_CTRL6 4284671392 #define VPP2_HOLD_LINES 6434 #define P_HEVC_DBLK_CLIP_CTRL8 4284671400 #define P_HEVC_DBLK_CLIP_CTRL3 4284671380 #define P_HEVC_DBLK_CLIP_CTRL2 4284671376 #define HEVC_MPRED_DBG_DATA_7 12887 #define P_HEVC_DBLK_CLIP_CTRL5 4284671388 #define HEVC_MPRED_DBG_DATA_6 12886 #define P_HEVC_DBLK_CLIP_CTRL4 4284671384 #define HEVC_MPRED_DBG_DATA_5 12885 #define HEVC_ANC8_CANVAS_ADDR 14744 #define P_VD2_AFBC_MODE 4287677956 #define LVDS_PACK_CNTL_ADDR 5328 #define VSYNC_VS_ADDR 5339 #define P_VIU_OSD1_TEST_RDDATA 4287654064 #define LDIM_STTS_HIST_START_RD_REGION 6867 #define P_VPU_VLOCK_CTRL 4287676416 #define P_ENCP_DE_V_BEGIN_ODD 4287656184 #define P_D2D3_DBR_OUTPIC_SIZE 4287671304 #define QDCT_PIC_INFO 7963 #define P_VIU_ADDR_START 4287653888 #define HEVC_ASSIST_AXI_STATUS 12413 #define HCODEC_MINDEX5_REG 4879 #define P_VPP_HSC_REGION4_ENDP 4287657032 #define P_ENCI_SYNC_VSO_ODDLN 4287654972 #define P_ENCI_DVI_VSO_ELINE_EVN 4287655952 #define P_VLC_PIC_INFO 4284642504 #define P_VPP2_HSC_REGION3_PHASE_SLOPE 4287652952 #define P_HCODEC_PMV2_Y 4284641420 #define AUDIN_FIFO2_CTRL 13386 #define P_HCODEC_PMV2_X 4284641416 #define VDIN0_LFIFO_CTRL 4634 #define AO_CPU_IRQ_IN0_INTR_FIRQ_SEL 15379 #define DET3D_RO_MAT_VEDG_TB 6028 #define VPP2_POSTBLEND_VD1_V_START_END 6429 #define P_NR2_POLAR3_MODE 4287673952 #define P_HEVC_MPRED_L0_REF08_POC 4284663968 #define XVYCC_VD1_RGB_DLUT_8_11 12660 #define P_GE2D_SRC1_KEY 4287890232 #define P_VDEC2_MC_IDCT_DAT 4284654896 #define P_AIU_958_FORCE_LEFT 4291842068 #define DET3D_RO_DET_CB_VER 5950 #define AUDIN_HDMI_MEAS_CYCLES_M1 13473 #define SRSHARP1_DNLP_15 13397 #define ENCT_VIDEO_RGB_CTRL 7297 #define VDEC2_SCD_FOR_MV_X 11282 #define VDEC2_SCD_FOR_MV_Y 11283 #define P_VDEC2_DBKR_CANVAS_ADDR 4284655296 #define VDEC2_VLD_REVERVED_19 11289 #define ENCP_VBI_CTRL 7120 #define H_AUTO_INC 11 #define P_HEVC_MPRED_L1_REF06_POC 4284664024 #define P_VDEC2_AVSP_IQ_WQ_PARAM_01 4284659812 #define P_PARSER_VIDEO_WP 4291879432 #define P_VPU_HDMI_DITH_01_04 4287668160 #define VPP_OSDSC_DITHER_CTRL 12592 #define P_ENCP_VIDEO_VSO_END 4287655592 #define VPU_422TO444_CTRL1 10060 #define VPU_422TO444_CTRL0 10059 #define P_HEVC_CBREAK_CTRL 4284665060 #define P_AUDOUT_FIFO_RPTR 4291875360 #define ABUF_WR_INT_POS_LSB 16 #define P_HEVC_MCRCC_CTL3 4284671496 #define P_HEVC_MCRCC_CTL2 4284671492 #define STREAM_EVENT_CTL 11271 #define P_HEVC_MCRCC_CTL1 4284671488 #define P_D2D3_DWMIF_STATUS 4287671532 #define P_VDIN_HIST_SPL_VAL 4287645904 #define VPP2_OFIFO_SIZE 7719 #define VPU_ASYNC_STAT 10157 #define P_DNR_RO_DM_GMS_STAT_CNT 4287673820 #define VBO_GCLK_LANE_L 5232 #define VBO_GCLK_LANE_H 5233 #define P_VDEC2_AVSP_IQ_WQ_PARAM_23 4284659816 #define P_VPU_HDMI_DITH_01_26 4287668168 #define DET3D_RO_MAT_VEDG_LR 6027 #define HCODEC_ANC29_CANVAS_ADDR 6573 #define P_VPP_PREBLEND_VD1_H_START_END 4287657064 #define DOLBY_CORE2A_SWAP_CTRL5 13368 #define DOLBY_CORE2A_SWAP_CTRL1 13364 #define VPU_CONT_MMC_CTRL 10018 #define DOLBY_CORE2A_SWAP_CTRL2 13365 #define DOLBY_CORE2A_SWAP_CTRL3 13366 #define DOLBY_CORE2A_SWAP_CTRL4 13367 #define P_PARSER_VIDEO_RP 4291879436 #define HEVC_SCD_FOR_MV_Y 15379 #define P_VPU_HDMI_DITH_01_15 4287668164 #define HEVC_SCD_FOR_MV_X 15378 #define MCDI_REL_DET_GMV_DIF_CHK 12079 #define DOLBY_CORE2A_SWAP_CTRL0 13363 #define P_HCODEC_VLC_HCMD_T_L_INFO 4284642444 #define VDEC_ASSIST_MBOX0_IRQ_REG 112 #define P_DI_BLEND_CTRL 4287650868 #define ADAPTIVE_SCALE_REG0 12624 #define ADAPTIVE_SCALE_REG1 12625 #define P_VDEC2_AVSP_IQ_WQ_PARAM_45 4284659820 #define HCODEC_DCAC_DMA_CTRL 7698 #define ADAPTIVE_SCALE_REG2 12626 #define ADAPTIVE_SCALE_REG3 12627 #define ADAPTIVE_SCALE_REG4 12628 #define VPP_IN_H_V_SIZE 7590 #define VPU_ARB_DBG_STAT_L1C1 10164 #define VPU_ARB_DBG_STAT_L1C2 10166 #define P_VD2_AFBC_HEAD_BADDR 4287677976 #define P_DET3D_SPLT_CFG 4287651032 #define P_VIU_OSD1_FIFO_CTRL_STAT 4287654060 #define P_HEVC_CABAC_TOP_INFO 4284662896 #define HEVC_PARSER_RESERVED_27 12583 #define P_SPICC1_RXDATA 4291907584 #define P_ENCP_MACV_TIME_DOWN 4287655724 #define HCODEC_MC_HALF_PEL_ONE 6403 #define ABUF_RD_PLY_ONCE_PLS 4 #define ENCT_TST_Y 7210 #define VIU2_OSD2_HL1_H_START_END 7731 #define P_HCODEC_MC_MPORT_CTRL 4284638464 #define P_HEVC_LMEM_DMA_ADR 4284665156 #define P_OSD1_AFBCD_MODE 4287678084 #define P_VDEC_ASSIST_DMA_INT2 4284613016 #define P_ENCP_VFIFO2VD_LINE_TOP_START 4287655276 #define ENCL_VIDEO_PR_SCL 7331 #define HCODEC_M4_TABLE_SELECT 7208 #define HCODEC_MB_SKIP_RUN 7507 #define MPEG1_2_REG 3073 #define AUDIN_FIFO1_CTRL1 13369 #define HEVC_MC_CTRL_REG 14592 #define P_HEVCD_IPP_DYNCLKGATE_STATUS 4284665988 #define P_HCODEC_BYTE_ALIGN_PEAK_LO 4284641392 #define NR2_MATNR_YBETA_SCL 5979 #define HCODEC_QDCT_PIC_INFO 7963 #define P_HEVC_PSCALE_PICO_SHIFT_XY 4284671136 #define VIU_OSD_BLEND_DIN1_SCOPE_V 14772 #define VPU_D2D3_MMC_CTRL 10017 #define VDEC2_VLD_MEM_VIFIFO_START_PTR 11328 #define P_AUDIN_SOURCE_SEL 4291874884 #define VIU_OSD_BLEND_DIN1_SCOPE_H 14771 #define VENC_VDAC_DAC2_GAINCTRL 7156 #define P_NR2_MATNR_SNR_NRM_CFG 4287651148 #define VIU_OSD2_MATRIX_COEF20_21 6836 #define P_VDEC2_MCPU_INTR_MSK 4284648464 #define DI_MC_REG4_Y 5929 #define DI_MC_REG4_X 5928 #define HEVC_SAO_VB_RPTR 13847 #define P_HEVC_PARSER_MEM_RW_DATA 4284662968 #define P_PMV4_X 4284625048 #define P_PMV4_Y 4284625052 #define P_HCODEC_CINDEX1_REG 4284632236 #define P_QDCT_MB_END_PTR 4284644420 #define VPU_PROT2_DDR 10087 #define I2C_M_DELAY_MSB 21 #define P_HCODEC_GCLK_EN 4284638732 #define VDIN0_DUMMY_DATA 4646 #define P_HCODEC_VLC_COEFF 4284642568 #define HEVC_VLD_MEM_VIFIFO_WRAP_COUNT 15441 #define HCODEC_QDCT_Q_QUANT_I 7964 #define P_GE2D_VSC_PHASE_SLOPE 4287890152 #define LDIM_STTS_MATRIX_PRE_OFFSET0_1 6858 #define HCODEC_MFDIN_REGA_CAV1 4114 #define VDEC2_ASSIST_MBOX1_FIQ_SEL 8311 #define HCODEC_QDCT_Q_QUANT_P 7965 #define P_VIU_OSD2_MATRIX_PROBE_COLOR 4287654632 #define P_VDEC2_ANC4_CANVAS_ADDR 4284655184 #define P_VLD_MEM_VIFIFO_END_PTR 4284625160 #define PARSER_FETCH_ADDR 14433 #define EE_ASSIST_MBOX2_IRQ_REG 8312 #define P_DI_MC_REG1_Y 4287650956 #define P_DI_MC_REG1_X 4287650952 #define P_VPU_DI_MTNRD_MMC_CTRL 4287667232 #define HEVCD_IPP_DBG_SEL 13360 #define P_DNR_DM_DIF2NORM_LUT6_8 4287673812 #define P_HCODEC_ASSIST_AMR1_INT0 4284629140 #define P_HCODEC_ASSIST_AMR1_INT2 4284629148 #define P_HCODEC_ASSIST_AMR1_INT1 4284629144 #define GE2D_HSC_INI_CTRL 190 #define VPP_VE_DITHER_LUT_12 12588 #define VPP_VE_DITHER_LUT_11 12587 #define VPP_VE_DITHER_LUT_10 12586 #define P_HCODEC_ASSIST_AMR1_INTD 4284629192 #define P_HCODEC_ASSIST_AMR1_INTC 4284629188 #define P_HCODEC_ASSIST_AMR1_INTF 4284629200 #define P_HCODEC_ASSIST_AMR1_INTE 4284629196 #define VIU2_OSD1_MATRIX_EN_CTRL 7805 #define P_VD2_AFBC_OUT_YSCOPE 4287677988 #define P_HCODEC_ASSIST_AMR1_INT4 4284629156 #define P_HCODEC_ASSIST_AMR1_INT3 4284629152 #define P_VBO_TMCHK_VDE_STATE_H 4287648732 #define P_HCODEC_ASSIST_AMR1_INT6 4284629164 #define P_HCODEC_ASSIST_AMR1_INT5 4284629160 #define P_HCODEC_ASSIST_AMR1_INT8 4284629172 #define P_HCODEC_ASSIST_AMR1_INT7 4284629168 #define P_VBO_TMCHK_VDE_STATE_L 4287648728 #define P_QDCT_MB_RD_PTR 4284644428 #define P_HCODEC_ASSIST_AMR1_INT9 4284629176 #define P_HCODEC_ASSIST_AMR1_INTB 4284629184 #define P_HCODEC_ASSIST_AMR1_INTA 4284629180 #define HEVC_ASSIST_TIMER1_LO 12386 #define ENCI_DE_V_BEGIN_ODD 6938 #define P_PARSER_FETCH_CMD 4291879304 #define P_ENCP_VIDEO_MATRIX_CR 4287655664 #define VPP2_OSD_HSC_PHASE_STEP 6595 #define P_HEVC_IQ_QUANT 4284676188 #define P_PARSER_FETCH_INFO 4291879484 #define P_ENCT_DBG_LN_RST 4287656360 #define P_ENCP_VIDEO_MATRIX_CB 4287655660 #define VIDEO_FRM_BUF_LSB_BIT 2 #define P_GE2D_CMD_CTRL 4287890060 #define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 15801 #define HEVC_IQIT_SCALELUT_RD_ADDR 14083 #define SANA_SHIFT_COMMAND 12333 #define VPP_WRAP_OSD1_MATRIX_COEF15_25 15719 #define P_I2C_M_2_CONTROL_REG 4291940352 #define P_AUD_RESAMPLE_CTRL0 4291875580 #define P_AUD_RESAMPLE_CTRL1 4291875584 #define P_AUD_RESAMPLE_CTRL2 4291875592 #define DOS_SECURE_REG_NULL 16258 #define ENCI_VIDEO_CONT 6916 #define HEVC_MPRED_L0_REF03_POC 12835 #define NR2_CONV_MODE 6015 #define mLVDS_data_latch_1_toggle 16 #define ASYNC_FIFO_TO_HIU 24 #define P_HEVC_ASSIST_TIMER0_LO 4284662144 #define HCODEC_RESYNC_MARKER_LENGTH 7182 #define P_VIU_OSD1_MATRIX_PROBE_POS 4287654512 #define P_VPP_OSD_SCO_V_START_END 4287657772 #define P_HEVC_PARSER_CORE_CONTROL 4284662860 #define P_RDMA_SRAM_REGDATA 4287644808 #define HCODEC_MBREAK_TYPE 4888 #define SHARP_SR2_YBIC_VCOEF1 12893 #define SHARP_SR2_YBIC_VCOEF0 12892 #define HEVC_ASSIST_TIMER1_HI 12387 #define P_DOLBY_CORE2A_DMA_PORT 4287680764 #define P_VIU_OSD1_MATRIX_COEF22_30 4287654516 #define P_HCODEC_QDCT_JPEG_SOF_RESUME 4284644520 #define P_DNR_RO_GBS_STAT_LL 4287673444 #define P_VPP_OSDSR_GCLK_CTRL 4287657440 #define P_DNR_RO_GBS_STAT_LR 4287673440 #define P_VPU_PROT1_RPT_LOOP 4287667540 #define P_HEVC_MPRED_IMP_CMD2 4284664088 #define P_HEVC_MPRED_IMP_CMD3 4284664092 #define P_HEVC_MPRED_IMP_CMD0 4284664080 #define P_HEVC_MPRED_IMP_CMD1 4284664084 #define FITLER_CFG_REG 518 #define ENCT_VIDEO_MODE_ADV 7272 #define WM_CTRL 12720 #define DI_IF1_DUMMY_PIXEL 6129 #define MINDEX3_REG 781 #define VPP_SMOKE_CTRL 7465 #define ENCL_TCON_INVERT_CTL 7165 #define P_MCDI_RO_COL_CFD_9 4287676132 #define P_MCDI_RO_COL_CFD_8 4287676128 #define P_VPP2_POSTBLEND_H_SIZE 4287652996 #define P_MCDI_RO_COL_CFD_7 4287676124 #define P_MCDI_RO_COL_CFD_6 4287676120 #define D2D3_DWMIF_CTRL 11044 #define P_MCDI_RO_COL_CFD_1 4287676100 #define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 6562 #define P_MCDI_RO_COL_CFD_0 4287676096 #define DNR_DM_RNG_THD 11618 #define P_MCDI_RO_COL_CFD_5 4287676116 #define P_HCODEC_PMV3_X 4284641424 #define P_MCDI_RO_COL_CFD_4 4287676112 #define P_MCDI_RO_COL_CFD_3 4287676108 #define P_MCDI_RO_COL_CFD_2 4287676104 #define P_HCODEC_PMV3_Y 4284641428 #define NR4_RO_NR4_BLDVS2_SUM 14117 #define AVS2_CONTROL 12626 #define CPV2_VE_ADDR 5286 #define P_HCODEC_BYTE_ALIGN_PEAK_HI 4284641388 #define P_VDEC2_MC_OM_MB_XY 4284654652 #define P_AUDOUT_INTR_PTR 4291875364 #define P_SPICC0_LD_CNTL1 4291899436 #define P_SPICC0_LD_CNTL0 4291899432 #define P_NR2_MET_NMFRM_TNR_YLEV 4287651108 #define P_VENC_VDAC_DAC4_OFFSET 4287655908 #define P_NR2_MET_NMFRM_TNR_CLEV 4287651116 #define P_OEV1_VS_ADDR 4287648452 #define P_QDCT_Q_STATUS 4284644456 #define VPP_HLTI_GAIN 7633 #define P_MC_MPORT_DAT 4284622084 #define LVDS_DUAL 6 #define HCODEC_DCAC_CPU_ADDRESS 7700 #define ABUF_RD_CTL2 15478 #define ABUF_RD_CTL1 15477 #define ABUF_RD_CTL0 15476 #define ABUF_RD_CTL3 15479 #define P_CPC_D 4284615836 #define P_CPC_E 4284615840 #define SRSHARP1_SR3_DERING_CTRL 13419 #define P_NR4_RO_NM_SAD_CNT 4287683712 #define GE2D_MATRIX_COEF11_12 200 #define ME_START_POSITION 8010 #define P_CPC_W 4284615844 #define P_CPC_P 4284615832 #define MCDI_CHK_EDGE_GAIN_OFFST 12043 #define P_SHARP_SR2_YBIC_HCOEF1 4287678820 #define P_HCODEC_QDCT_TOP_BASE_MEM 4284644480 #define SHARP_DB_FLT_RANDLUT 12921 #define HCODEC_MC_OMDN_MB_XY 6471 #define TCON_MISC_SEL_ADDR 5313 #define P_SHARP_SR2_YBIC_HCOEF0 4287678816 #define DOLBY_CORE3_SWAP_CTRL9 14074 #define P_HCODEC_VLC_PIC_SIZE 4284642500 #define DOLBY_CORE3_SWAP_CTRL4 14069 #define DOLBY_CORE3_SWAP_CTRL3 14068 #define DOLBY_CORE3_SWAP_CTRL2 14067 #define DOLBY_CORE3_SWAP_CTRL1 14066 #define DOLBY_CORE3_SWAP_CTRL8 14073 #define DOLBY_CORE3_SWAP_CTRL7 14072 #define DOLBY_CORE3_SWAP_CTRL6 14071 #define DOLBY_CORE3_SWAP_CTRL5 14070 #define VPP_HSC_REGION34_STARTP 7441 #define MCDI_RO_FLD_VLD_CNT 12199 #define DOLBY_CORE3_SWAP_CTRL0 14065 #define P_DNR_RO_GBS_STAT_RR 4287673448 #define P_PARSER_AUDIO_START_PTR 4291879444 #define PK_CIRFB_BLEND_GAIN 12819 #define ANC1_CANVAS_ADDR 2449 #define NR2_MET_NM_YCTRL 5958 #define P_VPU_DI_DIWR_MMC_CTRL 4287667248 #define HEVC_VLD_TIME_STAMP_SYNC_0 15434 #define HEVC_VLD_TIME_STAMP_SYNC_1 15435 #define GAMMA_SET 1 #define OSD_BLENDO_H_START_END 6825 #define P_HEVC_ANC31_CANVAS_ADDR 4284671676 #define P_D2D3_DBR_LRDMX_CTRL 4287671484 #define HCODEC_MC_HALF_PEL_TWO 6404 #define P_OEV2_HE_ADDR 4287648464 #define LDIM_STTS_MATRIX_COEF22 6855 #define VDEC2_CDB_ADDR_REG 9019 #define P_GE2D_VSC_START_PHASE_STEP 4287890148 #define P_VPP2_OSD_SCO_V_START_END 4287653676 #define P_VPP2_VADJ1_MA_MB 4287653128 #define ENCP_DE_H_END 7227 #define VPU_ARB_DBG_STAT_L2C1 10168 #define P_MCDI_MCINFORD_CANVAS_SIZE 4287675808 #define REG_BASE_VCBUS 4287627264 #define P_CMIN_REG 4284615880 #define VDEC2_DBLK_STRONG 10613 #define VLC_ADV_CONFIG 7461 #define HEVC_VLD_MEM_VIFIFO_RP 15430 #define GE2D_ANTIFLICK_CTRL1 217 #define GE2D_ANTIFLICK_CTRL0 216 #define P_VDEC2_ANC23_CANVAS_ADDR 4284655260 #define P_AUDOUT_BUF0_STA 4291875336 #define VLC_HCMD_T_L_INFO 7459 #define SRSHARP1_VCTI_BST_CORE 13377 #define P_HEVC_VLD_TIME_STAMP_LENGTH 4284674368 #define P_VPP2_VE_ENABLE_CTRL 4287653508 #define VPP_MATRIX_PRE_OFFSET2 7528 #define P_VIU_OSD2_MATRIX_COEF02_10 4287654600 #define DOS_VDEC2_INT_EN 16138 #define VPP_SMOKE2_H_START_END 7471 #define P_VDEC2_MC_PIC_INFO 4284654600 #define P_ENCP_VIDEO_YC_DLY 4287655512 #define P_VPU_PROT3_X_START_END 4287667656 #define L_OEV1_VE_ADDR 5170 #define SRSHARP1_PK_CON_2CIRHPGAIN_TH_RATE 13317 #define P_HEVC_PSCALE_DRAM_BUF_CTRL 4284671108 #define P_DI_BLEND_REG3_Y 4287650908 #define P_DI_BLEND_REG3_X 4287650904 #define mLVDS_en 0 #define P_MCDI_REL_BADW_THD_GAIN_OFFST 4287675532 #define P_SHARP_SR3_SAD_CTRL 4287678852 #define ENCL_DBG_LN_RST 7338 #define HCODEC_VLD_TIME_STAMP_CNTL 7241 #define P_HEVC_MC_MPORT_CTRL 4284671232 #define P_DI_MEM_URGENT_CTRL 4287660692 #define P_NR2_POLAR3_THRD 4287673956 #define VPP2_FIFO_STATUS 6440 #define VDEC2_QP_VALUE_REG 11269 #define P_VDEC2_VLD_MEM_VIFIFO_BUF_CNTL 4284657952 #define HCODEC_MPC_P 4870 #define GPIO_ADR_H8 1026 #define MIPI_DSI_DWC_HS_RD_TO_CNT_OS 7199 #define P_VDEC_ASSIST_MBOX2_MASK 4284613096 #define HCODEC_MPC_W 4873 #define P_NR4_MCNR_ALP1_GLB_CTRL 4287674204 #define VIU2_VD1_IF0_CHROMA0_RPT_PAT 7773 #define P_VLC_VB_START_PTR 4284642368 #define P_DOLBY_CORE3_STATUS1 4287683568 #define P_DOLBY_CORE3_STATUS2 4287683572 #define P_DOLBY_CORE3_STATUS0 4287683564 #define P_STH1_VE_ADDR 4287648332 #define VPU_PROT3_STAT_2 10107 #define VPU_PROT3_STAT_1 10106 #define P_DOLBY_CORE3_STATUS3 4287683576 #define VPU_PROT3_STAT_0 10105 #define NR4_MCNR_SAD_GAIN 14080 #define VP9_MEM_OPERATION 12621 #define VD2_BLEND_SRC_CTRL 7676 #define P_ENCT_VIDEO_VOFFST 4287656448 #define HCODEC_PSCALE_PICO_W 6420 #define P_MLVDS_CONFIG_LO 4287648544 #define HCODEC_PSCALE_PICO_H 6421 #define P_HCODEC_DBLK_GCLK_OFF 4284638644 #define P_MCDI_FLT_MODESEL 4287675428 #define P_VPP_SMOKE2_VAL 4287657132 #define LDIM_STTS_MATRIX_COEF11_12 6853 #define QDCT_TOP_BASE_MEM 7968 #define P_HCODEC_PSCALE_PICO_START_X 4284638296 #define P_HCODEC_PSCALE_PICO_START_Y 4284638300 #define HSYNC_HS_ADDR 5333 #define HEVC_VLD_MEM_VIFIFO_WP 15429 #define P_VDEC2_PSCALE_PICI_H 4284654668 #define P_VPP_FRONT_CTI_CTRL 4287657712 #define SANA_SHIFT_STATUS 12330 #define P_VPP_SCALE_COEF 4287656976 #define NR3_CMOT_PARA 12276 #define P_VDEC2_PSCALE_PICI_W 4284654664 #define AUDIN_SPDIF_FS_CLK_RLTN 13313 #define P_HEVC_MC_DP_MB_XY 4284671032 #define P_ENCP_VIDEO_HSO_END 4287655584 #define HEVC_ANC10_CANVAS_ADDR 14746 #define VLD_MEM_SWAP_CTL 3158 #define VPP_XVYCC_GCLK_CTRL 7545 #define WATCHDOG_CNTL1 15413 #define P_MLVDS_CONFIG_HI 4287648540 #define AUDIN_SPDIF_MODE 13312 #define P_DECOMB_MTN_GAIN_OFST 4287673888 #define MINT_VEC_BASE 770 #define P_HCODEC_ME_SKIP_LINE 4284644660 #define L_RGB_COEFF_ADDR 5126 #define P_VDEC_ASSIST_MBOX0_FIQ_SEL 4284613068 #define P_VDEC2_PSCALE_CANVAS_WR_ADDR 4284654772 #define P_ENCT_VIDEO_HSO_END 4287656408 #define P_VD1_IF0_LUMA_PSEL 4287654272 #define P_GE2D_SRC1_RANGE_MAP_CB_CTRL 4287890320 #define P_VDEC2_DBLK_CB_FILT 4284654972 #define P_VD1_IF0_URGENT_CTRL 4287654332 #define AHB_BRIDGE_CNTL_WR 15488 #define VDEC2_VCOP_CTRL_REG 11776 #define P_CPV2_VS_ADDR 4287648404 #define P_MCDI_REF_BS_THD_GAIN 4287675496 #define VDEC2_MC_DPDN_MB_XY 10566 #define PARSER_FETCH_LEVEL 14436 #define HCODEC_DBLK_Y_BHFILT 6487 #define P_HEVCD_IPP_AXIIF_CONFIG 4284665900 #define MC_MPORT_CTRL 2368 #define WM_VIDEO_RESOLUTION 12730 #define P_DI_IF2_LUMA_FIFO_SIZE 4287660136 #define P_ENCT_TST_Y 4287656104 #define ENCI_VFIFO2VD_PIXEL_START 7193 #define D2D3_RESEV_STATUS2 11071 #define HCODEC_ASSIST_DMA_INT2 4198 #define D2D3_RESEV_STATUS1 11070 #define VLC_HCMD_DBLK_INFO 7509 #define P_HCODEC_DBLK_VHMVD 4284638672 #define HEVC_CM_HEADER_START_ADDR 13864 #define VIU2_OSD1_MATRIX_COEF22 7796 #define P_DECOMB_PARA 4287673872 #define P_L_LCD_PWM0_HI_ADDR 4287647988 #define VPP2_HSC_INI_PAT_CTRL 6453 #define P_CINDEX5_REG 4284615868 #define HCODEC_VLC_ENC_PEND_CMD 7478 #define P_AIU_MEM_IEC958_LEVEL 4291842552 #define P_HEVC_PSCALE_CMD_CTRL 4284671084 #define P_MDEC_PIC_DC_CTRL 4284622392 #define P_HCODEC_VLC_MV_INDEX 4284642592 #define VIU_OSD2_BLK1_CFG_W1 6720 #define P_MCDI_MCINFOWR_Y 4287676004 #define VIU_OSD2_BLK1_CFG_W2 6721 #define VIU_OSD2_BLK1_CFG_W3 6722 #define VIU_OSD2_BLK1_CFG_W4 6757 #define P_MCDI_MCINFOWR_X 4287676000 #define VDEC2_PSCALE_STATUS 10526 #define VIU_OSD2_BLK1_CFG_W0 6719 #define P_DI_CHAN2_CHROMA_Y0 4287651816 #define HEVC_PARSER_MEM_RD_ADDR 12588 #define P_HCODEC_VLC_HCMD_MBXY_AUTO 4284642456 #define P_ENCT_VIDEO_RGBIN_CTRL 4287656476 #define VD2_IF0_CHROMA_X0 6773 #define VD2_IF0_CHROMA_X1 6777 #define VDEC2_PSCALE_DUMMY 10520 #define P_LDIM_STTS_MATRIX_COEF22 4287654684 #define VPU_ARB4_V1_MMC_CTRL 10027 #define HCODEC_V3_TOP_INTRA_INFO 8054 #define P_D2D3_DBLD_LPF_VCOEFF 4287671380 #define P_DNR_DB_YHDELTA2_GAIN 4287673412 #define P_ISA_DEBUG_REG0 4291883008 #define P_ISA_DEBUG_REG3 4291883020 #define P_ISA_DEBUG_REG2 4291883016 #define P_VDEC_ASSIST_MBOX0_IRQ_REG 4284613056 #define P_ISA_DEBUG_REG1 4291883012 #define P_DNR_DB_CVDELTA_GAIN 4287673436 #define HCODEC_ANC15_CANVAS_ADDR 6559 #define P_ENCI_SYNC_TO_PIXEL 4287656204 #define P_VPU_WRARB_REQEN_SLV_L1C2 4287667900 #define P_VPU_WRARB_REQEN_SLV_L1C1 4287667796 #define VDIN_SYNC_MASK 4724 #define P_ENCT_VIDEO_MODE 4287656348 #define P_HEVCD_IPP_DBG_DATA 4284666052 #define HEVC_M4_TABLE_SELECT 15400 #define V3_TOP_MV 8046 #define HCODEC_DBLK_RST 6480 #define ENCP_VIDEO_VAVON_ELINE 7087 #define VD2_IF0_CHROMA_Y1 6778 #define P_MCDI_REL_DET_LUT_4_7 4287675644 #define P_HEVC_MDEC_DOUBLEW_STATUS 4284671884 #define VD2_IF0_CHROMA_Y0 6774 #define RDMA_STATUS2 4374 #define DI_POST_SIZE 5890 #define RDMA_STATUS3 4375 #define P_ENCL_VIDEO_VSO_ELINE 4287656680 #define INV_EN 4 #define P_VPU_VLOCK_RO_LOOP0_ACCUM 4287676472 #define P_VDEC2_CCPU_INTR_REQ 4284648596 #define P_VPP_HSHARP_CHROMA_GAIN 4287657304 #define P_DI_CHAN2_CHROMA_X0 4287651812 #define VPP2_OSD_SCI_WH_M1 6601 #define P_LMEM_DMA_COUNT 4284616008 #define VPP2_POSTBLEND_VD1_H_START_END 6428 #define VDIN0_DOLBY_DSC_STATUS1 4734 #define VDIN0_DOLBY_DSC_STATUS0 4733 #define P_ENCP_VIDEO_FILT_CTRL 4287655648 #define VDIN0_DOLBY_DSC_STATUS3 4637 #define VDIN0_DOLBY_DSC_STATUS2 4735 #define P_QDCT_DBG_READ 4284644496 #define HEVC_PARSER_MEM_RW_DATA 12590 #define P_AUDIO_PTS 4291879380 #define HEVC_VLD_MEM_VIFIFO_MEM_CTL 15442 #define SRSHARP1_CTI_DIR_ALPHA 13355 #define HCODEC_VLC_DBG_IDX 7510 #define P_HEVC_MSFTINT1 4284664956 #define P_HEVC_MSFTINT0 4284664952 #define VDIN0_COM_CTRL0 4610 #define P_VIU_OSD1_MATRIX_CTRL 4287654464 #define MEDIA_CPU_INTR_FIRQ_SEL 15403 #define P_MEDIA_CPU_INTR_FIRQ_SEL 4291883180 #define VIU_SW_RESET 6657 #define P_D2D3_CG_PARAM_1 4287671332 #define P_D2D3_CG_PARAM_2 4287671336 #define P_VPU_ARB_URG_CTRL 4287667484 #define P_CPV1_VS_ADDR 4287648388 #define VPP_EOTF_COEF11_12 12755 #define mLVDS2_en 0 #define MPEG_RESET 512 #define P_DI_IF1_CHROMA0_RPT_PAT 4287651776 #define VDEC2_DBLK_CR_BFILT 10587 #define P_DI_CHAN2_GEN_REG3 4287660712 #define P_DI_CHAN2_GEN_REG2 4287651548 #define HEVC_SAO_Y_LENGTH 13836 #define VD2_PPS_DUMMY_DATA 7668 #define HEVC_CABAC_CONTROL 12560 #define P_ENCT_VIDEO_Y_SCL 4287656324 #define P_HCODEC_ANC19_CANVAS_ADDR 4284638860 #define GE2D_HSC_NRND_PHASE 196 #define HCODEC_QDCT_MB_BUFF 7959 #define VLD_TIME_STAMP_CNTL 3145 #define HCODEC_PSCALE_MCMD_XSIZE 6435 #define P_HEVC_AVSP_IQ_CTL 4284676208 #define PARSER_AUDIO_END_PTR 14470 #define P_D2D3_DBR_DDD_CTRL 4287671472 #define P_AIU_I2S_CBUS_DDR_ADDR 4291842732 #define GE2D_SRC2_KEY 208 #define VDEC2_BYTE_ALIGN_PEAK_HI 11291 #define P_HCODEC_ME_SUB_SNAP_GLITCH 4284644728 #define HEVC_CM_BODY_START_ADDR 13862 #define DI_CHAN2_LUMA_FIFO_SIZE 6067 #define ENCI_DVI_VSO_ELINE_ODD 7173 #define HEVC_DCAC_DMA_ADDRESS 15891 #define WM_THRES_DATA_PORT 12749 #define P_VDEC2_WRRSP_DCAC 4284655460 #define P_VDEC2_MDB_CTRL 4284648564 #define HCODEC_MDEC_EXTIF_CFG0 6628 #define HCODEC_MDEC_EXTIF_CFG1 6629 #define P_D2D3_DBG_CTRL 4287671436 #define P_HEVC_ANC5_CANVAS_ADDR 4284671572 #define DNR_DB_CHDELTA2_GAIN 11539 #define P_VLC_INT_CONTROL 4284642496 #define REG_BASE_DSI_HOST 4291821568 #define P_VDIN_SCALE_COEF 4287645700 #define VLC_STATUS_CTRL 7424 #define HCODEC_MC_MBBOT_ST_EVEN_ADDR 6468 #define HEVC_ASSIST_MBOX1_MASK 12406 #define P_PSCALE_MCMD_YSIZE 4284621968 #define SRSHARP1_SR3_DRTLPF_EN 13414 #define VDEC2_BYTE_ALIGN_PEAK_LO 11292 #define P_HCODEC_ME_SUB_ANY_WEIGHT_SAD 4284644716 #define P_VD2_IF0_DUMMY_PIXEL 4287654408 #define QDCT_JPEG_DCT_COEFF67 7984 #define P_FST_FOR_MV_X 4284624960 #define P_FST_FOR_MV_Y 4284624964 #define P_WM_STORAGE_SETTING 4287678180 #define SRSHARP1_PK_DRTFB_LPF_MODE 13326 #define P_ENCP_VIDEO_MAX_PXCNT 4287655516 #define NR_ALP0Y_ERR2CURV_TH_RATE 12821 #define P_HEVC_DBLK_GCLK_OFF 4284671412 #define DUAL_LVDC_EN 3 #define PSCALE_CMD_BLK_Y 2333 #define PSCALE_CMD_BLK_X 2332 #define RESET0_MASK 1040 #define QDCT_JPEG_DCT_COEFF89 7985 #define P_ENCL_TCON_INVERT_CTL 4287655924 #define VIU2_VD1_FMT_W 7785 #define IE_RESULT_BUFFER 8004 #define P_VDIN_BLKBAR_CTRL1 4287646076 #define P_VDIN_BLKBAR_CTRL0 4287646080 #define P_VIU_OSD1_MATRIX_COEF00_01 4287654468 #define QDCT_JPEG_DCT_COEFF23 7982 #define P_MDEC_EXTIF_STS0 4284622744 #define M4_TABLE_SELECT 3112 #define P_HEVC_CM_BODY_START_ADDR 4284668056 #define VPP2_MATRIX_PRE_OFFSET0_1 6503 #define VPP_WRAP_OSD2_MATRIX_COEF20_21 15731 #define QDCT_JPEG_DCT_COEFF45 7983 #define P_VDEC2_MCPU_INTR_GRP 4284648460 #define P_GE2D_SRC2_DEF_COLOR 4287890108 #define AIU_AIFIFO_CTRL 5248 #define P_L_DUAL_PORT_CNTL_ADDR 4287648008 #define P_MCDI_YCBCR_BLEND_CRTL 4287675792 #define MCPU_INTR_REQ 773 #define HEVC_ASSIST_MBX_SSEL 12357 #define MIPI_DSI_DWC_PHY_ULPS_CTRL_OS 7210 #define MINDEX4_REG 782 #define VPP_DUMMY_DATA1 7529 #define P_MMAX_REG 4284615756 #define QDCT_JPEG_DCT_COEFF01 7981 #define P_HCODEC_VLD_MEM_VIFIFO_CURR_PTR 4284641540 #define HCODEC_MPC_D 4871 #define HCODEC_MPC_E 4872 #define SRSHARP0_DEMO_CRTL 12886 #define DEMO_SPLT_CFG_REG 538 #define P_I2C_M_1_CONTROL_REG 4291944448 #define P_QDCT_TOP_WRRSP 4284644488 #define SPI_FLASH_WRSR 26 #define P_L_HSYNC_VE_ADDR 4287648096 #define LDIM_STTS_WIDTHM1_HEIGHTM1 6850 #define PK_ALP2_MIN_MAX 12833 #define P_VDEC2_RESYNC_MARKER_LENGTH 4284657720 #define NR2_SAD2NORM_LUT0 5982 #define P_VDEC2_ANC3_CANVAS_ADDR 4284655180 #define NR2_SAD2NORM_LUT3 5985 #define HCODEC_CINDEX3_REG 4909 #define NR2_SAD2NORM_LUT1 5983 #define NR2_SAD2NORM_LUT2 5984 #define SRSHARP1_SHARP_SR2_MISC 13408 #define P_ASSIST_HW_REV 4291854668 #define P_OSD1_AFBCD_CONV_CTRL 4287678104 #define P_SLICE_VER_POS_PIC_TYPE 4284624912 #define P_VPP2_VSC_REGION34_STARTP 4287652888 #define P_HCODEC_ANC3_CANVAS_ADDR 4284638796 #define P_VDEC2_VLD_DC_PRED 4284657844 #define P_PK_CON_2DRTHPGAIN_LIMIT 4287678504 #define VPU_VDIN_ASYNC_HOLD_CTRL 10052 #define P_CPV2_HE_ADDR 4287648400 #define VIU_OSD_BLEND_CTRL1 14784 #define P_VPP_MATRIX_COEF20_21 4287657356 #define MCDI_RO_GMV_VLD_CNT 12193 #define P_VPU_PROT3_REQ_ONOFF 4287667696 #define MSFTINT0 798 #define MSFTINT1 799 #define P_VD2_AFBC_SIZE_OUT 4287677984 #define P_DI_CHAN2_FMT_CTRL 4287651552 #define DBLK_RV8_QUANT 2422 #define P_VPU_WRARB_REQEN_SLV_L2C1 4287667852 #define SANA_SHIFTED_DATA 12331 #define P_NR4_SNR_ALPHA0_MAX_MIN 4287674024 #define P_GE2D_SRC2_CLIPX_START_END 4287890112 #define VIU_OSD1_OETF_3X3_OFST_1 6817 #define VIU_OSD1_OETF_3X3_OFST_0 6816 #define HEVC_DBKW_CANVAS_ADDR 14769 #define EE_ASSIST_MBOX3_FIQ_SEL 8319 #define P_HCODEC_AV_SCRATCH_9 4284639012 #define P_VPU_DI_INP_MMC_CTRL 4287667228 #define P_HCODEC_AV_SCRATCH_5 4284638996 #define ASYNC_FIFO_RESET 22 #define P_HCODEC_AV_SCRATCH_6 4284639000 #define VDEC2_MC_CTRL_REG 10496 #define P_HCODEC_AV_SCRATCH_7 4284639004 #define P_HCODEC_AV_SCRATCH_8 4284639008 #define P_HCODEC_AV_SCRATCH_1 4284638980 #define P_HCODEC_AV_SCRATCH_2 4284638984 #define P_HCODEC_AV_SCRATCH_3 4284638988 #define P_HCODEC_AV_SCRATCH_4 4284638992 #define P_HCODEC_AV_SCRATCH_M 4284639064 #define P_HCODEC_AV_SCRATCH_N 4284639068 #define P_HCODEC_AV_SCRATCH_I 4284639048 #define P_HCODEC_AV_SCRATCH_J 4284639052 #define P_HCODEC_AV_SCRATCH_K 4284639056 #define P_HCODEC_AV_SCRATCH_L 4284639060 #define P_HCODEC_AV_SCRATCH_E 4284639032 #define P_HCODEC_AV_SCRATCH_F 4284639036 #define P_HCODEC_AV_SCRATCH_G 4284639040 #define P_HCODEC_AV_SCRATCH_H 4284639044 #define P_HCODEC_AV_SCRATCH_A 4284639016 #define P_HCODEC_AV_SCRATCH_B 4284639020 #define P_HCODEC_AV_SCRATCH_C 4284639024 #define P_HCODEC_AV_SCRATCH_D 4284639028 #define HUE_LUM_RANGE_REG00 3 #define HUE_LUM_RANGE_REG01 9 #define VDIN1_VSC_INI_CTRL 5156 #define HUE_LUM_RANGE_REG02 15 #define HUE_LUM_RANGE_REG03 21 #define P_HCODEC_VLC_COEFF_RD_REQ 4284642564 #define P_VIU2_ADDR_END 4287659004 #define VBO_LANE_OUTPUT 5237 #define P_QDCT_MIX_I_PRED_STATUS 4284644604 #define VPP_WRAP_OSD3_MATRIX_COEF00_01 15792 #define PARSER_FETCH_CMD 14434 #define HUE_LUM_RANGE_REG04 27 #define HUE_LUM_RANGE_REG05 33 #define HUE_LUM_RANGE_REG06 39 #define HUE_LUM_RANGE_REG07 45 #define P_HCODEC_MC_OM_MB_XY 4284638268 #define P_DI_BLEND_REG1_Y 4287650892 #define P_DI_DIWR_CTRL 4287651616 #define P_SHARP_DB_FLT_RANDLUT 4287678948 #define P_DI_BLEND_REG1_X 4287650888 #define P_HCODEC_DEBLK_CMD 4284643392 #define VERSION_CTRL 1024 #define MIPI_DSI_DWC_GEN_VCID_OS 7180 #define P_QDCT_TOP_CONTROL 4284644476 #define VIU_OSD1_MATRIX_COEF02_10 6802 #define P_VDEC2_ANC22_CANVAS_ADDR 4284655256 #define VPU_VDIN_PRE_ARB_CTRL 10004 #define P_L_OEH_VS_ADDR 4287647848 #define SPICC0_PERIODREG 19462 #define QDCT_JPEG_Y_START_END 7975 #define ENCP_VIDEO_MATRIX_CR 7100 #define DOS_SCRATCH31 16175 #define DOS_SCRATCH30 16174 #define P_VDEC2_MPC_P 4284648472 #define DOS_SCRATCH29 16173 #define DOS_SCRATCH28 16172 #define DOS_SCRATCH27 16171 #define DOS_SCRATCH26 16170 #define DOS_SCRATCH25 16169 #define P_DI_MEM_RANGE_MAP_Y 4287651572 #define DOS_SCRATCH24 16168 #define DOS_SCRATCH23 16167 #define P_VDEC2_MPC_W 4284648484 #define ENCL_VFIFO2VD_LINE_BOT_START 7317 #define P_HCODEC_LAST_SLICE_MV_ADDR 4284641472 #define DI_MTNPRD_X 6091 #define DI_MTNPRD_Y 6092 #define HCODEC_MC_MPORT_CTRL 6464 #define ENCP_VIDEO_MATRIX_CB 7099 #define ENCI_VFIFO2VD_CTL 7192 #define P_VLC_JPEG_COEFF_BUF_STAT 4284642660 #define PSCALE_PICO_H 2325 #define P_LVDS_BIST_MUX1 4287648680 #define DOS_SCRATCH11 16155 #define P_LVDS_BIST_MUX0 4287648676 #define DOS_SCRATCH10 16154 #define P_ENCI_VBI_CC525_LN 4287655052 #define P_HEVCD_MPP_L0_WEIGHT_FLAG_ADDR 4284666352 #define PSCALE_PICO_W 2324 #define P_VPP_HCTI_GAIN 4287657808 #define P_AIU_958_BRST 4291842052 #define VPP2_MATRIX_PROBE_POS 6494 #define VPU_DI_DIWR_MMC_CTRL 9996 #define DOS_SCRATCH22 16166 #define DOS_SCRATCH21 16165 #define DOS_SCRATCH20 16164 #define P_VDEC2_MPC_D 4284648476 #define P_VDEC2_MPC_E 4284648480 #define P_VPP_HSC_PHASE_CTRL 4287657056 #define P_HCODEC_MC_OMDN_MB_XY 4284638492 #define CBREAK_CTRL 825 #define DOS_SCRATCH19 16163 #define P_VPP_HSHARP_CTRL 4287657280 #define DOS_SCRATCH18 16162 #define DOS_SCRATCH17 16161 #define P_HCODEC_AV_SCRATCH_0 4284638976 #define DOS_SCRATCH16 16160 #define DOS_SCRATCH15 16159 #define DOS_SCRATCH14 16158 #define HEVC_PARSER_QUANT_READ 12582 #define DOS_SCRATCH13 16157 #define DOS_SCRATCH12 16156 #define mLVDS_data_latch_0_toggle 14 #define HEVC_CINDEX0_REG 13098 #define P_HEVC_SAO_C_START_ADDR 4284667956 #define P_VDEC2_MDEC_PICW_BUF2_STATUS 4284655348 #define SRSHARP0_PKGAIN_VSLUMA_LUT_H 12927 #define P_XVYCC_VD1_RGB_DLUT_0_3 4287677896 #define HEVC_SCD_BAK_MV_Y 15383 #define HEVC_SCD_BAK_MV_X 15382 #define P_DOLBY_CORE3_REG_START 4287682560 #define XVYCC_VD1_RGB_CTRST 12656 #define P_AFBC_PIXEL_VER_SCOPE 4287654848 #define P_SPICC1_INTREG 4291907596 #define VKS_PARA_ADDR_PORT 12558 #define SPI_FLASH_WREN 30 #define P_VLD_MEM_SWAP_ADDR 4284625236 #define VPP2_OSD_HSC_INI_PHASE 6596 #define DI_MEM_CHROMA_X0 6111 #define VIDEO_PTS_DTS_WR_PTR 14452 #define P_VDEC_ASSIST_MBOX2_FIQ_SEL 4284613100 #define P_HEVCD_MPP_VDEC_MCR_CTL 4284666656 #define P_ENCP_MACV_WAVE_END 4287655704 #define SPI_FLASH_WRDI 29 #define HEVC_MPRED_DBG2_MODE 12867 #define SRSHARP1_DB_FLT_SEED_V 13437 #define SRSHARP1_DB_FLT_SEED_U 13436 #define SRSHARP0_PKGAIN_VSLUMA_LUT_L 12926 #define DI_MEM_CHROMA_Y0 6112 #define SRSHARP1_DB_FLT_SEED_Y 13435 #define P_HEVC_CINDEX6_REG 4284665024 #define VDEC2_SLICE_QP 11274 #define P_NR2_CFR_PARA_CFG1 4287651444 #define P_NR2_CFR_PARA_CFG0 4287651440 #define DI_INFO_DATA 5938 #define P_DOS_APB_ERR_CTRL 4284677132 #define VPU_PROT2_Y_LEN_STEP 10084 #define NR_ALP1_ERR2CURV_TH_RATE 12827 #define VPP_SMOKE1_H_START_END 7469 #define P_HCODEC_WRRSP_LMEM 4284632396 #define P_VDEC2_PATTERN_CODE 4284657836 #define P_HEVC_MMAX_REG 4284664908 #define VDIN_HIST_H_START_END 4657 #define P_ENCP_DVI_VSO_ELINE_ODD 4287656148 #define P_AIU_MEM_AIFIFO2_START_PTR 4291842472 #define P_HCODEC_MC_MB_INFO 4284638212 #define P_HCODEC_QDCT_I_PRED_REF_WR_IDX 4284644552 #define VDEC2_ANC11_CANVAS_ADDR 10651 #define mLVDS_reset_length 23 #define AUDIN_FIFO1_RDPTR 13367 #define P_SHARP_HVSIZE 4287678464 #define VDIN1_WIN_V_START_END 5230 #define P_HCODEC_ME_STEP0_CLOSE_MV 4284644680 #define P_VDEC2_MSP 4284648448 #define HEVC_MPRED_MV_WPTR 12821 #define SPI_FLASH_SLAVE 20492 #define VIU_OSD_BLEND_BLEND0_SIZE 14779 #define VDEC2_DBLK_CB_BFILT 10586 #define VDEC2_RV_AI_Y_X 11785 #define P_NR2_MATNR_DEGHOST 4287651256 #define P_VLC_VB_BUFF 4284642412 #define P_DI_IF1_FMT_W 4287651792 #define P_NR4_MCNR_SKIN_CENT 4287674184 #define REG_CM2_ENH_COEFF1_H09 329 #define MCDI_HV_BLKSIZEIN 12033 #define REG_CM2_ENH_COEFF1_H00 257 #define P_ENCI_DBG_FLDLN_RST 4287655204 #define REG_CM2_ENH_COEFF1_H06 305 #define REG_CM2_ENH_COEFF1_H05 297 #define REG_CM2_ENH_COEFF1_H08 321 #define REG_CM2_ENH_COEFF1_H07 313 #define REG_CM2_ENH_COEFF1_H02 273 #define REG_CM2_ENH_COEFF1_H01 265 #define REG_CM2_ENH_COEFF1_H04 289 #define P_HENC_TOP_MV_0 4284642600 #define REG_CM2_ENH_COEFF1_H03 281 #define P_HENC_TOP_MV_1 4284642604 #define P_HENC_TOP_MV_2 4284642608 #define P_HENC_TOP_MV_3 4284642612 #define P_HEVC_SAO_PIC_SIZE 4284667924 #define COI_H_SCOPE_REG 525 #define P_ENCT_VIDEO_VAVON_ELINE 4287656396 #define VPP_VD2_HDR_IN_SIZE 7664 #define P_HEVC_MDB_ADDR_REG 4284664940 #define REG_CM2_ENH_COEFF1_H11 345 #define REG_CM2_ENH_COEFF1_H10 337 #define VIU2_VD1_IF0_CHROMA1_RPT_PAT 7775 #define P_HCODEC_IE_DATA_FEED_BUFF_INFO 4284640096 #define REG_CM2_ENH_COEFF1_H13 361 #define REG_CM2_ENH_COEFF1_H12 353 #define P_VPP2_VADJ2_Y 4287653136 #define HEVC_MPRED_REF_NUM 12809 #define HCODEC_ASSIST_AMR1_INTF 4148 #define HCODEC_ASSIST_AMR1_INTE 4147 #define P_VPP_SCALE_COEF_IDX 4287656972 #define HCODEC_ASSIST_AMR1_INTD 4146 #define ENCP_VIDEO_HOFFST 7093 #define CPH2_POL 7 #define HCODEC_ASSIST_AMR1_INT9 4142 #define HCODEC_ASSIST_AMR1_INT8 4141 #define P_DOS_MEM_PD_HCODEC 4284677320 #define HCODEC_ASSIST_AMR1_INT7 4140 #define HCODEC_ASSIST_AMR1_INT6 4139 #define HCODEC_ASSIST_AMR1_INT5 4138 #define HCODEC_ASSIST_AMR1_INT4 4137 #define HCODEC_ASSIST_AMR1_INTC 4145 #define HCODEC_ASSIST_AMR1_INTB 4144 #define VDIN_CM_BRI_CON_CTRL 4653 #define HCODEC_ASSIST_AMR1_INTA 4143 #define HCODEC_ASSIST_AMR1_INT3 4136 #define HCODEC_ASSIST_AMR1_INT2 4135 #define P_VPP_CLIP_MISC0 4287657828 #define HCODEC_ASSIST_AMR1_INT1 4134 #define P_VPP_CLIP_MISC1 4287657832 #define HCODEC_ASSIST_AMR1_INT0 4133 #define P_HEVC_MPRED_IF_WAIT_CNT 4284663004 #define VENC_VIDEO_EXSRC 7009 #define P_NR4_MCNR_LPF_CTRL 4287683588 #define ENCL_VIDEO_EN 7328 #define P_OEV1_HE_ADDR 4287648448 #define ANC0_CANVAS_ADDR 2448 #define P_HEVC_MDB_DATA_REG 4284664944 #define P_SHARP_SR3_DERING_PARAM0 4287678920 #define OEV3_VE_ADDR 5306 #define P_WATCHDOG_TCNT 4291883224 #define P_VDEC2_DCAC_MB_COUNT 4284659800 #define P_VPP2_OSD_HSC_PHASE_STEP 4287653644 #define VDIN1_VSHRK_CTRL 5233 #define HCODEC_PSCALE_CTRL2 6446 #define HCODEC_PSCALE_CTRL1 6441 #define MDEC_PIC_DC_MUX_CTRL 2445 #define P_D2D3_DBLD_PATH_CTRL 4287671384 #define HEVCD_MCRCC_CTL1 13552 #define HEVCD_MCRCC_CTL2 13553 #define HEVCD_MCRCC_CTL3 13554 #define P_HCODEC_QDCT_VLC_QUANT_CTL_1 4284644596 #define P_HCODEC_QDCT_VLC_QUANT_CTL_0 4284644592 #define AHB_BRIDGE_REMAP0 15489 #define AHB_BRIDGE_REMAP1 15490 #define AHB_BRIDGE_REMAP2 15491 #define AHB_BRIDGE_REMAP3 15492 #define P_OEV3_HE_ADDR 4287648480 #define P_MCDI_REL_DET_LPF_MSK_22_30 4287675628 #define SRSHARP0_PK_ALP2_MIN_MAX 12833 #define VPP_POSTBLEND_CURRENT_XY 7461 #define P_ENCP_VBI_HVAL 4287655760 #define P_HCODEC_QDCT_MB_PAUSE_CTL 4284644472 #define VDIN_MATRIX_PROBE_POS 4650 #define P_VIU2_OSD2_TCOLOR_AG3 4287658216 #define P_VIU2_OSD2_TCOLOR_AG2 4287658212 #define P_VIU2_OSD2_TCOLOR_AG1 4287658208 #define P_VIU2_OSD2_TCOLOR_AG0 4287658204 #define PK_CON_2DRTBPGAIN_LIMIT 12812 #define P_RDMA_ACCESS_MAN 4287644748 #define P_ENCP_MACV_MAXY_VAL 4287655684 #define P_VIUB_SW_RESET 4287660036 #define P_VENC_VDAC_DAC3_OFFSET 4287655900 #define VPP_SCO_FIFO_CTRL 7475 #define TCON_VS_SEL 4 #define P_ENCL_VIDEO_VSO_END 4287656672 #define P_VIU_OSD1_MATRIX_HL_COLOR 4287654508 #define P_VI_HIST_PIC_SIZE 4287674528 #define P_MCDI_RO_FLD_BAD_REL_CNT 4287676052 #define POI_XY_DIR_REG 523 #define MCDI_REL_BADW_GAIN_OFFST_01 12065 #define SRSHARP1_SR3_DRTLPF_THETA 13427 #define SRSHARP1_DEJ_CTRL 13412 #define LCD_LVDS_SEL27 5 #define P_HCODEC_VLD_MEM_VIFIFO_MEM_CTL 4284641608 #define ENCI_MACV_BKP_MAX 6995 #define P_VIU2_OSD1_COLOR_ADDR 4287658052 #define VDEC2_CURR_CANVAS_CTRL 10675 #define P_HCODEC_ME_AB_MEM_CTL 4284644664 #define HEVC_SAO_ABV_WPTR 13844 #define P_VIU2_OSD2_CTRL_STAT2 4287658292 #define P_PARSER_SEARCH_MASK 4291879336 #define mLVDS_bit_num 6 #define VPP_OSD_SC_DUMMY_DATA 7623 #define HCODEC_QDCT_MIX_I_PRED_STATUS 7999 #define MCDI_REL_BADW_GAIN_OFFST_23 12066 #define SANA_STREAM_RD_PTR 12324 #define P_HCODEC_DCAC_CPU_ADDRESS 4284643408 #define P_DI_BLEND_REG2_X 4287650896 #define VPP_WRAP_OSD1_MATRIX_EN_CTRL 15725 #define P_DI_BLEND_REG2_Y 4287650900 #define HEVC_IQIDCT_DEBUG_INFO_0 15887 #define P_HEVCD_MPP_ANC2AXI_TBL_DATA 4284666256 #define VLD_STATUS_CTRL 3072 #define NR4_MCNR_BLD_VS3LUT0 14082 #define NR4_MCNR_BLD_VS3LUT1 14083 #define NR4_MCNR_BLD_VS3LUT2 14084 #define P_VLC_VB_PRE_BUFF_HI 4284642416 #define P_HCODEC_IMEM_DMA_CTRL 4284632320 #define NR4_MCNR_AC_DC_CRTL 11716 #define P_VPP_HSC_REGION34_STARTP 4287657028 #define P_VD2_AFBC_PIXEL_VER_SCOPE 4287678016 #define P_MCDI_CHAR_DET_DIF_THD 4287675740 #define VDEC2_MC_WT_PRED_CTRL 10562 #define P_HEVC_PARSER_RESERVED_27 4284662940 #define P_PK_OS_ADPT_MISC 4287678612 #define PARSER_SCR 14446 #define HLTI_CON_2_GAIN_1 12856 #define HLTI_CON_2_GAIN_0 12855 #define HCODEC_ANC28_CANVAS_ADDR 6572 #define P_ENCP_VIDEO_RGB_CTRL 4287655644 #define VLC_INT_CONTROL_INTER 7471 #define ENCT_VIDEO_VAVON_BLINE 7284 #define P_VDEC2_MDEC_EXTIF_STS0 4284655512 #define P_VDEC2_MAC_CTRL1 4284648832 #define P_VDEC2_MAC_CTRL2 4284648896 #define P_ENCL_MAX_LINE_SWITCH_POINT 4287656736 #define P_OEH_HS_ADDR 4287648352 #define P_ENCP_VBI_WIDTH 4287655756 #define I2C_M_DATA_CNT_LSB 8 #define VDEC2_HDEC_MC_MBRIGHT_IDX 10545 #define P_L_GAMMA_PROBE_HL_COLOR 4287647792 #define VPU_PROT1_REQ_ONOFF 10076 #define AUDIN_FIFO1_HOLD0_EN 19 #define VIU2_OSD1_MATRIX_COEF23_24 7798 #define DI_MC_32LVL0 5930 #define DI_MC_32LVL1 5931 #define NR4_MCNR_ALP1_LP_PRAM 14108 #define P_VP9_SHADOW_CTRL 4284663104 #define VBO_GCLK_MAIN 5234 #define P_HCODEC_ANC2_CANVAS_ADDR 4284638792 #define HEVC_PSCALE_SRCKEY_CTRL1 14635 #define MCDI_REL_DET_LUT_0_3 12094 #define HEVC_PSCALE_SRCKEY_CTRL0 14634 #define ENCI_MACV_N1 6961 #define ENCI_MACV_N0 6960 #define LCD_LVDS_SEL54 6 #define ENCT_SYNC_LINE_LENGTH 7240 #define ENCI_MACV_N7 6967 #define ENCI_MACV_N6 6966 #define SPICC0_TXDATA 19457 #define ENCI_MACV_N9 6969 #define ENCI_MACV_N8 6968 #define ENCI_MACV_N3 6963 #define ENCI_MACV_N2 6962 #define VIU2_OSD1_MATRIX_COEF11_12 7794 #define ENCI_MACV_N5 6965 #define ENCI_MACV_N4 6964 #define OSDSR_CTRL_MODE 12593 #define HCODEC_ANC30_CANVAS_ADDR 6574 #define AUDIN_FIFO1_CHAN 11 #define P_VDEC_ASSIST_MBOX1_FIQ_SEL 4284613084 #define HEVC_MPRED_L0_REF14_POC 12846 #define VDIN1_BLKBAR_IND_LEFT1_CNT 5223 #define P_VLC_ADV_CONFIG 4284642452 #define STH1_SEL 11 #define HEVC_VLD_MEM_VIFIFO_LEVEL 15431 #define P_VIU_OSD2_COLOR_ADDR 4287654084 #define D2D3_INTF_CTRL0 6665 #define VPU_SECURE_DUMMY 10056 #define AUDIN_HDMI_MEAS_INTR_MASKN 13474 #define OSD2_BLEND_SRC_CTRL 7678 #define P_ASYNC_FIFO_REG5 4291862548 #define P_ASYNC_FIFO_REG3 4291862540 #define P_ASYNC_FIFO_REG4 4291862544 #define P_ASYNC_FIFO_REG1 4291862532 #define P_ASYNC_FIFO_REG2 4291862536 #define P_ASYNC_FIFO_REG0 4291862528 #define NR4_DRT_SAD_ALP_CORE 11687 #define P_D2D3_DRMIF_CTRL 4287671456 #define DNR_HVSIZE 11521 #define HEVC_ASSIST_AMR2_INTF 12356 #define HEVC_ASSIST_AMR2_INTE 12355 #define HEVC_ASSIST_AMR2_INTB 12352 #define HEVC_ASSIST_AMR2_INTA 12351 #define HEVC_ASSIST_AMR2_INTD 12354 #define HEVC_ASSIST_AMR2_INTC 12353 #define VIU_OSD1_TEST_RDDATA 6700 #define P_LTI_DIR_CORE_ALPHA 4287678632 #define P_ENCT_VIDEO_VSO_ELINE 4287656424 #define VDEC2_CINDEX1_REG 9003 #define P_VDEC2_DECODER_BUFFER_INFO 4284657724 #define P_HCODEC_VLC_VB_MEM_CTL 4284642396 #define HEVC_CBREAK0_REG 13108 #define P_IE_ME_MB_INFO 4284644616 #define HEVC_ANC7_CANVAS_ADDR 14743 #define HEVC_ASSIST_AMR2_INT9 12350 #define HEVC_ASSIST_AMR2_INT6 12347 #define HEVC_ASSIST_AMR2_INT5 12346 #define HEVC_ASSIST_AMR2_INT8 12349 #define HEVC_ASSIST_AMR2_INT7 12348 #define HEVC_ASSIST_AMR2_INT2 12343 #define HEVC_ASSIST_AMR2_INT1 12342 #define HEVC_ASSIST_AMR2_INT4 12345 #define HEVC_ASSIST_AMR2_INT3 12344 #define HEVC_ASSIST_AMR2_INT0 12341 #define HEVC_SAO_CTRL9 13869 #define HEVC_SAO_CTRL8 13868 #define HEVC_SAO_CTRL7 13861 #define HEVC_SAO_CTRL6 13860 #define HEVC_SAO_CTRL5 13859 #define HEVC_SAO_CTRL4 13858 #define HEVC_SAO_CTRL3 13857 #define P_VENC_VDAC_DAC5_FILT_CTRL0 4287656280 #define HEVC_SAO_CTRL2 13856 #define P_VENC_VDAC_DAC5_FILT_CTRL1 4287656284 #define HEVC_SAO_CTRL1 13826 #define HEVC_SAO_CTRL0 13825 #define P_DNR_RO_VBOF_STAT_CNT_9 4287673624 #define P_HCODEC_VLD_ERROR_MASK 4284641464 #define P_DNR_RO_VBOF_STAT_CNT_6 4287673612 #define P_DNR_RO_VBOF_STAT_CNT_5 4287673608 #define P_DNR_RO_VBOF_STAT_CNT_8 4287673620 #define AFBC_VD_CFMT_CTRL 6891 #define P_DNR_RO_VBOF_STAT_CNT_7 4287673616 #define P_DNR_RO_VBOF_STAT_CNT_2 4287673596 #define P_DNR_RO_VBOF_STAT_CNT_1 4287673592 #define P_DNR_RO_VBOF_STAT_CNT_4 4287673604 #define P_DNR_RO_VBOF_STAT_CNT_3 4287673600 #define P_DNR_RO_VBOF_STAT_CNT_0 4287673588 #define SPICC1_TESTREG 21511 #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 15739 #define HEVC_PSCALE_STATUS 14622 #define MCDI_FIELD_MV 12128 #define VDEC2_MBREAK3_REG 8983 #define HEVC_VCOP_CTRL_REG 15872 #define P_SPI_FLASH_B8 4291903584 #define P_SPI_FLASH_B9 4291903588 #define HEVC_ANC11_CANVAS_ADDR 14747 #define P_ENCT_VIDEO_HOFFST 4287656444 #define P_ENCP_VIDEO_SYNC_WAVE_CURVE 4287655604 #define ME_SUB_ACT_CTL 8031 #define P_CCPU_INTR_MSK 4284615824 #define HEVC_ASSIST_DMA_INT_MSK2 12391 #define P_L_DE_VE_ADDR 4287648080 #define P_HEVC_LAST_SLICE_MV_ADDR 4284674240 #define P_PARSER_STATUS 4291879488 #define VDEC2_WRRSP_IMEM 9027 #define VDIN0_CM_BRI_CON_CTRL 4653 #define QDCT_ADV_CONFIG 7988 #define CINDEX7_REG 817 #define P_ENCP_MACV_1ST_PSSYNC_STRT 4287655688 #define GE2D_GEN_CTRL1 161 #define GE2D_GEN_CTRL2 162 #define GE2D_GEN_CTRL3 232 #define GE2D_GEN_CTRL4 234 #define P_AIU_958_AUTO_PAUSE 4291842200 #define GE2D_GEN_CTRL0 160 #define P_SPI_FLASH_C6 4291903576 #define P_SPI_FLASH_C7 4291903580 #define P_HCODEC_RV_AI_Y_X 4284643364 #define P_SPI_FLASH_C0 4291903552 #define P_SPI_FLASH_C1 4291903556 #define P_SPI_FLASH_C2 4291903560 #define P_SPI_FLASH_C3 4291903564 #define P_SPI_FLASH_C4 4291903568 #define P_SPI_FLASH_C5 4291903572 #define P_ENCL_VIDEO_RGB_CTRL 4287656708 #define P_HEVC_MPRED_INT_EN 4284663820 #define P_VPP2_VADJ1_Y 4287653124 #define P_VPP2_FIFO_STATUS 4287653024 #define VLTI_FLT_CON_CLP 12858 #define P_HEVC_SHIFT_LENGTH_PROTECT 4284663016 #define ENCT_VIDEO_VSO_END 7288 #define VPP_VSC_REGION4_ENDP 7431 #define P_VDEC2_DBLK_Y_VFILT 4284654968 #define LVDS_BIST_MUX0 5353 #define LVDS_BIST_MUX1 5354 #define P_IE_CONTROL 4284644608 #define VSYNC_HE_ADDR 5338 #define P_VPP2_HSC_REGION4_PHASE_SLOPE 4287652956 #define P_HEVC_MINDEX3_REG 4284664884 #define P_VIU2_VD1_IF0_GEN_REG2 4287658420 #define QDCT_TOP_WRRSP 7970 #define P_HCODEC_MMAX_REG 4284632140 #define P_ENCI_VBI_WSS_LN 4287655064 #define P_VDEC2_MC_CTRL_GCLK_CTRL 4284654900 #define VIU2_SW_RESET 7681 #define VPU_VLOCK_OVWRITE_ACCUM1 12296 #define VPU_VLOCK_OVWRITE_ACCUM0 12295 #define P_VDEC2_LMEM_DMA_ADR 4284648772 #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 15805 #define VIU_OSD1_FIFO_CTRL_STAT 6699 #define P_HCODEC_DBLK_AVSFLAGS 4284638648 #define AIU_MEM_I2S_LEVEL 5237 #define VDEC2_DBLK_VLD_HCMD1 10619 #define VDEC2_DBLK_VLD_HCMD0 10620 #define VDEC2_DBLK_VLD_HCMD2 10618 #define SHARP_SR3_DERING_GAINVS_MADSAD 12912 #define HCODEC_BYTE_ALIGN_PEAK_HI 7195 #define P_DVIN_CTRL_STAT 4291830676 #define V3_SKIP_CONTROL 8044 #define DE_VS_ADDR 5331 #define MC_PIC_W_H 2312 #define I2SIN_LRCLK_INVT 7 #define P_HEVC_IQIT_BITDEPTH 4284668972 #define ENCP_VIDEO_FILT_CTRL 7096 #define mLVDS2_dual_gate 7 #define P_VDEC2_ANC25_CANVAS_ADDR 4284655268 #define GAMMA_VCOM_HSWITCH_ADDR 5251 #define P_OSD1_AFBCD_SIZE_IN 4287678088 #define P_HCODEC_VLC_DELTA_QP 4284642548 #define P_HEVC_PSCALE_RST 4284671040 #define P_HCODEC_VLD_MEM_VIFIFO_CONTROL 4284641552 #define AIU_958_SYNWORD3_MASK 5153 #define P_VIU2_ADDR_START 4287657984 #define P_VKS_PRELPF_YCOEF0 4287677448 #define P_VKS_PRELPF_YCOEF1 4287677452 #define P_ENCL_TST_MDSEL 4287656548 #define VDEC2_CINDEX4_REG 9006 #define VDIN0_HIST_SPL_PIX_CNT 4661 #define VLD_DECODE_CONTROL 3096 #define VDEC2_ANC18_CANVAS_ADDR 10658 #define ENCP_VIDEO_OFLD_VOAV_OFST 7098 #define VDEC2_MC_MBBOT_WRRSP_CNT 10684 #define VDIN0_LCNT_SHADOW_STATUS 4615 #define P_MCDI_MCINFORD_CTRL 4287676020 #define HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT 7249 #define AIU_MEM_AIFIFO_MAN_WP 5257 #define HEVC_MINDEX4_REG 13070 #define HCODEC_HENC_TOP_MV_0 7498 #define HCODEC_HENC_TOP_MV_1 7499 #define AUDIN_HDMI_MEAS_CTRL 13472 #define HCODEC_HENC_TOP_MV_2 7500 #define HCODEC_HENC_TOP_MV_3 7501 #define AIU_958_PAUSE_PAYLOAD 5157 #define P_HCODEC_IE_ME_MB_INFO 4284644616 #define ENCI_VBI_CCDT_EVN 6945 #define VDIN1_MATRIX_HL_COLOR 5161 #define mLVDS_PN_SWAP 1 #define SAD_CONTROL 8003 #define HCODEC_VLC_VB_CONTROL 7446 #define SRSHARP1_PK_CON_2CIRBPGAIN_TH_RATE 13319 #define tcon_double_ini 8 #define P_VPU_VLOCK_LOOP0_CTRL0 4287676428 #define P_ENCL_VIDEO_PR_OFFST 4287656600 #define VD2_IF0_CHROMA_PSEL 6785 #define HCODEC_VLC_VB_SW_RD_PTR 7444 #define NR4_MCNR_GREEN_GAIN_PAR0 11726 #define NR4_MCNR_GREEN_GAIN_PAR1 11727 #define tcon_double_inv 0 #define OSDSR_UK_GRAD2DDIAG_LIMIT 12604 #define PSCALE_PICI_H 2323 #define P_HCODEC_MBREAK3_REG 4284632156 #define P_NR4_RO_NM_VAR_SUM 4287683716 #define PSCALE_PICI_W 2322 #define DET3D_SPLT_CFG 5942 #define P_VC1_CONTROL_REG 4284625016 #define P_DOS_SCRATCH8 4284677216 #define P_LCD_PWM0_HI_ADDR 4287648500 #define P_DOS_SCRATCH9 4284677220 #define P_VDEC2_LAST_MVX 4284657860 #define P_DOS_SCRATCH2 4284677192 #define P_VDEC2_LAST_MVY 4284657864 #define P_DOS_SCRATCH3 4284677196 #define P_DOS_SCRATCH0 4284677184 #define P_DOS_SCRATCH1 4284677188 #define P_DOS_SCRATCH6 4284677208 #define P_DOS_SCRATCH7 4284677212 #define P_VPU_RDARB_MODE_L2C1 4287667828 #define P_DOS_SCRATCH4 4284677200 #define P_DOS_SCRATCH5 4284677204 #define P_STV2_VS_ADDR 4287648436 #define P_HEVC_DBLK_CTRL 4284671300 #define SRSHARP1_SR3_DERING_GAINVS_VR2MAX 13425 #define P_HEVC_DCAC_DMA_CTRL 4284676168 #define P_GE2D_HSC_START_PHASE_STEP 4287890160 #define VDEC2_PSCALE_PICO_H 10517 #define MCDI_RPTMV_THD1 12047 #define MCDI_RPTMV_THD0 12046 #define MCDI_RPTMV_THD2 12048 #define VDEC2_PSCALE_PICO_W 10516 #define HCODEC_VLD_MEM_VIFIFO_MEM_CTL 7250 #define HEVC_MPRED_VERSION 12800 #define DOS_VDEC_MCRCC_STALL2_CTRL 16194 #define HEVC_MBREAK_CTRL 13081 #define P_VDEC2_VLD_MEM_VIFIFO_WP 4284657940 #define P_VDEC2_DBLK_OST_CBCRDIFF 4284655096 #define P_VDEC2_DBLK_STATUS1 4284655020 #define MCDI_REF_MV_NUM 12055 #define P_DECOMB_DET_VERT_CON0 4287673856 #define P_DECOMB_DET_VERT_CON1 4287673860 #define PK_CIRFB_HP_CORING 12815 #define HEVC_CBREAK3_REG 13111 #define P_VDEC2_DBLK_CTRL 4284654916 #define P_HCODEC_VLC_ENC_COEFF_BITS 4284642676 #define CPSR 801 #define P_VPU_WRARB_MODE_L2C1 4287667848 #define P_UART3_DF_REG_A129 4291956868 #define P_UART3_DF_REG_A128 4291956864 #define P_VPU_ARB_PATH_CTRL 4287667940 #define HEVC_STREAM_WR_PTR 12548 #define VPP_CHROMA_DATA_PORT 7537 #define VDEC2_ANC7_CANVAS_ADDR 10647 #define HCODEC_MINDEX6_REG 4880 #define P_VPP_VADJ1_MC_MD 4287657228 #define VIU_OSD1_TCOLOR_AG0 6679 #define VIU2_OSD1_FIFO_CTRL_STAT 7755 #define HEVC_SAO_VB_RD_START_ADDR 13843 #define P_VDEC2_VLD_MEM_VIFIFO_RP 4284657944 #define P_ENCT_VIDEO_PB_OFFST 4287656340 #define IDCT_TM1_PT0 4 #define HEVC_CINT_VEC_BASE 13090 #define VIU_OSD1_TCOLOR_AG3 6682 #define IDCT_TM1_PT1 8 #define VIU_OSD1_TCOLOR_AG2 6681 #define OSDSR_UK_GRAD2DDIAG_TH_RATE 12603 #define VIU_OSD1_TCOLOR_AG1 6680 #define P_VDEC2_DCAC_DMA_ADDRESS 4284659788 #define P_UART3_DF_REG_A136 4291956896 #define P_UART3_DF_REG_A134 4291956888 #define P_UART3_DF_REG_A135 4291956892 #define DI_BLEND_REG2_X 5908 #define P_UART3_DF_REG_A132 4291956880 #define DI_BLEND_REG2_Y 5909 #define P_UART3_DF_REG_A133 4291956884 #define P_UART3_DF_REG_A130 4291956872 #define P_UART3_DF_REG_A131 4291956876 #define P_NR4_MCNR_ALP1_MVX_LUT1 4287683684 #define P_NR4_MCNR_ALP1_MVX_LUT2 4287683688 #define P_NR4_MCNR_ALP1_MVX_LUT3 4287683692 #define P_DET3D_RO_MAT_LUMA_TB 4287651344 #define DECOMB_MTN_GAIN_OFST 11656 #define HEVC_DBLK_STATUS 14675 #define ME_SUB_SNAP_GLITCH 8030 #define P_HEVC_MPRED_L0_REF09_POC 4284663972 #define P_V5_MB_DIFF_SUM 4284644848 #define IEC958_TIME_STAMP_1 5284 #define IEC958_TIME_STAMP_0 5283 #define IEC958_TIME_STAMP_3 5286 #define IEC958_TIME_STAMP_2 5285 #define ROI_X_SCOPE_REG 521 #define P_ENCI_SYNC_HSO_BEGIN 4287654952 #define VPP2_VE_H_V_SIZE 6564 #define VDEC2_DBLK_STATUS1 10603 #define VPP_SMOKE2_VAL 7467 #define HCODEC_QP_CTRL_REG 7681 #define P_VPP_HSC_PHASE_CTRL1 4287657168 #define NR4_MCNR_ALP1_SGN_COR 14103 #define HCODEC_IQIDCT_DEBUG_INFO_0 7695 #define HEVC_MPRED_MV_RD_END_ADDR 12898 #define GE2D_MATRIX_COEF02_10 199 #define P_MCPU_INTR_MSK 4284615696 #define P_VIU2_OSD2_FIFO_CTRL_STAT 4287658284 #define P_AUD_RESAMPLE_STATUS 4291875588 #define HEVC_IQIT_AVS2_WQP_0123 14093 #define MCDI_UNI_MVDST 12037 #define VPP_PEAKING_GAIN_ADD1 7606 #define P_VKS_FILL_VAL 4287677464 #define VPP_PEAKING_GAIN_ADD2 7607 #define P_VDEC2_MINDEX0_REG 4284648488 #define VIU_OSD1_MATRIX_OFFSET0_1 6806 #define P_DI_INFO_DATA 4287651016 #define P_HEVC_DBLK_CBPY_ADJ 4284671428 #define P_VBO_VIN_CTRL 4287648144 #define VDEC2_VLD_MEM_VBUF2_RD_PTR 11348 #define ANC22_CANVAS_ADDR 2470 #define P_HCODEC_SLICE_VER_POS_PIC_TYPE 4284641296 #define VP9_EMD_CMD 12609 #define P_HEVC_STREAM_SWAP_CTRL 4284662996 #define MCDI_RPTMV_GAIN 12051 #define mLVDS_data_latch_0_ini 13 #define P_HEVC_CINDEX3_REG 4284665012 #define P_VDEC2_ANC2_CANVAS_ADDR 4284655176 #define P_VPP_SMOKE3_H_START_END 4287657156 #define P_AHB_BRIDGE_REMAP0 4291883524 #define P_AHB_BRIDGE_REMAP1 4291883528 #define P_AHB_BRIDGE_REMAP2 4291883532 #define P_AHB_BRIDGE_REMAP3 4291883536 #define PK_NR_ENABLE 12839 #define P_LCD_PWM1_LO_ADDR 4287648504 #define VDEC2_CBREAK1_REG 9013 #define P_AIU_DELTA_SIGMA_LCNTS 4291842420 #define P_DET3D_RO_MAT_LUMA_LR 4287651340 #define XVYCC_LUT_G_ADDR_PORT 12640 #define P_HCODEC_ANC4_CANVAS_ADDR 4284638800 #define ENCI_SYNC_VSO_EVN 6924 #define PK_OS_HORZ_CORE_GAIN 12835 #define ENCI_MACV_PULSE_LO 6993 #define AIU_MEM_AIFIFO_MAN_RP 5258 #define P_HEVC_PARSER_PICTURE_SIZE 4284662924 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD_BG0 4287678212 #define P_SMARTCARD_FIFO 4291973148 #define VKS_IWIN_VSIZE 12552 #define P_MC_HALF_PEL_ONE 4284621836 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD_BG5 4287678232 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD_BG4 4287678228 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD_BG3 4287678224 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD_BG2 4287678220 #define P_WM_EMBEDDING_STRENGTH_THRESHOLD_BG1 4287678216 #define P_GE2D_HSC_PHASE_SLOPE 4287890164 #define HCODEC_QDCT_INT_STATUS 7998 #define P_HEVC_SAO_MMU_WPTR 4284668144 #define VIU_OSD2_COLOR 6706 #define P_HEVC_DBLK_GCLK_FREE 4284671408 #define VPU_VPUARB2_ASYNC_HOLD_CTRL 10054 #define HEVC_MPRED_COLREF_EN_L0 12814 #define HEVC_MPRED_COLREF_EN_L1 12815 #define VPP2_VSC_REGION3_PHASE_SLOPE 6411 #define VDEC2_VLD_DBG_DATA 11327 #define ENCI_MACV_PULSE_HI 6994 #define I2C_M_MANUAL_EN 22 #define ME_SAD_0 8033 #define ME_SAD_1 8034 #define ME_SAD_2 8035 #define ME_SAD_3 8036 #define DI_IF2_RPT_LOOP 8214 #define VKS_SCL_STEP04 30 #define VKS_SCL_STEP05 31 #define VKS_SCL_STEP06 32 #define VKS_SCL_STEP07 33 #define VKS_SCL_STEP08 34 #define VKS_SCL_STEP09 35 #define SRSHARP1_LTI_CTI_DF_GAIN 13356 #define VKS_SCL_STEP00 26 #define VKS_SCL_STEP01 27 #define P_HEVC_CABAC_LEFT_INFO_2 4284662908 #define VKS_SCL_STEP02 28 #define P_LMEM_DMA_ADR 4284616004 #define P_HEVC_CABAC_LEFT_INFO_3 4284663072 #define VKS_SCL_STEP03 29 #define P_HEVC_CABAC_LEFT_INFO_4 4284663080 #define P_HEVC_CABAC_LEFT_INFO_5 4284663088 #define VKS_SCL_STEP15 41 #define VKS_SCL_STEP16 42 #define P_NR4_MCNR_CM_CTRL0 4287674132 #define HEVC_MB_WIDTH 15369 #define VKS_SCL_STEP10 36 #define VKS_SCL_STEP11 37 #define VKS_SCL_STEP12 38 #define VKS_SCL_STEP13 39 #define VKS_SCL_STEP14 40 #define HCODEC_ME_PIC_INFO 8015 #define P_D2D3_DBR_DDD_DBG 4287671476 #define HEVC_SAO_MMU_VH1_ADDR 13883 #define P_WRRSP_VLD 4284622696 #define AUDIN_FIFO0_END 13345 #define P_HEVC_CPC_W 4284664996 #define AIU_RESET 64 #define P_MC_OTHER_GCLK_CTRL 4284622136 #define P_HEVC_CPC_P 4284664984 #define VPU_RDWR_ARB_STATUS_L2C1 10145 #define HEVC_ASSIST_DMA_INT2 12390 #define P_HCODEC_ANC20_CANVAS_ADDR 4284638864 #define P_HEVC_ASSIST_MBOX2_CLR_REG 4284662244 #define ENCL_VIDEO_VAVON_BLINE 7348 #define P_AUDIN_FIFO1_INTR 4291875032 #define P_QDCT_TOP_MEM_CTL 4284644484 #define P_DNR_GBS_STAT 4287673372 #define P_VDEC2_MPSR 4284648452 #define VPU_PROT3_RPT_PAT 10102 #define HLTI_BST_GAIN 12853 #define VBO_LANES 5219 #define ENCI_DE_V_BEGIN_EVEN 6936 #define P_GE2D_SRC2_X_START_END 4287890120 #define HEVC_DBLK_Y_VFILT 14686 #define TS_TOP_CONFIG 6385 #define VBO_TMCHK_HSYNC_STATE_H 5247 #define HEVC_BLOCK_NUM 15402 #define EE_ASSIST_MBOX3_MASK 8318 #define VBO_TMCHK_HSYNC_STATE_L 5246 #define P_DBLK_OST_CBCRDIFF 4284622328 #define P_VDEC2_MINT_VEC_BASE 4284648456 #define VLC_VB_END_PTR 7441 #define VIU2_OSD2_TCOLOR_AG2 7737 #define VIU2_OSD2_TCOLOR_AG3 7738 #define VIU2_OSD2_TCOLOR_AG0 7735 #define VIU2_OSD2_TCOLOR_AG1 7736 #define P_MCDI_RO_FLD_LUMA_AVG_SUM 4287676032 #define NR3_YMOT_PARA 12275 #define CBREAK_STAUTS 826 #define P_VPP_VADJ1_BLACK_VAL 4287657564 #define ENCI_DBG_PX_RST 6984 #define P_VDEC2_DBLK_Y_HFILT 4284654960 #define P_MINDEX5_REG 4284615740 #define P_HEVC_ANC2_CANVAS_ADDR 4284671560 #define MCDI_REF_ERR_GAIN0 12059 #define P_ME_SKIP_LINE 4284644660 #define SRSHARP0_SHARP_SR2_CBIC_HCOEF1 12891 #define SRSHARP0_SHARP_SR2_CBIC_HCOEF0 12890 #define MCDI_REF_ERR_GAIN1 12060 #define P_HCODEC_ANC9_CANVAS_ADDR 4284638820 #define P_DET3D_RO_SPLT_HB 4287651328 #define VIU_OSD1_MATRIX_COEF40_41 6815 #define DET3D_RO_MAT_MOTN_TB 6030 #define P_DET3D_RO_SPLT_HT 4287651068 #define P_ANC5_CANVAS_ADDR 4284622420 #define VDEC2_MPC_P 8966 #define P_QDCT_JPEG_QUANT_DATA 4284644516 #define P_HCODEC_PSCALE_MCMD_XSIZE 4284638348 #define VDEC2_MPC_W 8969 #define DET3D_RO_MAT_MOTN_LR 6029 #define P_ENCL_DBG_LN_RST 4287656616 #define VDEC2_MPC_E 8968 #define VDEC2_MPC_D 8967 #define P_ENCI_DE_V_END_EVEN 4287655012 #define P_HEVC_CPC_E 4284664992 #define P_HEVC_CPC_D 4284664988 #define P_VIU_OSD1_OETF_LUT_ADDR_PORT 4287654772 #define VDIN_COM_GCLK_CTRL2 4720 #define P_HCODEC_IE_C_PRED_MODE 4284644636 #define P_AUDIN_MEM_PD 4291875496 #define SRSHARP0_NR_TI_DNLP_BLEND 12841 #define P_HCODEC_VLC_VB_CONTROL 4284642392 #define VLC_CONFIG 7425 #define VD2_IF0_GEN_REG2 6797 #define VD2_IF0_GEN_REG3 6824 #define SHARP_SR3_DERING_PARAM0 12914 #define P_HEVCD_MPP_DECOMP_AXIURG_CTL 4284666652 #define VDEC2_M4_CONTROL_REG 11305 #define P_DNR_DM_LDIF_LUT0_2 4287673792 #define VDEC2_DC_AC_SCALE_DIV 11783 #define P_VPP_HLTI_PARA 4287657800 #define MCPU_INTR_MSK 772 #define HCODEC_MC_PIC_INFO 6402 #define VDEC2_MMIN_REG 8978 #define P_VD1_IF0_RANGE_MAP_Y 4287654312 #define P_HCODEC_DBLK_Y_BHFILT 4284638556 #define P_I2C_M_1_WDATA_REG0 4291944464 #define P_I2C_M_1_WDATA_REG1 4291944468 #define HEVC_ANC13_CANVAS_ADDR 14749 #define OSD1_AFBCD_SIZE_IN 12706 #define I2C_M_3_TOKEN_LIST1 28675 #define I2C_M_3_TOKEN_LIST0 28674 #define P_L_STH2_VE_ADDR 4287647836 #define GE2D_SRC2_DST_CANVAS 184 #define HEVC_PSCALE_CMD_BLK_Y 14621 #define HEVC_PSCALE_CMD_BLK_X 14620 #define DEBLK_CMD 3600 #define P_VPP2_OSD_VSC_CTRL0 4287653640 #define MINDEX2_REG 780 #define HCODEC_SCD_FOR_MV_Y 7187 #define HCODEC_SCD_FOR_MV_X 7186 #define P_VDEC2_DBLK_STRONG 4284655060 #define FLD_MOT 256 #define GE2D_SRC1_CLIPX_START_END 167 #define VDEC2_MBREAK_TYPE 8984 #define P_VLD_DECODE_CONTROL 4284624992 #define P_VPP_VCTI_PARA 4287657816 #define DOS_MEM_PD_VDEC 16176 #define VENC_UPSAMPLE_CTRL2 7014 #define VENC_UPSAMPLE_CTRL0 7012 #define VENC_UPSAMPLE_CTRL1 7013 #define HEVC_PSCALE_CANVAS_WR_ADDR 14637 #define P_VPU_WRARB_MODE_L1C2 4287667896 #define P_VPU_VPUARB2_PRE_ARB_CTRL 4287667288 #define ENCP_VIDEO_EQPULS_ELINE 7074 #define P_DC_AC_SCALE_MUL 4284626968 #define P_VPU_WRARB_MODE_L1C1 4287667792 #define HCODEC_PSCALE_BMEM_ADDR 6431 #define P_I2C_M_1_SLAVE_ADDR 4291944452 #define VPP_SHARP_DEMO_WIN_CTRL1 7609 #define VPP_SHARP_DEMO_WIN_CTRL2 7610 #define DI_BLEND_REG1_X 5906 #define DI_MEM_LUMA_FIFO_SIZE 6117 #define ENCP_DVI_VSO_END_EVN 7224 #define DI_BLEND_REG1_Y 5907 #define P_NR4_DRT_SAD_ALP_CORE 4287674012 #define AUDOUT_BUF1_EDA 13446 #define HEVC_MPRED_CUR_POC 12896 #define VDIN_MEAS_VS_COUNT_HI 4699 #define HEVC_MPRED_L1_REF01_POC 12849 #define ENCI_MACV_N22 6982 #define P_DET3D_RO_SPLT_VL 4287651332 #define ENCI_MACV_N21 6981 #define ENCI_MACV_N20 6980 #define P_DET3D_RO_SPLT_VR 4287651336 #define ISA_TIMERE_HI 15459 #define CSFTINT1 831 #define CSFTINT0 830 #define P_PARSER_FETCH_STOP_ADDR 4291879308 #define VDIN0_VSHRK_CTRL 4721 #define P_ENCP_SYNC_PIXEL_EN 4287656212 #define HEVC_PARSER_INT_STATUS 12577 #define P_HCODEC_ME_SUB_FIX_SAD 4284644720 #define CBREAK1_REG 821 #define P_HEVC_VLD_MEM_SWAP_ADDR 4284674388 #define P_VBO_HBK_CTRL 4287648176 #define HCODEC_ANC31_CANVAS_ADDR 6575 #define AIU_MEM_AIFIFO_BUF_CNTL 5260 #define ENCI_MACV_N16 6976 #define ENCI_MACV_N15 6975 #define ENCI_MACV_N14 6974 #define ENCI_MACV_N13 6973 #define ENCI_MACV_N12 6972 #define ENCI_MACV_N11 6971 #define ENCI_MACV_N10 6970 #define VPP2_OSD_HSC_CTRL0 6597 #define ENCI_MACV_N19 6979 #define ENCI_MACV_N18 6978 #define ENCI_MACV_N17 6977 #define NR4_COEF123_SUM 14120 #define P_VD2_IF0_RANGE_MAP_Y 4287654440 #define P_HEVC_DCAC_DMA_ADDRESS 4284676172 #define PARSER_CONTROL 14432 #define VPP_SC_MISC 7449 #define P_VIU2_OSD1_BLK0_CFG_W0 4287658220 #define P_VDEC2_POWER_CTL_VLD 4284657696 #define P_HCODEC_V3_SKIP_WEIGHT 4284644800 #define P_VIU2_OSD1_BLK0_CFG_W1 4287658224 #define P_IEC958_TIME_STAMP_SYNC_1 4291842696 #define P_VIU2_OSD1_BLK0_CFG_W4 4287658384 #define P_VIU2_OSD1_BLK0_CFG_W2 4287658228 #define P_IEC958_TIME_STAMP_SYNC_0 4291842692 #define P_VIU2_OSD1_BLK0_CFG_W3 4287658232 #define HEVC_MC_IDCT_DAT 14668 #define P_VENC_VDAC_DAC2_FILT_CTRL1 4287656308 #define P_VENC_VDAC_DAC2_FILT_CTRL0 4287656304 #define AIU_I2S_MED_THRESH 5135 #define P_VD2_IF0_LUMA_PSEL 4287654400 #define P_AIU_CRC_SHIFT_REG 4291842328 #define P_MBREAK2_REG 4284615768 #define HCODEC_MSFTINT1 4895 #define P_VPU_PROT1_RPT_PAT 4287667544 #define HCODEC_MSFTINT0 4894 #define P_DI_IF2_DUMMY_PIXEL 4287660132 #define SRSHARP1_VLTI_BST_CORE 13372 #define VPP2_GAINOFF_CTRL1 6507 #define VPP2_GAINOFF_CTRL2 6508 #define VPP2_GAINOFF_CTRL3 6509 #define VPP2_GAINOFF_CTRL4 6510 #define P_VLC_INPUT_STATUS 4284642512 #define P_ENCI_DE_H_BEGIN 4287655000 #define VPP2_GAINOFF_CTRL0 6506 #define P_TS_TOP_CONFIG 4291847108 #define HCODEC_DBLK_CR_FILT 6496 #define P_ENCT_SYNC_LINE_LENGTH 4287656224 #define P_VDIN_BLKBAR_IND_RIGHT_START_END 4287646104 #define VIU_OSD2_MATRIX_CTRL 6832 #define SRSHARP1_PK_DRTFB_BP_CORING 13330 #define VPU_RDWR_ARB_STATUS_L1C2 10140 #define VPU_RDWR_ARB_STATUS_L1C1 10136 #define DBLK_Y_VFILT 2398 #define PARSER_VIDEO2_HOLE 14487 #define HENC_LEFT_MV_1 7503 #define HENC_LEFT_MV_2 7504 #define P_FST_BAK_MV_Y 4284624980 #define MC_MB_INFO 2305 #define HENC_LEFT_MV_0 7502 #define P_FST_BAK_MV_X 4284624976 #define HENC_LEFT_MV_3 7505 #define P_HCODEC_ME_SUB_MERGE_CTL 4284644708 #define ASSIST_GEN_CNTL 8296 #define P_CCPU_INTR_GRP 4284615820 #define VPP_WRAP_OSD2_MATRIX_COEF15_25 15735 #define P_L_HSYNC_VS_ADDR 4287648092 #define VPP_OSD2_BLD_H_SCOPE 7671 #define VDEC2_F_CODE_REG 11266 #define HCODEC_ACC0REG1 4961 #define HCODEC_ACC0REG2 4977 #define HCODEC_DBLK_QP 6486 #define P_HEVC_CSP 4284664960 #define SHARP_SR2_CBIC_HCOEF0 12890 #define SHARP_SR2_CBIC_HCOEF1 12891 #define HCODEC_CCPU_INTR_MSK 4900 #define HEVC_NEXT_ALIGN_PEAK 15389 #define P_HEVC_ANC14_CANVAS_ADDR 4284671608 #define P_DET3D_RO_MAT_MOTN_TB 4287651384 #define P_GE2D_SRC_OUTSIDE_ALPHA 4287890264 #define P_L_TCON_DOUBLE_CTL 4287648036 #define P_I2C_M_0_TOKEN_LIST1 4291948556 #define P_I2C_M_0_TOKEN_LIST0 4291948552 #define P_HEVC_PSCALE_MCMD_XSIZE 4284671116 #define VPU_VENCL_DITH_LUT_1 10209 #define VPU_VENCL_DITH_LUT_2 10210 #define VPU_VENCL_DITH_LUT_3 10211 #define VPU_VENCL_DITH_LUT_4 10212 #define VPU_VENCL_DITH_LUT_5 10213 #define VPU_VENCL_DITH_LUT_6 10214 #define VENC_VDAC_SETTING 7038 #define VPU_VENCL_DITH_LUT_7 10215 #define VPU_VENCL_DITH_LUT_8 10216 #define VPU_VENCL_DITH_LUT_9 10217 #define HCODEC_MDEC_PICW_BUF2_STATUS 6589 #define DBLK_Y_BHFILT 2391 #define SPICC1_DMAREG 21508 #define P_HEVC_SAO_IF_WAIT_CNT 4284663008 #define P_L_TCON_PATTERN_LO 4287648044 #define VLC_IPRED_MODE_HI 7483 #define P_VDEC2_CINDEX2_REG 4284648624 #define P_VDEC2_PMV4_Y 4284657820 #define P_VDEC2_PMV4_X 4284657816 #define P_VPP_SMOKE2_V_START_END 4287657152 #define P_VDEC2_MC_MBBOT_WRRSP_CNT 4284655344 #define VDEC2_FST_BAK_MV_Y 11285 #define VDEC2_FST_BAK_MV_X 11284 #define P_LDIM_STTS_GCLK_CTRL0 4287654656 #define TS_PL_PID_INDEX 6387 #define P_ENCI_SYNC_ADJ 4287654984 #define P_HCODEC_CURR_CANVAS_CTRL 4284638924 #define P_HCODEC_MC_HCMD_L 4284638508 #define P_VIU_OSD1_BLK1_CFG_W4 4287653968 #define P_CBREAK_STAUTS 4284615912 #define P_VIU_OSD1_BLK1_CFG_W3 4287654024 #define P_HEVC_IMEM_DMA_CTRL 4284665088 #define P_HCODEC_MC_HCMD_H 4284638504 #define P_VIU_OSD1_BLK1_CFG_W0 4287654012 #define HCODEC_VC1_BITPLANE_CTL 7704 #define P_VIU_OSD1_BLK1_CFG_W2 4287654020 #define P_VIU_OSD1_BLK1_CFG_W1 4287654016 #define MCDI_GMV_LOCK_ABS_DIF_THD 12110 #define ENCI_TST_CR 7188 #define DI_INP_DUMMY_PIXEL 6103 #define P_HCODEC_ASSIST_MBOX1_FIQ_SEL 4284629468 #define VPP_HCTI_GAIN 7636 #define ENCI_TST_CB 7187 #define HEVC_ANC24_CANVAS_ADDR 14760 #define H_SEL_R 10 #define VDIN_MEAS_HS_RANGE 4701 #define P_HCODEC_IQIDCT_DEBUG_INFO_0 4284643388 #define P_DOLBY_TV_SWAP_CTRL1 4287680460 #define P_DOLBY_TV_SWAP_CTRL0 4287680456 #define P_ENCI_SYNC_CTRL 4287654948 #define I2C_M_MANUAL_SCL_O 23 #define P_DOLBY_TV_SWAP_CTRL3 4287680468 #define P_DOLBY_TV_SWAP_CTRL2 4287680464 #define DET3D_RAMRD_ADDR_PORT 6042 #define I2C_M_MANUAL_SCL_I 25 #define P_ENCT_VIDEO_HSO_BEGIN 4287656404 #define H_SEL_G 9 #define H_SEL_B 8 #define P_DOLBY_CORE2A_CLKGATE_CTRL 4287680712 #define VBO_TMCHK_THRD_L 5240 #define P_DET3D_RO_FRM_MOTN 4287651388 #define VPP_PEAKING_DNLP 7608 #define VBO_TMCHK_THRD_H 5241 #define ENCI_TST_EN 7184 #define P_DOLBY_TV_SWAP_CTRL5 4287680476 #define P_DOLBY_TV_SWAP_CTRL4 4287680472 #define P_DOLBY_TV_SWAP_CTRL7 4287680484 #define P_DOLBY_TV_SWAP_CTRL6 4287680480 #define P_WM_SYMBOLS_NUM 4287678152 #define P_V3_L1_SKIP_MAX_SAD 4284644804 #define P_D2D3_DBG_STATUS_1 4287671520 #define P_D2D3_DBG_STATUS_2 4287671524 #define P_VDEC2_DEBLK_CMD 4284659776 #define VDEC2_ANC2_CANVAS_ADDR 10642 #define HEVC_MPRED_TILE_START 12807 #define VIU2_OSD1_MATRIX_COEF15_25 7799 #define MC_OTHER_GCLK_CTRL 2382 #define VIU2_OSD2_FIFO_CTRL_STAT 7755 #define P_HCODEC_RV_AI_V_X 4284643372 #define VDIN_MATRIX_COEF22 4629 #define P_VLC_MV 4284642596 #define P_VPU_PROT3_DDR 4287667676 #define P_MCDI_GMV_GAIN 4287675476 #define ENCT_INFO_READ 10014 #define VPU_HDMI_DATA_OVR 10023 #define AIUin_FIFO_THRESHOLD_MSB 5 #define HCODEC_PSCALE_PICO_START_Y 6423 #define HCODEC_PSCALE_PICO_START_X 6422 #define P_QDCT_Q_QUANT_P 4284644468 #define P_HCODEC_DBLK_Y_HFILT_HIGH 4284638580 #define P_QDCT_Q_QUANT_I 4284644464 #define D2D3_DBR_LRDMX_CTRL 11055 #define VPP_SMOKE1_V_START_END 7470 #define HCODEC_ASSIST_MBOX2_FIQ_SEL 4219 #define VLC_IPRED_MODE_LO 7484 #define P_ME_F_SKIP_WEIGHT 4284644688 #define HCTI_BST_GAIN 12847 #define P_HCODEC_NEXT_INTRA_DMA_ADDRESS 4284643380 #define VDEC2_DCAC_CPU_DATA 11797 #define ENCT_VIDEO_HSO_BEGIN 7285 #define DI_BLEND_REG0_X 5904 #define DI_BLEND_REG0_Y 5905 #define P_DOS_VDIN_LCNT 4284677164 #define SPICC1_INTREG 21507 #define P_L_OEH_VE_ADDR 4287647852 #define ENCP_VIDEO_YC_DLY 7062 #define P_HCODEC_DBLK_CR_BFILT 4284638572 #define P_LCD_PWR_ADDR 4287648492 #define VIU_RESET 32 #define WM_EMBEDDING_STRENGTH_THRESHOLD_BG0 12737 #define WM_EMBEDDING_STRENGTH_THRESHOLD_BG1 12738 #define WM_EMBEDDING_STRENGTH_THRESHOLD_BG4 12741 #define WM_EMBEDDING_STRENGTH_THRESHOLD_BG5 12742 #define WM_EMBEDDING_STRENGTH_THRESHOLD_BG2 12739 #define WM_EMBEDDING_STRENGTH_THRESHOLD_BG3 12740 #define NR4_MCNR_CM_BLUE_CLIP0 11723 #define NR4_MCNR_CM_BLUE_CLIP1 11724 #define NR2_MATNR_SNR_OS 5970 #define P_VDIN_HIST_CHROMA_SUM 4287645912 #define MIPI_DSI_DWC_LP_RD_TO_CNT_OS 7200 #define P_VIU2_OSD2_CTRL_STAT 4287658176 #define P_L_STH1_HS_ADDR 4287647808 #define VDIN_BLKBAR_IND_LEFT2_CNT 4712 #define VLD_TIME_STAMP_LENGTH 3152 #define STB_TOP_CONFIG 6384 #define P_VLC_DC 4284642584 #define P_ENCL_TST_CLRBAR_WIDTH 4287656568 #define P_VIU2_OSD2_PROT_CTRL 4287658296 #define ENCP_VIDEO_SYNC_WAVE_CURVE 7085 #define P_HEVC_IMEM_DMA_ADR 4284665092 #define P_DET3D_RO_MAT_MOTN_LR 4287651380 #define P_HCODEC_ASSIST_AMR2_INT2 4284629212 #define P_HCODEC_ASSIST_AMR2_INT3 4284629216 #define P_HCODEC_ASSIST_AMR2_INT0 4284629204 #define P_HCODEC_ASSIST_AMR2_INT1 4284629208 #define VPP_POST2_MATRIX_COEF11_12 14754 #define P_TCON_PATTERN_LO 4287648556 #define P_VPU_ARB_PATH_MAP10 4287667960 #define P_VPU_ARB_PATH_MAP11 4287667964 #define DEMO_SPLT_YHS_REG 539 #define P_VPP_IN_H_V_SIZE 4287657624 #define P_VPU_ARB_PATH_MAP12 4287667968 #define P_VPU_ARB_PATH_MAP13 4287667972 #define P_AIU_CODEC_DAC_LRCLK_CTRL 4291842208 #define VPP_SMOKE3_H_START_END 7473 #define HCODEC_DBLK_GCLK_OFF 6509 #define ABUF_RD_CUR_BLK_MSB 14 #define NR4_MCNR_SAD2BET0_LUT3 11753 #define NR4_MCNR_SAD2BET0_LUT1 11751 #define HEVC_STREAM_END_ADDR 12547 #define NR4_MCNR_SAD2BET0_LUT2 11752 #define NR4_MCNR_SAD2BET0_LUT0 11750 #define P_MCDI_REL_DIF_THD_34 4287675520 #define P_VPP2_OSD_HSC_CTRL0 4287653652 #define P_DBLK_CR_BFILT 4284622188 #define HCODEC_PRE_START_CODE 7179 #define ANC27_CANVAS_ADDR 2475 #define P_TCON_PATTERN_HI 4287648552 #define P_VPU_ARB_PATH_MAP00 4287667944 #define P_VPP2_HOLD_LINES 4287653000 #define P_VPU_ARB_PATH_MAP03 4287667956 #define P_VPU_ARB_PATH_MAP01 4287667948 #define P_VPU_ARB_PATH_MAP02 4287667952 #define VPP_POST2_MATRIX_COEF23_24 14758 #define P_VPU_PROT3_RBUF_ROOM 4287667680 #define ENCT_VIDEO_Y_OFFST 7268 #define P_SPICC0_PERIODREG 4291899416 #define ENCL_VIDEO_MODE_ADV 7336 #define L_STH2_HE_ADDR 5141 #define XVYCC_VADJ1_CURV_1 12647 #define XVYCC_VADJ1_CURV_0 12646 #define XVYCC_VADJ1_CURV_3 12649 #define XVYCC_VADJ1_CURV_2 12648 #define ENCP_VIDEO_SY2_VAL 7089 #define P_VPU_VD1_MMC_CTRL 4287667212 #define VIU_OSD1_EOTF_LUT_DATA_PORT 6875 #define P_HCODEC_BLOCK_NUM 4284641448 #define HEVC_VLD_STATUS_CTRL 15360 #define VBO_SOFT_RST 5218 #define L_GAMMA_PROBE_POS_X 5133 #define HEVC_MPRED_L0_REF07_POC 12839 #define HCODEC_DBLK_OST_CBCRDIFF 6526 #define P_ANC31_CANVAS_ADDR 4284622524 #define L_GAMMA_PROBE_POS_Y 5134 #define P_OEH_HE_ADDR 4287648356 #define P_VDIN_SCALE_COEF_IDX 4287645696 #define P_AUDIN_HDMI_MEAS_CYCLES_M1 4291875460 #define P_HCODEC_ASSIST_MBX_SSEL 4284629268 #define VDIN0_MATRIX_HL_COLOR 4649 #define SPI_FLASH_ADDR 20481 #define P_HCODEC_ASSIST_AMR2_INT8 4284629236 #define P_HCODEC_ASSIST_AMR2_INT9 4284629240 #define P_HCODEC_ASSIST_AMR2_INT6 4284629228 #define P_HCODEC_ASSIST_AMR2_INT7 4284629232 #define P_HCODEC_ASSIST_AMR2_INT4 4284629220 #define P_HCODEC_ASSIST_AMR2_INT5 4284629224 #define P_HCODEC_ASSIST_AMR2_INTB 4284629248 #define P_HCODEC_ASSIST_AMR2_INTC 4284629252 #define P_HCODEC_ASSIST_AMR2_INTA 4284629244 #define P_HCODEC_ASSIST_AMR2_INTF 4284629264 #define P_HCODEC_ASSIST_AMR2_INTD 4284629256 #define P_HCODEC_ASSIST_AMR2_INTE 4284629260 #define HCODEC_PSCALE_MCMD_YSIZE 6436 #define VDEC2_MSP 8960 #define DI_IF1_RANGE_MAP_Y 6140 #define VLC_VB_SW_RD_PTR 7444 #define P_CINDEX1_REG 4284615852 #define P_VIU2_OSD1_BLK2_CFG_W4 4287658392 #define MDEC_EXTIF_CFG1 2533 #define P_VIU2_OSD1_BLK2_CFG_W0 4287658124 #define MDEC_EXTIF_CFG0 2532 #define P_VIU2_OSD1_BLK2_CFG_W1 4287658128 #define P_VIU2_OSD1_BLK2_CFG_W2 4287658132 #define P_VIU2_OSD1_BLK2_CFG_W3 4287658136 #define HEVC_STREAM_FIFO_CTL 12551 #define P_AV_SCRATCH_J 4284622668 #define P_AV_SCRATCH_K 4284622672 #define P_AV_SCRATCH_H 4284622660 #define P_AV_SCRATCH_I 4284622664 #define P_AV_SCRATCH_F 4284622652 #define P_AV_SCRATCH_G 4284622656 #define P_AV_SCRATCH_D 4284622644 #define P_AV_SCRATCH_E 4284622648 #define P_AV_SCRATCH_B 4284622636 #define P_AV_SCRATCH_C 4284622640 #define P_AV_SCRATCH_A 4284622632 #define P_ENCT_VIDEO_BLANKPR_VAL 4287656440 #define P_AV_SCRATCH_N 4284622684 #define P_AV_SCRATCH_L 4284622676 #define P_AV_SCRATCH_M 4284622680 #define DECOMB_DET_VERT_CON1 11649 #define P_HEVC_IQIT_SCALELUT_DATA 4284668944 #define DECOMB_DET_VERT_CON0 11648 #define P_AV_SCRATCH_8 4284622624 #define P_AV_SCRATCH_9 4284622628 #define P_AV_SCRATCH_6 4284622616 #define P_AV_SCRATCH_7 4284622620 #define P_AV_SCRATCH_4 4284622608 #define P_AV_SCRATCH_5 4284622612 #define P_AV_SCRATCH_2 4284622600 #define P_AV_SCRATCH_3 4284622604 #define P_AV_SCRATCH_0 4284622592 #define P_AV_SCRATCH_1 4284622596 #define P_HCODEC_V3_L1_SKIP_MAX_SAD 4284644804 #define P_VDEC_ASSIST_MBOX0_MASK 4284613064 #define P_HCODEC_VLC_DC_INFO 4284642588 #define UART1_REG5 35845 #define HEVC_VLD_TIME_STAMP_CNTL 15433 #define P_PARSER_PARAMETER 4291879356 #define ENCI_VFIFO2VD_LINE_BOT_START 7197 #define HEVC_MPRED_L1_REF13_POC 12861 #define ENCP_VIDEO_MODE_ADV 7054 #define ENCT_DBG_LN_RST 7274 #define P_AFBC_MIF_VER_SCOPE 4287654840 #define VKS_SCL_OFSET00 9 #define VKS_SCL_OFSET01 10 #define VPP_FRONT_CTI_CTRL 7612 #define VKS_SCL_OFSET02 11 #define VKS_SCL_OFSET03 12 #define VKS_SCL_OFSET04 13 #define VKS_SCL_OFSET05 14 #define VKS_SCL_OFSET06 15 #define VKS_SCL_OFSET07 16 #define VKS_SCL_OFSET08 17 #define VKS_SCL_OFSET09 18 #define P_VIU_OSD1_EOTF_COEF02_10 4287654744 #define P_ANC0_CANVAS_ADDR 4284622400 #define P_GE2D_SRC1_Y_START_END 4287890092 #define VDEC2_MDEC_PIC_DC_THRESH 10680 #define WM_AM_LUT_ADDR_PORT 12744 #define PATTERN_CODE 3115 #define VKS_SCL_OFSET10 19 #define VKS_SCL_OFSET11 20 #define VKS_SCL_OFSET12 21 #define VKS_SCL_OFSET13 22 #define VKS_SCL_OFSET14 23 #define P_VDEC2_MDEC_PIC_DC_MUX_CTRL 4284655156 #define VKS_SCL_OFSET15 24 #define VKS_SCL_OFSET16 25 #define HCODEC_PSCALE_CMD_CTRL 6427 #define P_VDEC2_MDEC_PICW_BUF_STATUS 4284655336 #define AIU_MEM_I2S_START_PTR 5216 #define HCODEC_MCRCC_CTL3 6530 #define HCODEC_MCRCC_CTL2 6529 #define HCODEC_MCRCC_CTL1 6528 #define HEVC_PARSER_MANUAL_CMD 12587 #define P_VPU_RDARB_MODE_L1C2 4287667812 #define P_VPU_RDARB_MODE_L1C1 4287667776 #define HCODEC_DBLK_BETAX_QP_SEL 6497 #define VPU_DI_IF1_MMC_CTRL 9989 #define AIU_958_LENGTH_PER_PAUSE 5155 #define P_HEVC_MPRED_REF_EN_L0 4284663856 #define P_HEVC_MPRED_REF_EN_L1 4284663860 #define AUDIN_FIFO2_RDPTR 13385 #define RGB_SWP 1 #define L_DE_HE_ADDR 5202 #define P_HEVC_VC1_CONTROL_REG 4284674168 #define FLD_PIC 0 #define P_ENCP_VIDEO_PB_OFFST 4287655460 #define ABUF_WR_CTL2 15474 #define ABUF_WR_CTL3 15475 #define ABUF_WR_CTL0 15472 #define ABUF_WR_CTL1 15473 #define P_HEVC_MC_MBBOT_WRRSP_CNT 4284671728 #define P_HCODEC_MC_PIC_INFO 4284638216 #define AIU_MEM_I2S_END_PTR 5218 #define P_VPP2_DNLP_CTRL_09 4287653416 #define EE_ASSIST_MBOX3_IRQ_REG 8316 #define P_VPP2_DNLP_CTRL_07 4287653408 #define P_VPP2_DNLP_CTRL_08 4287653412 #define P_VPP2_DNLP_CTRL_05 4287653400 #define P_VPP2_DNLP_CTRL_06 4287653404 #define SRSHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 13421 #define P_VPP2_DNLP_CTRL_03 4287653392 #define AIU_958_CHSTAT_L1 5129 #define P_VPP2_DNLP_CTRL_04 4287653396 #define P_VPP2_DNLP_CTRL_01 4287653384 #define P_VPP2_DNLP_CTRL_02 4287653388 #define AIU_958_CHSTAT_L0 5128 #define P_VPP2_DNLP_CTRL_00 4287653380 #define mLVDS2_bit_num 6 #define P_HCODEC_RV_AI_U_X 4284643368 #define CM_ENH_CTL_REG 520 #define tcon_pattern_loop_end 8 #define HEVC_MPRED_DBG_MODE0 12865 #define P_VCOM_VS_ADDR 4287648372 #define HEVC_MPRED_DBG_MODE1 12866 #define P_SHARP_SR3_DRTLPF_ALPHA_2 4287678884 #define P_PSCALE_PICI_H 4284621900 #define P_SHARP_SR3_DRTLPF_ALPHA_1 4287678880 #define P_VDEC2_DC_AC_CTRL 4284659732 #define P_DBLK_Y_HFILT 4284622192 #define P_VIU_OSD2_PROT_CTRL 4287654200 #define DI_CHAN2_RANGE_MAP_Y 6068 #define P_SHARP_SR3_DRTLPF_ALPHA_0 4287678876 #define VPP2_VDO_MEAS_VS_COUNT_LO 6570 #define P_AIU_MIX_ADCCFG 4291842140 #define VIU_OSD_BLEND_DIN0_SCOPE_V 14770 #define P_DOLBY_CORE2A_AXI2DMA_CTRL0 4287680768 #define P_DOLBY_CORE2A_AXI2DMA_CTRL2 4287680776 #define P_DOLBY_CORE2A_AXI2DMA_CTRL1 4287680772 #define HEVC_DCAC_CPU_ADDRESS 15892 #define P_DOLBY_CORE2A_AXI2DMA_CTRL3 4287680780 #define P_ENCP_VIDEO_PR_OFFST 4287655464 #define P_VIU_SW_RESET0 4287653896 #define MCDI_MCVECRD_X 12181 #define MCDI_MCVECRD_Y 12182 #define VDIN_BLKBAR_V_START_END 4706 #define DI_INP_LUMA_FIFO_SIZE 6104 #define P_VPP2_DNLP_CTRL_14 4287653436 #define P_VPP2_DNLP_CTRL_15 4287653440 #define P_VPP2_DNLP_CTRL_12 4287653428 #define P_VPP2_DNLP_CTRL_13 4287653432 #define P_VPP2_DNLP_CTRL_10 4287653420 #define P_VPP2_DNLP_CTRL_11 4287653424 #define VIU_OSD_BLEND_DIN0_SCOPE_H 14769 #define P_HEVC_SAO_DBG_MODE0 4284668024 #define VDIN_LFIFO_CTRL 4634 #define P_L_TCON_PATTERN_HI 4287648040 #define SANA_STREAM_WR_PTR 12323 #define P_ENCI_MACV_MAX_AMP 4287655232 #define P_HEVC_SAO_DBG_MODE1 4284668028 #define P_PK_OS_STATIC 4287678616 #define P_AVSP_IQ_WQ_PARAM_23 4284627048 #define P_VIU2_OSD1_CTRL_STAT2 4287658292 #define SHARP_SATPRT_CTRL 12916 #define VLC_MV 7497 #define QDCT_MIX_I_PRED_STATUS 7999 #define VDEC2_MDEC_EXTIF_CFG1 10725 #define VDEC2_MDEC_EXTIF_CFG0 10724 #define AUDIN_FIFO2_INTR 13384 #define P_DNR_DM_LDIF_LUT3_5 4287673796 #define P_AUDIN_HDMI_MEAS_CTRL 4291875456 #define AIU_958_CHSTAT_R0 5168 #define P_VDEC2_VIFF_BIT_CNT 4284657768 #define AIU_958_CHSTAT_R1 5169 #define VPP2_VDO_MEAS_VS_COUNT_HI 6569 #define P_AVSP_IQ_WQ_PARAM_45 4284627052 #define P_SANA_STREAM_FIFO_CTL 4291870872 #define P_HEVC_MPRED_L0_REF10_POC 4284663976 #define SPICC0_DWADDR 19465 #define VDIN1_HIST_H_START_END 5169 #define HCODEC_V5_SIMPLE_MB_ME_WEIGHT 8064 #define DBLK_CTRL 2385 #define P_ME_STEP0_CLOSE_MV 4284644680 #define P_VLC_DC_INFO 4284642588 #define VD2_AFBC_SIZE_OUT 12680 #define GPIO_INTR_FILTER_SEL0 15395 #define HEVC_MC_MPORT_DAT 14657 #define VPP_WRAP_OSD1_MATRIX_COEF00_01 15712 #define P_HEVC_MPRED_COL_POC 4284664196 #define P_VIU2_VD1_IF0_CHROMA_PSEL 4287658372 #define MCDI_REL_DET_FRQ_CHK 12081 #define P_MSFTINT0 4284615800 #define P_MSFTINT1 4284615804 #define VDIN_BLKBAR_IND_LEFT_START_END 4709 #define VPP2_MATRIX_PRE_OFFSET2 6504 #define VPU_ARB_PATH_MAP13 10177 #define VPU_ARB_PATH_MAP11 10175 #define VPU_ARB_PATH_MAP12 10176 #define VPU_ARB_PATH_MAP10 10174 #define P_VPP2_VDO_MEAS_VS_COUNT_LO 4287653544 #define P_AVSP_IQ_WQ_PARAM_01 4284627044 #define UART0_WFIFO 36864 #define VPU_ARB_PATH_MAP02 10172 #define VPU_ARB_PATH_MAP03 10173 #define VPU_ARB_PATH_MAP00 10170 #define VPU_ARB_PATH_MAP01 10171 #define VDIN0_SCIN_HEIGHTM1 4645 #define AHB_BRIDGE_CNTL_REG1 15493 #define VDEC2_ANC23_CANVAS_ADDR 10663 #define VIU_OSD1_MATRIX_PROBE_POS 6812 #define AHB_BRIDGE_CNTL_REG2 15494 #define P_DI_IF1_RPT_LOOP 4287651768 #define HCODEC_BYTE_ALIGN_PEAK_LO 7196 #define HCODEC_MFDIN_REGB_AMPC 4115 #define P_NR4_COEFBLT_CONV 4287683648 #define P_VPP_SRSHARP1_CTRL 4287657544 #define HEVC_PSCALE_CTRL 14609 #define HEVC_MPRED_POC24_CTRL0 12878 #define HEVC_MPRED_POC24_CTRL1 12879 #define P_VPP_CHROMA_DATA_PORT 4287657412 #define DNR_BLK_OFFST 11523 #define P_HEVC_IQIT_DEQUANT_CTRL 4284668932 #define DI_IF2_CHROMA_Y0 8213 #define VKS_PPS_CCOEF00 76 #define P_PSCALE_PICI_W 4284621896 #define P_VPP2_VDO_MEAS_VS_COUNT_HI 4287653540 #define P_RESET2_LEVEL 4291825800 #define DI_IF1_RPT_LOOP 6126 #define VKS_PPS_CCOEF10 86 #define P_HCODEC_ANC14_CANVAS_ADDR 4284638840 #define VKS_PPS_CCOEF11 87 #define DI_IF2_CHROMA_X0 8212 #define ABUF_RD_CUR_BLK_LSB 0 #define VPP_INT_LINE_NUM 7630 #define VKS_PPS_CCOEF09 85 #define VLC_DC 7494 #define VKS_PPS_CCOEF03 79 #define VKS_PPS_CCOEF04 80 #define VKS_PPS_CCOEF01 77 #define P_AIU_MEM_I2S_MEM_CTL 4291842528 #define VKS_PPS_CCOEF02 78 #define VKS_PPS_CCOEF07 83 #define P_HEVC_DBKR_CANVAS_ADDR 4284671680 #define VKS_PPS_CCOEF08 84 #define VKS_PPS_CCOEF05 81 #define VKS_PPS_CCOEF06 82 #define VKS_PPS_CCOEF21 97 #define VKS_PPS_CCOEF22 98 #define VKS_PPS_CCOEF20 96 #define VIU2_OSD2_CTRL_STAT2 7757 #define mLVDS2_pair_num 5 #define VKS_PPS_CCOEF14 90 #define VKS_PPS_CCOEF15 91 #define VKS_PPS_CCOEF12 88 #define VKS_PPS_CCOEF13 89 #define VKS_PPS_CCOEF18 94 #define VKS_PPS_CCOEF19 95 #define GE2D_SCALE_COEF_IDX 212 #define VKS_PPS_CCOEF16 92 #define VKS_PPS_CCOEF17 93 #define P_VPP_HCTI_PARA 4287657812 #define P_MCPU_INTR_REQ 4284615700 #define VKS_PPS_CCOEF32 108 #define VKS_PPS_CCOEF30 106 #define VKS_PPS_CCOEF31 107 #define I_PIC 1 #define HEVC_MPRED_MV_RLCUY 12831 #define P_HEVC_ASSIST_DMA_INT2 4284662168 #define SANA_SHIFT_CONTROL 12327 #define HEVC_DBLK_CBPC 14706 #define P_HEVC_MINT_VEC_BASE 4284664840 #define HEVC_DBLK_CBPY 14704 #define VKS_PPS_CCOEF25 101 #define VKS_PPS_CCOEF26 102 #define CPU_TRACE 896 #define VKS_PPS_CCOEF23 99 #define VKS_PPS_CCOEF24 100 #define VKS_PPS_CCOEF29 105 #define VKS_PPS_CCOEF27 103 #define VKS_PPS_CCOEF28 104 #define GAMMA_PROBE_HL_COLOR 5260 #define HEVC_CABAC_TOP_INFO_2 12573 #define HEVC_CABAC_TOP_INFO_3 12615 #define HEVC_CABAC_TOP_INFO_4 12617 #define REG_DEMO_HLIGHT_MODE 50 #define NR4_RO_NM_SAD_SUM 14111 #define HEVC_CABAC_TOP_INFO_5 12619 #define mLVDS_reset_pattern 0 #define P_HEVC_VLD_STATUS_CTRL 4284674048 #define HCODEC_V5_SMALL_DIFF_CNT 8061 #define P_HEVC_STREAM_FIFO_CTL 4284662812 #define VDEC2_ASSIST_MBOX0_FIQ_SEL 8307 #define ENCL_VIDEO_Y_SCL 7329 #define HEVC_ASSIST_DMA_INT 12388 #define VDIN_HSC_PHASE_STEP 4620 #define DI_IF1_FMT_W 6132 #define HCODEC_ME_STEP0_CLOSE_MV 8018 #define P_HCODEC_CBREAK0_REG 4284632272 #define DI_NR_CTRL1 5896 #define VDIN1_BLKBAR_IND_RIGHT1_CNT 5225 #define DI_NR_CTRL0 5895 #define DI_NR_CTRL2 5897 #define P_VD2_AFBC_PIXEL_HOR_SCOPE 4287678012 #define AIU_DELTA_SIGMA_RCNTS 5214 #define P_PK_OS_HORZ_CORE_GAIN 4287678604 #define VPP_OSD1_BLD_H_SCOPE 7669 #define HEVC_MDB_DATA_REG 13084 #define P_ENCL_VIDEO_HOFFST 4287656700 #define RDMA_ACCESS_AUTO2 4369 #define RDMA_ACCESS_AUTO4 4376 #define RDMA_ACCESS_AUTO3 4370 #define P_HEVC_MPRED_L1_REF07_POC 4284664028 #define HEVC_MPRED_REF_EN_L1 12813 #define HEVC_MPRED_REF_EN_L0 12812 #define IQ_QUANT 3607 #define NR4_MCNR_RO_U_SUM 11762 #define VDEC2_ANC12_CANVAS_ADDR 10652 #define P_VDIN_SC_MISC_CTRL 4287645740 #define HEVC_NON_I_QUANT_MATRIX 15875 #define HCODEC_MSP 4864 #define VDEC2_DBLK_CLIP_CTRL0 10594 #define VDEC2_DBLK_CLIP_CTRL3 10597 #define VDEC2_DBLK_CLIP_CTRL4 10598 #define VDEC2_DBLK_CLIP_CTRL1 10595 #define VDEC2_DBLK_CLIP_CTRL2 10596 #define P_MCDI_RPTMV_THD2 4287675456 #define ENCI_VBI_WSSDT 6949 #define P_MCDI_RPTMV_THD1 4287675452 #define P_MCDI_RPTMV_THD0 4287675448 #define P_ME_SUB_MERGE_CTL 4284644708 #define MIPI_DSI_DWC_GEN_HDR_OS 7195 #define HEVC_PSCALE_CTRL2 14638 #define HEVC_PSCALE_CTRL1 14633 #define VIU_OSD2_HL1_V_START_END 6708 #define P_VPP_SMOKE1_V_START_END 4287657144 #define VDEC2_DBLK_CLIP_CTRL7 10601 #define VDEC2_DBLK_CLIP_CTRL8 10602 #define VDEC2_DBLK_CLIP_CTRL5 10599 #define VDEC2_DBLK_CLIP_CTRL6 10600 #define P_HCODEC_MC_WT_PRED_CTRL 4284638472 #define P_HCODEC_PSCALE_PICO_SHIFT_XY 4284638368 #define P_VDEC2_PMV2_Y 4284657804 #define P_VDEC2_PMV2_X 4284657800 #define VDEC2_DBLK_CTRL 10577 #define HCODEC_V3_LEFT_SMALL_MAX_SAD 8058 #define P_D2D3_GLB_CTRL 4287671296 #define SRSHARP1_PK_DRT_SAD_MISC 13352 #define P_HCODEC_MC_MPORT_DAT 4284638468 #define HCODEC_DBLK_VLD_HCMD1 6523 #define HCODEC_DBLK_VLD_HCMD0 6524 #define HCODEC_DBLK_VLD_HCMD2 6522 #define P_AUDOUT_BUF1_EDA 4291875352 #define P_VPP_CTI_CTRL2 4287657648 #define VIU2_VD1_IF0_DUMMY_PIXEL 7778 #define P_HEVC_ANC13_CANVAS_ADDR 4284671604 #define HEVC_CINDEX1_REG 13099 #define VDEC2_DBLK_RST 10576 #define VDEC2_MC_HCMDBUF_H 10568 #define VPP_VADJ1_MC_MD 7491 #define VDEC2_MC_HCMDBUF_L 10569 #define P_VPU_RDARB_REQEN_SLV_L1C1 4287667780 #define P_VPU_RDARB_REQEN_SLV_L1C2 4287667816 #define P_VPP_SMOKE_CTRL 4287657124 #define ENCI_DVI_HSO_END 7169 #define ANC7_CANVAS_ADDR 2455 #define P_DECOMB_YC_THRD 4287673884 #define SPDIF_CHNL_ORDER 19 #define ANC3_CANVAS_ADDR 2451 #define P_VDEC2_CINDEX1_REG 4284648620 #define NR4_MCNR_BANDSPLIT_PRAM 14102 #define VPP_HCTI_PARA 7637 #define P_DOLBY_INT_STAT 4287653908 #define P_AIU_MEM_I2S_BUF_WRAP_COUNT 4291842524 #define HCODEC_CINDEX7_REG 4913 #define HCODEC_DBLK_Y_BHFILT_HIGH 6488 #define CPH1_POL 6 #define WM_FREQ_DIST_LEFT 12724 #define P_DNR_DM_LDIF_LUT6_8 4287673800 #define P_HCODEC_POWER_CTL_MC 4284638228 #define P_VPP2_POSTBLEND_VD1_V_START_END 4287652980 #define STH1_HE_ADDR 5265 #define VIU2_ADDR_START 7680 #define NR4_MCNR_BET1_AND_BET2_REG 11715 #define P_DNR_RO_DM_GMS_STAT_MS 4287673824 #define P_HEVC_SAO_INT_STATUS 4284667920 #define HCODEC_MC_MB_INFO 6401 #define VDEC2_MB_INFO 11308 #define VDEC2_ANC1_CANVAS_ADDR 10641 #define HEVC_MC_OM_MB_XY 14607 #define P_HCODEC_HDEC_MC_MBRIGHT_IDX 4284638404 #define P_VPU_VD3_MMC_CTRL 4287667300 #define P_VPP2_SMOKE1_H_START_END 4287653044 #define P_VLD_DBG_DATA 4284625148 #define P_V4_FORCE_SKIP_CFG 4284644844 #define P_ENCI_MACV_BKP_MAX 4287655244 #define RGB_COEFF_ADDR 5254 #define DI_EI_XWIN0 6040 #define VIU2_OSD1_CTRL_STAT2 7757 #define VPP_MATRIX_CLIP 7646 #define DI_EI_XWIN1 6041 #define P_MCDI_PD_22_CHK_WND1_X 4287675756 #define P_MCDI_PD_22_CHK_WND1_Y 4287675760 #define P_DNR_RO_VBOF_STAT_CNT_12 4287673636 #define P_DNR_RO_VBOF_STAT_CNT_13 4287673640 #define P_DNR_RO_VBOF_STAT_CNT_10 4287673628 #define P_DNR_RO_VBOF_STAT_CNT_11 4287673632 #define P_F_CODE_REG 4284624904 #define VDIN1_MATRIX_PROBE_POS 5162 #define P_DI_EI_DRT_UNBITREND_TH 4287651316 #define MIPI_DSI_DWC_MODE_CFG_OS 7181 #define SRSHARP0_PK_FINALGAIN_HP_BP 12834 #define P_LVDS_BLANK_DATA_LO 4287648572 #define PORT_SWP 2 #define P_V3_SKIP_CONTROL 4284644784 #define P_MDEC_DOUBLEW_STATUS 4284622732 #define ENCP_VIDEO_VSO_BLINE 7083 #define P_VPP2_DUMMY_DATA 4287652864 #define P_HCODEC_POWER_CTL_IQIDCT 4284643360 #define AIU_CLK_CTRL 5142 #define ENCL_VIDEO_Y_OFFST 7332 #define SPDIF_EN 31 #define P_VDEC2_CDB_ADDR_REG 4284648684 #define VDIN_CHROMA_DATA_PORT 4652 #define P_HEVC_MBREAK_TYPE 4284664928 #define P_UART2_STATUS 4291960844 #define VIU_OSD1_MATRIX_HL_COLOR 6811 #define DI_MC_REG1_X 5922 #define DI_MC_REG1_Y 5923 #define VPU_DI_NRWR_MMC_CTRL 9995 #define VLD_STATUS 3130 #define P_DBLK_STATUS1 4284622252 #define P_VPU_SW_RESET 4287667328 #define P_VPP_POSTBLEND_CURRENT_XY 4287657108 #define P_VPP_CCORING_CTRL 4287657600 #define MC_CTRL_GCLK_CTRL 2381 #define P_VPP_VSC_INI_PHASE 4287657016 #define P_VDEC2_MC_DP_MB_XY 4284654648 #define P_HEVC_DBLK_STATUS1 4284671404 #define HCODEC_PSCALE_RBUF_START_BLKX 6437 #define HCODEC_PSCALE_RBUF_START_BLKY 6438 #define P_DOS_MEM_PD_VDEC2 4284677316 #define C656_VS_LNED_O 7141 #define HEVC_PSCALE_RST 14608 #define C656_VS_LNED_E 7140 #define VDEC2_LMEM_DMA_ADR 9041 #define SRSHARP1_PK_OS_HORZ_CORE_GAIN 13347 #define P_VPP2_MATRIX_COEF20_21 4287653260 #define DNR_DM_VAR_THD 11623 #define P_MCDI_HV_BLKSIZEIN 4287675396 #define P_DBLK_RST 4284622144 #define DI_CHAN2_LUMA0_RPT_PAT 6064 #define P_MCDI_LMV_LOCK_ROW 4287675692 #define ENCL_DACSEL_1 7370 #define ENCL_DACSEL_0 7369 #define P_HCODEC_VLC_WRRSP 4284642404 #define P_VDIN_MATRIX_COEF20_21 4287645776 #define P_MCDI_RPTMV_GAIN 4287675468 #define VAS_STREAM_ID 14449 #define P_I2C_M_1_TOKEN_LIST1 4291944460 #define P_I2C_M_1_TOKEN_LIST0 4291944456 #define P_HEVC_MPRED_MV_RD_END_ADDR 4284664200 #define P_V5_SIMPLE_MB_DQUANT 4284644860 #define VLC_DC_RD_REQ 7493 #define P_VPP2_HSC_REGION0_PHASE_SLOPE 4287652944 #define OSD_DB_FLT_SEED_U 12615 #define OSD_DB_FLT_SEED_V 12616 #define AIU_MEM_IEC958_BUF_CNTL 5247 #define OSD_DB_FLT_SEED_Y 12614 #define P_MSR_CLK_REG0 4291919876 #define P_STV1_HE_ADDR 4287648416 #define CVBS_IRQ1_COUNTER 15399 #define P_VDEC2_MBREAK3_REG 4284648540 #define VDEC2_DBKR_CANVAS_ADDR 10672 #define THIRD_DEMUX_OFFSET_0 160 #define P_MCDI_REL_DIF_THD_02 4287675516 #define VIU_OSD2_COLOR_ADDR 6705 #define MCDI_TXT_THD 12040 #define P_MSR_CLK_REG4 4291919892 #define P_MSR_CLK_REG3 4291919888 #define P_MSR_CLK_REG2 4291919884 #define P_MSR_CLK_REG1 4291919880 #define VDEC2_DBKW_CANVAS_ADDR 10673 #define P_MSR_CLK_REG5 4291919896 #define P_HEVC_VLD_MEM_VIFIFO_MEM_CTL 4284674376 #define AUDIN_FIFO1_HOLD2_SEL 26 #define HCODEC_ANC2_CANVAS_ADDR 6546 #define VBO_FSM_HOLDER_L 5242 #define VBO_FSM_HOLDER_H 5243 #define P_PMV2_X 4284625032 #define PARSER_CONFIG 14437 #define P_PMV2_Y 4284625036 #define MIPI_DSI_TOP_CNTL 7410 #define VPP2_VADJ2_Y 6468 #define ENCI_SYNC_PIXEL_EN 7233 #define HEVC_VLD_MEM_SWAP_ADDR 15445 #define P_HEVC_SAO_C_LENGTH 4284667960 #define P_ENCL_VIDEO_BLANKPB_VAL 4287656692 #define SCD_BAK_MV_X 3094 #define P_MCDI_GMV_LOCK_ABS_DIF_THD 4287675704 #define SCD_BAK_MV_Y 3095 #define P_HCODEC_QDCT_JPEG_DCT_STATUS0 4284644524 #define P_HCODEC_QDCT_JPEG_DCT_STATUS1 4284644528 #define ENCL_VIDEO_RGB_CTRL 7361 #define P_VIU2_OSD1_TCOLOR_AG1 4287658208 #define P_VIU2_OSD1_TCOLOR_AG0 4287658204 #define P_DI_CLKG_CTRL 4287650912 #define P_VIU2_OSD1_TCOLOR_AG3 4287658216 #define P_VIU2_OSD1_TCOLOR_AG2 4287658212 #define P_VDEC2_HDEC_MC_MBRIGHT_RD 4284654792 #define HCODEC_ME_CONTROL 8009 #define HEVC_MPRED_L1_REF12_POC 12860 #define D2D3_SCALER_CTRL 11014 #define P_VPP_OSD_SCALE_COEF 4287657780 #define SPICC1_LD_CNTL0 21514 #define PARSER_FETCH_STOP_ADDR 14435 #define SPICC1_LD_CNTL1 21515 #define MCDI_RO_FLD_LUMA_AVG_SUM 12192 #define VDEC2_CBREAK2_REG 9014 #define P_MCDI_MC_REL_GAIN_OFFST_1 4287675868 #define MCDI_REL_DET_COL_CFD_AVG_LUMA 12099 #define HEVC_PARSER_CMD_WRITE 12562 #define ASSIST_AMR_SCRATCH3 8274 #define P_LDIM_STTS_MATRIX_PROBE_COLOR 4287654712 #define ASSIST_AMR_SCRATCH1 8272 #define P_MCDI_MC_REL_GAIN_OFFST_0 4287675864 #define ASSIST_AMR_SCRATCH2 8273 #define P_HCODEC_ANC15_CANVAS_ADDR 4284638844 #define ASSIST_AMR_SCRATCH0 8271 #define ENCP_VFIFO2VD_LINE_BOT_END 7006 #define LDIM_STTS_MATRIX_COEF20_21 6854 #define VIU_OSD2_MATRIX_PRE_OFFSET0_1 6840 #define HADR_MSB 7 #define HEVC_PMV4_Y 15399 #define HEVC_PMV4_X 15398 #define HCODEC_VLD_MEM_SWAP_CTL 7254 #define P_VDEC2_PMV3_X 4284657808 #define HLTI_OS_MARGIN 12857 #define VDEC2_DBLK_GCLK_OFF 10605 #define P_LVDS_BLANK_DATA_HI 4287648568 #define P_VKS_PARA_ADDR_PORT 4287677496 #define VDIN0_MATRIX_PROBE_COLOR 4648 #define P_GE2D_SRC1_X_START_END 4287890088 #define IDCT_TM2_PT1 2 #define HCODEC_DCAC_DMA_ADDRESS 7699 #define P_XVYCC_POST_RGB_DLUT_8_11 4287677924 #define IDCT_TM2_PT0 1 #define HEVC_MC_MPORT_CTRL 14656 #define P_VDEC2_PMV3_Y 4284657812 #define LCD_GPI_MSB 3 #define D2D3_INTF_LENGTH 6664 #define VD1_IF0_GEN_REG3 6823 #define VD1_IF0_GEN_REG2 6765 #define P_GE2D_ANTIFLICK_COLOR_FILT2 4287890288 #define P_GE2D_ANTIFLICK_COLOR_FILT1 4287890284 #define P_GE2D_ANTIFLICK_COLOR_FILT3 4287890292 #define P_GE2D_ANTIFLICK_COLOR_FILT0 4287890280 #define P_AUDIN_DECODE_FORMAT 4291874888 #define HCODEC_QDCT_MB_END_PTR 7953 #define VPU_VENCL_DITH_CTRL 10208 #define AIU_AIFIFO2_GBIT 5186 #define P_HEVC_SAO_ABV_RPTR 4284667988 #define P_VDEC2_GCLK_EN 4284655116 #define P_GE2D_MATRIX_OFFSET 4287890220 #define DI_INP_GEN_REG 6094 #define VDEC2_CBREAK_STAUTS 9018 #define P_HEVC_PMV1_X 4284674176 #define P_HEVC_PMV1_Y 4284674180 #define P_VPP2_SCALE_COEF 4287652880 #define P_VDIN_HIST_MAX_MIN 4287645900 #define HEVC_IMEM_DMA_CTRL 13120 #define VPU_ISP_GCLK_CTRL1 10050 #define VPU_ISP_GCLK_CTRL0 10049 #define HEVC_VLD_TIME_STAMP_1 15437 #define HEVC_VLD_TIME_STAMP_0 15436 #define P_RV_AI_Y_X 4284626980 #define HEVC_VLD_TIME_STAMP_3 15439 #define HEVC_VLD_TIME_STAMP_2 15438 #define AIU_MEM_IEC958_END_PTR 5223 #define P_ME_CONTROL 4284644644 #define P_SANA_STREAM_RD_PTR 4291870864 #define DOLBY_CORE2A_REG_START 13312 #define P_VPU_RDARB_REQEN_SLV_L2C1 4287667832 #define P_RESET2_MASK 4291825736 #define SHARP_SR3_DERING_CTRL 12907 #define ENCP_MACV_MAXY_VAL 7105 #define P_SANA_ELEMENT_RESULT 4291870904 #define EE_ASSIST_MBOX0_IRQ_REG 8304 #define OEH_VS_ADDR 5274 #define DI_IF2_LUMA_Y0 8211 #define VPU_VIU_VENC_MUX_CTRL 10010 #define HEVC_MAC_CTRL2 13168 #define AIUin_FIFO_THRESHOLD_LSB 0 #define HEVC_MAC_CTRL1 13152 #define P_MCDI_PD_22_CHK_WND0_X 4287675748 #define P_MCDI_PD_22_CHK_WND0_Y 4287675752 #define HEVC_ANC19_CANVAS_ADDR 14755 #define VDIN1_LDIM_STTS_HIST_READ_REGION 5209 #define DI_IF2_LUMA_X0 8210 #define SPI_FLASH_USR_ADDR 15 #define P_VPP2_SMOKE2_H_START_END 4287653052 #define ENCT_VIDEO_VSO_ELINE 7290 #define HEVC_MC_DP_MB_XY 14606 #define P_HCODEC_VLD_MEM_VIFIFO_BUF_CNTL 4284641568 #define LDIM_STTS_GCLK_CTRL0 6848 #define P_HEVC_STREAM_END_ADDR 4284662796 #define VDIN1_MEAS_HS_COUNT 5214 #define MC_OMDN_MB_XY 2375 #define VI_HIST_MAX_MIN 11779 #define ENCT_MAX_LINE_SWITCH_POINT 7304 #define P_PARSER_CONFIG 4291879316 #define DOLBY_TV_ADAPTIVE_SCALE_LUTDATA 13283 #define P_NR4_MCNR_AC2NORM_LUT2 4287674228 #define P_VPP_PREBLEND_VD1_V_START_END 4287657068 #define P_NR4_MCNR_AC2NORM_LUT1 4287674224 #define P_NR4_MCNR_AC2NORM_LUT0 4287674220 #define P_DC_SCALER 4284626960 #define HADR 0 #define P_AIU_958_FFRDOUT_THD 4291842184 #define P_VDEC2_VC1_BITPLANE_CTL 4284659808 #define P_AIU_DELTA_SIGMA7 4291842416 #define P_AIU_DELTA_SIGMA5 4291842408 #define P_AIU_DELTA_SIGMA6 4291842412 #define P_AIU_DELTA_SIGMA3 4291842400 #define P_AIU_DELTA_SIGMA4 4291842404 #define P_AIU_DELTA_SIGMA1 4291842392 #define P_AIU_DELTA_SIGMA2 4291842396 #define P_AIU_DELTA_SIGMA0 4291842388 #define P_SPICC1_LD_WADDR 4291907636 #define P_NR4_COEF123_SUM 4287683744 #define AIU_MEM_AIFIFO_CONTROL 5256 #define HEVC_VC1_CONTROL_REG 15390 #define P_HSYNC_VE_ADDR 4287648608 #define GE2D_HSC_PHASE_SLOPE 189 #define P_L_TCON_MISC_SEL_ADDR 4287648004 #define VDIN0_BLKBAR_H_START_END 4705 #define P_DNR_DM_RNG_THD 4287673736 #define SRSHARP0_SR3_DRTLPF_ALPHA_1 12904 #define SRSHARP0_SR3_DRTLPF_ALPHA_2 12905 #define SRSHARP0_SR3_DRTLPF_ALPHA_0 12903 #define P_HEVC_ACC1REG2 4284665288 #define P_VPP2_VSC_REGION4_ENDP 4287652892 #define P_MC_HALF_PEL_TWO 4284621840 #define P_VPP2_MATRIX_PRE_OFFSET0_1 4287653276 #define DI_MC_REG2_Y 5925 #define DI_MC_REG2_X 5924 #define P_HEVC_ACC1REG1 4284665224 #define P_HCODEC_ME_F_SKIP_SAD 4284644684 #define P_DNR_DB_CHDELTA_GAIN 4287673416 #define L_RGB_BASE_ADDR 5125 #define P_VDEC2_WRRSP_FIFO_PICW_DBK 4284655352 #define SRSHARP1_PK_CIRFB_LPF_MODE 13325 #define P_VPP_EOTF_LUT_ADDR_PORT 4287678296 #define V3_MV_SAD_TABLE 8051 #define P_DBLK_BETAX_QP_SEL 4284622212 #define P_PMV1_Y 4284625028 #define P_PMV1_X 4284625024 #define HEVC_PSCALE_MCMD_XSIZE 14627 #define VDEC2_MINDEX7_REG 8977 #define P_HEVC_PSCALE_BMEM_ADDR 4284671100 #define VPP2_VSC_REGION12_STARTP 6405 #define ANC23_CANVAS_ADDR 2471 #define P_VLC_ELEMENT_DATA 4284642436 #define P_L_GAMMA_ADDR_PORT 4287647752 #define P_QDCT_I_PRED_REF_WR_DATA 4284644556 #define HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL 7235 #define HCODEC_MBBOT_EVEN_ADDR 7991 #define RESET4_MASK 1044 #define HEVCD_IPP_TOP_FRMCONFIG 13314 #define P_PARSER_AUDIO_RP 4291879456 #define VDEC2_CINDEX5_REG 9007 #define DI_EI_DRT_UNBITREND_TH 6013 #define VPP_SCALE_COEF_IDX 7427 #define DI_EI_DRT_RECTG_WAVE 6011 #define VDEC2_ASSIST_DMA_INT_MSK2 8295 #define AIU_AUDIO_AMP_REG1 5181 #define AIU_AUDIO_AMP_REG0 5180 #define AIU_AUDIO_AMP_REG3 5183 #define AIU_AUDIO_AMP_REG2 5182 #define P_HEVC_PSCALE_CANVAS_RD_ADDR 4284671152 #define P_VDEC2_ANC26_CANVAS_ADDR 4284655272 #define D2D3_DRMIF_CTRL 11048 #define P_HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR 4284666624 #define P_PARSER_AUDIO_WP 4291879452 #define VDIN_MEAS_VS_COUNT_LO 4700 #define SRSHARP1_PK_DRTFB_HP_CORING 13329 #define P_NR4_MCNR_GREEN_GAIN_PAR1 4287674172 #define P_NR4_MCNR_GREEN_GAIN_PAR0 4287674168 #define VDEC2_ASSIST_MBOX1_IRQ_REG 8308 #define P_VDIN_WIDTHM1I_WIDTHM1O 4287645736 #define UART0_MISC 36868 #define MCDI_REL_COL_REF_RT 12117 #define VD2_AFBC_BODY_BADDR 12679 #define P_GE2D_VSC_INI_CTRL 4287890156 #define ENCP_DVI_HSO_END 7217 #define P_DI_CHAN2_LUMA0_RPT_PAT 4287651520 #define VD1_IF0_DUMMY_PIXEL 6754 #define ISA_PLL_CLK_SIM0 15368 #define P_UART2_CONTROL 4291960840 #define QDCT_JPEG_CTRL 7973 #define HCODEC_CBREAK_TYPE 4920 #define VDEC2_CPC_P 8998 #define P_VPP2_VADJ1_MC_MD 4287653132 #define P_VKS_LBUF_SIZE 4287677484 #define P_HEVC_VLD_DC_PRED 4284674228 #define DOLBY_TV_ADAPTIVE_SCALE_REGDATA 13281 #define P_HEVC_MDB_CTRL 4284664948 #define P_AIU_958_MISC 4291842064 #define VDEC2_CPC_W 9001 #define P_ME_STATUS 4284644652 #define VIU_OSD2_HL2_V_START_END 6710 #define ENCP_MACV_WAVE_END 7110 #define HEVC_DBLK_AVSFLAGS 14702 #define P_NON_I_QUANT_MATRIX 4284626956 #define P_D2D3_DPG_INPIC_SIZE 4287671300 #define VDEC2_CPC_D 8999 #define VDEC2_CPC_E 9000 #define VCTI_FLT_CON_CLP 12863 #define P_PSCALE_PICO_W 4284621904 #define P_PSCALE_PICO_H 4284621908 #define SRSHARP0_NR_ALP1_ERR2CURV_TH_RATE 12827 #define P_VPP2_VDO_MEAS_CTRL 4287653536 #define VIU2_OSD1_PROT_CTRL 7758 #define D2D3_DBR_DDD_CTRL 11052 #define VDIN1_BLKBAR_CNT_THRESHOLD 5219 #define LVDS_GEN_CNTL 5344 #define P_HEVC_PMV2_Y 4284674188 #define P_HEVC_PMV2_X 4284674184 #define ISA_BIST_REG1 15409 #define HCODEC_MINDEX7_REG 4881 #define ISA_BIST_REG0 15408 #define P_DI_MC_REG4_Y 4287650980 #define P_DI_MC_REG4_X 4287650976 #define P_VPU_VLOCK_ADJ_EN_SYNC_CTRL 4287676532 #define ME_SAD_ENOUGH_23 8017 #define HEVC_DBLK_Y_BHFILT 14679 #define P_D2D3_CG_THRESHOLD_1 4287671324 #define P_D2D3_CG_THRESHOLD_2 4287671328 #define HCODEC_CCPU_INTR_REQ 4901 #define P_I2C_M_1_RDATA_REG1 4291944476 #define P_AUDIN_ADDR_END 4291875616 #define SPI_FLASH_USR_CMD 0 #define P_ASSIST_SPARE16_REG2 4291854684 #define P_ASSIST_SPARE16_REG1 4291854680 #define HEVC_PMV3_X 15396 #define P_I2C_M_1_RDATA_REG0 4291944472 #define HEVC_PMV3_Y 15397 #define DOLBY_CORE2A_AXI2DMA_CTRL2 13378 #define DOLBY_CORE2A_AXI2DMA_CTRL3 13379 #define VDEC2_ANC19_CANVAS_ADDR 10659 #define DOLBY_CORE2A_AXI2DMA_CTRL0 13376 #define DOLBY_CORE2A_AXI2DMA_CTRL1 13377 #define VPU_VLOCK_LOOP1_CTRL0 12292 #define ME_SAD_ENOUGH_01 8016 #define P_HCODEC_MINDEX0_REG 4284632104 #define P_HEVC_MPC_E 4284664864 #define P_HEVC_MPC_D 4284664860 #define P_HEVC_MPC_P 4284664856 #define P_SANA_SHIFT_STATUS 4291870888 #define P_HEVC_MPC_W 4284664868 #define P_HEVC_MINDEX7_REG 4284664900 #define P_HCODEC_VLC_DC_BUF_STATUS 4284642576 #define P_CBREAK3_REG 4284615900 #define P_HEVC_PARSER_DEBUG_DAT 4284663036 #define VP9_QUANT_WR 12614 #define P_VIU_OSD1_EOTF_COEF00_01 4287654740 #define STREAM_BUS_CONFIG 11268 #define P_HLTI_BST_CORE 4287678680 #define DCAC_MB_COUNT 3606 #define P_MCRCC_CTL2 4284622340 #define P_MCRCC_CTL1 4284622336 #define P_MCRCC_CTL3 4284622344 #define AUDIN_SPDIF_NPCM_PCPD 13317 #define ENCL_VIDEO_VSO_BEGIN 7351 #define HCODEC_PATTERN_CODE 7211 #define VDEC2_DBLK_CBUS_HCMD0 10617 #define VDEC2_DBLK_CBUS_HCMD2 10615 #define VDEC2_DBLK_CBUS_HCMD1 10616 #define VPP_HSC_PHASE_CTRL 7448 #define P_ENCP_VIDEO_MAX_LNCNT 4287655608 #define VPP_SMOKE3_VAL 7468 #define P_GE2D_HSC_NRND_PHASE 4287890192 #define VIDEO_DTS 14450 #define MB_SKIP_RUN 7507 #define P_HEVC_MPRED_DBG_MODE1 4284664072 #define P_HEVC_MPRED_DBG_MODE0 4284664068 #define P_VDEC2_MINDEX1_REG 4284648492 #define VDEC2_WRRSP_LMEM 9043 #define P_VENC_C656_CTRL 4287655308 #define P_NR2_MATNR_MTN_COR 4287651248 #define HCODEC_V4_FORCE_SKIP_CFG 8059 #define ENCI_VFIFO2VD_CTL2 7199 #define P_DI_INP_DUMMY_PIXEL 4287651676 #define P_VIU2_VD1_IF0_LUMA_X1 4287658332 #define P_VIU2_VD1_IF0_LUMA_X0 4287658316 #define P_MC_IDCT_DAT 4284622128 #define VPU_TVDVBI_MMC_CTRL 10001 #define P_VPU_MEM_PD_REG0 4287667348 #define P_VPU_MEM_PD_REG1 4287667352 #define P_HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT 4284641604 #define P_HCODEC_MDEC_PIC_DC_MUX_CTRL 4284638772 #define P_DI_MEM_CANVAS0 4287651696 #define P_OSD_DB_FLT_SEED5 4287677740 #define P_AIU_AMCLK_GATE_LO 4291842372 #define VPP2_OSD_VSC_INI_PHASE 6593 #define ENCP_SYNC_LINE_LENGTH 7236 #define P_OSD_DB_FLT_SEED4 4287677736 #define ANC8_CANVAS_ADDR 2456 #define P_OSD_DB_FLT_SEED3 4287677732 #define HCODEC_VLC_HCMD_MBXY_AUTO 7462 #define P_HEVC_PARSER_CMD_SKIP_0 4284662944 #define ANC2_CANVAS_ADDR 2450 #define P_HEVC_PARSER_CMD_SKIP_1 4284662948 #define ENCP_VBI_DATA1 7126 #define P_HEVC_PARSER_CMD_SKIP_2 4284662952 #define DI_MTN_1_CTRL3 5954 #define AUDIN_FIFO2_CTRL1 13387 #define P_VIU2_VD1_IF0_LUMA_Y0 4287658320 #define DI_MTN_1_CTRL4 5955 #define DI_MTN_1_CTRL5 5956 #define DI_MTN_1_CTRL6 6057 #define P_VIU2_VD1_IF0_LUMA_Y1 4287658336 #define DI_MTN_1_CTRL1 5952 #define P_HCODEC_V3_TOP_INTRA_INFO 4284644824 #define DI_MTN_1_CTRL2 5953 #define ENCT_VIDEO_BLANKPB_VAL 7293 #define GE2D_ANTIFLICK_COLOR_FILT2 220 #define GE2D_ANTIFLICK_COLOR_FILT3 221 #define GE2D_ANTIFLICK_COLOR_FILT0 218 #define GE2D_ANTIFLICK_COLOR_FILT1 219 #define HUE_RANGE_INV_REG07 44 #define P_I2C_M_3_CONTROL_REG 4291936256 #define P_L_LCD_PWM1_LO_ADDR 4287647992 #define DI_MTN_1_CTRL7 6058 #define DI_MTN_1_CTRL8 6059 #define DI_MTN_1_CTRL9 6060 #define P_CPV1_HS_ADDR 4287648380 #define HUE_RANGE_INV_REG01 8 #define HUE_RANGE_INV_REG02 14 #define HUE_RANGE_INV_REG00 2 #define HUE_RANGE_INV_REG05 32 #define HUE_RANGE_INV_REG06 38 #define HUE_RANGE_INV_REG03 20 #define HUE_RANGE_INV_REG04 26 #define P_VD2_IF0_CHROMA_X1 4287654372 #define P_PK_CON_2CIRHPGAIN_TH_RATE 4287678484 #define VDEC2_PSCALE_PICI_H 10515 #define VDEC2_PSCALE_PICI_W 10514 #define P_V5_SMALL_DIFF_CNT 4284644852 #define P_VD2_IF0_CHROMA_X0 4287654356 #define ENCP_VBI_DATA0 7125 #define P_MCDI_CHAR_DET_CNT_THD 4287675744 #define DBLK_AVSFLAGS 2414 #define P_VD2_IF0_CHROMA_Y0 4287654360 #define P_VD2_IF0_CHROMA_Y1 4287654376 #define VPP_HOLD_LINES 7458 #define MIPI_DSI_DWC_VID_VBP_LINES_OS 7190 #define DB_LINE_SW 8 #define P_HEVC_NEXT_ALIGN_PEAK 4284674164 #define VPP_HSHARP_CTRL 7504 #define P_AIU_AMCLK_GATE_HI 4291842368 #define VDIN1_CHROMA_ADDR_PORT 5163 #define VI_HIST_SPL_PIX_CNT 11781 #define P_HEVC_PSCALE_STATUS 4284671096 #define P_HEVC_MPRED_ABV_START_ADDR 4284663880 #define HEVCD_MCRCC_PERFMON_CTL 13555 #define P_HEVC_PARSER_RESULT_1 4284662884 #define P_HEVC_PARSER_RESULT_0 4284662880 #define P_HEVC_PARSER_RESULT_3 4284662892 #define P_HEVC_PARSER_RESULT_2 4284662888 #define P_HCODEC_QDCT_MB_BUFF 4284644444 #define VENC_VIDEO_TST_Y 7026 #define GE2D_MATRIX_COEF00_01 198 #define P_HEVC_CINDEX2_REG 4284665008 #define VDIN0_WIN_H_START_END 4717 #define DI_IF2_DUMMY_PIXEL 8217 #define DE_HE_ADDR 5330 #define DOLBY_CORE3_STATUS3 14078 #define DOLBY_CORE3_STATUS2 14077 #define DOLBY_CORE3_STATUS1 14076 #define DOLBY_CORE3_STATUS0 14075 #define GPIO_INTR_EDGE_POL 15392 #define VDEC2_ANC13_CANVAS_ADDR 10653 #define OSDSR_UK_GRAD2DADJA_LIMIT 12606 #define TCON_DE_SEL_DVI 9 #define P_DI_IF1_LUMA_Y0 4287651756 #define P_VIU_VD1_FMT_CTRL 4287654304 #define SPI_FLASH_USR_DIN 13 #define P_DI_IF1_LUMA_X0 4287651752 #define NR2_MATNR_DEGHOST 5998 #define P_SHARP_DB_FLT_SEED_U 4287678960 #define P_SHARP_DB_FLT_SEED_V 4287678964 #define HCODEC_HDEC_MC_MBRIGHT_IDX 6449 #define HEVC_ASSIST_MBOX0_CLR_REG 12401 #define P_SHARP_DB_FLT_SEED_Y 4287678956 #define HEVC_ASSIST_SW_RESET 12292 #define P_DNR_BLK_OFFST 4287673356 #define P_VDEC2_MC_STATUS0 4284654628 #define P_VDEC2_MC_STATUS1 4284654632 #define P_HCODEC_ASSIST_TIMER1_HI 4284629388 #define ENCT_VIDEO_OFLD_VPEQ_OFST 7299 #define UART1_STATUS 35843 #define HCODEC_IE_I4_PRED_MODE_HI 8005 #define P_HCODEC_PSCALE_CTRL2 4284638392 #define HEVC_GCLK_EN 14723 #define DI_CHAN2_FMT_W 6073 #define ENCL_VIDEO_BLANKPR_VAL 7358 #define VDEC2_VLD_MEM_VIFIFO_LEVEL 11335 #define P_HCODEC_PSCALE_CTRL1 4284638372 #define NR4_MCNR_SKIN_CENT 11730 #define P_HEVC_MC_MBBOT_ST_ODD_ADDR 4284671252 #define P_PARSER_FETCH_LEVEL 4291879312 #define P_VPU_OSD3_MMC_CTRL 4287667292 #define P_MCDI_RO_RPT_FLG_CNT 4287676040 #define D2D3_DBLD_LPF_HCOEFF 11028 #define CBREAK0_REG 820 #define P_GE2D_DST_CLIPX_START_END 4287890128 #define P_WRRSP_LMEM 4284616012 #define VPP_SLEEP_CTRL 7674 #define P_HCODEC_QDCT_TOP_WRRSP 4284644488 #define P_HCODEC_ASSIST_TIMER1_LO 4284629384 #define HCODEC_IE_I4_PRED_MODE_LO 8006 #define DOS_GEN_CTRL0 16130 #define VBO_CTRL_H 5217 #define MCDI_MCINFORD_CANVAS_SIZE 12136 #define ENCT_VFIFO2VD_PIXEL_END 7202 #define HEVCD_MPP_DECOMP_CTL1 13506 #define HEVCD_MPP_DECOMP_CTL2 13507 #define VBO_CTRL_L 5216 #define HEVCD_MPP_DECOMP_CTL3 13508 #define AUDIN_FIFO0_ENDIAN 8 #define P_VD1_IF0_RPT_LOOP 4287654252 #define P_PSCALE_SRCKEY_CTRL0 4284621992 #define P_PSCALE_SRCKEY_CTRL1 4284621996 #define MIPI_DSI_DWC_EDPI_CMD_SIZE_OS 7193 #define AIU_I2S_FF_CTRL 5140 #define P_HEVC_ASSIST_MBOX0_MASK 4284662216 #define HEVC_SAO_MMU_STATUS 13881 #define VDEC2_MCRCC_CTL3 10626 #define VDEC2_MCRCC_CTL2 10625 #define VDEC2_MCRCC_CTL1 10624 #define PK_OS_VERT_CORE_GAIN 12836 #define P_DOS_VDIN_CCTL 4284677172 #define VIU_SW_RESET0 6658 #define P_AIU_MEM_I2S_MAN_RP 4291842512 #define P_SPICC0_DWADDR 4291899428 #define P_VLTI_CON_2_GAIN_1 4287678712 #define P_MCDI_REF_MV_NUM 4287675484 #define P_HEVC_PMV3_X 4284674192 #define P_VLTI_CON_2_GAIN_0 4287678708 #define P_HEVC_PMV3_Y 4284674196 #define VDEC2_VLD_MEM_SWAP_ADDR 11349 #define GPIO_ADR 1025 #define P_DNR_RO_VBOF_STAT_CNT_30 4287673708 #define P_DNR_RO_VBOF_STAT_CNT_31 4287673712 #define P_DNR_RO_VBOF_STAT_CNT_29 4287673704 #define P_DNR_RO_VBOF_STAT_CNT_27 4287673696 #define P_DNR_RO_VBOF_STAT_CNT_28 4287673700 #define P_DNR_RO_VBOF_STAT_CNT_25 4287673688 #define P_DNR_RO_VBOF_STAT_CNT_26 4287673692 #define HEVC_WRRSP_CO_MB 14808 #define P_HCODEC_CCPU_INTR_GRP 4284632204 #define NR4_NM_X_CFG 14099 #define P_HCODEC_ANC5_CANVAS_ADDR 4284638804 #define P_DNR_RO_VBOF_STAT_CNT_23 4287673680 #define P_DNR_RO_VBOF_STAT_CNT_24 4287673684 #define P_DNR_RO_VBOF_STAT_CNT_21 4287673672 #define P_DNR_RO_VBOF_STAT_CNT_22 4287673676 #define P_AUDIN_SPDIF_MISC 4291874832 #define P_DNR_RO_VBOF_STAT_CNT_20 4287673668 #define P_DNR_RO_VBOF_STAT_CNT_18 4287673660 #define P_DNR_RO_VBOF_STAT_CNT_19 4287673664 #define P_DNR_RO_VBOF_STAT_CNT_16 4287673652 #define P_DNR_RO_VBOF_STAT_CNT_17 4287673656 #define P_DNR_RO_VBOF_STAT_CNT_14 4287673644 #define P_DNR_RO_VBOF_STAT_CNT_15 4287673648 #define P_GE2D_MATRIX_COEF11_12 4287890208 #define MCDI_HV_SIZEIN 12032 #define NR2_POLAR3_THRD 11673 #define DI_INP_CHROMA_Y0 6099 #define HEVC_PMV2_X 15394 #define HEVC_PMV2_Y 15395 #define P_AIU_MEM_I2S_MAN_WP 4291842508 #define P_VPU_VLOCK_GCLK_EN 4287676536 #define VPP_SMOKE2_V_START_END 7472 #define DI_IF2_RANGE_MAP_Y 8219 #define VDEC2_DCAC_MB_COUNT 11798 #define HCODEC_PIC_HEAD_INFO 7171 #define SPICC1_RXDATA 21504 #define DI_INP_CHROMA_X0 6098 #define VDIN_HIST_CHROMA_SUM 4662 #define P_VDEC2_DCAC_DMA_CTRL 4284659784 #define P_VPP_EOTF_COEF11_12 4287678284 #define P_NR4_DRT_YSAD_GAIN 4287674004 #define VDEC2_CMAX_REG 9011 #define P_HEVC_WRRSP_FIFO_PICW_DBK 4284671736 #define HCODEC_MBA_INC 7174 #define HEVC_SAO_DBG_DATA_2 13874 #define HEVC_SAO_DBG_DATA_3 13875 #define HEVC_SAO_DBG_DATA_0 13872 #define HEVC_SAO_DBG_DATA_1 13873 #define P_VPP_VADJ1_MA_MB 4287657224 #define HEVC_SAO_DBG_DATA_6 13878 #define HEVC_SAO_DBG_DATA_7 13879 #define HEVC_SAO_DBG_DATA_4 13876 #define P_AFBC_STAT 4287654824 #define P_VDEC2_MDEC_PIC_DC_THRESH 4284655328 #define HEVC_SAO_DBG_DATA_5 13877 #define HEVC_MC_OMDN_MB_XY 14663 #define I2C_M_2_WDATA_REG0 29700 #define I2C_M_2_WDATA_REG1 29701 #define ENCP_VIDEO_HSPULS_BEGIN 7064 #define HCODEC_VLC_PUSH_ELEMENT 7456 #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 15724 #define VDIN1_MATRIX_OFFSET2 5143 #define VDIN0_MATRIX_OFFSET2 4631 #define DI_MEM_RANGE_MAP_Y 6077 #define HEVC_ANC14_CANVAS_ADDR 14750 #define MIPI_DSI_DWC_PHY_TST_CTRL1_OS 7214 #define P_VLC_HCMD_MBXY_AUTO 4284642456 #define HEVC_PMV1_X 15392 #define HEVC_PMV1_Y 15393 #define ENCL_VIDEO_MAX_PXCNT 7344 #define P_DOS_SECURE_CTL_DATA 4284677636 #define P_HCODEC_DBLK_STRONG 4284638676 #define HCODEC_MFDIN_REG10 4120 #define HEVC_MB_MOTION_MODE 15367 #define HCODEC_MFDIN_REG15 4125 #define HCODEC_MFDIN_REG16 4126 #define HCODEC_MFDIN_REG11 4121 #define HCODEC_MFDIN_REG12 4122 #define HCODEC_MFDIN_REG13 4123 #define P_HEVC_MPRED_MV_RPTR 4284663896 #define HCODEC_MFDIN_REG14 4124 #define VIU_OSD1_OETF_LUT_DATA_PORT 6878 #define P_TS_PL_PID_DATA 4291847120 #define HCODEC_MFDIN_REG0D 4117 #define HCODEC_MFDIN_REG0E 4118 #define HCODEC_MFDIN_REG0F 4119 #define DI_BLEND_REG3_X 5910 #define DI_BLEND_REG3_Y 5911 #define MC_CMD 2310 #define STH2_HS_ADDR 5268 #define P_VDEC2_PMV1_Y 4284657796 #define P_VDEC2_PMV1_X 4284657792 #define VPP2_MATRIX_HL_COLOR 6493 #define P_VLC_DBG_READ 4284642652 #define VPU_BT656_MMC_CTRL 9999 #define P_DBLK_STRONG 4284622292 #define VPP2_VSC_REGION4_PHASE_SLOPE 6412 #define P_VPU_VENCL_DITH_LUT_10 4287668136 #define P_VPU_VENCL_DITH_LUT_12 4287668144 #define P_VPU_VENCL_DITH_LUT_11 4287668140 #define MEDIA_CPU_PCR 15456 #define ANC28_CANVAS_ADDR 2476 #define HCODEC_DBKR_CANVAS_ADDR 6576 #define P_CDB_ADDR_REG 4284615916 #define HEVC_SAO_AXI_WCTRL 13833 #define P_ENCP_MACV_BLANKY_VAL 4287655680 #define P_SHARP_3DLIMIT 4287678736 #define P_VDIN_WR_V_START_END 4287645832 #define P_NR4_NM_Y_CFG 4287683664 #define ALL_RAM_PTS 127 #define VPP_HSC_REGION12_STARTP 7440 #define DECOMB_WIND10 11660 #define DECOMB_WIND11 11661 #define VDIN_BLKBAR_STATUS0 4715 #define VPU_VLOCK_OUTPUT1_CAPT_LMT 12299 #define VDIN_BLKBAR_STATUS1 4716 #define P_MCDI_CHK_EDGE_GAIN_OFFST 4287675436 #define VDEC2_VLD_DC_PRED 11309 #define P_HEVC_PSCALE_MCMD_YSIZE 4284671120 #define L_OEH_VE_ADDR 5147 #define ENCP_VIDEO_PR_SCL 7045 #define MIPI_DSI_DWC_VERSION_OS 7168 #define VDIN0_LDIM_STTS_HIST_READ_REGION 4697 #define ASYNC_FIFO_FIFO_EMPTY 29 #define VPP2_SMOKE_CTRL 6441 #define HCODEC_ASSIST_MBOX0_IRQ_REG 4208 #define NEXT_INTRA_DMA_ADDRESS 3597 #define P_SPI_FLASH_CLOCK 4291903512 #define SRSHARP0_NR_ALP0Y_ERR2CURV_LIMIT 12822 #define P_AUDIN_FIFO0_REQID 4291875008 #define P_VIU_OSD2_BLK1_CFG_W2 4287654148 #define P_VIU_OSD2_BLK1_CFG_W3 4287654152 #define P_VIU_OSD2_BLK1_CFG_W4 4287654292 #define P_HEVC_CBREAK_TYPE 4284665056 #define P_VIU_OSD2_BLK1_CFG_W0 4287654140 #define P_VIU_OSD2_BLK1_CFG_W1 4287654144 #define P_QDCT_ADV_CONFIG 4284644560 #define P_VPU_VENCL_DITH_LUT_1 4287668100 #define P_VPU_VENCL_DITH_LUT_2 4287668104 #define P_VPU_VENCL_DITH_LUT_3 4287668108 #define P_VPU_VENCL_DITH_LUT_4 4287668112 #define P_VPU_VENCL_DITH_LUT_5 4287668116 #define P_VPU_VENCL_DITH_LUT_6 4287668120 #define P_VPU_VENCL_DITH_LUT_7 4287668124 #define P_VPU_VENCL_DITH_LUT_8 4287668128 #define P_VPU_VENCL_DITH_LUT_9 4287668132 #define P_VPU_PROT1_GEN_CNTL 4287667524 #define DI_CHAN2_FMT_CTRL 6072 #define P_VDEC2_VLD_DBG_DATA 4284657916 #define P_RESET5_LEVEL 4291825812 #define P_HCODEC_MBREAK_STAUTS 4284632168 #define P_NR3_COOP_PARA 4287676356 #define HEVC_PARSER_CORE_CONTROL 12563 #define P_PK_CON_2CIRBPGAIN_TH_RATE 4287678492 #define DECOMB_WIND01 11659 #define DECOMB_WIND00 11658 #define DI_MC_REG0_Y 5921 #define DI_MC_REG0_X 5920 #define P_HEVC_MPRED_PIC_SIZE_LCU 4284663832 #define P_NEXT_ALIGN_PEAK 4284625012 #define NR4_MCNR_BLUE_CENT 11720 #define HCODEC_VLC_PIC_SIZE 7473 #define P_VDIN_BLKBAR_IND_LEFT2_CNT 4287646112 #define P_PSCALE_DUMMY 4284621920 #define P_HEVC_CM_HEADER_OFFSET 4284668076 #define P_HEVC_SHIFT_COMMAND 4284662840 #define VKS_TOP_MISC 12553 #define DOLBY_PATH_CTRL 6668 #define HCODEC_VCOP_CTRL_REG 7680 #define P_DI_NRWR_CTRL 4287651592 #define ME_SUB_ANY_WEIGHT_SAD 8027 #define PK_CIRFB_BP_CORING 12816 #define P_VDEC2_ANC29_CANVAS_ADDR 4284655284 #define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 15721 #define P_ENCI_CFILT_CTRL2 4287655976 #define QDCT_I_PRED_REF_WR_IDX 7986 #define VDEC2_PSCALE_MCMD_XSIZE 10531 #define SANA_SHIFT_STARTCODE 12328 #define SRSHARP0_VCTI_BST_CORE 12865 #define PK_DRTFB_LPF_MODE 12814 #define P_NR4_MCNR_SAD2ALP0_LUT0 4287674232 #define P_NR4_MCNR_SAD2ALP0_LUT1 4287674236 #define P_NR4_MCNR_SAD2ALP0_LUT2 4287674240 #define P_NR4_MCNR_SAD2ALP0_LUT3 4287674244 #define P_VP9D_MPP_REFINFO_DATA 4284666124 #define P_HCODEC_DBLK_RST 4284638528 #define AIU_I2S_CBUS_DDR_CNTL 5289 #define P_VPP2_MISC1 4287653336 #define P_GE2D_SRC1_RANGE_MAP_CR_CTRL 4287890324 #define MIPI_DSI_DWC_VID_VACTIVE_LINES_OS 7192 #define RAM_TEST_WR_CMD 32768 #define AIU_CRC_CTRL 5188 #define VDEC2_MDEC_PICW_BUF2_STATUS 10685 #define DOS_MEM_PD_HCODEC 16178 #define mLVDS2_reset_start 0 #define P_ENCI_TST_CLRBAR_WIDTH 4287656024 #define SLICE_START_BYTE_01 3084 #define Q_QUANT_CONTROL 7990 #define P_AIU_958_PAUSE_PD_LENGTH 4291842204 #define mLVDS_RESERVED 15 #define VDEC2_ANC14_CANVAS_ADDR 10654 #define NR_DB_FLT_SEED3 14143 #define ENCP_VIDEO_MACV_SCL 7047 #define VPP_PREBLEND_H_SIZE 7456 #define SLICE_START_BYTE_23 3085 #define ENCP_DVI_VSO_ELINE_ODD 7221 #define VPU_VDISP_PRE_ARB_CTRL 10005 #define P_HEVC_PMV4_Y 4284674204 #define P_HEVC_PMV4_X 4284674200 #define HEVC_DEBLK_CMD 15888 #define NR4_MCNR_RO_GRDV_SUM 11765 #define P_RV_AI_V_X 4284626988 #define DNR_DBLK_BLANK_NUM 11522 #define P_HEVC_ASSIST_AXI_STATUS 4284662260 #define P_ENCP_VFIFO2VD_CTL2 4287656256 #define P_ENCP_VIDEO_EQPULS_BLINE 4287655556 #define P_L_STH1_VE_ADDR 4287647820 #define MIPI_DSI_TOP_INTR_CNTL_STAT 7420 #define HCODEC_DBLK_Y_VFILT 6494 #define SRSHARP0_PKOSHT_VSLUMA_LUT_H 12804 #define SRSHARP0_PKOSHT_VSLUMA_LUT_L 12803 #define VLD_TIME_STAMP_SYNC_0 3146 #define P_L_STH2_HE_ADDR 4287647828 #define P_HEVC_MCPU_INTR_MSK 4284664848 #define VLD_TIME_STAMP_SYNC_1 3147 #define RESET5_MASK 1045 #define VPP_OSD2_BLD_V_SCOPE 7672 #define P_HCTI_BST_CORE 4287678656 #define P_SPI_FLASH_ADDR 4291903492 #define VBO_REGION_01 5223 #define VBO_REGION_02 5224 #define VBO_REGION_03 5225 #define HCODEC_MC_DPDN_MB_XY 6470 #define SHARP_SR2_CTRL 12887 #define SRSHARP1_VLTI_FLT_CON_CLP 13370 #define DBLK_CBPY_ADJ 2417 #define VBO_REGION_00 5222 #define P_DBKW_CANVAS_ADDR 4284622532 #define P_PARSER_VIDEO2_END_PTR 4291879504 #define P_AFBC_VD_CFMT_W 4287654832 #define HEVC_ASSIST_DMA_INT_MSK 12389 #define DECOMB_FRM_SIZE 11663 #define MIPI_DSI_DWC_VID_NUM_CHUNKS_OS 7184 #define P_NR4_MCNR_ALP1_SGN_PRAM 4287683680 #define P_HEVC_MPRED_L1_REF09_POC 4284664036 #define P_VIU2_VD1_IF0_LUMA_FIFO_SIZE 4287658380 #define VDEC2_WRRSP_CO_MB 10712 #define HCODEC_VLC_PIC_POSITION 7475 #define P_AFBC_VD_CFMT_H 4287654852 #define P_SHARP_SR3_DERING_GAINVS_VR2MAX 4287678916 #define P_HEVC_MAC_CTRL1 4284665216 #define P_HEVC_MAC_CTRL2 4284665280 #define P_L_STH1_VS_ADDR 4287647816 #define VD1_IF0_CHROMA1_RPT_PAT 6751 #define P_DI_IF2_LUMA0_RPT_PAT 4287660124 #define P_VPP_MATRIX_COEF22 4287657360 #define P_HEVC_MC_MB_INFO 4284670980 #define P_ENCL_VIDEO_MAX_PXCNT 4287656640 #define P_HLTI_OS_MARGIN 4287678692 #define P_DOS_VDEC2_MCRCC_STALL2_CTRL 4284677388 #define P_VENC_VDAC_DAC3_FILT_CTRL1 4287656316 #define HCODEC_ME_STATUS 8011 #define P_VENC_VDAC_DAC3_FILT_CTRL0 4287656312 #define P_UART1_CONTROL 4291964936 #define ASYNC_FLUSH_SIZE_IRQ_LSB 0 #define VDIN_HIST_SPL_VAL 4660 #define P_VPP_SC_GCLK_CTRL 4287657424 #define DOS_GCLK_EN0 16129 #define DOS_GCLK_EN1 16137 #define LVDS_BIST_FIXED1 5356 #define P_HEVC_DBLK_Y_BVFILT 4284671332 #define LVDS_BIST_FIXED0 5355 #define P_NR4_MCNR_ALP0_REG 4287674116 #define CRT_MASK 1047 #define VDEC2_PSCALE_PICO_SHIFT_XY 10536 #define P_NR_ALPY_SSD_GAIN_OFST 4287678544 #define DBLK_VHMVD 2420 #define P_ENCT_TST_EN 4287656096 #define P_HCODEC_ME_STATUS 4284644652 #define VPP_SC_GCLK_CTRL 7540 #define P_VPU_PROT2_DDR 4287667612 #define P_VIU2_OSD2_COLOR_ADDR 4287658180 #define P_VPP_OSD_VSC_INI_PHASE 4287657732 #define DEVICE_MMCP_CNTL 15435 #define P_HEVC_PARSER_HEADER_INFO2 4284662932 #define P_MCDI_RO_FLD_PD_22_FLT_CNT1 4287676208 #define P_ENCT_TST_CR 4287656112 #define MCDI_MC_COL_CFD_19 12171 #define MCDI_MC_COL_CFD_17 12169 #define MCDI_MC_COL_CFD_18 12170 #define MCDI_MC_COL_CFD_15 12167 #define MCDI_MC_COL_CFD_16 12168 #define MCDI_MC_COL_CFD_13 12165 #define MCDI_MC_COL_CFD_14 12166 #define MCDI_MC_COL_CFD_11 12163 #define MCDI_MC_COL_CFD_12 12164 #define P_PSCALE_CTRL 4284621892 #define MCDI_MC_COL_CFD_10 12162 #define P_MCDI_RO_FLD_PD_22_FLT_CNT2 4287676220 #define P_ENCT_TST_CB 4287656108 #define ENCP_VFIFO2VD_CTL 7000 #define VD2_IF0_LUMA_FIFO_SIZE 6787 #define P_VI_HIST_SPL_PIX_CNT 4287674388 #define ENCL_VFIFO2VD_PIXEL_END 7314 #define MCDI_MC_COL_CFD_24 12176 #define MCDI_MC_COL_CFD_25 12177 #define MCDI_MC_COL_CFD_22 12174 #define MCDI_MC_COL_CFD_23 12175 #define MCDI_MC_COL_CFD_20 12172 #define P_VLD_MEM_VIFIFO_BUF_CNTL 4284625184 #define MCDI_MC_COL_CFD_21 12173 #define VDIN_MEAS_HS_COUNT 4702 #define VENC_VDAC_DAC0_FILT_CTRL1 7257 #define VENC_VDAC_DAC0_FILT_CTRL0 7256 #define STH2_VE_ADDR 5271 #define VENC_VDAC_DAC4_GAINCTRL 7160 #define P_SPICC0_LD_RADDR 4291899440 #define P_ENCL_VIDEO_MODE 4287656604 #define ENCP_DE_V_BEGIN_EVEN 7228 #define P_V5_SIMPLE_MB_ME_WEIGHT 4284644864 #define L_DE_VE_ADDR 5204 #define P_NR2_MET_NM_CCTRL 4287651100 #define P_HEVC_ASSIST_SCRATCH_4 4284662544 #define P_HEVC_ASSIST_SCRATCH_3 4284662540 #define P_HEVC_ASSIST_SCRATCH_2 4284662536 #define P_HEVC_ASSIST_SCRATCH_1 4284662532 #define P_HEVC_ASSIST_SCRATCH_8 4284662560 #define P_HEVC_ASSIST_SCRATCH_7 4284662556 #define P_HEVC_ASSIST_SCRATCH_6 4284662552 #define P_HEVC_ASSIST_SCRATCH_5 4284662548 #define P_HEVC_ASSIST_SCRATCH_0 4284662528 #define NR4_RO_NM_VAR_SCNT 14114 #define P_HCODEC_DBLK_Y_BHFILT_HIGH 4284638560 #define ENCI_SYNC_VSO_ODDLN 6927 #define P_HEVC_ASSIST_SCRATCH_L 4284662612 #define P_HEVC_ASSIST_SCRATCH_K 4284662608 #define HCODEC_VLC_HCMD_CONFIG 7508 #define P_HEVC_ASSIST_SCRATCH_J 4284662604 #define P_HEVC_ASSIST_SCRATCH_I 4284662600 #define P_HEVC_ASSIST_SCRATCH_N 4284662620 #define P_VD1_IF0_DUMMY_PIXEL 4287654280 #define P_HEVC_ASSIST_SCRATCH_M 4284662616 #define P_HEVC_ASSIST_SCRATCH_D 4284662580 #define HCODEC_VLC_HCMD_T_L_INFO 7459 #define P_HEVC_ASSIST_SCRATCH_C 4284662576 #define P_HEVC_ASSIST_SCRATCH_B 4284662572 #define P_HEVC_ASSIST_SCRATCH_A 4284662568 #define P_HEVC_ASSIST_SCRATCH_H 4284662596 #define P_HEVC_ASSIST_SCRATCH_G 4284662592 #define P_HEVC_ASSIST_SCRATCH_F 4284662588 #define P_HEVC_ASSIST_SCRATCH_E 4284662584 #define P_HEVC_ASSIST_SCRATCH_9 4284662564 #define QDCT_Q_QUANT_I 7964 #define HCODEC_QDCT_MB_PAUSE_CTL 7966 #define QDCT_Q_QUANT_P 7965 #define AIU_958_AUTO_PAUSE 5158 #define P_DI_MEM_DUMMY_PIXEL 4287651728 #define P_VDIN_DNLP_HIST06 4287645940 #define VLD_MEM_VIFIFO_END_PTR 3138 #define P_VDIN_DNLP_HIST07 4287645944 #define P_MCDI_REL_BADW_GAIN_OFFST_01 4287675524 #define P_VDIN_DNLP_HIST08 4287645948 #define P_VDIN_DNLP_HIST09 4287645952 #define P_VDIN_DNLP_HIST13 4287645968 #define STH2_VS_ADDR 5270 #define P_VDIN_DNLP_HIST14 4287645972 #define VDIN_BLKBAR_IND_LEFT1_CNT 4711 #define P_VDIN_DNLP_HIST15 4287645976 #define P_VDIN_DNLP_HIST16 4287645980 #define P_VDIN_DNLP_HIST10 4287645956 #define P_VDIN_DNLP_HIST11 4287645960 #define P_VDIN_DNLP_HIST12 4287645964 #define mLVDS2_data_latch_0_toggle 14 #define P_WATCHDOG_RESET 4291883228 #define P_ENCP_VFIFO2VD_LINE_BOT_END 4287655288 #define ENCL_SYNC_TO_PIXEL 7247 #define HCODEC_PSCALE_BMEM_DAT 6432 #define P_VDIN_DNLP_HIST02 4287645924 #define P_VDIN_DNLP_HIST03 4287645928 #define DOS_GCLK_EN3 16181 #define P_VDIN_DNLP_HIST04 4287645932 #define DOS_GCLK_EN4 16184 #define P_VDIN_DNLP_HIST05 4287645936 #define P_VDIN_DNLP_HIST00 4287645916 #define P_VDIN_DNLP_HIST01 4287645920 #define DI_INP_RANGE_MAP_Y 6074 #define P_VLC_VB_CONTROL 4284642392 #define P_VIU_OSD1_OETF_LUT_DATA_PORT 4287654776 #define P_HEVC_PARSER_QUANT_READ 4284662936 #define P_VDIN_DNLP_HIST28 4287646028 #define P_VDIN_DNLP_HIST29 4287646032 #define P_MCDI_REL_BADW_GAIN_OFFST_23 4287675528 #define P_VDIN_DNLP_HIST31 4287646040 #define P_ENCL_DBG_PX_INT 4287656620 #define P_VDIN_DNLP_HIST32 4287646152 #define VPP_OSD_VSC_CTRL0 7618 #define P_VDIN_DNLP_HIST30 4287646036 #define DVIN_ACTIVE_START_PIX 2274 #define VDIN1_HIST_V_START_END 5170 #define P_VDIN_DNLP_HIST17 4287645984 #define P_VDIN_DNLP_HIST18 4287645988 #define P_VDIN_DNLP_HIST19 4287645992 #define I2C_M_STATUS 2 #define VPP_HSC_REGION1_PHASE_SLOPE 7445 #define P_VDIN_DNLP_HIST24 4287646012 #define P_VDIN_DNLP_HIST25 4287646016 #define P_VDIN_DNLP_HIST26 4287646020 #define P_HCODEC_ANC10_CANVAS_ADDR 4284638824 #define P_VDIN_DNLP_HIST27 4287646024 #define P_VDIN_DNLP_HIST20 4287645996 #define P_VDIN_DNLP_HIST21 4287646000 #define P_VDIN_DNLP_HIST22 4287646004 #define P_VDIN_DNLP_HIST23 4287646008 #define P_HCODEC_VLC_ENC_MV_BITS 4284642672 #define XVYCC_VD1_RGB_DLUT_4_7 12659 #define DBLK_GCLK_FREE 2412 #define ENCI_CFILT_CTRL2 7178 #define GAMMA_RVS_OUT 6 #define VIUB_ADDR_END 8447 #define VPP_WRBAK_CTRL 7673 #define P_HCODEC_Q_QUANT_CONTROL 4284644568 #define P_DI_MEM_CHROMA0_RPT_PAT 4287651724 #define HCODEC_WRRSP_FIFO_PICW_DBK 6590 #define P_LCD_PWM0_LO_ADDR 4287648496 #define DECOMB_YC_THRD 11655 #define RESET4_REGISTER 1029 #define VPU_PROT1_Y_LEN_STEP 10068 #define UART2_REG5 34821 #define L_DE_VS_ADDR 5203 #define P_AFBC_VD_CFMT_CTRL 4287654828 #define REG_BASE_PERIPHS 4284694528 #define QDCT_MB_BUFF 7959 #define ENCP_VBI_HVAL 7124 #define P_HCODEC_QDCT_ADV_CONFIG 4284644560 #define mLVDS2_double_pattern 14 #define P_ANC10_CANVAS_ADDR 4284622440 #define P_MLVDS_CONTROL 4287648524 #define AIU_MEM_I2S_MASKS 5219 #define P_HEVC_MPRED_L1_REF10_POC 4284664040 #define HCODEC_VLC_VB_RD_PTR 7443 #define SPI_SST_AAI 16 #define P_HCODEC_QDCT_TOP_MEM_CTL 4284644484 #define P_VPP_GAINOFF_CTRL4 4287657400 #define P_HCODEC_DBLK_MB_XY 4284638548 #define P_VPP_GAINOFF_CTRL3 4287657396 #define P_VPP_GAINOFF_CTRL2 4287657392 #define P_VPP_HOLD_LINES 4287657096 #define P_VPP_GAINOFF_CTRL1 4287657388 #define P_VPP_GAINOFF_CTRL0 4287657384 #define P_HCODEC_DBLK_CB_BFILT 4284638568 #define P_HCODEC_CINT_VEC_BASE 4284632200 #define AUDIO_MMCP_CNTL 15436 #define P_MCDI_REL_DET_LUT_8_11 4287675648 #define P_GE2D_SRC1_CLIPX_START_END 4287890076 #define P_NR3_MODE 4287676352 #define P_AIU_958_LENGTH 4291842056 #define P_HCODEC_QDCT_Q_STATUS 4284644456 #define AUDIN_FIFO1_START 13363 #define VPP_CHROMA_ADDR_PORT 7536 #define P_VDEC2_AV_SCRATCH_G 4284655424 #define P_VDEC2_AV_SCRATCH_H 4284655428 #define P_VDEC2_AV_SCRATCH_I 4284655432 #define P_VDEC2_AV_SCRATCH_J 4284655436 #define PK_ALP2_ERR2CURV_LIMIT 12832 #define P_VDEC2_AV_SCRATCH_C 4284655408 #define P_VDEC2_AV_SCRATCH_D 4284655412 #define P_VDEC2_AV_SCRATCH_E 4284655416 #define P_VDEC2_AV_SCRATCH_F 4284655420 #define P_HCODEC_CCPU_INTR_REQ 4284632212 #define VPP_VE_DEMO_CENTER_BAR 7587 #define P_VDEC2_AV_SCRATCH_K 4284655440 #define P_VDEC2_AV_SCRATCH_L 4284655444 #define P_VDEC2_AV_SCRATCH_M 4284655448 #define P_VDEC2_AV_SCRATCH_N 4284655452 #define P_VDEC2_AV_SCRATCH_7 4284655388 #define VDIN1_LDIM_STTS_HIST_SET_REGION 5208 #define P_VDEC2_AV_SCRATCH_8 4284655392 #define P_VDEC2_AV_SCRATCH_9 4284655396 #define P_VDEC2_AV_SCRATCH_3 4284655372 #define P_VDEC2_AV_SCRATCH_4 4284655376 #define P_VDEC2_AV_SCRATCH_5 4284655380 #define P_VDEC2_AV_SCRATCH_6 4284655384 #define P_VDEC2_AV_SCRATCH_A 4284655400 #define P_VDEC2_AV_SCRATCH_B 4284655404 #define HEVC_MPRED_L0_REF06_POC 12838 #define P_DI_INP_URGENT_CTRL 4287660688 #define P_VDEC2_AV_SCRATCH_0 4284655360 #define P_VDEC2_AV_SCRATCH_1 4284655364 #define P_VDEC2_AV_SCRATCH_2 4284655368 #define P_HCODEC_ANC13_CANVAS_ADDR 4284638836 #define SKIP_MB 4 #define VDEC2_MBA_INC 11270 #define P_VDEC2_SCD_FOR_MV_X 4284657736 #define P_VDEC2_SCD_FOR_MV_Y 4284657740 #define P_MCDI_REL_SAD_THD_GAIN_OFFST 4287675548 #define P_RV_AI_U_X 4284626984 #define VLC_VB_WR_PTR 7442 #define P_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 4287657608 #define DI_INFO_ADDR 5937 #define OSDSR_CBIC_HCOEF 12596 #define ENCI_VIDEO_EN 6999 #define SRSHARP1_HLTI_CON_2_GAIN_1 13368 #define SRSHARP1_HLTI_CON_2_GAIN_0 13367 #define P_PK_CIRFB_BLEND_GAIN 4287678540 #define P_HCODEC_ASSIST_MBOX0_FIQ_SEL 4284629452 #define DI_DIWR_CTRL 6088 #define HCODEC_MC_CTRL1 6411 #define HCODEC_MC_CTRL2 6479 #define HCODEC_MC_CTRL0 6407 #define HEVC_MCW_DBLK_WRRSP_CNT 14779 #define DI_IF1_CANVAS0 6121 #define P_AVS2_CONTROL 4284663112 #define P_HCODEC_MB_MOTION_MODE 4284641308 #define MCDI_QME_LPF_MSK 12062 #define PARSER_FETCH_INFO 14479 #define P_SPI_START_ADDR 4211081216 #define DBLK_CR_FILT 2400 #define VPU_PROT2_RBUF_ROOM 10088 #define HEVC_MPRED_L1_REF14_POC 12862 #define VPP_SRSCL_GCLK_CTRL 7543 #define P_VDEC_ASSIST_AMR2_INT1 4284612824 #define P_VDEC_ASSIST_AMR2_INT0 4284612820 #define P_VDEC_ASSIST_AMR2_INT9 4284612856 #define AUD_RESAMPLE_COEF4 13511 #define P_VDEC_ASSIST_AMR2_INT8 4284612852 #define P_VDEC_ASSIST_AMR2_INT7 4284612848 #define P_VDEC_ASSIST_AMR2_INT6 4284612844 #define P_VDEC_ASSIST_AMR2_INT5 4284612840 #define P_VDEC_ASSIST_AMR2_INT4 4284612836 #define P_VDEC_ASSIST_AMR2_INT3 4284612832 #define P_VDEC_ASSIST_AMR2_INT2 4284612828 #define P_VDEC_ASSIST_AMR2_INTA 4284612860 #define D2D3_DRMIF_STATUS 11066 #define AUD_RESAMPLE_COEF1 13508 #define AUD_RESAMPLE_COEF0 13507 #define AUD_RESAMPLE_COEF3 13510 #define AUD_RESAMPLE_COEF2 13509 #define P_VDEC2_MMAX_REG 4284648524 #define P_DI_CHAN2_CANVAS0 4287651800 #define P_VDEC_ASSIST_AMR2_INTF 4284612880 #define P_VDEC_ASSIST_AMR2_INTE 4284612876 #define P_VDEC_ASSIST_AMR2_INTD 4284612872 #define P_VDEC_ASSIST_AMR2_INTC 4284612868 #define P_VDEC_ASSIST_AMR2_INTB 4284612864 #define DI_INP_LUMA0_RPT_PAT 6101 #define P_QDCT_JPEG_SOF_RESUME 4284644520 #define P_UART3_DF_REG_A79 4291956760 #define VLD_MEM_VIFIFO_CONTROL 3140 #define P_UART3_DF_REG_A78 4291956756 #define P_UART3_DF_REG_A77 4291956752 #define P_UART3_DF_REG_A76 4291956748 #define P_UART3_DF_REG_A75 4291956744 #define P_UART3_DF_REG_A74 4291956740 #define P_UART3_DF_REG_A73 4291956736 #define P_UART3_DF_REG_A81 4291956768 #define P_UART3_DF_REG_A80 4291956764 #define VI_HIST_GCLK_CTRL 11818 #define VDEC2_CSP 8992 #define P_L_HSYNC_HE_ADDR 4287648088 #define P_HEVC_CSFTINT0 4284665080 #define P_HEVC_CSFTINT1 4284665084 #define VDEC2_ANC3_CANVAS_ADDR 10643 #define VPP2_SCALE_COEF 6404 #define VDEC2_ANC6_CANVAS_ADDR 10646 #define P_UART3_DF_REG_A89 4291956824 #define P_UART3_DF_REG_A88 4291956820 #define P_DCAC_DMA_CTRL 4284627016 #define P_UART3_DF_REG_A87 4291956816 #define P_UART3_DF_REG_A86 4291956812 #define P_UART3_DF_REG_A85 4291956808 #define P_UART3_DF_REG_A84 4291956804 #define P_UART3_DF_REG_A83 4291956800 #define P_UART3_DF_REG_A82 4291956772 #define UART3_DF_REG_A78 33797 #define UART3_DF_REG_A79 33798 #define UART3_DF_REG_A74 33793 #define P_HCODEC_MC_MBBOT_WRRSP_CNT 4284638960 #define UART3_DF_REG_A75 33794 #define P_PK_ALP2_ERR2CURV_TH_RATE 4287678588 #define UART3_DF_REG_A76 33795 #define UART3_DF_REG_A77 33796 #define UART3_DF_REG_A73 33792 #define UART3_DF_REG_A80 33799 #define P_ENCL_VIDEO_MATRIX_CB 4287656724 #define UART3_DF_REG_A89 33814 #define UART3_DF_REG_A85 33810 #define UART3_DF_REG_A86 33811 #define UART3_DF_REG_A87 33812 #define UART3_DF_REG_A88 33813 #define P_HEVC_VLD_MEM_SWAP_CTL 4284674392 #define UART3_DF_REG_A81 33800 #define UART3_DF_REG_A82 33801 #define UART3_DF_REG_A83 33808 #define UART3_DF_REG_A84 33809 #define NR_ALP0C_ERR2CURV_LIMIT 12824 #define HEVC_CINDEX2_REG 13100 #define P_IEC958_TIME_STAMP_LENGTH 4291842716 #define VDEC2_DBLK_Y_HFILT_HIGH 10589 #define P_ENCL_VIDEO_MATRIX_CR 4287656728 #define UART3_DF_REG_A96 33815 #define UART3_DF_REG_A97 33816 #define VDEC2_MCPU_INTR_MSK 8964 #define P_HCODEC_VLC_JPEG_CTRL 4284642656 #define P_HEVC_QP_VALUE_REG 4284674068 #define VD2_AFBC_ENABLE 12672 #define P_MCDI_MCVECRD_Y 4287675992 #define P_MCDI_MCVECRD_X 4287675988 #define VPP2_OSD_SCO_H_START_END 6602 #define HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR 13408 #define P_VPP_MATRIX_COEF00_01 4287657344 #define P_GE2D_ALU_CONST_COLOR 4287890228 #define ANC26_CANVAS_ADDR 2474 #define P_UART3_DF_REG_A97 4291956832 #define P_UART3_DF_REG_A96 4291956828 #define P_VLC_MB_INFO 4284642516 #define tcon_pattern_loop_data 16 #define P_ENCL_VIDEO_OFLD_VOAV_OFST 4287656720 #define HEVC_MDEC_PIC_DC_CTRL 14734 #define GE2D_ARB_BURST_NUM 230 #define OEH_HS_ADDR 5272 #define HEVC_VLD_REVERVED_19 15385 #define ENCT_VIDEO_PR_OFFST 7270 #define VDIN0_MATRIX_COEF11_12 4627 #define VDIN_COM_GCLK_CTRL 4635 #define P_VPP_PIC_IN_HEIGHT 4287656968 #define P_HEVC_CBREAK_STAUTS 4284665064 #define P_ME_AB_MEM_CTL 4284644664 #define P_VDEC2_MBREAK1_REG 4284648532 #define VD1_IF0_CHROMA_Y0 6742 #define P_VDEC2_DC_SCALER 4284659728 #define ENCL_VIDEO_OFLD_VPEQ_OFST 7363 #define VD1_IF0_CHROMA_Y1 6746 #define P_VPP_SMOKE2_H_START_END 4287657148 #define P_HEVC_MPRED_L0_REF11_POC 4284663980 #define DBKW_CANVAS_ADDR 2481 #define VD1_IF0_CHROMA_X1 6745 #define VD1_IF0_CHROMA_X0 6741 #define P_XVYCC_LUT_B_ADDR_PORT 4287677832 #define P_WM_AM_LUT_DATA_PORT 4287678236 #define P_L_HSYNC_HS_ADDR 4287648084 #define P_CMAX_REG 4284615884 #define DNR_CTRL 11520 #define VPP_VD2_CLIP_MISC0 7651 #define HEVCD_MPP_YLOG2WGHTDENOM_ADDR 13438 #define VPP_VD2_CLIP_MISC1 7652 #define ME_SUB_REF_MV_CTL 8026 #define VPP_FRONT_HLTI_CTRL 7611 #define HEVC_CABAC_TOP_INFO 12572 #define HCODEC_QDCT_CONFIG 7937 #define SRSHARP0_PK_CIRFB_LPF_MODE 12813 #define P_HEVC_PARSER_LCU_INFO 4284662872 #define P_SPI_FLASH_STATUS 4291903504 #define P_STV2_HS_ADDR 4287648428 #define VP9D_MPP_REF_SCALE_ENBL 13377 #define DI_CHAN2_CANVAS0 6134 #define SRSHARP0_PK_DRT_SAD_MISC 12840 #define P_VPP_HSC_REGION1_PHASE_SLOPE 4287657044 #define P_DI_IF2_FMT_CTRL 4287660156 #define P_ISA_CNTL_REG0 4291883044 #define DI_MEM_LUMA_Y0 6110 #define P_VPU_PROT2_MMC_CTRL 4287667364 #define P_VDEC2_REC_CANVAS_ADDR 4284655304 #define VDIN_INTF_WIDTHM1 4636 #define P_SLICE_QP 4284624936 #define REG_DEMO_CENTER_BAR 49 #define P_ENCL_VIDEO_EN 4287656576 #define DI_MEM_LUMA_X0 6109 #define P_VD1_IF0_LUMA_FIFO_SIZE 4287654284 #define P_VPU_ASYNC_RD_MODE0 4287667860 #define P_VPP_INPUT_CTRL 4287657644 #define P_VPU_ASYNC_RD_MODE1 4287667864 #define P_VPU_ASYNC_RD_MODE2 4287667868 #define HCODEC_MDEC_PIC_DC_THRESH 6584 #define P_VPU_ASYNC_RD_MODE3 4287667872 #define HEVC_POWER_CTL_IQIDCT 15880 #define P_VPU_ASYNC_RD_MODE4 4287667876 #define P_PK_OS_VERT_CORE_GAIN 4287678608 #define P_HEVC_CDB_ADDR_REG 4284665068 #define RESET1_REGISTER 1026 #define HEVC_ASSIST_MBOX2_CLR_REG 12409 #define P_AIU_MEM_I2S_LEVEL 4291842516 #define VDEC2_HDEC_MC_OMEM_AUTO 10544 #define SRSHARP1_PK_NR_ENABLE 13351 #define AUDIN_SPDIF_CHNL_STS_B 13315 #define AUDIN_SPDIF_CHNL_STS_A 13314 #define P_HEVC_MDEC_SW_RESET 4284671504 #define RDMA_AHB_START_ADDR_2 4356 #define RDMA_AHB_START_ADDR_3 4358 #define RDMA_AHB_START_ADDR_1 4354 #define SRSHARP0_PK_CON_2CIRHPGAIN_TH_RATE 12805 #define RDMA_AHB_START_ADDR_6 4364 #define RDMA_AHB_START_ADDR_7 4366 #define RDMA_AHB_START_ADDR_4 4360 #define RDMA_AHB_START_ADDR_5 4362 #define VDEC2_DBLK_RV8_QUANT 10614 #define HCODEC_QDCT_JPEG_QUANT_DATA 7977 #define SRSHARP0_HCTI_CON_2_GAIN_0 12849 #define SRSHARP0_HCTI_CON_2_GAIN_1 12850 #define MIPI_DSI_DWC_PHY_TMR_CFG_OS 7207 #define PARSER_AUDIO_HOLE 14473 #define HEVC_MCRCC_CTL3 14722 #define HEVC_MCRCC_CTL2 14721 #define HEVC_MCRCC_CTL1 14720 #define P_HEVC_MDEC_EXTIF_CFG0 4284671888 #define P_HEVC_MDEC_EXTIF_CFG1 4284671892 #define VLD_MEM_VIFIFO_CURR_PTR 3137 #define P_AIU_MEM_AIFIFO2_CONTROL 4291842488 #define OEH_HE_ADDR 5273 #define P_VPU_VLOCK_OUTPUT0_CAPT_LMT 4287676452 #define DOS_APB_ERR_STAT 16132 #define STREAM_DATA_IN_CONFIG 11269 #define P_VPP_OSD_HSC_PHASE_STEP 4287657740 #define SRSHARP0_NR_GAUSSIAN_MODE 12802 #define ENCT_VIDEO_HOFFST 7295 #define TCON_PATTERN_HI 5322 #define HEVC_MPRED_ABV_WPTR 12826 #define GE2D_SRC1_KEY_MASK 207 #define P_EE_ASSIST_MBOX1_CLR_REG 4291854804 #define PMV3_Y 3109 #define P_HEVC_CINDEX4_REG 4284665016 #define VPP2_VADJ1_Y 6465 #define PMV3_X 3108 #define P_VPP2_MISC 4287658136 #define P_NR_ALP0Y_ERR2CURV_LIMIT 4287678552 #define VPP_WRAP_OSD1_MATRIX_OFFSET2 15722 #define MIPI_DSI_DWC_HS_WR_TO_CNT_OS 7201 #define HCODEC_VLC_HUFFMAN_ADDR 7514 #define P_MCDI_MOTION_PARADOX_RT 4287675724 #define HEVC_SAO_VB_WPTR 13846 #define VPU_VLOCK_STBDET_CLP 12312 #define P_HEVC_SAO_VB_RD_START_ADDR 4284667980 #define VDIN1_DNLP_HIST06 5181 #define VDIN1_DNLP_HIST07 5182 #define VDIN1_DNLP_HIST08 5183 #define VDIN1_DNLP_HIST09 5184 #define VDIN1_DNLP_HIST02 5177 #define VDIN1_DNLP_HIST03 5178 #define VDIN1_DNLP_HIST04 5179 #define VDIN1_DNLP_HIST05 5180 #define P_WM_FREQ_DIST_TOP 4287678168 #define AIU_MEM_IEC958_CONTROL 5225 #define P_HEVCD_IPP_LINEBUFF_BASE 4284665892 #define P_VDEC2_VLD_MEM_VIFIFO_MEM_CTL 4284657992 #define VDIN1_DNLP_HIST00 5175 #define VDIN1_DNLP_HIST01 5176 #define P_HEVCD_IPP_INTR_MASK 4284665896 #define SRSHARP0_DB_FLT_SEED_V 12925 #define L_STH1_HE_ADDR 5137 #define SRSHARP0_DB_FLT_SEED_Y 12923 #define VDEC2_CINDEX3_REG 9005 #define SRSHARP0_DB_FLT_SEED_U 12924 #define P_HCODEC_V5_MB_DIFF_SUM 4284644848 #define ENCI_VIDEO_MODE_ADV 6913 #define ENCI_VBI_TTXDT0 6956 #define ENCI_VBI_TTXDT1 6957 #define HEVC_CBREAK2_REG 13110 #define VD1_IF0_CANVAS0 6737 #define VD1_IF0_CANVAS1 6738 #define PFIFO_DATA 14440 #define P_NR4_RO_NR4_DBGPIX_NUM 4287683728 #define ENCI_VBI_TTXDT2 6958 #define ENCI_VBI_TTXDT3 6959 #define HEVC_ANC20_CANVAS_ADDR 14756 #define VDIN1_CHROMA_DATA_PORT 5164 #define VDIN1_DNLP_HIST31 5206 #define VDIN1_DNLP_HIST32 5234 #define VDIN1_DNLP_HIST30 5205 #define VIU2_OSD2_COLOR 7730 #define VIU2_VD1_IF0_GEN_REG 7760 #define P_HCODEC_MPSR 4284632068 #define P_HCODEC_MC_HALF_PEL_TWO 4284638224 #define VDIN1_DNLP_HIST17 5192 #define VDIN1_DNLP_HIST18 5193 #define VDIN1_DNLP_HIST19 5194 #define VDIN1_DNLP_HIST13 5188 #define VDIN1_DNLP_HIST14 5189 #define VDIN1_DNLP_HIST15 5190 #define VDIN1_DNLP_HIST16 5191 #define P_HCODEC_MBREAK2_REG 4284632152 #define VDIN1_DNLP_HIST10 5185 #define VDIN1_DNLP_HIST11 5186 #define VDIN1_DNLP_HIST12 5187 #define P_VDEC2_BLOCK_NUM 4284657832 #define VDIN1_DNLP_HIST28 5203 #define VDIN1_DNLP_HIST29 5204 #define VDIN1_DNLP_HIST24 5199 #define VDIN1_DNLP_HIST25 5200 #define VDIN1_DNLP_HIST26 5201 #define VDIN1_DNLP_HIST27 5202 #define P_VIU_OSD1_MATRIX_COEF40_41 4287654524 #define VDEC2_DBLK_STATUS 10579 #define P_AUDOUT_BUF0_EDA 4291875340 #define VDIN1_DNLP_HIST20 5195 #define VDIN1_DNLP_HIST21 5196 #define VDIN1_DNLP_HIST22 5197 #define VDIN1_DNLP_HIST23 5198 #define AIU_I2S_MED_CTRL 5134 #define P_VDEC2_VC1_CONTROL_REG 4284657784 #define P_ENCP_VBI_DATA0 4287655764 #define P_ENCP_VBI_DATA1 4287655768 #define P_VD2_IF0_RANGE_MAP_CR 4287654448 #define P_VDEC_ASSIST_MBOX1_MASK 4284613080 #define P_VLC_HCMD_T_L_INFO 4284642444 #define P_VD2_IF0_RANGE_MAP_CB 4287654444 #define P_TS_PL_PID_INDEX 4291847116 #define P_NR4_MCNR_RO_GRDU_SUM 4287674320 #define P_VP9_DECODING_INFO 4284663100 #define HEVC_ANC15_CANVAS_ADDR 14751 #define ODD_EVEN_SWP 2 #define VPU_VLOCK_MISC_CTRL 12289 #define HCODEC_ME_MV_MERGE_CTL 8021 #define HEVC_MC_OTHER_GCLK_CTRL 14670 #define VPP2_PREBLEND_VD1_H_START_END 6426 #define P_SDRAM_CTL8 4291883384 #define P_SDRAM_CTL6 4291883376 #define P_SDRAM_CTL7 4291883380 #define PCMIN_CTRL1 13409 #define PCMIN_CTRL2 13410 #define PCMIN_CTRL0 13408 #define HEVC_DBLK_CR_FILT 14688 #define P_SDRAM_CTL0 4291883356 #define P_SDRAM_CTL4 4291883368 #define P_SDRAM_CTL5 4291883372 #define P_SDRAM_CTL2 4291883360 #define MBREAK0_REG 788 #define P_TCON_MISC_SEL_ADDR 4287648516 #define NR4_DRT_ALP_MINMAX 11688 #define P_L_GAMMA_VCOM_HSWITCH_ADDR 4287647756 #define MIPI_DSI_TOP_SUSPEND_LINE 7412 #define P_VPP2_HSC_PHASE_CTRL 4287652960 #define P_PARSER_SUB_END_PTR 4291879468 #define P_HCODEC_VIFF_BIT_CNT 4284641384 #define INTRA_QUANT_MATRIX 3586 #define ENCT_SYNC_TO_PIXEL 7243 #define MC_HCMDBUF_H 2376 #define MC_HCMDBUF_L 2377 #define P_ENCI_DVI_VSO_BEGIN_ODD 4287655964 #define P_ENCL_VIDEO_FILT_CTRL 4287656712 #define HEVC_CM_COLOR 13866 #define MCDI_HOR_SADOFST 12054 #define P_ASSIST_GEN_CNTL 4291854752 #define ENCL_MAX_LINE_SWITCH_POINT 7368 #define VD2_AFBC_STAT 12682 #define VPP_HSHARP_CHROMA_GAIN 7510 #define P_HCODEC_ASSIST_DMA_INT 4284629392 #define P_VDEC2_NEXT_ALIGN_PEAK 4284657780 #define P_VDIN_LDIM_STTS_HIST_READ_REGION 4287646052 #define P_VPU_VLOCK_MX4096 4287676504 #define P_HCODEC_QDCT_DBG_READ 4284644496 #define TCON_PATTERN_LO 5323 #define HCODEC_MC_MPORT_DAT 6465 #define P_HCODEC_DC_AC_SCALE_MUL 4284643352 #define DNR_DB_HBS 11534 #define DE_HS_ADDR 5329 #define P_VPU_PROT2_RBUF_ROOM 4287667616 #define P_HEVC_CPSR 4284664964 #define P_VDIN_HSC_INI_CTRL 4287645748 #define HCODEC_MFDIN_REGC_MBLP 4116 #define P_VDEC2_DBLK_BETAX_QP_SEL 4284654980 #define SMARTCARD_FIFO 37895 #define VPP2_SCALE_COEF_IDX 6403 #define HCODEC_ANC10_CANVAS_ADDR 6554 #define VENC_VDAC_DAC5_OFFSET 7163 #define P_ANC6_CANVAS_ADDR 4284622424 #define P_VIU2_OSD2_TEST_RDDATA 4287658288 #define HCODEC_DBLK_CTRL 6481 #define GAMMA_VCOM_POL 7 #define P_NR3_SUREMOT_CGAIN 4287676376 #define VIU2_VD1_IF0_RANGE_MAP_Y 7786 #define VDEC2_IMEM_DMA_ADR 9025 #define ENCI_DBG_PX_INT 6986 #define P_HCODEC_VLC_DBG_IDX 4284642648 #define P_ENCP_VIDEO_HAVON_BEGIN 4287655568 #define P_LDIM_STTS_MATRIX_COEF20_21 4287654680 #define P_D2D3_DBLD_STATUS 4287671540 #define P_ENCP_VIDEO_OFLD_VOAV_OFST 4287655656 #define P_ENCI_TST_Y 4287656008 #define VDEC_ASSIST_MBX_SSEL 69 #define SRSHARP0_PK_CON_2CIRBPGAIN_TH_RATE 12807 #define P_VLC_VB_LEFT 4284642388 #define SRSHARP0_NR_ALP0C_ERR2CURV_TH_RATE 12823 #define P_OEH_VE_ADDR 4287648364 #define SPI_FLASH_ADDR_START 0 #define P_MCDI_MC_COL_CFD_0 4287675872 #define P_MCDI_MC_COL_CFD_4 4287675888 #define P_MCDI_MC_COL_CFD_3 4287675884 #define P_MCDI_MC_COL_CFD_2 4287675880 #define P_MCDI_MC_COL_CFD_1 4287675876 #define P_MCDI_MC_LPF_MSK_0 4287675844 #define P_MCDI_MC_LPF_MSK_2 4287675852 #define P_MCDI_MC_LPF_MSK_1 4287675848 #define P_MCDI_MC_LPF_MSK_4 4287675860 #define P_MCDI_MC_LPF_MSK_3 4287675856 #define P_MCDI_MC_COL_CFD_8 4287675904 #define P_MCDI_MC_COL_CFD_7 4287675900 #define P_MCDI_MC_COL_CFD_6 4287675896 #define P_MCDI_MC_COL_CFD_5 4287675892 #define P_MCDI_MC_COL_CFD_9 4287675908 #define SRSHARP0_VLTI_BST_CORE 12860 #define MAC_CTRL2 880 #define MAC_CTRL1 864 #define VDIN_DNLP_HIST31 4694 #define OSDSR_UK_BST_GAIN 12607 #define VDIN_DNLP_HIST30 4693 #define VDIN_DNLP_HIST32 4722 #define HCODEC_VLC_VB_INT_PTR 7448 #define VDIN_DNLP_HIST20 4683 #define P_GAMMA_PROBE_POS_Y 4287648312 #define VDIN_DNLP_HIST22 4685 #define VDIN_DNLP_HIST21 4684 #define VDIN_DNLP_HIST24 4687 #define mLVDS2_reset_length 23 #define VDIN_DNLP_HIST23 4686 #define P_GAMMA_PROBE_POS_X 4287648308 #define VDIN_DNLP_HIST26 4689 #define VDIN_DNLP_HIST25 4688 #define HEVC_VLD_DBG_INDEX 15422 #define VDIN_DNLP_HIST28 4691 #define VDIN_DNLP_HIST27 4690 #define VDIN_DNLP_HIST29 4692 #define VDIN_DNLP_HIST11 4674 #define P_NR4_BLDVS3_SUM 4287683736 #define VDIN_DNLP_HIST10 4673 #define VDIN_DNLP_HIST13 4676 #define VDIN_DNLP_HIST12 4675 #define VDIN_DNLP_HIST15 4678 #define VDIN_DNLP_HIST14 4677 #define GE2D_DST_CLIPX_START_END 180 #define P_DET3D_RO_MAT_CHRV_TB 4287651360 #define VDIN_DNLP_HIST17 4680 #define VDIN_DNLP_HIST16 4679 #define VDIN_DNLP_HIST19 4682 #define P_HCODEC_CMAX_REG 4284632268 #define VDIN_DNLP_HIST18 4681 #define PMV4_X 3110 #define VDIN_DNLP_HIST00 4663 #define VDEC2_CBREAK3_REG 9015 #define PMV4_Y 3111 #define VDIN_DNLP_HIST02 4665 #define VDIN_DNLP_HIST01 4664 #define VDIN_DNLP_HIST04 4667 #define VDIN_DNLP_HIST03 4666 #define P_VPP2_SMOKE1_V_START_END 4287653048 #define PSCALE_FILT0_COEF1 2330 #define VDIN_DNLP_HIST06 4669 #define PSCALE_FILT0_COEF0 2329 #define VDIN_DNLP_HIST05 4668 #define VDIN_DNLP_HIST08 4671 #define VDIN_DNLP_HIST07 4670 #define P_PFIFO_WR_PTR 4291879320 #define VDIN_DNLP_HIST09 4672 #define DBLK_CBPC_ADJ 2419 #define VDIN_VSC_INI_CTRL 4644 #define P_ASSIST_SPARE8_REG3 4291854696 #define P_ASSIST_SPARE8_REG1 4291854688 #define P_ASSIST_SPARE8_REG2 4291854692 #define AUDOUT_BUF0_EDA 13443 #define HEVC_POWER_CTL_MC 14597 #define PSCALE_CTRL1 2345 #define PSCALE_CTRL2 2350 #define P_DNR_HBOFFST_STAT 4287673364 #define SECOND_DEMUX_OFFSET_0 80 #define P_VIU_OSD1_MATRIX_PROBE_COLOR 4287654504 #define P_VPP2_SCALE_COEF_IDX 4287652876 #define HCODEC_IQIDCT_CONTROL 7694 #define P_MLVDS_RESET_PATTERN_HI 4287648528 #define P_VPU_VENCL_DITH_CTRL 4287668096 #define P_VIU_OSD2_COLOR 4287654088 #define P_DI_EI_DRT_PIX_DIFFTH 4287651312 #define P_VLC_HCMD_CUR_INFO 4284642448 #define P_ENCI_MACV_N1 4287655108 #define P_ENCI_MACV_N2 4287655112 #define P_ENCI_MACV_N0 4287655104 #define P_MCDI_RO_FLD_BAD_SAD_CNT 4287676044 #define HEVC_SHIFT_CONTROL 12552 #define P_HCODEC_VLC_INPUT_STATUS 4284642512 #define GE2D_ALU_CONST_COLOR 205 #define HCODEC_VIFF_BIT_CNT 7194 #define P_DNR_DM_SDIF_LUT6_8 4287673788 #define P_ENCI_MACV_N9 4287655140 #define P_ENCI_MACV_N7 4287655132 #define P_ENCI_MACV_N8 4287655136 #define P_ENCI_MACV_N5 4287655124 #define P_ENCI_MACV_N6 4287655128 #define P_ENCI_MACV_N3 4287655116 #define P_ENCI_MACV_N4 4287655120 #define P_SPICC0_TXDATA 4291899396 #define P_HCODEC_MDB_DATA_REG 4284632176 #define L_OEH_HS_ADDR 5144 #define P_VBO_GCLK_MAIN 4287648200 #define P_IMEM_DMA_ADR 4284615940 #define VDIN_WR_CTRL 4640 #define P_DI_IF2_CANVAS0 4287660100 #define VPP2_HSC_PHASE_CTRL 6424 #define HEVC_SAO_MMU_VH0_ADDR 13882 #define P_VPU_OSD1_MMC_CTRL 4287667204 #define MCDI_PD_22_CHK_FRC_LMV 12125 #define PWM_MISC_REG_AB 27650 #define V5_MB_DIFF_SUM 8060 #define P_HEVC_SAO_AXI_RCTRL 4284667944 #define P_HEVC_ANC1_CANVAS_ADDR 4284671556 #define P_ADAPTIVE_SCALE_REG3 4287677772 #define SRSHARP0_CTI_DIR_ALPHA 12843 #define P_ADAPTIVE_SCALE_REG4 4287677776 #define P_ADAPTIVE_SCALE_REG1 4287677764 #define P_ADAPTIVE_SCALE_REG2 4287677768 #define P_ENCL_VIDEO_PB_SCL 4287656584 #define P_DET3D_RO_MAT_CHRV_LR 4287651356 #define HEVC_SAO_ABV_START_ADDR 13841 #define P_ADAPTIVE_SCALE_REG0 4287677760 #define P_NR4_MTN_CTRL 4287674068 #define P_GAMMA_PROBE_HL_COLOR 4287648304 #define P_ENCL_VFIFO2VD_CTL2 4287656540 #define PWM_MISC_REG_CD 26626 #define HCODEC_MBBOT_ODD_ADDR 7992 #define SRSHARP1_NR_ALP0Y_ERR2CURV_LIMIT 13334 #define P_NR3_SUREMOT_YGAIN 4287676372 #define P_DOS_MEM_PD_HEVC 4284677324 #define NR2_CFR_PARA_CFG0 6044 #define NR2_CFR_PARA_CFG1 6045 #define P_NR4_SNR_ALPA1_RATE_AND_OFST 4287674044 #define PWM_MISC_REG_EF 25602 #define REC_CANVAS_ADDR 2482 #define DNR_DB_CHDELTA_GAIN 11538 #define P_HEVC_PSCALE_PICI_W 4284671048 #define VPP_OSD_HSC_CTRL0 7621 #define P_HEVC_PSCALE_PICI_H 4284671052 #define P_SANA_SHIFTED_DATA 4291870892 #define HCODEC_VLC_TOTAL_BYTES 7450 #define HCODEC_V3_L1_SKIP_MAX_SAD 8049 #define P_VDEC2_WRRSP_LMEM 4284648780 #define VKS_PARA_DATA_PORT 12559 #define P_DBLK_QP 4284622168 #define UART2_WFIFO 34816 #define P_ENCP_VIDEO_HSPULS_END 4287655524 #define P_V5_SIMPLE_MB_CTL 4284644856 #define NR4_SNR_ALPA1_RATE_AND_OFST 11695 #define P_VPU_PROT2_REQ_ONOFF 4287667632 #define VPU_MISC_CTRL 10048 #define VDIN1_CM_BRI_CON_CTRL 5165 #define ENCP_VIDEO_MAX_LNCNT 7086 #define ENCI_DBG_MAXLN 6989 #define P_AIU_958_PADDSIZE 4291842060 #define P_AUDIN_I2SIN_CTRL 4291874880 #define AUDIN_FIFO0_HOLD_LVL 28 #define P_DI_IF1_CANVAS0 4287651748 #define P_GE2D_SRC1_RANGE_MAP_Y_CTRL 4287890316 #define LVDS_PHY_CLK_CNTL 5359 #define P_ENCP_VIDEO_MACV_SCL 4287655452 #define VPU_PROT1_MMC_CTRL 10024 #define HCODEC_ASSIST_MBOX0_MASK 4210 #define P_HCODEC_ME_DEBUG 4284644656 #define HEVC_VLD_SHIFT_STATUS 15419 #define P_LDIM_STTS_MATRIX_OFFSET0_1 4287654688 #define P_PARSER_INT_ENABLE 4291879340 #define SRSHARP1_SATPRT_DIVM 13429 #define HEVC_ASSIST_GCLK_EN 12291 #define HCODEC_WRRSP_IMEM 4931 #define QDCT_JPEG_SOF_RESUME 7978 #define HEVC_DBLK_CFGB 13579 #define HEVC_DBLK_CFGA 13578 #define NR4_MCNR_ALP1_AND_BET0_REG 11714 #define HEVC_DBLK_CFG8 13576 #define HEVC_DBLK_CFG7 13575 #define HEVC_DBLK_CFG9 13577 #define HEVC_DBLK_CFG4 13572 #define P_DNR_DB_YC_VEDGE_THD 4287673424 #define GE2D_SRC1_CANVAS 169 #define HEVC_DBLK_CFG3 13571 #define HEVC_DBLK_CFG6 13574 #define HEVC_DBLK_CFG5 13573 #define ANC4_CANVAS_ADDR 2452 #define ENCI_DBG_MAXPX 6988 #define ENCT_DACSEL_0 7305 #define ENCT_DACSEL_1 7306 #define VLC_MV_INDEX 7496 #define HEVC_DBLK_CFGC 13580 #define P_HEVC_MINDEX5_REG 4284664892 #define P_HCODEC_ASSIST_MBOX2_FIQ_SEL 4284629484 #define P_SANA_SHIFT_BYTE_COUNT 4291870896 #define P_VPP2_OSD_SC_DUMMY_DATA 4287653660 #define P_RDMA_AHB_START_ADDR_MAN 4287644672 #define HEVC_DBLK_CFG0 13568 #define HEVC_DBLK_CFG2 13570 #define HEVC_DBLK_CFG1 13569 #define P_HCODEC_MINDEX2_REG 4284632112 #define DI_MTNRD_CTRL 6093 #define P_VIU_OSD1_COLOR_ADDR 4287653956 #define AIU_958_FFRDOUT_THD 5154 #define VIU_OSD1_MATRIX_PROBE_COLOR 6810 #define P_VLD_DC_PRED 4284625076 #define SHARP_SR3_SAD_CTRL 12897 #define ENCT_DBG_LN_INT 7276 #define HEVC_MPRED_AXI_RCTRL 12817 #define P_HEVC_PARSER_DEBUG_IDX 4284663032 #define DECOMB_PARA 11652 #define VCTI_CON_2_GAIN_0 12866 #define P_VPP_SRSCL_GCLK_CTRL 4287657436 #define P_WRRSP_PARSER 4291879496 #define SRSHARP0_SR3_DERING_LUMA2PKGAIN_0TO3 12908 #define VCTI_CON_2_GAIN_1 12867 #define P_MLVDS_RESET_PATTERN_LO 4287648532 #define MCPU_INTR_GRP 771 #define VDEC2_ANC20_CANVAS_ADDR 10660 #define STREAM_OUTPUT_CONFIG 11265 #define P_RESET0_LEVEL 4291825792 #define P_AO_CPU_IRQ_IN0_INTR_STAT_CLR 4291883076 #define P_MBREAK3_REG 4284615772 #define P_LVDS_CLKB_CLKA 4287648696 #define MIPI_DSI_TOP_SUSPEND_CNTL 7411 #define DI_IF1_GEN_REG3 8359 #define DI_IF1_GEN_REG2 6032 #define P_L_GAMMA_DATA_PORT 4287647748 #define P_VDEC2_VLD_MEM_VIFIFO_LEVEL 4284657948 #define P_HCTI_FLT_CLP_DC 4287678648 #define P_QDCT_JPEG_X_START_END 4284644504 #define P_HCODEC_V3_F_ZERO_CTL_1 4284644820 #define P_HCODEC_V3_F_ZERO_CTL_0 4284644816 #define HCODEC_SLICE_QP 7178 #define P_VPU_VDIN0_MMC_CTRL 4287667252 #define P_HEVC_POWER_CTL_VLD 4284674080 #define P_PCMOUT_CTRL0 4291875264 #define WFIFO_PointerWidth 3 #define P_ME_SUB_FIX_MIN_SAD 4284644724 #define MIPI_DSI_DWC_INT_ST1_OS 7216 #define P_PCMOUT_CTRL2 4291875272 #define P_PCMOUT_CTRL1 4291875268 #define P_VBO_INFILTER_CTRL 4287648740 #define VPU_PROT2_RPT_LOOP 10085 #define HEVC_PIC_HEAD_INFO 15363 #define SAT_BYYB_NODE_REG1 513 #define SAT_BYYB_NODE_REG2 514 #define SAT_BYYB_NODE_REG0 512 #define P_PCMOUT_CTRL4 4291875280 #define P_PCMOUT_CTRL3 4291875276 #define HCODEC_DBLK_OST_YBASE 6525 #define HEVCD_MPP_VDEC_MCR_CTL 13512 #define ENCT_VIDEO_OFLD_VOAV_OFST 7300 #define P_VPP2_POSTBLEND_VD1_H_START_END 4287652976 #define FRM_SIZE_REG 517 #define D2D3_DPG_INPIC_SIZE 11009 #define VPP2_CHROMA_DATA_PORT 6513 #define P_VLD_MEM_VIFIFO_START_PTR 4284625152 #define P_HCODEC_ASSIST_MBOX2_IRQ_REG 4284629472 #define HCODEC_LMEM_DMA_COUNT 4946 #define ABUF_RD_INT_EN 31 #define P_QDCT_MB_START_PTR 4284644416 #define HCODEC_PSCALE_RST 6416 #define ABUF_WR_CUR_BLK_MSB 14 #define ENCP_VIDEO_Y_SCL 7043 #define UART1_MISC 35844 #define DET3D_RO_MAT_CHRV_TB 6024 #define HCODEC_V3_TOP_MV 8046 #define VDIN0_DNLP_HIST31 4694 #define VDIN0_DNLP_HIST30 4693 #define VDIN0_DNLP_HIST32 4722 #define IE_DATA_FEED_BUFF_INFO 6872 #define ENCP_DVI_VSO_BLINE_ODD 7219 #define P_ENCT_VIDEO_YC_DLY 4287656380 #define P_HCODEC_WRRSP_DCAC 4284639076 #define mLVDS2_msb_first 4 #define ACC1REG2 882 #define ACC1REG1 866 #define VDIN0_DNLP_HIST15 4678 #define VDIN0_DNLP_HIST14 4677 #define VDIN0_DNLP_HIST17 4680 #define VDIN0_DNLP_HIST16 4679 #define VDIN0_DNLP_HIST19 4682 #define P_NR4_MCNR_LUMAPRE_CAL_PRAM 4287674096 #define VDIN0_DNLP_HIST18 4681 #define P_ENCP_MACV_TIME_RST 4287655736 #define VDEC2_CMIN_REG 9010 #define QDCT_JPEG_QUANT_DATA 7977 #define VDEC2_ANC16_CANVAS_ADDR 10656 #define VD2_IF0_CHROMA0_RPT_PAT 6781 #define VDIN0_DNLP_HIST11 4674 #define VDIN0_DNLP_HIST10 4673 #define XVYCC_USCP_REG 541 #define VDIN0_DNLP_HIST13 4676 #define VDIN0_DNLP_HIST12 4675 #define VDIN0_DNLP_HIST26 4689 #define SPI_CLKCNT_H 4 #define VDIN0_DNLP_HIST25 4688 #define AUDIN_ATV_DEMOD_CTRL 13520 #define VDIN0_DNLP_HIST28 4691 #define VDIN0_DNLP_HIST27 4690 #define VDIN0_DNLP_HIST29 4692 #define P_HCODEC_PIC_HEAD_INFO 4284641292 #define P_VDEC2_ANC30_CANVAS_ADDR 4284655288 #define SPI_CLKCNT_N 8 #define SPI_CLKCNT_L 0 #define VDIN0_DNLP_HIST20 4683 #define P_VPP_VSC_START_PHASE_STEP 4287656992 #define VDIN0_DNLP_HIST22 4685 #define VDIN0_DNLP_HIST21 4684 #define VDIN0_DNLP_HIST24 4687 #define VDIN0_DNLP_HIST23 4686 #define NR2_MATNR_SNR_NRM_GAIN 5972 #define SRSHARP1_SR3_SAD_CTRL 13409 #define P_HEVC_MPRED_AXI_RCTRL 4284663876 #define P_NR4_MCNR_CM_PRAM 4287674136 #define P_HEVC_MPRED_ABV_WPTR 4284663912 #define P_VPU_RDARB_WEIGH0_SLV_L2C1 4287667836 #define P_HCODEC_ASSIST_MBOX2_MASK 4284629480 #define P_VD2_AFBC_SIZE_IN 4287677960 #define P_VPP_SMOKE1_H_START_END 4287657140 #define SHARP_HVBLANK_NUM 12801 #define ENCL_VIDEO_OFLD_VOAV_OFST 7364 #define P_DI_IF2_URGENT_CTRL 4287660164 #define VD2_IF0_PROT_CNTL 6798 #define DNR_HBOFFST_STAT 11525 #define HCODEC_CCPU_INTR_GRP 4899 #define P_HEVC_MPRED_L0_REF00_POC 4284663936 #define VDIN_LFIFO_URG_CTRL 4638 #define P_VD2_AFBC_BODY_BADDR 4287677980 #define P_HCODEC_MINDEX1_REG 4284632108 #define P_HCODEC_QDCT_DBG_IDX 4284644492 #define NR2_SNR_MASK 5981 #define DET3D_RO_MAT_LUMA_LR 6019 #define MIPI_DSI_DWC_PHY_STATUS_OS 7212 #define L_HSYNC_HE_ADDR 5206 #define P_VD2_IF0_LUMA_Y1 4287654368 #define P_VDEC2_MINDEX2_REG 4284648496 #define VKS_PRELPF_CCOEF1 12549 #define VKS_PRELPF_CCOEF0 12548 #define VIU_OSD1_MATRIX_COEF20_21 6804 #define P_ENCT_TST_MDSEL 4287656100 #define P_ENCP_DVI_VSO_END_EVN 4287656160 #define P_VD2_IF0_LUMA_X1 4287654364 #define P_VD2_IF0_LUMA_X0 4287654348 #define P_ENCT_VIDEO_HAVON_END 4287656388 #define DBLK_MB_WID_HEIGHT 2386 #define SPDIF_INT_EN 30 #define P_VD2_IF0_LUMA_Y0 4287654352 #define P_VI_HIST_CHROMA_SUM 4287674392 #define VDIN1_COM_CTRL0 5122 #define VIU_OSD2_CTRL_STAT 6704 #define ENCL_VIDEO_MATRIX_CB 7365 #define HEVC_MBREAK_TYPE 13080 #define ENCL_VIDEO_MATRIX_CR 7366 #define VDEC2_LAST_MVY 11314 #define VDEC2_LAST_MVX 11313 #define tcon_delay 0 #define HEVCD_MPP_WEIGHT_ADDR 13440 #define P_SHARP_SR2_CTRL 4287678812 #define NR4_RO_NM_VAR_MIN_MAX 14115 #define P_AIU_MIX_GAIN 4291842156 #define L_STH1_VE_ADDR 5139 #define VPP2_SCO_FIFO_CTRL 6451 #define HEVC_ANC18_CANVAS_ADDR 14754 #define WM_THRES_ADDR_PORT 12747 #define V5_SIMPLE_MB_CTL 8062 #define HCODEC_QDCT_TOP_CONTROL 7967 #define P_HEVC_IQIT_CLK_RST_CTRL 4284668928 #define P_PARSER_ES_CONTROL 4291879388 #define HEVC_HDEC_MC_OMEM_AUTO 14640 #define P_VPU_PROT3_Y_START_END 4287667660 #define DET3D_RO_MAT_LUMA_TB 6020 #define P_CBREAK2_REG 4284615896 #define VENC_VDAC_DAC0_OFFSET 7153 #define AIU_DELTA_SIGMA3 5208 #define P_VIU2_OSD2_BLK0_CFG_W2 4287658228 #define MCDI_REL_DIF_THD_34 12064 #define AIU_DELTA_SIGMA2 5207 #define P_VIU2_OSD2_BLK0_CFG_W1 4287658224 #define AIU_DELTA_SIGMA1 5206 #define P_VIU2_OSD2_BLK0_CFG_W4 4287658384 #define AIU_DELTA_SIGMA0 5205 #define P_VIU2_OSD2_BLK0_CFG_W3 4287658232 #define AIU_DELTA_SIGMA7 5212 #define AIU_DELTA_SIGMA6 5211 #define AIU_DELTA_SIGMA5 5210 #define P_VIU2_OSD2_BLK0_CFG_W0 4287658220 #define AIU_DELTA_SIGMA4 5209 #define P_HEVC_VLD_DBG_DATA 4284674300 #define D2D3_MBDG_STATUS_1 11057 #define D2D3_MBDG_STATUS_3 11059 #define D2D3_MBDG_STATUS_2 11058 #define ANC24_CANVAS_ADDR 2472 #define MCDI_REL_DIF_THD_02 12063 #define D2D3_MBDG_STATUS_5 11061 #define D2D3_MBDG_STATUS_4 11060 #define MBREAK1_REG 789 #define D2D3_MBDG_STATUS_7 11063 #define P_AIU_MEM_AIFIFO_CURR_PTR 4291842580 #define D2D3_MBDG_STATUS_6 11062 #define VC1_CONTROL_REG 3102 #define HCODEC_QDCT_JPEG_SOF_RESUME 7978 #define P_AIFIFO_TIME_STAMP_LENGTH 4291842652 #define XVYCC_VD1_RGB_DLUT_0_3 12658 #define P_VDEC2_AVSP_IQ_CTL 4284659824 #define ENCP_INFO_READ 10013 #define P_HCODEC_M4_TABLE_SELECT 4284641440 #define VIU_OSD1_CTRL_STAT2 6701 #define VDIN0_DNLP_HIST04 4667 #define VDIN0_DNLP_HIST03 4666 #define VDIN0_DNLP_HIST06 4669 #define VDIN0_DNLP_HIST05 4668 #define VDIN0_DNLP_HIST08 4671 #define VDIN0_DNLP_HIST07 4670 #define VDIN0_DNLP_HIST09 4672 #define PMV1_Y 3105 #define PMV1_X 3104 #define VDEC2_MC_IDCT_DAT 10572 #define VDIN1_WR_CTRL2 5151 #define VPP_OUT_H_V_SIZE 7589 #define P_VENC_VIDEO_TST_EN 4287655360 #define P_AO_CPU_IRQ_IN0_INTR_FIRQ_SEL 4291883084 #define VDIN0_DNLP_HIST00 4663 #define VDIN0_DNLP_HIST02 4665 #define VDIN0_DNLP_HIST01 4664 #define P_VENC_VIDEO_TST_CR 4287655376 #define P_XVYCC_VADJ2_CURV_2 4287677872 #define P_XVYCC_VADJ2_CURV_3 4287677876 #define P_XVYCC_VADJ2_CURV_0 4287677864 #define P_XVYCC_VADJ2_CURV_1 4287677868 #define VD2_AFBC_PIXEL_VER_SCOPE 12688 #define P_ANC3_CANVAS_ADDR 4284622412 #define P_VENC_VIDEO_TST_CB 4287655372 #define VD2_IF0_CANVAS1 6770 #define VD2_IF0_CANVAS0 6769 #define NR2_POLAR3_MODE 11672 #define P_SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 4287678900 #define DET3D_RO_MAT_CHRV_LR 6023 #define P_DOLBY_TV_STATUS0 4287680504 #define P_DOLBY_TV_STATUS1 4287680508 #define VPP_WRAP_OSD2_MATRIX_COEF13_14 15733 #define AIU_AIFIFO2_CLB 5187 #define HEVC_DBLK_Y_HFILT_HIGH 14685 #define P_ENCT_VIDEO_VAVON_BLINE 4287656400 #define P_HEVC_AV_SCRATCH_E 4284671800 #define P_HEVC_AV_SCRATCH_F 4284671804 #define P_HEVC_AV_SCRATCH_G 4284671808 #define P_HEVC_AV_SCRATCH_H 4284671812 #define P_HEVC_AV_SCRATCH_I 4284671816 #define P_HEVC_AV_SCRATCH_J 4284671820 #define P_HEVC_AV_SCRATCH_K 4284671824 #define P_HEVC_AV_SCRATCH_L 4284671828 #define VPU_PROT1_CLK_GATE 10064 #define P_HEVC_AV_SCRATCH_A 4284671784 #define P_HEVC_AV_SCRATCH_B 4284671788 #define P_HEVC_AV_SCRATCH_C 4284671792 #define P_HEVC_AV_SCRATCH_D 4284671796 #define P_HEVC_AV_SCRATCH_5 4284671764 #define P_HEVC_AV_SCRATCH_6 4284671768 #define P_HEVC_AV_SCRATCH_7 4284671772 #define P_HEVC_AV_SCRATCH_8 4284671776 #define P_HEVC_AV_SCRATCH_9 4284671780 #define P_HEVC_AV_SCRATCH_0 4284671744 #define P_HEVC_AV_SCRATCH_1 4284671748 #define P_HEVC_AV_SCRATCH_2 4284671752 #define P_HEVC_AV_SCRATCH_3 4284671756 #define P_HEVC_AV_SCRATCH_4 4284671760 #define P_HEVC_SCD_FOR_MV_Y 4284674124 #define P_HEVC_SCD_FOR_MV_X 4284674120 #define P_EE_ASSIST_MBOX2_CLR_REG 4291854820 #define P_HEVC_AV_SCRATCH_M 4284671832 #define P_HEVC_AV_SCRATCH_N 4284671836 #define P_HCODEC_V4_FORCE_SKIP_CFG 4284644844 #define P_VENC_DVI_SETTING 4287655304 #define P_VENC_VDAC_TST_VAL 4287655420 #define P_HEVC_DECODER_BUFFER_INFO 4284674108 #define P_VLC_ENC_MV_BITS 4284642672 #define P_HEVC_IQIT_AVS2_QP_DELTA 4284668988 #define AIU_MEM_AIFIFO2_BUF_CNTL 5234 #define HEVC_SAO_C_WPTR 13840 #define DI_MEM_FMT_CTRL 6118 #define VPP_POST2_MATRIX_COEF13_14 14757 #define P_MC_DP_MB_XY 4284621880 #define P_CINDEX2_REG 4284615856 #define P_HEVC_DEBLK_CMD 4284676160 #define P_VPP2_VSC_REGION12_STARTP 4287652884 #define HCODEC_DBLK_CLIP_CTRL4 6502 #define ENCL_DBG_PX_INT 7339 #define P_SANA_SHIFT_COMMAND 4291870900 #define HCODEC_DBLK_CLIP_CTRL3 6501 #define HCODEC_DBLK_CLIP_CTRL2 6500 #define HCODEC_DBLK_CLIP_CTRL1 6499 #define HCODEC_DBLK_CLIP_CTRL0 6498 #define P_ENCL_SYNC_LINE_LENGTH 4287656240 #define P_VDIN_COM_CTRL0 4287645704 #define VPP_FIFO_STATUS 7464 #define P_PARSER_SUB_WP 4291879472 #define P_DBLK_GCLK_OFF 4284622260 #define P_DNR_DM_SDIF_LUT0_2 4287673780 #define HCODEC_DBLK_CLIP_CTRL8 6506 #define HCODEC_DBLK_CLIP_CTRL7 6505 #define HCODEC_DBLK_CLIP_CTRL6 6504 #define HCODEC_DBLK_CLIP_CTRL5 6503 #define VDIN1_MATRIX_COEF02_10 5138 #define AFBC_VD_CFMT_H 6897 #define SHARP_PKOSHT_VSLUMA_LUT_H 12804 #define SHARP_PKOSHT_VSLUMA_LUT_L 12803 #define HEVC_DBLK_QP 14678 #define AFBC_VD_CFMT_W 6892 #define P_MSR_CLK_DUTY 4291919872 #define P_NR4_DRT_CTRL 4287674000 #define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 4291842616 #define P_HEVC_SAO_MMU_STATUS 4284668132 #define P_HCODEC_V3_TOP_MV 4284644792 #define P_MCDI_REL_DET_FRQ_CHK 4287675588 #define mLVDS2_config_reserved 20 #define LAST_SLICE_MV_ADDR 3120 #define PMV2_X 3106 #define HCODEC_VLC_HCMD_CUR_INFO 7460 #define PMV2_Y 3107 #define VD2_AFBC_SIZE_IN 12674 #define P_SPICC1_CONREG 4291907592 #define HCODEC_VLC_ENC_COEFF_BITS 7517 #define P_VDEC2_BYTE_ALIGN_PEAK_LO 4284657776 #define HEVC_MC_MIX_RATIO1 14605 #define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 13406 #define HEVC_MC_MIX_RATIO0 14604 #define P_ENCI_SYNC_LINE_LENGTH 4287656192 #define HCODEC_MFDIN_REG9_ENDN 4113 #define SRSHARP1_SHARP_SR2_CBIC_VCOEF1 13407 #define P_VPU_VIU_ASYNC_MASK 4287667716 #define P_RDMA_CTRL 4287644752 #define CDB_DATA_REG 828 #define VPU_PROT3_GEN_CNTL 10097 #define P_D2D3_DBLD_MG_PARAM 4287671368 #define P_NR2_MATNR_SNR_LPF_CFG 4287651156 #define VDIN1_COM_GCLK_CTRL 5147 #define HCODEC_DC_SCALER 7684 #define P_XVYCC_LUT_CTL 4287677844 #define VDEC2_MDEC_PIC_DC_MUX_CTRL 10637 #define P_HEVC_SAO_VB_WPTR 4284667992 #define P_ENCP_DE_V_BEGIN_EVEN 4287656176 #define P_NR2_EDGE2BETA_LUT1 4287651212 #define VLC_ENC_PEND_CMD 7478 #define P_NR2_EDGE2BETA_LUT2 4287651216 #define P_NR2_EDGE2BETA_LUT3 4287651220 #define VPU_VPUARB2_PRE_ARB_CTRL 10006 #define P_NR2_EDGE2BETA_LUT0 4287651208 #define P_ENCP_VIDEO_VSPULS_BLINE 4287655540 #define P_VPU_RDARB_WEIGH0_SLV_L1C1 4287667784 #define P_VPU_RDARB_WEIGH0_SLV_L1C2 4287667820 #define HEVC_MBREAK_STAUTS 13082 #define NR2_RO_POLAR3_SMOOTHMV 11678 #define HCODEC_IE_ME_MB_INFO 8002 #define P_HEVC_DBLK_Y_BHFILT_HIGH 4284671328 #define P_VDEC2_BYTE_ALIGN_PEAK_HI 4284657772 #define P_VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL 4284657932 #define P_VDEC2_MDEC_DOUBLEW_STATUS 4284655500 #define P_AIFIFO_TIME_STAMP_2 4291842644 #define P_AIFIFO_TIME_STAMP_3 4291842648 #define P_AIFIFO_TIME_STAMP_0 4291842636 #define P_PARSER_SUB_RP 4291879476 #define P_AIFIFO_TIME_STAMP_1 4291842640 #define FRM_DCT 0 #define P_SANA_SHIFT_STARTCODE 4291870880 #define VIU_ADDR_END 6911 #define P_VPP2_MATRIX_HL_COLOR 4287653236 #define P_HCODEC_MC_CTRL1 4284638252 #define P_HCODEC_MC_CTRL0 4284638236 #define HEVC_RESYNC_MARKER_LENGTH 15374 #define P_HCODEC_MC_CTRL2 4284638524 #define VPU_PROT2_REQ_ONOFF 10092 #define ENCP_MACV_BLANKY_VAL 7104 #define P_HCODEC_ANC12_CANVAS_ADDR 4284638832 #define P_NR4_MTN_REF_PAR0 4287674072 #define P_NR4_MTN_REF_PAR1 4287674076 #define HEVC_PATTERN_CODE 15403 #define P_HEVCD_MPP_WEIGHTPRED_CNTL_ADDR 4284666348 #define P_HSYNC_HE_ADDR 4287648600 #define NR4_MTN_REF_PAR1 11703 #define PK_CON_2CIRBPGAIN_LIMIT 12808 #define NR4_MTN_REF_PAR0 11702 #define AIU_I2S_SOURCE_DESC 5133 #define SRSHARP0_PK_ALP2_MIERR_CORING 12830 #define SANA_STREAM_FIFO_CTL 12326 #define VDIN0_MEAS_VS_COUNT_HI 4699 #define IQIDCT_RESET 4 #define P_HCODEC_ME_F_SKIP_WEIGHT 4284644688 #define HCODEC_MPEG1_2_REG 7169 #define LVDS_CLKB_CLKA 5358 #define LDIM_BL_ADDR_PORT 5198 #define P_NR2_MATNR_ALPHAHP_LUT3 4287651288 #define P_NR2_MATNR_ALPHAHP_LUT0 4287651276 #define P_NR4_DBGWIN_YX0 4287683652 #define P_NR2_MATNR_ALPHAHP_LUT1 4287651280 #define P_NR2_MATNR_ALPHAHP_LUT2 4287651284 #define HEVC_MSFTINT0 13086 #define HEVC_MSFTINT1 13087 #define P_NR4_DBGWIN_YX1 4287683656 #define P_HEVC_MINDEX6_REG 4284664896 #define WFIFO_DEPTH 8 #define HCODEC_TOP_LEFT_READY 7506 #define OSD_DB_FLT_RANDLUT 12612 #define HEVC_CM_BODY_LENGTH 13863 #define VLD_REVERVED_19 3097 #define DNR_STAT_Y_START_END 11529 #define P_NR4_MCNR_BLUE_GAIN_PAR0 4287674148 #define XVYCC_POST_RGB_DLUT_8_11 12665 #define P_NR4_MCNR_BLUE_GAIN_PAR1 4287674152 #define P_VPP_HSC_REGION4_PHASE_SLOPE 4287657052 #define VPU_WRARB_REQEN_SLV_L2C1 10147 #define SHARP_SR3_DERING_LUMA2PKOS_0TO3 12910 #define DI_EI_DRT_CTRL 6008 #define HCODEC_MC_MBBOT_WRRSP_CNT 6588 #define P_MPSR 4284615684 #define P_HEVC_DBLK_Y_HFILT 4284671344 #define VDIN0_MEAS_VS_COUNT_LO 4700 #define ANC6_CANVAS_ADDR 2454 #define HCODEC_VLD_MEM_VIFIFO_CURR_PTR 7233 #define P_ENCI_INFO_READ 4287667312 #define MCDI_FIELD_HVF_PRDX_CNT 12129 #define AIU_AIFIFO_STATUS 5249 #define VLC_VB_BUFF 7451 #define GE2D_HSC_START_PHASE_STEP 188 #define P_VPU_D2D3_MMC_CTRL 4287667332 #define HLTI_FLT_CLP_DC 12852 #define L_HSYNC_VS_ADDR 5207 #define HCODEC_QUANT_TABLE_DATA 7993 #define VDEC2_PSCALE_DRAM_BUF_CTRL 10529 #define P_HCODEC_ASSIST_MBOX1_IRQ_REG 4284629456 #define P_HSYNC_HS_ADDR 4287648596 #define P_HCODEC_VLD_MEM_SWAP_ADDR 4284641620 #define P_EE_ASSIST_MBOX3_CLR_REG 4291854836 #define HCODEC_QDCT_MB_WR_PTR 7954 #define WM_SYMBOLS_XPOS 12727 #define VDEC2_MCPU_INTR_REQ 8965 #define P_VCTI_BST_GAIN 4287678720 #define P_RESET1_REGISTER 4291825672 #define WM_FREQ_DIST_TOP 12726 #define P_DI_EI_DRT_RECTG_WAVE 4287651308 #define P_HCODEC_MDEC_PIC_DC_THRESH 4284638944 #define P_ENCT_VIDEO_YFP2_HTIME 4287656376 #define VDEC2_DC_SCALER 11780 #define P_NR2_MATNR_MTN_GAIN 4287651252 #define VD2_IF0_CHROMA1_RPT_PAT 6783 #define P_HEVC_QP_CTRL_REG 4284676100 #define P_MC_OM_MB_XY 4284621884 #define P_ME_START_POSITION 4284644648 #define DUAL_PORT_CNTL_ADDR 5314 #define HCODEC_MDB_DATA_REG 4892 #define P_MCDI_REL_COL_REF_RT 4287675732 #define P_HCODEC_CCPU_INTR_MSK 4284632208 #define VDEC2_ANC17_CANVAS_ADDR 10657 #define QDCT_MB_MEM_CTL 7958 #define SHARP_DEJ_CTRL 12900 #define HCODEC_IE_RESULT_BUFFER 8004 #define VPP2_VSC_REGION34_STARTP 6406 #define DOS_MEM_PD_VP9DEC 16185 #define mLVDS2_RESERVED 15 #define DOS_SECURE_CTL_DATA 16257 #define ME_SUB_MERGE_CTL 8025 #define D2D3_SCU18_INPIC_SIZE 11031 #define VDEC_ASSIST_DMA_INT_MSK 101 #define P_VPU_PROT1_Y_LEN_STEP 4287667536 #define P_HEVC_VLD_TIME_STAMP_SYNC_0 4284674344 #define AIU_MEM_I2S_BUF_WRAP_COUNT 5239 #define VPU_WRARB_WEIGH1_SLV_L1C1 10135 #define VPU_WRARB_WEIGH1_SLV_L1C2 10161 #define P_HEVC_VLD_TIME_STAMP_SYNC_1 4284674348 #define P_VDEC2_CINDEX0_REG 4284648616 #define P_HEVC_MPRED_L1_REF08_POC 4284664032 #define P_VDEC2_ANC28_CANVAS_ADDR 4284655280 #define MDEC_DOUBLEW_CFG7 2530 #define MDEC_DOUBLEW_CFG5 2528 #define STH1_VS_ADDR 5266 #define MDEC_DOUBLEW_CFG6 2529 #define MDEC_DOUBLEW_CFG3 2526 #define MDEC_DOUBLEW_CFG4 2527 #define MDEC_DOUBLEW_CFG1 2524 #define MDEC_DOUBLEW_CFG2 2525 #define MDEC_DOUBLEW_CFG0 2523 #define HCODEC_QDCT_MB_CONTROL 7957 #define P_GE2D_SRC2_KEY_MASK 4287890244 #define HCODEC_DBLK_CB_BFILT 6490 #define VPP_VADJ1_MA_MB 7490 #define VPP_INPUT_CTRL 7595 #define VLC_VB_PRE_BUFF_LOW 7453 #define P_HEVC_ANC10_CANVAS_ADDR 4284671592 #define P_VPU_DI_CHAN2_MMC_CTRL 4287667236 #define P_STREAM_OUTPUT_CONFIG 4291866628 #define VPP_OSD_SCO_H_START_END 7626 #define REG_DEMO_OWR_DATA 51 #define P_NR2_SW_EN 4287651132 #define HCODEC_QDCT_MB_MAGIC_WORD 7960 #define SHARP_SR2_CBIC_VCOEF0 12894 #define P_DNR_DM_SDIF_LUT3_5 4287673784 #define SHARP_SR2_CBIC_VCOEF1 12895 #define P_HEVC_MCPU_INTR_GRP 4284664844 #define P_VPU_VDISP_ASYNC_HOLD_CTRL 4287667476 #define P_HCODEC_DC_SCALER 4284643344 #define P_NR2_3DEN_MODE 4287651124 #define P_ENCP_MACV_EN 4287655432 #define P_DNR_RO_HBOF_STAT_CNT_8 4287673492 #define P_DNR_RO_HBOF_STAT_CNT_7 4287673488 #define P_HCODEC_MDEC_DOUBLEW_STATUS 4284639116 #define P_DNR_RO_HBOF_STAT_CNT_9 4287673496 #define P_DNR_RO_HBOF_STAT_CNT_4 4287673476 #define P_DNR_RO_HBOF_STAT_CNT_3 4287673472 #define P_DNR_RO_HBOF_STAT_CNT_6 4287673484 #define P_DNR_RO_HBOF_STAT_CNT_5 4287673480 #define P_DNR_RO_HBOF_STAT_CNT_0 4287673460 #define P_DNR_RO_HBOF_STAT_CNT_2 4287673468 #define P_UART0_STATUS 4291969036 #define P_DNR_RO_HBOF_STAT_CNT_1 4287673464 #define VDIN1_BLKBAR_IND_RIGHT2_CNT 5226 #define P_VPP_CHROMA_ADDR_PORT 4287657408 #define HEVC_PARSER_HEADER_INFO 12567 #define P_HCODEC_IE_I4_PRED_MODE_HI 4284644628 #define VDIN_COM_CTRL0 4610 #define P_ENCL_VIDEO_VSO_BLINE 4287656676 #define P_ME_SAD_RANGE_INC 4284644704 #define MCDI_GMV_RT 12052 #define P_MLVDS_CLK_CTL1_LO 4287648016 #define NR4_COEF12_SUM 14119 #define SRSHARP0_SHARP_SR2_MISC 12896 #define WR_RDY 4 #define P_HCODEC_IE_CUR_REF_SEL 4284644640 #define VLC_COEFF 7490 #define P_COMM_DESC_KEY_RW 4291847132 #define VPP_OSD1_BLD_V_SCOPE 7670 #define DOLBY_TV_STATUS1 13311 #define DOLBY_TV_STATUS0 13310 #define P_HEVC_MC_IDCT_DAT 4284671280 #define P_HCODEC_IE_I4_PRED_MODE_LO 4284644632 #define HCODEC_CINDEX6_REG 4912 #define HEVC_PSCALE_MCMD_CTRL 14626 #define HCODEC_IMEM_DMA_COUNT 4930 #define P_MLVDS_CLK_CTL1_HI 4287648012 #define AUDIN_I2SIN_CTRL 13328 #define VDEC2_ASSIST_AMR1_INT1 8230 #define VDEC2_ASSIST_AMR1_INT0 8229 #define VDEC2_ASSIST_AMR1_INT3 8232 #define VDEC2_ASSIST_AMR1_INT2 8231 #define P_VIU2_VD1_IF0_LUMA_PSEL 4287658368 #define ANC25_CANVAS_ADDR 2473 #define WATCHDOG_CNTL 15412 #define P_LDIM_STTS_HIST_SET_REGION 4287654724 #define VDEC2_ASSIST_AMR1_INTE 8243 #define VDEC2_ASSIST_AMR1_INTD 8242 #define VDEC2_ASSIST_AMR1_INTF 8244 #define P_VDEC2_ANC31_CANVAS_ADDR 4284655292 #define P_DBLK_GCLK_FREE 4284622256 #define VDEC2_ASSIST_AMR1_INTA 8239 #define P_ENCI_TST_MDSEL 4287656004 #define VDEC2_ASSIST_AMR1_INTC 8241 #define VDEC2_ASSIST_AMR1_INTB 8240 #define VDEC2_ASSIST_AMR1_INT5 8234 #define VDEC2_ASSIST_AMR1_INT4 8233 #define VDEC2_ASSIST_AMR1_INT7 8236 #define VDEC2_ASSIST_AMR1_INT6 8235 #define VDEC2_ASSIST_AMR1_INT9 8238 #define P_ENCT_VIDEO_OFLD_VPEQ_OFST 4287656460 #define VDEC2_ASSIST_AMR1_INT8 8237 #define P_DI_CHAN2_RANGE_MAP_Y 4287651536 #define HCODEC_VLC_DELTA_QP 7485 #define P_HEVC_SHIFT_EMULATECODE 4284662824 #define P_HCODEC_MFDIN_REG1_CTRL 4284629028 #define P_VD1_IF0_LUMA_X0 4287654220 #define VIU_OSD1_PROT_CTRL 6702 #define VDEC2_ANC4_CANVAS_ADDR 10644 #define MDEC_SW_RESET 2436 #define P_VDEC_ASSIST_TIMER1_HI 4284613004 #define P_MC_CMD 4284621848 #define P_VDEC2_PSCALE_BMEM_ADDR 4284654716 #define COI_Y_SCOPE_REG 524 #define HEVC_ANC17_CANVAS_ADDR 14753 #define VPP_OSD_SCI_WH_M1 7625 #define MIPI_DSI_DWC_VID_HBP_TIME_OS 7187 #define mLVDS_data_write_ini 17 #define HCODEC_VLC_JPEG_CTRL 7512 #define P_QDCT_MB_PAUSE_CTL 4284644472 #define RESET4_LEVEL 1060 #define VPU_WRARB_REQEN_SLV_L1C2 10159 #define VPU_WRARB_REQEN_SLV_L1C1 10133 #define P_AVS2_DEC_INFO 4284663116 #define VDEC2_QP_CTRL_REG 11777 #define P_HCODEC_VLC_VB_BUFF 4284642412 #define P_HEVC_VC1_BITPLANE_CTL 4284676192 #define ASYNC_FIFO_FLUSH_EN 20 #define P_MC_CTRL2 4284622140 #define P_MC_CTRL1 4284621868 #define P_AIU_CLK_CTRL_MORE 4291842148 #define P_ENCP_VIDEO_OFLD_VPEQ_OFST 4287655652 #define VENC_VDAC_DACSEL3 7035 #define VENC_VDAC_DACSEL2 7034 #define VENC_VDAC_DACSEL1 7033 #define VENC_VDAC_DACSEL0 7032 #define VENC_VDAC_DACSEL5 7037 #define P_MC_CTRL0 4284621852 #define VENC_VDAC_DACSEL4 7036 #define VPU_HDMI_DITH_11_26 10234 #define P_HCODEC_DBLK_CTRL1 4284638716 #define P_HEVC_STREAM_RD_PTR 4284662804 #define HCODEC_V3_LEFT_INTRA_INFO 8055 #define VPU_HDMI_DITH_11_37 10235 #define SHARP_DB_FLT_SEED_Y 12923 #define P_MCDI_GMV_LOCK_CNT_THD_GAIN 4287675700 #define P_AUDIN_FIFO1_CTRL1 4291875044 #define SHARP_DB_FLT_SEED_U 12924 #define SHARP_DB_FLT_SEED_V 12925 #define VPP_MISC 7462 #define VPU_HDMI_DITH_11_04 10232 #define P_VD1_IF0_LUMA_X1 4287654236 #define P_MCDI_RO_FLD_PD_22_PRE_CNT 4287676064 #define mLVDS_data_write_toggle 18 #define P_VPP2_VE_H_V_SIZE 4287653520 #define AIU_958_PADDSIZE 5123 #define P_HCODEC_VLD_MEM_VBUF2_RD_PTR 4284641616 #define P_VDEC2_MC_CMD 4284654616 #define P_HCODEC_VLC_ELEMENT_DATA 4284642436 #define VPU_HDMI_DITH_11_15 10233 #define P_VD1_IF0_LUMA_Y0 4287654224 #define P_VD1_IF0_LUMA_Y1 4287654240 #define HEVC_PARSER_SLICE_INFO 12561 #define P_VLC_ENC_PEND_CMD 4284642520 #define HEVC_VLD_DECODE_CONTROL 15384 #define SAD_CONTROL_1 7995 #define ENCI_SYNC_HSO_BEGIN 6922 #define SAD_CONTROL_0 7994 #define P_VDEC2_CBREAK0_REG 4284648656 #define DI_IF2_LUMA0_RPT_PAT 8215 #define P_VPU_PROT1_STAT_0 4287667556 #define P_VPU_PROT1_STAT_1 4287667560 #define P_VPU_PROT1_STAT_2 4287667564 #define HEVC_MC_CMD 14598 #define P_HEVC_SLICE_VER_POS_PIC_TYPE 4284674064 #define FLD_DCT 1024 #define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT 4291842612 #define P_VBO_TMCHK_THRD_L 4287648224 #define VENC_VDAC_DAC3_FILT_CTRL0 7262 #define VENC_VDAC_DAC3_FILT_CTRL1 7263 #define VPP2_DUMMY_DATA 6400 #define P_VBO_TMCHK_THRD_H 4287648228 #define P_HCODEC_HENC_TOP_MV_2 4284642608 #define P_HCODEC_HENC_TOP_MV_1 4284642604 #define P_VDEC_ASSIST_TIMER1_LO 4284613000 #define P_HCODEC_HENC_TOP_MV_3 4284642612 #define VIU_OSD1_EOTF_COEF11_12 6871 #define P_HCODEC_HENC_TOP_MV_0 4284642600 #define P_DI_IF1_LUMA_FIFO_SIZE 4287651784 #define VDEC2_MDB_ADDR_REG 8987 #define VPU_VLOCK_RO_LOOP1_ACCUM 12303 #define HEVC_MINDEX5_REG 13071 #define P_HEVC_ANC0_CANVAS_ADDR 4284671552 #define AIU_958_SYNWORD2_MASK 5152 #define L_TCON_MISC_SEL_ADDR 5185 #define SANA_STREAM_CONTROL 12320 #define P_VDIN_BLKBAR_IND_LEFT1_CNT 4287646108 #define VPP2_OSD_SCO_V_START_END 6603 #define HCODEC_QDCT_Q_STATUS 7962 #define AIU_958_LENGTH 5122 #define HEVC_SAO_INT_STATUS 13828 #define P_HEVC_PSCALE_CANVAS_WR_ADDR 4284671156 #define SRSHARP0_SATPRT_DIVM 12917 #define SRSHARP1_PK_OS_VERT_CORE_GAIN 13348 #define P_HCODEC_DBLK_Y_VFILT 4284638584 #define P_HCODEC_ASSIST_MBOX0_IRQ_REG 4284629440 #define P_VPU_ARB4_V2_MMC_CTRL 4287667376 #define P_RESET3_MASK 4291825740 #define VDEC2_CDB_CTRL 9021 #define ENCP_SYNC_TO_PIXEL 7239 #define P_DI_IF2_CHROMA_Y0 4287660116 #define VENC_DVI_SETTING 7010 #define HEVC_SAO_IF_WAIT_CNT 12600 #define P_AIU_958_LENGTH_PER_PAUSE 4291842188 #define NINTRA_QM 16 #define VLC_SPECIAL_CTL 7458 #define P_AIU_I2S_MED_CTRL 4291842104 #define mLVDS2_data_write_ini 17 #define P_DI_IF2_CHROMA_X0 4287660112 #define DI_NRWR_Y 6081 #define DI_NRWR_X 6080 #define SPDIF_BIT_ORDER 20 #define P_ENCI_DE_V_END_ODD 4287655020 #define HCODEC_VLC_STREAM_BUFF 7454 #define SRSHARP0_HLTI_FLT_CLP_DC 12852 #define L_OEH_HE_ADDR 5145 #define P_MC_HCMD_L 4284622124 #define P_MC_HCMD_H 4284622120 #define HEVC_MPRED_L1_REF02_POC 12850 #define P_VPP_DAT_CONV_PARA1 4287657556 #define P_VPP_DAT_CONV_PARA0 4287657552 #define P_VPP2_SMOKE2_V_START_END 4287653056 #define HEVC_PARSER_LCU_INFO 12566 #define P_ENCP_VIDEO_YFP1_HTIME 4287655504 #define P_VDEC2_DBLK_RV8_QUANT 4284655064 #define WATCHDOG_RESET 15415 #define P_AIU_I2S_DAC_CFG 4291842112 #define P_VIU_OSD1_MATRIX_OFFSET2 4287654492 #define VLD_MEM_VIFIFO_RP 3142 #define P_VDEC2_MBREAK2_REG 4284648536 #define HCODEC_QDCT_DBG_READ 7972 #define P_HEVC_PSCALE_PICO_START_X 4284671064 #define P_HEVC_PSCALE_PICO_START_Y 4284671068 #define P_VPP_MATRIX_PROBE_COLOR1 4287657820 #define P_AIU_MEM_AIFIFO2_END_PTR 4291842480 #define DET3D_MAT_STA_RSFT 5947 #define P_HEVC_ASSIST_AFIFO_CTRL1 4284661768 #define L_STH1_VS_ADDR 5138 #define P_VDEC2_CMIN_REG 4284648648 #define P_VDEC2_ASSIST_MMC_CTRL0 4284645380 #define P_ENCL_VFIFO2VD_LINE_TOP_END 4287656528 #define P_VPU_TVDVBI_MMC_CTRL 4287667268 #define P_HCODEC_PSCALE_MCMD_YSIZE 4284638352 #define P_HCODEC_VLD_TIME_STAMP_LENGTH 4284641600 #define NR4_MCNR_CM_PRAM 11718 #define P_Q_QUANT_CONTROL 4284644568 #define P_SPICC1_DRADDR 4291907616 #define VLD_MEM_VIFIFO_WP 3141 #define P_AFBC_HEAD_BADDR 4287654808 #define NR4_DBGWIN_YX1 14098 #define P_VPP_HLTI_GAIN 4287657796 #define NR4_DBGWIN_YX0 14097 #define P_AIFIFO2_TIME_STAMP_LENGTH 4291842684 #define OSD1_AFBCD_HDR_PTR 12707 #define NR4_COEFBLT_CONV 14096 #define P_ANC4_CANVAS_ADDR 4284622416 #define P_VDEC2_ASSIST_MMC_CTRL1 4284645384 #define FWD_PRED 8 #define P_HCODEC_PATTERN_CODE 4284641452 #define P_MCDI_MOTINEN 4287675404 #define P_DOS_APB_ERR_STAT 4284677136 #define P_NR4_COEF12_SUM 4287683740 #define P_VLC_WRRSP 4284642404 #define GE2D_SRC1_FMT_CTRL 174 #define P_VPP_HSC_REGION3_PHASE_SLOPE 4287657048 #define P_NR4_MCNR_RO_GRDV_SUM 4287674324 #define VPP_HCTI_DN_FLT 7635 #define P_MINDEX4_REG 4284615736 #define AIU_MEM_IEC958_START_PTR 5221 #define MIPI_DSI_DWC_VID_VFP_LINES_OS 7191 #define P_VPP_MISC1 4287657432 #define P_LVDS_BIST_FIXED1 4287648688 #define P_LVDS_BIST_FIXED0 4287648684 #define VPP2_VSC_REGION1_PHASE_SLOPE 6410 #define VPP_SRSHARP0_CTRL 7569 #define P_HCODEC_ME_SAD_ENOUGH_23 4284644676 #define P_VDEC2_MB_MOTION_MODE 4284657692 #define P_VIU_OSD1_EOTF_COEF22_RS 4287654756 #define ENCI_INFO_READ 10012 #define P_AUDIN_FIFO2_REQID 4291875132 #define D2D3_CG_THRESHOLD_2 11016 #define D2D3_CG_THRESHOLD_1 11015 #define P_VPP_MATRIX_PROBE_POS 4287657336 #define L_STH2_VS_ADDR 5142 #define P_MCDI_HOR_SADOFST 4287675480 #define P_VD2_AFBC_DEC_DEF_COLOR 4287677964 #define DI_NR_1_CTRL3 6039 #define DI_NR_1_CTRL2 6038 #define P_DI_EI_DRT_CTRL 4287651296 #define DI_NR_1_CTRL1 6037 #define P_HCODEC_MBREAK1_REG 4284632148 #define DI_NR_1_CTRL0 6036 #define VDIN0_BLKBAR_IND_LEFT1_CNT 4711 #define VDIN_BLKBAR_CNT_THRESHOLD 4707 #define VDEC2_MINDEX6_REG 8976 #define SRSHARP1_VCTI_FLT_CON_CLP 13375 #define HCODEC_QDCT_JPEG_X_START_END 7974 #define P_HEVC_MDEC_PIC_DC_THRESH 4284671712 #define ASYNC_FIFO_ERR 30 #define P_HEVC_DBLK_CBPC_ADJ 4284671436 #define P_SHARP_DEJ_CTRL 4287678864 #define P_VDEC2_DBLK_GCLK_OFF 4284655028 #define DET3D_CB_CFG 5941 #define ENCI_TST_MDSEL 7185 #define NR4_MCNR_RO_GRDU_SUM 11764 #define P_VPP2_SMOKE_CTRL 4287653028 #define P_GE2D_SRC1_CANVAS 4287890084 #define P_HCODEC_ME_SAD_ENOUGH_01 4284644672 #define SHARP_SR3_DRTLPF_ALPHA_1 12904 #define SHARP_SR3_DRTLPF_ALPHA_0 12903 #define P_HEVC_MDEC_PICW_BUF_STATUS 4284671720 #define SHARP_SR3_DRTLPF_ALPHA_2 12905 #define WM_AM_LUT_DATA_PORT 12743 #define P_DI_INP_FMT_W 4287651688 #define SPI_FLASH_CLOCK 20486 #define HEVC_CINDEX3_REG 13101 #define VDEC2_DC_AC_CTRL 11781 #define VPP_HSC_REGION0_PHASE_SLOPE 7444 #define HCODEC_DECODER_BUFFER_INFO 7183 #define VDIN0_SC_MISC_CTRL 4619 #define VLD_C3D 3133 #define PARSER_AUDIO_WP 14471 #define VLD_C38 3128 #define P_D2D3_DPF_LPF_CTRL 4287671360 #define VLD_C39 3129 #define PWM_BLINK_AB 27655 #define P_RESET7_LEVEL 4291825820 #define P_VDEC2_DBLK_QP 4284654936 #define P_AIU_ACODEC_CTRL 4291842224 #define HIU_RESET 1 #define UVHS_OFST_REG 536 #define HEVC_VLD_DC_PRED_C 15407 #define VIU_OSD2_FIFO_CTRL_STAT 6731 #define NEXT_ALIGN_PEAK 3101 #define HEVC_MPRED_L0_REF05_POC 12837 #define P_HCODEC_ANC8_CANVAS_ADDR 4284638816 #define PWM_BLINK_CD 26631 #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 15803 #define P_DC_AC_CTRL 4284626964 #define ENCP_VFIFO2VD_LINE_TOP_START 7003 #define P_GE2D_SCALE_COEF_IDX 4287890256 #define P_HCODEC_QDCT_JPEG_CTRL 4284644500 #define VCOM_HSWITCH_ADDR 5276 #define SRSHARP1_LTI_CTI_DIR_AC_DBG 13357 #define PARSER_AUDIO_RP 14472 #define VDIN0_BLKBAR_IND_RIGHT1_CNT 4713 #define PWM_BLINK_EF 25607 #define SRSHARP1_PK_ALP2_ERR2CURV_TH_RATE 13343 #define VDIN0_HIST_MAX_MIN 4659 #define P_GE2D_SRC1_DEF_COLOR 4287890072 #define CPU_RESET 128 #define P_HEVC_MPRED_MV_RLCUY 4284663932 #define HCODEC_DBLK_CR_BFILT 6491 #define P_EE_ASSIST_MBOX3_MASK 4291854840 #define TCON_HSYNC_SEL_DVI 10 #define DITH_MD 8 #define P_VDEC2_VLD_TIME_STAMP_LENGTH 4284657984 #define P_VDEC2_FST_FOR_MV_Y 4284657732 #define P_VDEC2_FST_FOR_MV_X 4284657728 #define ASYNC_FLUSH_SIZE_IRQ_MSB 15 #define MINDEX1_REG 779 #define VIU2_OSD2_COLOR_ADDR 7729 #define P_HEVC_MPRED_L0_REF12_POC 4284663984 #define BL1_DEBUG_BUFFER 3640737280 #define BL1_SEC_MBX 3640735744 #define P_SHARED_DEBUG_BUFF 3640737280 #define SRAM_DEBUG_BUFF_SIZE 256 #define BL1_RAM_END 3640737792 #define BL1_EFUSE_MIRROR 3640736768 #define RAM_START 3640655872 #define _STACK_END 3640733696 #define RAM_SIZE 81920 #define BSS_SIZE 18432 #define CPU_BOOT_ENTRY 3640737536 #define P_SHARED_EFUSE_MIRROR 3640736768 #define BL1_USB_BUFF 3640706048 #define BL1_RAM_START 3640705024 #define ROMBOOT_START 3640918016 #define ROMBOOT_END 3640983552 #define BL1_NAND_BUFF 3640706048 #define ROM_SIZE 65536 #define BL1_RAM_SIZE 32768 #define BSS_START 3640707072 #define BL2_SIZE 65536 #define MEMORY_LOC 3640655872 typedef struct _IO_FILE FILE; #define SAR_ADC_REG11 4286615596 #define SAR_ADC_REG12 4286615600 #define SAMPLE_BIT_MASK 4095 #define SAR_ADC_REG13 4286615604 #define SAR_ADC_BASE 4286615552 #define SAR_ADC_DELTA_10 4286615592 #define SAR_ADC_LAST_RD 4286615572 #define SAR_ADC_REG3 4286615564 #define SAR_ADC_REG0 4286615552 #define SAR_BUS_CLK_EN 4286578752 #define SAR_ADC_DETECT_IDLE_SW 4286615588 #define SAR_ADC_AVG_CNTL 4286615560 #define SAR_CLK_CNTL 4286578832 #define SAR_ADC_DELAY 4286615568 #define SAR_ADC_CHAN_LIST 4286615556 #define SAR_ADC_AUX_SW 4286615580 #define SAR_ADC_FIFO_RD 4286615576 #define SAR_ADC_CHAN_10_SW 4286615584 #define FLAG_BUSY_BL30 32768 #define EN_BIT 7 #define FLAG_BUSY_KERNEL 16384 #define IO6 273408 #define IO4 276480 #define IO5 275456 #define NAND_MFR_NATIONAL 143 #define NAND_MFR_AMD 1 #define ERROR_NAND_BLANK_PAGE 133 #define NAND_MFR_EFUSE 257 #define ERROR_NAND_TIMEOUT 129 #define P_NAND_SADR 4292900908 #define P_NAND_BUF 4292900880 #define NAND_INFO_BUF 25166336 #define NAND_MFR_HYNIX 173 #define P_NAND_CFG 4292900868 #define INFO_BYTE_PER_ECCPAGE 8 #define CLE 81920 #define ADL 3145728 #define ADH 3211264 #define IDLE 196608 #define NAND_MFR_TOSHIBA 152 #define NAND_MFR_SANDISK 69 #define P_NAND_CMD 4292900864 #define SRC_ALIGN_SIZE 16384 #define NAND_SECTOR_SIZE 512 #define ERROR_NAND_MAGIC_WORD 131 #define P_NAND_DH 4292900900 #define RB 1048576 #define P_NAND_DC 4292900888 #define P_NAND_INFO 4292900884 #define NAND_MFR_STMICRO 32 #define DEFAULT_ECC_MODE 15461377 #define P_NAND_DL 4292900896 #define ASL 3407872 #define ASH 3473408 #define NAND_MFR_RENESAS 7 #define P_NAND_IADR 4292900876 #define ERROR_NAND_INIT_READ 132 #define NAND_MFR_USER 256 #define M2N 2621440 #define P_NAND_BASE 4292900864 #define NAND_MAX_PAGESIZE 16384 #define ALE 98304 #define DRD 131072 #define ERROR_NAND_UNALIGN_SRC 134 #define NAND_PAGE0_BUF 25165824 #define P_NAND_DADR 4292900872 #define STS 2490368 #define ERROR_NAND_ECC 130 #define CE2 11264 #define CE3 7168 #define CE0 14336 #define CE1 13312 #define P_CLK_CNTL 4292898816 #define NAND_MFR_INTEL 137 #define AIH 3342336 #define DWR 65536 #define P_NAND_CADR 4292900904 #define SEED 3670016 #define N2M 2752512 #define NAND_MFR_SAMSUNG 236 #define CEF 15360 #define AIL 3276800 #define P_NAND_ADR 4292900892 #define NAND_MFR_MICRON 44 #define NAND_MFR_FUJITSU 4 #define UPCTL_CMD_WAKEUP 4 #define UPCTL_CMD_SLEEP 3 #define PUB_PIR_DRAMINIT 256 #define PUB_PIR_ZCALBYP 1073741824 #define PUB_PIR_DCAL 32 #define PUB_PIR_RDDSKW 4096 #define PUB_PIR_PLLBYP 131072 #define UPCTL_STAT_CONFIG 1 #define UPCTL_STAT_MASK 7 #define PUB_PIR_INITBYP 2147483648 #define PUB_PIR_INIT 1 #define PUB_PIR_ICPC 65536 #define PUB_PIR_RDIMMINIT 524288 #define PUB_PIR_WRDSKW 8192 #define PUB_PIR_WLADJ 2048 #define UPCTL_STAT_ACCESS 3 #define PUB_PIR_QSGATE 1024 #define PUB_PIR_PHYRST 64 #define PUB_PIR_LOCKBYP 268435456 #define PUB_PIR_PLLINIT 16 #define PUB_PIR_CLRSR 134217728 #define PUB_PIR_DCALBYP 536870912 #define SCRATCH0 3239083324 #define UPCTL_STAT_LOW_POWER 5 #define PUB_PIR_CTLDINIT 262144 #define UPCTL_CMD_INIT 0 #define UPCTL_CMD_CONFIG 1 #define PUB_PIR_WL 512 #define PUB_PIR_ZCAL 2 #define PUB_PIR_DRAMRST 128 #define PUB_PIR_CA 4 #define UPCTL_STAT_INIT 0 #define UPCTL_CMD_GO 2 #define PUB_PIR_RDEYE 16384 #define PUB_PIR_WREYE 32768 #define PHYCLKRST_MPLL_MULTIPLIER_MASK 260096 #define PHYCLKRST_PORTRESET 2 #define PHYUTMI_FORCESLEEP 1 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF 4096 #define BOARD_USB_MODE_MAX 3 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK 8 #define PHYCLKRST_REF_CLKDIV2 262144 #define PHYBATCHG_UTMI_CLKSEL 4 #define USB_PHY2_ENABLE 268435456 #define PHYCLKRST_REF_SSP_EN 524288 #define PHYPARAM1_PCS_TXDEEMPH 28 #define BOARD_USB_MODE_CHARGER 2 #define PHYPARAM0_REF_LOSLEVEL 603979776 #define PHYCLKRST_RETENABLEN 16 #define PHYCLKRST_SSC_RANGE_MASK 6291456 #define PHYCLKRST_FSEL_PAD_24MHZ 1344 #define BOARD_USB_MODE_HOST 0 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF 256000 #define PHYCLKRST_SSC_REFCLKSEL_MASK 2139095040 #define USB_PHY_PORT_MAX 1 #define PHYCLKRST_FSEL_PAD_20MHZ 1568 #define LINKSYSTEM_XHCI_VERSION_CONTROL 134217728 #define PHYCLKRST_FSEL_MASK 2016 #define PHYTEST_POWERDOWN_HSP 4 #define PHYCLKRST_REFCLKSEL_MASK 12 #define FSEL_CLKSEL_24M 5 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF 51200 #define PHYPARAM0_REF_USE_PAD 2147483648 #define PHYTEST_POWERDOWN_SSP 8 #define BOARD_USB_MODE_SLAVE 1 #define USB_ID_MODE_SW_DEVICE 3 #define PHY_REGISTER_SIZE 32 #define PHYUTMI_OTGDISABLE 64 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF 212992 #define PHYCLKRST_COMMONONN 1 #define PHYCLKRST_SSC_EN 1048576 #define PHYUTMI_FORCESUSPEND 2 #define PHYCLKRST_FSEL_PAD_100MHZ 1248 #define PHYPARAM1_PCS_TXDEEMPH_MASK 31 #define USB_PHY2_RESET 536870912 #define USB_ID_MODE_SW_HOST 2 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF 4096 #define PHYPARAM0_REF_LOSLEVEL_MASK 2080374784 #define USB_ID_MODE_HARDWARE 1 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK 12 #define LINKSYSTEM_FLADJ_MASK 126 #define PHYCLKRST_FSEL_PAD_19_2MHZ 1792 typedef struct sram_hal_api_arg sram_hal_api_arg, *Psram_hal_api_arg; struct sram_hal_api_arg { uint cmd; uint req_len; uint res_len; ulong req_phy_addr; ulong res_phy_addr; ulong ret_phy_addr; }; #define AML_D_P_IMG_DECRYPT 64 #define JTAG_OFF 2181038145 #define GET_SHARE_MEM_OUTPUT_BASE 2181038113 #define EFUSE_WRITE_PATTERN 2181038130 #define GXB_IMG_SIZE 25165824 #define CALL_TRUSTZONE_HAL_API 5 #define JTAG_A53_AO 2 #define RUN_COMD_USB_BOOT 3 #define PANIC_DUMP_USB_BOOT 4 #define SECURITY_KEY_TELL 2181038179 #define GET_SHARE_STORAGE_BLOCK_BASE 2181038117 #define SECURITY_KEY_NOTIFY_EX 2181038185 #define GXB_EFUSE_PATTERN_SIZE 1280 #define GET_SHARE_STORAGE_OUT_BASE 2181038116 #define GET_SHARE_STORAGE_MESSAGE_BASE 2181038118 #define SECURITY_KEY_SET_ENCTYPE 2181038186 #define AML_D_P_W_EFUSE_CUSTOMER_ID 18 #define GET_SHARE_MEM_INPUT_BASE 2181038112 #define VIU_PREOBE_EN 2181038208 #define GET_SHARE_STORAGE_IN_BASE 2181038115 #define DEBUG_EFUSE_READ_PATTERN 2181038321 #define GET_SHARE_STORAGE_BLOCK_SIZE 2181038119 #define SECURITY_KEY_LIST 2181038183 #define GXB_IMG_DEC_KNL 1 #define FORCE_USB_BOOT 2 #define JTAG_STATE_ON 0 #define SECURITY_KEY_READ 2181038177 #define JTAG_M3_EE 1 #define TRUSTZONE_HAL_API_SRAM 1024 #define AML_D_Q_IMG_SIG_HDR_SIZE 256 #define GXB_IMG_LOAD_ADDR 17301504 #define AML_D_P_W_EFUSE_PASSWORD 17 #define EFUSE_WRITE 2181038129 #define SET_STORAGE_INFO 2181038120 #define JTAG_A53_EE 3 #define EFUSE_READ 2181038128 #define SECURITY_KEY_NOTIFY 2181038182 #define SECURITY_KEY_QUERY 2181038176 #define SECURITY_KEY_VERIFY 2181038180 #define AML_DATA_PROCESS 2181038335 #define GXB_IMG_DEC_ALL 7 #define SECURITY_KEY_STATUS 2181038181 #define JTAG_ON 2181038144 #define GXB_IMG_DEC_RMD 2 #define SECURITY_KEY_REMOVE 2181038184 #define SRAM_HAL_API_CHECK_EFUSE 1027 #define SECURITY_KEY_VERSION 2181038188 #define CLEAR_USB_BOOT 1 #define PSCI_SYS_REBOOT 2214592521 #define AML_D_P_UPGRADE_CHECK 128 #define EFUSE_USER_MAX 2181038131 #define GET_REBOOT_REASON 2181038114 #define JTAG_M3_AO 0 #define GXB_IMG_DEC_DTB 4 #define SECURITY_KEY_WRITE 2181038178 #define AML_D_P_W_EFUSE_AMLOGIC 32 #define AML_D_P_W_EFUSE_SECURE_BOOT 16 #define CLUSTER_BIT 2 #define SET_USB_BOOT_FUNC 2181038147 #define GET_CHIP_ID 2181038148 #define DEBUG_EFUSE_WRITE_PATTERN 2181038320 #define JTAG_STATE_OFF 1 #define SECURITY_KEY_GET_ENCTYPE 2181038187 #define SCPI_CMD_THERMAL_CALIB 197 #define LOW_PRIORITY 0 #define SCPI_CMD_REV_PWM_DELT 66 #define MHU_HIGH_SCP_TO_AP_PAYLOAD 291840 #define MHU_LOW_SCP_TO_AP_PAYLOAD 290816 #define SCPI_CMD_OPEN_SCP_LOG 196 #define MHU_LOW_AP_TO_SCP_PAYLOAD 291328 #define SCPI_CMD_USB_UNBOOT 177 #define SCPI_CMD_SDCARD_BOOT 178 #define SCPI_CMD_SENSOR_VALUE 28 #define MHU_HIGH_AP_TO_SCP_PAYLOAD 292352 #define HIGH_PRIORITY 1 #define SCPI_CMD_SET_USR_DATA 32 #define SRAM_SIZE 294912 #define P_SHARE_SRAM_BASE 4294574080 #define SCPI_CMD_CLEAR_BOOT 179 #define SCPI_CMD_USB_BOOT 176 #define UART_CNTL_MASK_PRTY_EN 524288 #define UART_CNTL_MASK_RINT_EN 134217728 #define UART_CNTL_MASK_INV_RTS 2147483648 #define UART_STAT_MASK_RFIFO_EMPTY 1048576 #define UART_CNTL_MASK_STP_BITS 196608 #define UART_PORT_0 36864 #define UART_CNTL_MASK_CHAR_7BIT 1048576 #define UART_STAT_MASK_TFIFO_CNT 32512 #define CONFIG_SERIAL_STP_BITS 1 #define UART_PRTY_BIT 0 #define UART_STAT_MASK_TFIFO_FULL 2097152 #define UART_PORT_AO 4286590976 #define UART_CNTL_MASK_INV_RX 33554432 #define UART_CHAR_LEN 0 #define UART_CNTL_MASK_TX_EN 4096 #define UART_CNTL_MASK_INV_CTS 536870912 #define UART_CLK_SRC 7 #define UART_STAT_MASK_WFULL_ERR 262144 #define UART_CNTL_MASK_TINT_EN 268435456 #define UART_CNTL_MASK_RX_EN 8192 #define UART_STAT_MASK_PRTY_ERR 65536 #define UART_CNTL_MASK_CHAR_5BIT 3145728 #define UART_CNTL_MASK_STP_2BIT 65536 #define UART_CNTL_MASK_PRTY_TYPE 262144 #define UART_STP_BIT 0 #define UART_STAT_MASK_XMIT_BUSY 33554432 #define UART_CNTL_MASK_PRTY_EVEN 0 #define UART_CNTL_MASK_CHAR_8BIT 0 #define UART_STAT_MASK_FRAM_ERR 131072 #define UART_CNTL_MASK_2WIRE 32768 #define UART_CNTL_MASK_CHAR_LEN 3145728 #define CONFIG_SERIAL_CHAR_LEN 8 #define UART_STAT_MASK_RFIFO_FULL 524288 #define UART_CNTL_MASK_RST_RX 8388608 #define UART_CNTL_MASK_PRTY_ODD 262144 #define UART_STAT_MASK_RFIFO_CNT 127 #define UART_STATUS 3 #define UART_CNTL_MASK_CHAR_6BIT 2097152 #define UART_CNTL_MASK_CLR_ERR 16777216 #define UART_CNTL_MASK_STP_1BIT 0 #define UART_RFIFO 1 #define UART_STAT_MASK_TFIFO_EMPTY 4194304 #define CONFIG_SERIAL_PRTY_TYPE 0 #define UART_STAT_MASK_RECV_BUSY 67108864 #define UART_CNTL_MASK_BAUD_RATE 4095 #define UART_PORT_1 35840 #define UART_CNTL_MASK_MASK_ERR 1073741824 #define UART_CNTL_MASK_RST_TX 4194304 #define UART_MISC 4 #define UART_CONTROL 2 #define UART_WFIFO 0 #define UART_CNTL_MASK_INV_TX 67108864 #define EFUSE_CLK_A73_CFG01 4284696344 #define P_EE_AUDIO_TDMIN_C_SWAP 4284752772 #define EE_AUDIO_TDMIN_LB_MUTE_VAL 4284752860 #define P_AO_IR_DEC_LDR_IDLE 4286611460 #define P_AO_MSG_INDEX1 4286579076 #define P_AO_MSG_INDEX0 4286579072 #define P_AO_MSG_INDEX3 4286579084 #define P_AO_MSG_INDEX2 4286579080 #define SEC_BUS_MON1_DATA 4284696088 #define EE_AUDIO_SPDIFOUT_B_CTRL1 4284753552 #define EE_AUDIO_SPDIFOUT_B_CTRL0 4284753548 #define P_AED_DRC_AD_1M_H 4284834324 #define SEC_EE_AUDIO_POW_DET_TH_LO 4284753420 #define P_AED_TOP_REQ_CTL 4284834340 #define SEC_EE_AUDIO_TDMIN_C_STAT 4284752792 #define P_EE_AUDIO_TDMOUT_B_CTRL0 4284753216 #define P_EE_AUDIO_TDMOUT_B_CTRL1 4284753220 #define AO_SEC_JTAG_SCP_CTRL 4286579416 #define EFUSE_WDATA3 4284678172 #define AO_RTI_PULL_UP_EN_REG 4286578736 #define EFUSE_WDATA2 4284678168 #define EFUSE_WDATA1 4284678164 #define EFUSE_WDATA0 4284678160 #define P_AO_TIMER_SEC_SP_CTRL 4286579656 #define HHI_TIMER90K 4284727548 #define P_RO_REF2OMCLK_CNT_H 4284784716 #define SEC_HHI_HDMI_PLL_VLOCK_CNTL 4284728132 #define P_RO_REF2OMCLK_CNT_L 4284784712 #define EE_AUDIO_TODDR_B_START_ADDR 4284752200 #define AO_IR_DEC_BIT_0 4286611468 #define P_EE_AUDIO_CLK_PDMIN_CTRL0 4284752044 #define P_EE_AUDIO_CLK_PDMIN_CTRL1 4284752048 #define P_PAD_DS_REG5A 4284696408 #define P_MIPI_ISP_ARB_DBG_CTRL 4284842032 #define EE_AUDIO_TDMOUT_C_GAIN1 4284753316 #define EE_AUDIO_TDMOUT_C_GAIN0 4284753312 #define SEC_EE_AUDIO_FRDDR_B_INT_ADDR 4284752400 #define AO_MF_IR_DEC_REPEAT_DET 4286611604 #define AO_WATCHDOG_TCNT 4286578984 #define AO_TIMERB_REG 4286579668 #define P_EE_AUDIO_CLK_TDMOUT_B_CTRL 4284752020 #define SEC_EE_AUDIO_CLK_SPDIFIN_CTRL 4284752028 #define SEC_EE_AUDIO_POW_DET_TH_HI 4284753416 #define P_PAD_DS_REG4A 4284696404 #define P_AO_SEC_JTAG_PWD_SCP_3 4286579432 #define P_AO_SEC_JTAG_PWD_SCP_2 4286579428 #define P_AO_SEC_JTAG_PWD_SCP_1 4286579424 #define P_AO_SEC_JTAG_PWD_SCP_0 4286579420 #define SEC_AED_DRC_AA_1M_H 4284834320 #define P_AO_SEC_SHARED_AHB_SRAM_REG3_2 4286579152 #define P_HHI_CSI_PHY_CNTL3 4284728152 #define P_HHI_CSI_PHY_CNTL2 4284728148 #define P_HHI_CSI_PHY_CNTL1 4284728144 #define P_HHI_CSI_PHY_CNTL0 4284728140 #define MIPI_ADAPT_PIXEL0_ST0 4284829864 #define P_AO_SEC_SHARED_AHB_SRAM_REG3_0 4286579144 #define P_HHI_CSI_PHY_CNTL5 4284728160 #define P_AO_SEC_SHARED_AHB_SRAM_REG3_1 4286579148 #define MIPI_ADAPT_PIXEL0_ST1 4284829868 #define P_HHI_CSI_PHY_CNTL4 4284728156 #define SEC_AO_TIMERC_CUR_REG 4286579680 #define P_EE_AUDIO_TDMOUT_A_STAT 4284753180 #define P_EE_AUDIO_MST_B_SCLK_CTRL1 4284751948 #define P_EE_AUDIO_MST_B_SCLK_CTRL0 4284751944 #define P_PAD_DS_REG3A 4284696400 #define P_AO_RTI_GEN_CNTL_REG0 4286578752 #define EE_AUDIO_TDMIN_LB_SWAP 4284752836 #define P_EFUSE_START 4284678148 #define P_EE_AUDIO_TORAM_FINISH_ADDR 4284753676 #define SEC_AO_TIMERF_REG 4286579692 #define P_PAD_DS_REG2A 4284696392 #define P_PAD_DS_REG2B 4284696396 #define P_M4_CPU_STAT1 4286579488 #define P_M4_CPU_STAT2 4286579492 #define AO_UART2_STATUS 4286595084 #define P_SYS_CPU_POR_CFG1 4284696132 #define P_PAD_DS_REG1A 4284696388 #define P_SYS_CPU_POR_CFG0 4284696128 #define SEC_PREG_PAD_GPIO4_EN_N 4284695664 #define SEC_AO_AHB2DDR_CNTL 4286578784 #define P_RNG_SEC_STS 4284678676 #define HHI_AXI_PIPEL_CNTL1 4284728268 #define P_HHI_MPEG_CLK_CNTL 4284727668 #define HHI_AXI_PIPEL_CNTL2 4284728260 #define P_PAD_DS_REG0A 4284696384 #define P_DMA_CFG 4284735552 #define P_SYS_CPU_CFG6 4284696160 #define P_SYS_CPU_CFG7 4284696164 #define P_SYS_CPU_CFG4 4284696152 #define P_SYS_CPU_CFG5 4284696156 #define P_SYS_CPU_CFG2 4284696144 #define P_SYS_CPU_CFG3 4284696148 #define P_SYS_CPU_CFG0 4284696136 #define P_SYS_CPU_CFG1 4284696140 #define SEC_AO_MAILBOX_SET_3 4286619688 #define SEC_AO_MAILBOX_SET_1 4286619664 #define SEC_AO_MAILBOX_SET_2 4286619676 #define SEC_AO_MAILBOX_SET_0 4286619652 #define AO_PWM_DELTA_SIGMA_AB 4286607372 #define AO_UART_RFIFO 4286590980 #define P_RESET1_SEC_MASK 4284801156 #define P_SYS_CPU_CFG8 4284696168 #define P_SYS_CPU_CFG9 4284696172 #define EE_AUDIO_SPDIFOUT_B_MUTE_VAL 4284753612 #define P_MIPI_ISP_RDARB_REQEN_SLV 4284841988 #define SEC_EE_AUDIO_RESAMPLE_COEF0 4284752976 #define SEC_EE_AUDIO_RESAMPLE_COEF1 4284752980 #define SEC_EE_AUDIO_RESAMPLE_COEF2 4284752984 #define SEC_EE_AUDIO_RESAMPLE_COEF3 4284752988 #define SEC_EE_AUDIO_RESAMPLE_COEF4 4284752992 #define SEC_EE_AUDIO_TORAM_START_ADDR 4284753672 #define SEC_EE_AUDIO_TDMOUT_B_MUTE_VAL 4284753256 #define SEC_AO_PWM_MISC_REG_AB 4286607368 #define P_EE_AUDIO_TDMOUT_A_MUTE_VAL 4284753192 #define SEC_AO_SAR_CLK 4286578832 #define AUD_LOCK_OMCLK_LAT_INT 4284784668 #define SEC_EE_AUDIO_MCLK_E_CTRL 4284751892 #define P_AO_TIMERB_REG 4286579668 #define EE_AUDIO_TDMOUT_A_MUTE0 4284753196 #define P_AED_NG_STEP 4284834332 #define EE_AUDIO_TDMOUT_C_SWAP 4284753288 #define SEC_PDM_CLKG_CTRL 4284743724 #define SEC_AO_PWM_MISC_REG_CD 4286586888 #define EE_AUDIO_TDMOUT_A_MUTE3 4284753208 #define EE_AUDIO_TDMOUT_A_MUTE1 4284753200 #define EE_AUDIO_TDMOUT_A_MUTE2 4284753204 #define SEC_RNG_SEC_DATA 4284678672 #define MIPI_ISP_RDWR_ARB_STATUS 4284842028 #define HHI_AXI_PIPEL_CNTL 4284728272 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_2 4286579176 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_1 4286579172 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG5_0 4286579168 #define P_AMLUSB_A17 4284702788 #define P_AO_UART_RFIFO 4286590980 #define P_AMLUSB_A16 4284702784 #define P_AMLUSB_A15 4284702780 #define P_AMLUSB_A14 4284702776 #define P_AMLUSB_A13 4284702772 #define P_EE_AUDIO_TDMIN_A_MUTE2 4284752680 #define MIPI_DSI_ULPS_CHECK 4284760120 #define P_AMLUSB_A12 4284702768 #define P_EE_AUDIO_TDMIN_A_MUTE1 4284752676 #define P_AMLUSB_A11 4284702764 #define P_AMLUSB_A10 4284702760 #define P_EE_AUDIO_TDMIN_A_MUTE3 4284752684 #define SEC_AED_MUTE 4284834204 #define P_EE_AUDIO_TDMIN_A_MUTE0 4284752672 #define HHI_GCLK_LOCK 4284727612 #define SEC_HHI_MPEG_CLK_CNTL 4284727668 #define SEC_AO_MF_IR_DEC_WIDTH_NEW 4286611600 #define SEC_HHI_VDEC_CLK_CNTL 4284727776 #define AO_CLK_GATE0_SP 4286578768 #define SEC_EE_AUDIO_TDMOUT_B_CTRL0 4284753216 #define SEC_EE_AUDIO_TDMOUT_B_CTRL1 4284753220 #define SEC_RESET2_SEC_REGISTER 4284801032 #define AO_IR_DEC_LDR_IDLE 4286611460 #define SEC_EE_AUDIO_CLK_TDMOUT_B_CTRL 4284752020 #define SEC_MIPI_DSI_ANA_UP_TIM 4284760088 #define SEC_EE_AUDIO_FRDDR_B_CTRL0 4284752384 #define SEC_EE_AUDIO_FRDDR_B_CTRL1 4284752388 #define AO_MF_IR_DEC_STATUS2 4286611572 #define AO_MF_IR_DEC_STATUS1 4286611568 #define AO_MF_IR_DEC_LDR_REPEAT 4286611528 #define P_AO_RTI_PWR_SYS_CPUB_CNTL1 4286579532 #define P_AO_RTI_PWR_SYS_CPUB_CNTL0 4286579528 #define AO_RTI_STATUS_REG2 4286578696 #define AO_RTI_STATUS_REG3 4286578700 #define AO_RTI_STATUS_REG0 4286578688 #define AO_RTI_STATUS_REG1 4286578692 #define P_AMLUSB_A28 4284702832 #define P_AMLUSB_A27 4284702828 #define P_AMLUSB_A26 4284702824 #define P_HHI_VDEC_CLK_CNTL 4284727776 #define P_AMLUSB_A25 4284702820 #define P_AMLUSB_A24 4284702816 #define P_AMLUSB_A23 4284702812 #define P_AMLUSB_A22 4284702808 #define P_AMLUSB_A21 4284702804 #define P_AMLUSB_A20 4284702800 #define SEC_MIPI_ADAPT_ALIG_CNTL1 4284829892 #define SEC_MIPI_ADAPT_ALIG_CNTL0 4284829888 #define SEC_MIPI_ADAPT_ALIG_CNTL3 4284829900 #define SEC_MIPI_ADAPT_ALIG_CNTL2 4284829896 #define SEC_MIPI_ADAPT_ALIG_CNTL5 4284829908 #define SEC_MIPI_ADAPT_ALIG_CNTL4 4284829904 #define P_HHI_WAVE420L_CLK_CNTL2 4284727916 #define SEC_MIPI_ADAPT_ALIG_CNTL7 4284829916 #define SEC_MIPI_ADAPT_ALIG_CNTL6 4284829912 #define SEC_MIPI_ADAPT_ALIG_CNTL9 4284829924 #define SEC_MIPI_ADAPT_ALIG_CNTL8 4284829920 #define KL_RESP1_1 4284678308 #define KL_RESP1_0 4284678304 #define P_AMLUSB_A19 4284702796 #define KL_RESP1_3 4284678316 #define P_AMLUSB_A18 4284702792 #define KL_RESP1_2 4284678312 #define P_MIPI_ISP_WRARB_REQEN_SLV 4284842012 #define EE_AUDIO_CLK_SPDIFOUT_B_CTRL 4284752052 #define P_AMLUSB_A31 4284702844 #define P_AMLUSB_A30 4284702840 #define P_EE_AUDIO_SPDIFOUT_GAIN1 4284753032 #define P_EE_AUDIO_SPDIFOUT_GAIN0 4284753028 #define TS_DDR_CFG_REG5 4284697620 #define TS_DDR_CFG_REG4 4284697616 #define TS_DDR_CFG_REG7 4284697628 #define TS_DDR_CFG_REG6 4284697624 #define TS_DDR_CFG_REG1 4284697604 #define TS_DDR_CFG_REG3 4284697612 #define TS_DDR_CFG_REG2 4284697608 #define P_EE_AUDIO_CLK_TDMIN_B_CTRL 4284752004 #define P_AMLUSB_A29 4284702836 #define AO_SAR_ADC_DELAY 4286615568 #define AO_SEC_REG0 4286579008 #define P_AO_CPU_STAT1 4286578892 #define P_AO_CPU_STAT2 4286578896 #define P_EFUSE_LIC0 4284678192 #define P_EFUSE_LIC1 4284678196 #define P_EFUSE_LIC2 4284678200 #define RO_REF2OMCLK_CNT_H 4284784716 #define P_EFUSE_LIC3 4284678204 #define SEC_AO_CEC_STICKY_DATA1 4286579500 #define SEC_AO_CEC_STICKY_DATA2 4286579504 #define RO_REF2OMCLK_CNT_L 4284784712 #define SEC_AO_CEC_STICKY_DATA0 4286579496 #define SEC_AO_CEC_STICKY_DATA5 4286579516 #define SEC_AO_CEC_STICKY_DATA6 4286579520 #define SEC_AO_CEC_STICKY_DATA3 4286579508 #define SEC_AO_CEC_STICKY_DATA4 4286579512 #define P_AO_SAR_ADC_AVG_CNTL 4286615560 #define SEC_AO_CEC_STICKY_DATA7 4286579524 #define P_EE_AUDIO_FRDDR_A_START_ADDRB 4284752348 #define P_EE_AUDIO_TDMOUT_B_MUTE_VAL 4284753256 #define AO_CECB_RW_REG 4286579340 #define SEC_EE_AUDIO_TDMOUT_B_SWAP 4284753224 #define SEC_EE_AUDIO_FRDDR_A_START_ADDRB 4284752348 #define AO_MSG_INDEX3 4286579084 #define SEC_MIPI_ADAPT_IRQ_MASK1 4284830088 #define SEC_MIPI_ADAPT_IRQ_MASK0 4284830080 #define AO_MSG_INDEX0 4286579072 #define AO_MSG_INDEX1 4286579076 #define P_EE_AUDIO_FRDDR_C_INT_ADDR 4284752464 #define AO_MSG_INDEX2 4286579080 #define EE_AUDIO_TDMOUT_A_MASK_VAL 4284753212 #define AO_GEN_CLK_CNTL 4286578792 #define P_HHI_MIPIDSI_PHY_CLK_CNTL 4284727892 #define SEC_EFUSE_WDATA3 4284678172 #define SEC_EFUSE_WDATA2 4284678168 #define SEC_EFUSE_WDATA1 4284678164 #define SEC_EFUSE_WDATA0 4284678160 #define P_PDM_F1_CTRL 4284743692 #define P_AO_RTI_PWR_SYS_CPUB_MEM_PD0 4286579536 #define P_AO_RTI_PWR_SYS_CPUB_MEM_PD1 4286579540 #define SEC_EE_AUDIO_TDMOUT_C_MUTE_VAL 4284753320 #define P_AO_SAR_ADC_CHAN_10_SW 4286615584 #define PDM_COEFF_ADDR 4284743716 #define AUD_LOCK_INT_CTRL 4284784692 #define P_PDM_MUTE_VALUE 4284743732 #define SEC_EE_AUDIO_TODDR_C_CTRL0 4284752256 #define SEC_EE_AUDIO_TODDR_C_CTRL1 4284752260 #define P_EE_AUDIO_TDMIN_A_CTRL 4284752640 #define P_HHI_APICALGDC_CNTL 4284727656 #define AO_UART_REG5 4286590996 #define AO_MF_IR_DEC_STATUS 4286611544 #define SEC_AO_CEC_INTR_STAT 4286578960 #define MIPI_ADAPT_ALIG_CNTL6 4284829912 #define P_AO_SEC_SHARED_AHB_SRAM_REG2_0 4286579132 #define MIPI_ADAPT_ALIG_CNTL7 4284829916 #define P_AO_SEC_SHARED_AHB_SRAM_REG2_1 4286579136 #define MIPI_ADAPT_ALIG_CNTL8 4284829920 #define P_AO_SEC_SHARED_AHB_SRAM_REG2_2 4286579140 #define MIPI_ADAPT_ALIG_CNTL9 4284829924 #define MIPI_DSI_INIT_TIM 4284760092 #define SEC_HHI_CSI_PHY_CNTL0 4284728140 #define SEC_HHI_HDMI_PLL_STS 4284728124 #define SEC_HHI_CSI_PHY_CNTL2 4284728148 #define SEC_HHI_CSI_PHY_CNTL1 4284728144 #define SEC_HHI_CSI_PHY_CNTL4 4284728156 #define SEC_HHI_CSI_PHY_CNTL3 4284728152 #define MIPI_ISP_ARB_DBG_CTRL 4284842032 #define SEC_HHI_CSI_PHY_CNTL5 4284728160 #define AUD_LOCK_SW_LATCH 4284784648 #define EE_AUDIO_TDMOUT_C_MUTE_VAL 4284753320 #define P_EE_AUDIO_CLK_SPDIFOUT_CTRL 4284752032 #define SEC_AO_SAR_ADC_LAST_RD 4286615572 #define SEC_RESET0_SEC_LEVEL 4284801088 #define SEC_AO_UART2_MISC 4286595088 #define SEC_AO_IR_DEC_DEMOD_THD0 4286611660 #define SEC_AO_IR_DEC_DEMOD_THD1 4286611664 #define SEC_AO_UART_MISC 4286590992 #define EE_AUDIO_TDMIN_C_SWAP 4284752772 #define PDM_F3_CTRL 4284743700 #define SEC_AO_PWM_PWM_A 4286607360 #define SEC_AO_PWM_PWM_B 4286607364 #define SEC_AO_PWM_PWM_C 4286586880 #define SEC_AO_PWM_PWM_D 4286586884 #define P_HHI_HDMI_PHY_CNTL0 4284728224 #define P_HHI_HDMI_PHY_CNTL1 4284728228 #define P_HHI_HDMI_PHY_CNTL2 4284728232 #define P_HHI_HDMI_PHY_CNTL3 4284728236 #define AO_I2C_S_CONTROL_REG 4286603264 #define P_HHI_HDMI_PHY_CNTL4 4284728240 #define P_HHI_HDMI_PHY_CNTL5 4284728244 #define SEC_EE_AUDIO_SPDIFOUT_GAIN0 4284753028 #define SEC_EE_AUDIO_SPDIFOUT_GAIN1 4284753032 #define SEC_EE_AUDIO_SW_RESET 4284751908 #define SEC_MIPI_ISP_RDARB_WEIGH0_SLV 4284841992 #define P_RESET0_SEC_MASK 4284801152 #define MIPI_ADAPT_ALIG_CNTL2 4284829896 #define MIPI_ADAPT_ALIG_CNTL3 4284829900 #define MIPI_ADAPT_ALIG_CNTL4 4284829904 #define MIPI_ADAPT_ALIG_CNTL5 4284829908 #define AED_NG_CNT_THD 4284834272 #define MIPI_ADAPT_ALIG_CNTL0 4284829888 #define MIPI_ADAPT_ALIG_CNTL1 4284829892 #define SEC_EE_AUDIO_SPDIFIN_STAT1 4284752928 #define P_AED_DRC_AE_1M 4284834224 #define SEC_EE_AUDIO_SPDIFIN_STAT0 4284752924 #define SEC_EE_AUDIO_SPDIFIN_STAT2 4284752932 #define P_PERIPHS_LOCK_PAD 4284696248 #define SEC_PAD_PULL_UP_REG4 4284695800 #define SEC_PAD_PULL_UP_REG5 4284695804 #define P_AO_PWM_C2 4286586900 #define P_AO_AHB2DDR_CNTL 4286578784 #define SEC_PAD_PULL_UP_REG0 4284695784 #define SEC_PAD_PULL_UP_REG1 4284695788 #define SEC_PAD_PULL_UP_REG2 4284695792 #define SEC_PAD_PULL_UP_REG3 4284695796 #define KL_RESP0_0 4284678288 #define SEC_MIPI_OTHER_ST0 4284829992 #define SEC_MIPI_OTHER_ST1 4284829996 #define SEC_AO_TIMER_SEC_SP_CTRL 4286579656 #define KL_RESP0_2 4284678296 #define KL_RESP0_1 4284678292 #define KL_RESP0_3 4284678300 #define AO_SEC_JTAG_PWD_SCP_0 4286579420 #define AO_SEC_JTAG_PWD_SCP_2 4286579428 #define P_AO_PWM_D2 4286586904 #define AO_SEC_JTAG_PWD_SCP_1 4286579424 #define AO_SEC_JTAG_PWD_SCP_3 4286579432 #define EE_AUDIO_TDMOUT_C_MASK_VAL 4284753340 #define RNG_SEC_DATA 4284678672 #define P_AO_WATCHDOG_TCNT 4286578984 #define P_HHI_HDMI_PLL_CNTL4 4284728112 #define P_HHI_HDMI_PLL_CNTL5 4284728116 #define P_HHI_HDMI_PLL_CNTL6 4284728120 #define P_HHI_HDMI_PLL_CNTL0 4284728096 #define P_HHI_HDMI_PLL_CNTL1 4284728100 #define P_HHI_HDMI_PLL_CNTL2 4284728104 #define P_HHI_HDMI_PLL_CNTL3 4284728108 #define P_EE_AUDIO_CLK_SPDIFIN_CTRL 4284752028 #define P_DMA_SEC 4284735556 #define EE_AUDIO_SPDIFOUT_CTRL1 4284753040 #define SEC_EE_AUDIO_TORAM_FINISH_ADDR 4284753676 #define EE_AUDIO_SPDIFOUT_CTRL0 4284753036 #define SEC_EE_AUDIO_FRDDR_B_STATUS2 4284752408 #define SEC_EE_AUDIO_FRDDR_B_STATUS1 4284752404 #define SEC_HHI_VIPNANOQ_CLK_CNTL 4284727752 #define SEC_EE_AUDIO_MST_B_SCLK_CTRL1 4284751948 #define SEC_EE_AUDIO_MST_B_SCLK_CTRL0 4284751944 #define EE_AUDIO_CLK_TDMIN_A_CTRL 4284752000 #define SEC_AED_DRC_AD_1M_H 4284834324 #define P_EFUSE_CLK_A53_CFG01 4284696324 #define SEC_EE_AUDIO_SECURITY_CTRL 4284753484 #define SEC_EE_AUDIO_CLK_TDMIN_B_CTRL 4284752004 #define P_AO_PWM_A2 4286607380 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_2 4286579164 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_1 4286579160 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG4_0 4286579156 #define SEC_EE_AUDIO_FRDDR_A_START_ADDR 4284752328 #define P_AO_PWM_B2 4286607384 #define SEC_AO_RTI_GEN_CNTL_REG0 4286578752 #define SYS_CPUB_STATUS0 4284696512 #define SYS_CPUB_STATUS3 4284696524 #define SYS_CPUB_STATUS4 4284696528 #define SYS_CPUB_STATUS1 4284696516 #define SYS_CPUB_STATUS2 4284696520 #define P_EE_AUDIO_SPDIFOUT_B_GAIN0 4284753540 #define SYS_CPUB_STATUS5 4284696532 #define P_EE_AUDIO_SPDIFOUT_B_GAIN1 4284753544 #define P_M4_CPU_TIMESTAMP 4286579480 #define P_AMLUSB_B27 4284719212 #define P_AMLUSB_B26 4284719208 #define P_AMLUSB_B25 4284719204 #define P_AMLUSB_B24 4284719200 #define P_AMLUSB_B23 4284719196 #define P_AMLUSB_B22 4284719192 #define P_AMLUSB_B21 4284719188 #define P_AMLUSB_B20 4284719184 #define MIPI_ADAPT_DDR_RD0_ST2 4284829724 #define P_HHI_SYS_CPU_RESET_CNTL 4284727648 #define P_AMLUSB_B19 4284719180 #define P_AMLUSB_B18 4284719176 #define P_AMLUSB_B17 4284719172 #define P_AMLUSB_B31 4284719228 #define P_AMLUSB_B30 4284719224 #define SEC_AO_I2C_M_0_CONTROL_REG 4286599168 #define AO_SEC_JTAG_SP_CTRL 4286579376 #define P_PDM_COEFF_DATA 4284743720 #define MIPI_ADAPT_DDR_RD0_ST0 4284829716 #define MIPI_ADAPT_DDR_RD0_ST1 4284829720 #define P_AO_SEC_SHARED_AHB_SRAM_MASK_2 4286579104 #define P_AO_SEC_SHARED_AHB_SRAM_MASK_1 4286579100 #define P_AMLUSB_B29 4284719220 #define P_AMLUSB_B28 4284719216 #define SEC_AO_IRQ_GPIO_REG 4286578820 #define P_AO_SEC_SHARED_AHB_SRAM_MASK_0 4286579096 #define AED_TOP_CTL 4284834336 #define P_EE_AUDIO_FRDDR_A_INT_ADDR 4284752336 #define P_AMLUSB_B16 4284719168 #define SEC_RESET2_SEC_MASK 4284801160 #define P_AMLUSB_B15 4284719164 #define P_AMLUSB_B14 4284719160 #define P_AMLUSB_B13 4284719156 #define P_AMLUSB_B12 4284719152 #define P_AMLUSB_B11 4284719148 #define P_AMLUSB_B10 4284719144 #define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB 4284752416 #define AO_IR_DEC_LDR_REPEAT 4286611464 #define SEC_EE_AUDIO_FRDDR_C_INT_ADDR 4284752464 #define EE_AUDIO_TDMIN_C_MASK0 4284752776 #define EE_AUDIO_TDMIN_C_MASK2 4284752784 #define EE_AUDIO_TDMIN_C_MASK1 4284752780 #define EE_AUDIO_TDMIN_C_MASK3 4284752788 #define SYS_CPU_POR_CFG0 4284696128 #define P_HHI_GCLK_MPEG0 4284727616 #define P_HHI_GCLK_MPEG1 4284727620 #define P_HHI_GCLK_MPEG2 4284727624 #define SYS_CPU_POR_CFG1 4284696132 #define P_EE_AUDIO_TDMOUT_C_MUTE_VAL 4284753320 #define P_MALI_CFG0 4284695612 #define SEC_EFUSE_CFG_LOCK 4284696320 #define SEC_EE_AUDIO_ARB_CTRL 4284752512 #define AO_SAR_ADC_AUX_SW 4286615580 #define SEC_HHI_HDMI_PHY_STATUS 4284728248 #define M4_CPU_TIMESTAMP 4286579480 #define SEC_AO_TIMEBASE_CNTL 4286578788 #define P_AO_TIMERC_CUR_REG 4286579680 #define SEC_PDM_CTRL 4284743680 #define PERIPHS_LOCK_PAD 4284696248 #define AO_MF_IR_DEC_FRAME1 4286611564 #define HHI_SYS_CPU_RESET_CNTL 4284727648 #define P_HHI_GCLK_LOCK 4284727612 #define RNG_USR_STS 4284678684 #define SEC_PREG_PAD_GPIO5_I 4284695688 #define SEC_HHI_CDAC_CLK_CNTL 4284728280 #define AO_WRITE_ONCE1 4286579060 #define AO_WRITE_ONCE0 4286579056 #define P_SYS_CPUB_STATUS2 4284696520 #define P_SYS_CPUB_STATUS3 4284696524 #define AO_WRITE_ONCE2 4286579064 #define P_SYS_CPUB_STATUS4 4284696528 #define P_SYS_CPUB_STATUS5 4284696532 #define SEC_PREG_PAD_GPIO5_O 4284695684 #define SEC_HHI_TIMER90K 4284727548 #define SEC_AO_RTI_PWR_SYS_CPUB_CNTL1 4286579532 #define SEC_AO_RTI_PWR_SYS_CPUB_CNTL0 4286579528 #define P_AO_CECB_INTR_MASKN 4286579344 #define P_AUD_LOCK_HW_LATCH 4284784652 #define P_HHI_VDIN_MEAS_CLK_CNTL 4284727888 #define AO_TIMERE_REG 4286579684 #define P_SYS_CPUB_STATUS0 4284696512 #define P_SYS_CPUB_STATUS1 4284696516 #define SEC_MIPI_ISP_RDWR_ARB_STATUS 4284842028 #define P_EE_AUDIO_TODDR_C_FINISH_ADDRB 4284752288 #define P_EE_AUDIO_TDMIN_A_STAT 4284752664 #define SEC_AO_IR_DEC_DEMOD_IIR_THD 4286611656 #define P_RO_REFCLK_PKG_CNT 4284784736 #define SEC_AO_PWM_DELTA_SIGMA_AB 4286607372 #define SEC_EE_AUDIO_SPDIFOUT_SWAP 4284753048 #define SEC_EE_AUDIO_CLK_PDMIN_CTRL1 4284752048 #define SEC_HHI_GCLK_OTHER 4284727632 #define SEC_EE_AUDIO_CLK_PDMIN_CTRL0 4284752044 #define SEC_RESET0_SEC_MASK 4284801152 #define P_MIPI_DSI_ANA_UP_TIM 4284760088 #define AO_SAR_ADC_AVG_CNTL 4286615560 #define SECE_TIMER_HIG 4284696108 #define P_HHI_HDMI_PLL_STS 4284728124 #define P_AO_OSCIN_CNTL 4286578776 #define AO_TIMER_SEC_SCP_CTRL 4286579652 #define SEC_HHI_SD_EMMC_CLK_CNTL 4284727908 #define SEC_AO_PWM_DELTA_SIGMA_CD 4286586892 #define MIPI_ISP_ARB_DBG_STAT 4284842036 #define SEC_AUD_LOCK_IMCLK_LAT_INT 4284784664 #define P_AO_SEC_SHARED_AHB_SRAM_REG1_0 4286579120 #define HHI_MIPI_CNTL1 4284727300 #define P_AO_SEC_SHARED_AHB_SRAM_REG1_1 4286579124 #define HHI_MIPI_CNTL2 4284727304 #define P_AO_SEC_SHARED_AHB_SRAM_REG1_2 4286579128 #define HHI_MIPI_CNTL0 4284727296 #define SEC_AUD_LOCK_HW_LATCH 4284784652 #define SEC_DMA_CFG 4284735552 #define SEC_RO_AUD_LOCK_INT_STATUS 4284784748 #define SEC_AO_CPU_CNTL 4286578744 #define P_RESET0_SEC_LEVEL 4284801088 #define SEC_EE_AUDIO_TDMIN_A_MASK3 4284752660 #define SEC_EE_AUDIO_TDMIN_A_MASK1 4284752652 #define P_MIPI_DSI_ULPS_CHECK 4284760120 #define SEC_EE_AUDIO_TDMIN_A_MASK2 4284752656 #define EE_AUDIO_FRDDR_B_INIT_ADDR 4284752420 #define SEC_EE_AUDIO_TDMIN_A_MASK0 4284752648 #define P_BUS_MON0_DATA 4284696076 #define ETH_PHY_STS2 4284792988 #define ETH_PHY_STS1 4284792984 #define ETH_PHY_STS0 4284792980 #define EE_AUDIO_TDMIN_A_CTRL 4284752640 #define P_AO_METAL_REVISION_1 4286578760 #define P_TS_DDR_STAT7 4284697692 #define P_TS_DDR_STAT6 4284697688 #define P_TS_DDR_STAT9 4284697700 #define P_TS_DDR_STAT8 4284697696 #define EE_AUDIO_TDMOUT_B_MUTE_VAL 4284753256 #define P_TS_DDR_STAT1 4284697668 #define P_TS_DDR_STAT0 4284697664 #define P_TS_DDR_STAT3 4284697676 #define P_TS_DDR_STAT2 4284697672 #define P_TS_DDR_STAT5 4284697684 #define P_TS_DDR_STAT4 4284697680 #define EE_AUDIO_PAD_CTRL0 4284751900 #define P_BUS_MONITOR_CNTL 4284696068 #define EE_AUDIO_PAD_CTRL1 4284751904 #define SEC_HHI_VIID_CLK_CNTL 4284727596 #define SEC_AO_CECB_INTR_STAT 4286579352 #define HHI_VIPNANOQ_CNTL 4284727748 #define P_EE_AUDIO_TDMOUT_A_MASK_VAL 4284753212 #define P_EE_AUDIO_TODDR_B_START_ADDR 4284752200 #define P_PREG_PAD_GPIO2_EN_N 4284695640 #define AO_I2C_S_CNTL1_REG 4286603276 #define SEC_AO_SAR_ADC_AVG_CNTL 4286615560 #define P_AO_UART_WFIFO 4286590976 #define P_AO_MF_IR_DEC_FRAME_RSV1 4286611584 #define P_AO_MF_IR_DEC_FRAME_RSV0 4286611580 #define SEC_PERIPHS_LOCK_PAD 4284696248 #define EE_AUDIO_TODDR_C_STATUS1 4284752276 #define EE_AUDIO_TODDR_C_STATUS2 4284752280 #define HHI_TS_CLK_CNTL 4284727696 #define EE_AUDIO_TDMOUT_B_MUTE1 4284753264 #define EE_AUDIO_TDMOUT_B_MUTE0 4284753260 #define EE_AUDIO_TDMOUT_B_MUTE3 4284753272 #define EE_AUDIO_TDMOUT_B_MUTE2 4284753268 #define SEC_AO_CPU_CNTL5 4286578964 #define SEC_AO_CPU_CNTL2 4286578748 #define SEC_AO_CPU_CNTL4 4286578940 #define SEC_AO_CPU_CNTL3 4286578908 #define P_EE_AUDIO_TDMIN_B_MUTE0 4284752736 #define P_EE_AUDIO_TDMIN_B_MUTE1 4284752740 #define P_EE_AUDIO_TDMIN_B_MUTE2 4284752744 #define P_AED_DRC_THD0 4284834244 #define P_EE_AUDIO_TDMIN_B_MUTE3 4284752748 #define P_AED_DRC_THD1 4284834248 #define EE_AUDIO_CLK_RESAMPLE_CTRL 4284752036 #define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDRB 4284752416 #define SEC_AO_CEC_INTR_CLR 4286578956 #define P_AO_CEC_STICKY_DATA0 4286579496 #define P_AO_CEC_STICKY_DATA1 4286579500 #define P_AO_CEC_STICKY_DATA2 4286579504 #define P_AO_CEC_STICKY_DATA3 4286579508 #define P_AO_CEC_STICKY_DATA4 4286579512 #define EE_AUDIO_CLK_TDMOUT_B_CTRL 4284752020 #define P_AO_CEC_STICKY_DATA5 4286579516 #define P_AO_CEC_STICKY_DATA6 4286579520 #define P_AO_CEC_STICKY_DATA7 4286579524 #define EE_AUDIO_TDMOUT_A_STAT 4284753180 #define HHI_WAVE420L_CLK_CNTL2 4284727916 #define SEC_EE_AUDIO_MCLK_B_CTRL 4284751880 #define P_HHI_VIID_CLK_CNTL 4284727596 #define AO_TIMER_CTRL 4286579648 #define P_MIPI_DSI_INIT_TIM 4284760092 #define SEC_AO_TIMERA_REG 4286579660 #define P_PAD_PULL_UP_EN_REG5 4284695860 #define P_EE_AUDIO_MST_F_SCLK_CTRL1 4284751980 #define P_PAD_PULL_UP_EN_REG4 4284695856 #define P_EE_AUDIO_MST_F_SCLK_CTRL0 4284751976 #define P_PAD_PULL_UP_EN_REG3 4284695852 #define P_PAD_PULL_UP_EN_REG2 4284695848 #define P_PAD_PULL_UP_EN_REG1 4284695844 #define P_PAD_PULL_UP_EN_REG0 4284695840 #define SEC_HHI_VID_PLL_CLK_DIV 4284727712 #define P_MIPI_DSI_CHAN_CTRL 4284760068 #define HHI_VIPNANOQ_CLK_CNTL 4284727752 #define P_AO_UART_REG5 4286590996 #define ETH_PHY_DBG_REG 4284792992 #define P_AO_SAR_ADC_FIFO_RD 4286615576 #define EE_AUDIO_TODDR_B_FINISH_ADDR 4284752204 #define BUS_MON1_ADDR 4284696084 #define P_AO_I2C_S_CNTL1_REG 4286603276 #define MIPI_ISP_RDARB_LIMT0 4284842004 #define AO_UART_MISC 4286590992 #define AO_I2C_S_RECV_REG 4286603272 #define P_AO_RTI_PWR_SYS_CPU_CNTL0 4286578912 #define P_AO_RTI_PWR_SYS_CPU_CNTL1 4286578916 #define SEC_HHI_MIPI_STS 4284727308 #define P_PREG_PAD_GPIO4_EN_N 4284695664 #define SEC_AUD_LOCK_REFCLK_DS_INT 4284784672 #define HHI_VID_CLK_DIV 4284727652 #define SEC_AO_PWM_LOCK_AB 4286607392 #define SEC_HHI_XTAL_DIVN_CNTL 4284727484 #define PAD_DS_REG4A 4284696404 #define HHI_VDAC_CNTL0 4284728044 #define PAD_DS_REG3A 4284696400 #define SEC_AO_UART_REG5 4286590996 #define HHI_VDAC_CNTL1 4284728048 #define EE_AUDIO_SPDIFOUT_B_CHSTS8 4284753596 #define EE_AUDIO_SPDIFOUT_B_CHSTS7 4284753592 #define EE_AUDIO_SPDIFOUT_B_CHSTS9 4284753600 #define EE_AUDIO_SPDIFOUT_B_CHSTS4 4284753580 #define EE_AUDIO_SPDIFOUT_B_CHSTS3 4284753576 #define EE_AUDIO_SPDIFOUT_B_CHSTS6 4284753588 #define EE_AUDIO_SPDIFOUT_B_CHSTS5 4284753584 #define SEC_BUS_STS0 4284695960 #define EE_AUDIO_SPDIFOUT_B_CHSTS0 4284753564 #define EE_AUDIO_SPDIFOUT_B_CHSTS2 4284753572 #define EE_AUDIO_MST_A_SCLK_CTRL0 4284751936 #define EE_AUDIO_SPDIFOUT_B_CHSTS1 4284753568 #define EE_AUDIO_MST_A_SCLK_CTRL1 4284751940 #define SEC_BUS_STS5 4284695980 #define SEC_BUS_STS6 4284695984 #define SEC_BUS_STS7 4284695988 #define SEC_BUS_STS8 4284695992 #define SEC_BUS_STS1 4284695964 #define P_HHI_SD_EMMC_CLK_CNTL 4284727908 #define SEC_BUS_STS2 4284695968 #define SEC_BUS_STS3 4284695972 #define SEC_BUS_STS4 4284695976 #define EE_AUDIO_MST_F_SCLK_CTRL1 4284751980 #define SEC_BUS_STS9 4284695996 #define EE_AUDIO_MST_F_SCLK_CTRL0 4284751976 #define EE_AUDIO_TDMIN_C_STAT 4284752792 #define P_AO_RTI_PULL_UP_EN_REG 4286578736 #define PAD_DS_REG5A 4284696408 #define SEC_MIPI_DSI_INIT_TIM 4284760092 #define EE_AUDIO_SPDIFOUT_B_CHSTSB 4284753608 #define EE_AUDIO_SPDIFOUT_B_CHSTSA 4284753604 #define SEC_EFUSE_CLK_A53_CFG01 4284696324 #define EE_AUDIO_TDMOUT_A_MUTE_VAL 4284753192 #define SEC_PDM_F2_CTRL 4284743696 #define P_EFUSE_CLK_A73_CFG01 4284696344 #define SEC_EE_AUDIO_POW_DET_CTRL0 4284753408 #define SEC_EE_AUDIO_POW_DET_CTRL1 4284753412 #define PAD_DS_REG0A 4284696384 #define SEC_EE_AUDIO_TODDR_B_CTRL1 4284752196 #define SEC_EE_AUDIO_TODDR_B_CTRL0 4284752192 #define P_MIPI_ADAPT_ALIG_CNTL0 4284829888 #define P_MIPI_ADAPT_ALIG_CNTL4 4284829904 #define P_MIPI_ADAPT_ALIG_CNTL3 4284829900 #define P_MIPI_ADAPT_ALIG_CNTL2 4284829896 #define P_MIPI_ADAPT_ALIG_CNTL1 4284829892 #define P_MIPI_ADAPT_ALIG_CNTL8 4284829920 #define P_MIPI_ADAPT_ALIG_CNTL7 4284829916 #define P_MIPI_ADAPT_ALIG_CNTL6 4284829912 #define P_MIPI_ADAPT_ALIG_CNTL5 4284829908 #define P_MIPI_ADAPT_ALIG_CNTL9 4284829924 #define SEC_PREG_PAD_GPIO4_I 4284695672 #define SEC_PREG_PAD_GPIO4_O 4284695668 #define DDR_RD0_LBUF_STATUS 4284830016 #define P_AO_IR_BLASTER_ADDR3 4286579032 #define P_AO_IR_BLASTER_ADDR2 4286579028 #define P_AO_IR_BLASTER_ADDR1 4286579024 #define P_AO_IR_BLASTER_ADDR0 4286579020 #define EE_AUDIO_TODDR_A_INT_ADDR 4284752144 #define PAD_DS_REG2A 4284696392 #define PAD_DS_REG2B 4284696396 #define P_AO_TIMERG_REG 4286579700 #define P_AO_RTI_PINMUX_REG0 4286578708 #define SEC_MIPI_DSI_LPOK_TIM 4284760100 #define PAD_DS_REG1A 4284696388 #define P_AO_RTI_PINMUX_REG1 4286578712 #define SEC_RESET1_SEC_MASK 4284801156 #define SEC_DMA_SEC 4284735556 #define HHI_VIID_CLK_DIV 4284727592 #define P_EE_AUDIO_TDMOUT_B_MASK_VAL 4284753276 #define MIPI_DSI_CHAN_CTRL 4284760068 #define SEC_AO_SEC_JTAG_PWD_SCP_3 4286579432 #define P_MIPI_ADAPT_DDR_RD1_ST2 4284829788 #define P_EE_AUDIO_RESAMPLE_COEF4 4284752992 #define P_MIPI_ADAPT_DDR_RD1_ST1 4284829784 #define P_EE_AUDIO_RESAMPLE_COEF2 4284752984 #define P_MIPI_ADAPT_DDR_RD1_ST0 4284829780 #define P_EE_AUDIO_RESAMPLE_COEF3 4284752988 #define SEC_AO_SEC_JTAG_PWD_SCP_1 4286579424 #define P_EE_AUDIO_RESAMPLE_COEF0 4284752976 #define SEC_AO_SEC_JTAG_PWD_SCP_2 4286579428 #define P_EE_AUDIO_RESAMPLE_COEF1 4284752980 #define SEC_AO_SEC_JTAG_PWD_SCP_0 4286579420 #define HHI_APICALGDC_CNTL 4284727656 #define P_HHI_AXI_PIPEL_CNTL 4284728272 #define AO_WATCHDOG_RESET 4286578988 #define AO_SEC_JTAG_PWD_SCP_ADDR0 4286579440 #define AO_SEC_JTAG_PWD_SCP_ADDR1 4286579444 #define P_EE_AUDIO_FRDDR_A_START_ADDR 4284752328 #define SEC_EE_AUDIO_TDMIN_C_CTRL 4284752768 #define AO_SEC_JTAG_PWD_SCP_ADDR2 4286579448 #define AO_SEC_JTAG_PWD_SCP_ADDR3 4286579452 #define SEC_SYS_CPUB_STATUS2 4284696520 #define SEC_SYS_CPUB_STATUS1 4284696516 #define SEC_SYS_CPUB_STATUS0 4284696512 #define AO_IR_BLASTER_ADDR0 4286579020 #define AO_IR_BLASTER_ADDR1 4286579024 #define AO_IR_BLASTER_ADDR2 4286579028 #define AO_IR_BLASTER_ADDR3 4286579032 #define PREG_PAD_GPIO5_I 4284695688 #define SEC_ETH_PHY_CNTL0 4284792960 #define SEC_AO_UART2_WFIFO 4286595072 #define SEC_ETH_PHY_CNTL2 4284792968 #define SEC_ETH_PHY_CNTL1 4284792964 #define AO_CPU_CNTL5 4286578964 #define MIPI_ADAPT_PIXEL0_CNTL0 4284829824 #define AO_CPU_CNTL4 4286578940 #define AO_CPU_CNTL3 4286578908 #define AO_CPU_CNTL2 4286578748 #define EE_AUDIO_TDMIN_A_MUTE1 4284752676 #define EE_AUDIO_TDMIN_A_MUTE0 4284752672 #define MIPI_ADAPT_PIXEL0_CNTL1 4284829828 #define EE_AUDIO_TDMIN_A_MUTE3 4284752684 #define EE_AUDIO_TDMIN_A_MUTE2 4284752680 #define SEC_SYS_CPUB_STATUS5 4284696532 #define SEC_SYS_CPUB_STATUS4 4284696528 #define SEC_SYS_CPUB_STATUS3 4284696524 #define PREG_PAD_GPIO5_O 4284695684 #define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_0 4286579096 #define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_1 4286579100 #define SEC_AO_SEC_SHARED_AHB_SRAM_MASK_2 4286579104 #define SEC_M4_CPU_CNTL_NS 4286579460 #define SEC_EE_AUDIO_SPDIFIN_CTRL3 4284752908 #define SEC_EE_AUDIO_SPDIFIN_CTRL4 4284752912 #define SEC_EE_AUDIO_SPDIFIN_CTRL5 4284752916 #define SEC_EE_AUDIO_SPDIFIN_CTRL6 4284752920 #define P_EE_AUDIO_TORAM_START_ADDR 4284753672 #define SEC_EE_AUDIO_SPDIFIN_CTRL0 4284752896 #define SEC_EE_AUDIO_SPDIFIN_CTRL1 4284752900 #define P_EE_AUDIO_MCLK_E_CTRL 4284751892 #define SEC_EE_AUDIO_SPDIFIN_CTRL2 4284752904 #define AO_RTI_STICKY_REG3 4286579004 #define SEC_AO_MF_IR_DEC_STATUS 4286611544 #define AO_RTI_STICKY_REG0 4286578992 #define P_EE_AUDIO_TODDR_B_INIT_ADDR 4284752228 #define AO_RTI_STICKY_REG2 4286579000 #define AO_RTI_STICKY_REG1 4286578996 #define EE_AUDIO_TDMOUT_A_GAIN0 4284753184 #define EE_AUDIO_TDMOUT_A_GAIN1 4284753188 #define P_PDM_HPF_CTRL 4284743704 #define EFUSE_RDATA3 4284678188 #define SEC_HHI_SYS_CPUB_CLK_CNTL 4284727816 #define EFUSE_RDATA1 4284678180 #define EFUSE_RDATA2 4284678184 #define EFUSE_RDATA0 4284678176 #define SEC_AED_EQ_VOLUME_SLEW_CNT 4284834200 #define MALI_CFG0 4284695612 #define SEC_AO_I2C_S_CONTROL_REG 4286603264 #define SEC_RO_REFCLK_PKG_CNT 4284784736 #define P_EE_AUDIO_TDMOUT_A_SWAP 4284753160 #define SEC_PREG_NAND_CFG_KEY0 4284695880 #define SEC_MIPI_ISP_ARB_DBG_CTRL 4284842032 #define SEC_PREG_NAND_CFG_KEY1 4284695884 #define P_AO_TIMEBASE_CNTL 4286578788 #define SEC_SYS_CPU_CFG10 4284696176 #define SEC_AO_SEC_JTAG_SP_CTRL 4286579376 #define SEC_ETH_PHY_STS1 4284792984 #define SEC_ETH_PHY_STS0 4284792980 #define SEC_ETH_PHY_STS2 4284792988 #define SEC_EE_AUDIO_TDMOUT_A_MASK2 4284753172 #define SEC_EE_AUDIO_TDMOUT_A_MASK3 4284753176 #define AO_RTI_GEN_PWR_SLEEP0 4286578920 #define SEC_EE_AUDIO_TDMOUT_A_MASK0 4284753164 #define SEC_EE_AUDIO_TDMOUT_A_MASK1 4284753168 #define SEC_RNG_USR_DATA 4284678680 #define SEC_PAD_PULL_UP_EN_REG1 4284695844 #define SEC_PAD_PULL_UP_EN_REG0 4284695840 #define SEC_PAD_PULL_UP_EN_REG3 4284695852 #define AO_SAR_ADC_REG12 4286615600 #define SEC_PAD_PULL_UP_EN_REG2 4284695848 #define AO_SAR_ADC_REG13 4286615604 #define P_MIPI_ADAPT_PIXEL0_ST0 4284829864 #define SEC_PAD_PULL_UP_EN_REG5 4284695860 #define P_MIPI_ADAPT_PIXEL0_ST1 4284829868 #define SEC_PAD_PULL_UP_EN_REG4 4284695856 #define AO_SAR_ADC_REG11 4286615596 #define AO_TIMERB_CUR_REG 4286579672 #define SYS_CPUB_MISC 4284696544 #define SEC_DDR_RD1_LBUF_STATUS 4284830020 #define AED_DRC_AE_1M 4284834224 #define P_EE_AUDIO_TODDR_C_FINISH_ADDR 4284752268 #define AO_SAR_ADC_FIFO_RD 4286615576 #define P_ETH_PHY_DBG_REG 4284792992 #define P_EE_AUDIO_FRDDR_B_INT_ADDR 4284752400 #define SEC_AED_DRC_AD_H 4284834316 #define AED_EQ_EN 4284834192 #define P_EE_AUDIO_FRDDR_C_FINISH_ADDR 4284752460 #define SEC_PAD_DS_REG5A 4284696408 #define SEC_AO_RTI_PWR_SYS_CPU_CNTL1 4286578916 #define SEC_AO_RTI_PWR_SYS_CPU_CNTL0 4286578912 #define SEC_EFUSE_RDATA2 4284678184 #define SEC_EFUSE_RDATA1 4284678180 #define SEC_EFUSE_RDATA3 4284678188 #define HHI_MIPI_STS 4284727308 #define SEC_SYS_CPU_MISC 4284696224 #define P_HHI_TIMER90K 4284727548 #define P_EE_AUDIO_ARB_CTRL 4284752512 #define SEC_EE_AUDIO_SPDIFOUT_B_GAIN0 4284753540 #define SEC_EE_AUDIO_SPDIFOUT_B_GAIN1 4284753544 #define AED_DRC_K1 4284834256 #define SEC_AO_METAL_REVISION_1 4286578760 #define AED_DRC_K0 4284834252 #define EE_AUDIO_MCLK_C_CTRL 4284751884 #define PREG_PAD_GPIO2_EN_N 4284695640 #define SEC_AO_UART2_REG5 4286595092 #define P_MIPI_ISP_RDARB_WEIGH0_SLV 4284841992 #define HHI_MIPI_CSI_PHY_CLK_CNTL 4284728128 #define P_AO_IR_DEC_LDR_REPEAT 4286611464 #define P_HHI_SYS_CPUB_CLK_CNTL1 4284727808 #define SEC_EFUSE_RDATA0 4284678176 #define P_AO_MF_IR_DEC_STATUS 4286611544 #define SEC_AO_MF_IR_DEC_FRAME 4286611540 #define P_HHI_MIPI_CSI_PHY_CLK_CNTL 4284728128 #define AED_DRC_EN 4284834208 #define RO_IMCLK_PKG_CNT 4284784740 #define SEC_EE_AUDIO_TDMOUT_A_MUTE_VAL 4284753192 #define SEC_AO_IR_DEC_LDR_ACTIVE 4286611456 #define P_ACODEC_0 4284686336 #define AO_TIMERC_CUR_REG 4286579680 #define P_ACODEC_1 4284686340 #define P_ACODEC_2 4284686344 #define P_ACODEC_3 4284686348 #define P_ACODEC_4 4284686352 #define P_ACODEC_5 4284686356 #define P_ACODEC_6 4284686360 #define P_ACODEC_7 4284686364 #define P_AO_MF_IR_DEC_FRAME1 4286611564 #define SEC_RNG_SEC_STS 4284678676 #define P_MIPI_DSI_HS_TIM 4284760080 #define P_AO_SAR_ADC_DELAY 4286615568 #define SEC_BUS_CFG7 4284695580 #define SEC_BUS_CFG8 4284695584 #define SEC_BUS_CFG9 4284695588 #define SEC_BUS_CFG3 4284695564 #define SEC_BUS_CFG4 4284695568 #define SEC_BUS_CFG5 4284695572 #define SEC_BUS_CFG6 4284695576 #define AED_DRC_AE 4284834212 #define AED_DRC_AD 4284834220 #define P_AO_IR_DEC_DEMOD_THD0 4286611660 #define P_AO_PWM_DELTA_SIGMA_CD 4286586892 #define P_AO_IR_DEC_DEMOD_THD1 4286611664 #define P_AO_GPIO_O_EN_N 4286578724 #define SEC_SYS_CPU_POR_CFG1 4284696132 #define SEC_SYS_CPU_POR_CFG0 4284696128 #define SYS_CPU_MISC 4284696224 #define AED_DRC_AA 4284834216 #define SEC_EE_AUDIO_TODDR_A_START_ADDRB 4284752156 #define P_AO_SEC_JTAG_SP_CTRL 4286579376 #define EE_AUDIO_TORAM_INT_ADDR 4284753680 #define AO_MAILBOX_SET_1 4286619664 #define AO_MAILBOX_SET_2 4286619676 #define AO_MAILBOX_SET_3 4286619688 #define SEC_EE_AUDIO_MST_D_SCLK_CTRL0 4284751960 #define AO_MAILBOX_SET_0 4286619652 #define SEC_EE_AUDIO_MST_D_SCLK_CTRL1 4284751964 #define SEC_AO_WATCHDOG_CNTL 4286578976 #define SEC_BUS_CFG0 4284695552 #define SEC_BUS_CFG1 4284695556 #define SEC_BUS_CFG2 4284695560 #define P_AO_PWM_DELTA_SIGMA_AB 4286607372 #define SEC_EE_AUDIO_CLK_RESAMPLE_CTRL 4284752036 #define P_EE_AUDIO_TDMOUT_A_MASK0 4284753164 #define P_EE_AUDIO_TDMOUT_A_MASK1 4284753168 #define P_EE_AUDIO_TDMOUT_A_MASK2 4284753172 #define P_EE_AUDIO_TDMOUT_A_MASK3 4284753176 #define SEC_AO_SAR_ADC_DETECT_IDLE_SW 4286615588 #define SEC_PROD_TEST_REG0 4284695936 #define BUS_MON0_ADDR 4284696072 #define SEC_PROD_TEST_REG1 4284695940 #define SEC_PROD_TEST_REG2 4284695944 #define SEC_PROD_TEST_REG3 4284695948 #define AED_DRC_AD_H 4284834316 #define P_AO_SEC_SHARED_AHB_SRAM_REG0_1 4286579112 #define P_AO_SEC_SHARED_AHB_SRAM_REG0_2 4286579116 #define P_EE_AUDIO_LB_DAT_CH_ID0 4284752584 #define P_EE_AUDIO_LB_DAT_CH_ID1 4284752588 #define P_AO_SEC_SHARED_AHB_SRAM_REG0_0 4286579108 #define SEC_EE_AUDIO_FRDDR_C_START_ADDR 4284752456 #define HHI_SYS1_PLL_CNTL0 4284728192 #define P_AO_CPU_CNTL_NS 4286578756 #define HHI_SYS1_PLL_CNTL1 4284728196 #define SEC_MIPI_ISP_WRARB_REQEN_SLV 4284842012 #define HHI_SYS1_PLL_CNTL2 4284728200 #define RESET1_SEC_REGISTER 4284801028 #define RNG_USR_DATA 4284678680 #define EE_AUDIO_FRDDR_B_STATUS1 4284752404 #define EE_AUDIO_FRDDR_B_STATUS2 4284752408 #define SEC_AUD_LOCK_SW_RESET 4284784644 #define P_AED_DRC_AA_H 4284834312 #define HHI_NAND_CLK_CNTL 4284727900 #define SEC_MIPI_DSI_LP_WCHDOG 4284760104 #define HHI_ETH_CLK_CNTL 4284727768 #define HHI_SYS1_PLL_CNTL3 4284728204 #define HHI_SYS1_PLL_CNTL4 4284728208 #define HHI_SYS1_PLL_CNTL5 4284728212 #define HHI_SYS1_PLL_CNTL6 4284728216 #define SEC_PREG_PAD_GPIO3_O 4284695656 #define SEC_PREG_PAD_GPIO3_I 4284695660 #define P_EE_AUDIO_TDMIN_LB_MUTE3 4284752876 #define P_EE_AUDIO_TDMIN_LB_MUTE2 4284752872 #define P_EE_AUDIO_TDMIN_LB_MUTE1 4284752868 #define P_EE_AUDIO_TDMIN_LB_MUTE0 4284752864 #define AO_CECB_INTR_CLR 4286579348 #define SEC_EFUSE_START 4284678148 #define SEC_AO_MF_IR_DEC_DURATN3 4286611560 #define SEC_AO_MF_IR_DEC_DURATN2 4286611556 #define HHI_GP0_PLL_STS 4284727388 #define P_HHI_VIID_CLK_DIV 4284727592 #define EE_AUDIO_MCLK_E_CTRL 4284751892 #define HHI_SYS_CPUB_RESET_CNTL 4284727812 #define SEC_EE_AUDIO_TDMIN_C_MUTE0 4284752800 #define SEC_EE_AUDIO_TDMIN_C_MUTE1 4284752804 #define SEC_AUD_LOCK_IMCLK_DS_INT 4284784676 #define SEC_EE_AUDIO_TDMIN_C_MUTE2 4284752808 #define SEC_EE_AUDIO_TDMIN_C_MUTE3 4284752812 #define P_AED_DRC_AD_1M 4284834232 #define SEC_EE_AUDIO_TDMIN_C_MUTE_VAL 4284752796 #define AO_UART2_REG5 4286595092 #define EE_AUDIO_MST_D_SCLK_CTRL1 4284751964 #define EE_AUDIO_MST_D_SCLK_CTRL0 4284751960 #define P_HHI_MPLL_CNTL8 4284727960 #define P_HHI_MPLL_CNTL7 4284727956 #define P_HHI_MPLL_CNTL6 4284727952 #define EE_AUDIO_TODDR_C_INT_ADDR 4284752272 #define P_AO_SAR_CLK 4286578832 #define P_HHI_MPLL_CNTL1 4284727932 #define P_HHI_MPLL_CNTL0 4284727928 #define AUD_LOCK_INT_CLR 4284784684 #define P_HHI_MPLL_CNTL5 4284727948 #define P_HHI_MPLL_CNTL4 4284727944 #define P_HHI_MPLL_CNTL3 4284727940 #define P_HHI_MPLL_CNTL2 4284727936 #define SEC_SYS_CPUB_MISC 4284696544 #define EE_AUDIO_TORAM_INIT_ADDR 4284753692 #define SEC_EE_AUDIO_TODDR_B_START_ADDR 4284752200 #define P_AO_IR_DEC_STATUS 4286611480 #define MIPI_DSI_LP_TIM 4284760084 #define SEC_AO_RTI_STICKY_REG0 4286578992 #define SEC_AO_RTI_STICKY_REG3 4286579004 #define SEC_AO_RTI_STICKY_REG1 4286578996 #define SEC_AO_RTI_STICKY_REG2 4286579000 #define SEC_EE_AUDIO_TDMIN_B_MASK0 4284752712 #define EE_AUDIO_TDMIN_A_MASK0 4284752648 #define SEC_EE_AUDIO_TDMIN_B_MASK1 4284752716 #define EE_AUDIO_TDMIN_A_MASK1 4284752652 #define SEC_EE_AUDIO_TODDR_A_STATUS2 4284752152 #define SEC_EE_AUDIO_TDMIN_B_MASK2 4284752720 #define EE_AUDIO_TDMIN_A_MASK2 4284752656 #define SEC_EE_AUDIO_TDMIN_B_MASK3 4284752724 #define SEC_EE_AUDIO_TODDR_A_STATUS1 4284752148 #define EE_AUDIO_LB_DAT_CH_ID0 4284752584 #define EE_AUDIO_LB_DAT_CH_ID1 4284752588 #define EE_AUDIO_TODDR_C_FINISH_ADDRB 4284752288 #define EE_AUDIO_TDMIN_A_MASK3 4284752660 #define P_EE_AUDIO_FRDDR_C_START_ADDR 4284752456 #define SEC_AO_MF_IR_DEC_STATUS2 4286611572 #define P_DDR_RD0_LBUF_STATUS 4284830016 #define AO_SEC_JTAG_PWD_SP_CNTL 4286579396 #define SEC_AO_MF_IR_DEC_STATUS1 4286611568 #define P_HHI_SYS_PLL_STS 4284728080 #define HHI_CCI_CLK_CNTL 4284727724 #define ETH_PLL_STS 4284792896 #define SEC_EE_AUDIO_FRDDR_C_START_ADDRB 4284752476 #define P_MIPI_ISP_WRARB_WEIGH0_SLV 4284842016 #define SEC_EE_AUDIO_FRDDR_B_INIT_ADDR 4284752420 #define P_HHI_MPLL_STS 4284727964 #define P_AO_TIMESTAMP_RD1 4286578876 #define P_AO_TIMESTAMP_RD0 4286578872 #define SEC_M4_CPU_STAT1 4286579488 #define SEC_M4_CPU_STAT2 4286579492 #define RO_IMCLK2REF_CNT_H 4284784724 #define SYS_CPUB_CFG10 4284696496 #define RO_IMCLK2REF_CNT_L 4284784720 #define SEC_AO_CLK_GATE0_SP 4286578768 #define SEC_MIPI_ADAPT_PIXEL0_CNTL1 4284829828 #define EE_AUDIO_SPDIFOUT_SWAP 4284753048 #define SEC_MIPI_ADAPT_PIXEL0_CNTL0 4284829824 #define SEC_EE_AUDIO_FRDDR_C_INIT_ADDR 4284752484 #define SEC_PDM_CHAN_CTRL 4284743708 #define AED_NG_THD0 4284834264 #define AED_NG_THD1 4284834268 #define P_HHI_HDCP22_CLK_CNTL 4284727792 #define AO_SEC_M4_CPU_SRAM_REG1_1 4286579368 #define AO_SEC_M4_CPU_SRAM_REG1_0 4286579364 #define SEC_HHI_VAPBCLK_CNTL 4284727796 #define P_AO_I2C_M_0_WDATA_REG0 4286599184 #define P_AO_I2C_M_0_WDATA_REG1 4286599188 #define SEC_AO_SAR_ADC_CHNL67 4286615620 #define P_MIPI_DSI_PHY_CTRL 4284760064 #define EE_AUDIO_FRDDR_A_FINISH_ADDR 4284752332 #define SEC_EE_AUDIO_TODDR_A_CTRL0 4284752128 #define SEC_EE_AUDIO_TODDR_A_CTRL1 4284752132 #define P_MIPI_OTHER_CNTL4 4284829968 #define SEC_EE_AUDIO_TORAM_INT_ADDR 4284753680 #define P_MIPI_OTHER_CNTL3 4284829964 #define P_MIPI_OTHER_CNTL2 4284829960 #define P_MIPI_OTHER_CNTL1 4284829956 #define P_RO_IMCLK2REF_CNT_L 4284784720 #define P_MIPI_OTHER_CNTL0 4284829952 #define P_RO_IMCLK2REF_CNT_H 4284784724 #define SEC_AMLUSB_A10 4284702760 #define P_EE_AUDIO_TDMIN_A_SWAP 4284752644 #define SEC_AMLUSB_A15 4284702780 #define MIPI_ADAPT_ALIG_ST1 4284829932 #define SEC_AMLUSB_A16 4284702784 #define MIPI_ADAPT_ALIG_ST0 4284829928 #define SEC_AMLUSB_A17 4284702788 #define SEC_AMLUSB_A18 4284702792 #define SEC_AMLUSB_A11 4284702764 #define AO_SEC_M4_CPU_SRAM_REG2_0 4286579372 #define SEC_AMLUSB_A12 4284702768 #define P_EE_AUDIO_TDMIN_C_MUTE_VAL 4284752796 #define SEC_AMLUSB_A13 4284702772 #define SEC_AMLUSB_A14 4284702776 #define SEC_AO_SAR_ADC_CHNL45 4286615616 #define AED_DRC_AA_1M 4284834228 #define SEC_HHI_VDEC2_CLK_CNTL 4284727780 #define P_EE_AUDIO_TODDR_C_INIT_ADDR 4284752292 #define SEC_RO_REF2IMCLK_CNT_H 4284784708 #define SEC_AO_UART_CONTROL 4286590984 #define SEC_RO_REF2IMCLK_CNT_L 4284784704 #define EE_AUDIO_MST_C_SCLK_CTRL1 4284751956 #define EE_AUDIO_MST_C_SCLK_CTRL0 4284751952 #define P_AED_TOP_CTL 4284834336 #define MIPI_DSI_ANA_CTRL 4284760108 #define SEC_AO_SAR_ADC_CHNL23 4286615612 #define P_AO_SAR_ADC_DETECT_IDLE_SW 4286615588 #define P_EE_AUDIO_CLK_RESAMPLE_CTRL 4284752036 #define SEC_HHI_VID_CLK_CNTL 4284727676 #define SEC_AO_FR_EE_WR_ONCE 4286578888 #define P_AO_IR_DEC_REG1 4286611484 #define P_AO_IR_DEC_REG0 4286611472 #define SEC_EE_AUDIO_TDMOUT_C_STAT 4284753308 #define P_AO_TIMERE_HI_REG 4286579688 #define SEC_AO_SAR_ADC_CHNL01 4286615608 #define HHI_GCLK2_OTHER 4284727504 #define SEC_AO_SAR_ADC_REG0 4286615552 #define SEC_AO_SAR_ADC_REG3 4286615564 #define P_AM_RING_OSC_REG0 4284696060 #define AO_MF_IR_DEC_FRAME 4286611540 #define SEC_AO_IR_DEC_BIT_0 4286611468 #define AO_GPIO_I 4286578728 #define P_EE_AUDIO_TODDR_C_STATUS2 4284752280 #define AO_GPIO_O 4286578740 #define P_EE_AUDIO_TODDR_C_STATUS1 4284752276 #define SEC_MIPI_ISP_RDARB_UGT 4284842000 #define SEC_MIPI_ADAPT_DDR_RD1_ST0 4284829780 #define SEC_MIPI_ADAPT_DDR_RD1_ST1 4284829784 #define SEC_MIPI_ADAPT_DDR_RD1_ST2 4284829788 #define RESET2_SEC_REGISTER 4284801032 #define SEC_PDM_MUTE_VALUE 4284743732 #define SEC_PREG_VPU_SECURE0 4284695888 #define P_AO_UART2_CONTROL 4286595080 #define SEC_PREG_VPU_SECURE1 4284695892 #define SEC_EE_AUDIO_TOHDMITX_CTRL0 4284753732 #define SEC_AED_DRC_AD_1M 4284834232 #define SEC_EFUSE_LIC0 4284678192 #define SEC_EFUSE_LIC2 4284678200 #define SEC_EFUSE_LIC1 4284678196 #define P_EE_AUDIO_SPDIFOUT_PREAMB 4284753044 #define SEC_EFUSE_LIC3 4284678204 #define P_EE_AUDIO_MCLK_F_CTRL 4284751896 #define SEC_AED_DRC_K0 4284834252 #define SEC_AED_DRC_K1 4284834256 #define SEC_AO_SEC_SD_CFG5 4286579220 #define SEC_AO_SEC_SD_CFG6 4286579224 #define SEC_MIPI_ISP_RDARB_WEIGH1_SLV 4284841996 #define SEC_AO_SEC_SD_CFG3 4286579212 #define SEC_AO_SEC_SD_CFG4 4286579216 #define SEC_AO_SEC_SD_CFG9 4286579236 #define P_TS_DDR_CFG_REG7 4284697628 #define SEC_AO_SEC_SD_CFG7 4286579228 #define SEC_AO_SEC_SD_CFG8 4286579232 #define P_TS_DDR_CFG_REG3 4284697612 #define P_TS_DDR_CFG_REG4 4284697616 #define P_AO_IR_DEC_BIT_0 4286611468 #define P_TS_DDR_CFG_REG5 4284697620 #define P_TS_DDR_CFG_REG6 4284697624 #define SEC_EE_AUDIO_CLK_TDMIN_C_CTRL 4284752008 #define P_TS_DDR_CFG_REG1 4284697604 #define P_TS_DDR_CFG_REG2 4284697608 #define SEC_EE_AUDIO_RESAMPLE_STATUS1 4284752996 #define SEC_AO_SEC_SD_CFG1 4286579204 #define AO_AHB2DDR_CNTL 4286578784 #define SEC_AO_SEC_SD_CFG2 4286579208 #define SEC_AO_SEC_SD_CFG0 4286579200 #define SEC_AO_SEC_SD_CFG13 4286579252 #define SEC_AO_SEC_SD_CFG12 4286579248 #define SEC_AO_SEC_SD_CFG15 4286579260 #define SEC_AO_SEC_SD_CFG14 4286579256 #define SEC_AO_SEC_SD_CFG11 4286579244 #define SEC_AO_SEC_SD_CFG10 4286579240 #define P_EE_AUDIO_MCLK_C_CTRL 4284751884 #define AO_PWM_LOCK_AB 4286607392 #define EE_AUDIO_TDMOUT_C_MASK2 4284753300 #define EE_AUDIO_TDMOUT_C_MASK3 4284753304 #define P_AED_NG_CNT_THD 4284834272 #define EE_AUDIO_CLK_TDMOUT_A_CTRL 4284752016 #define EE_AUDIO_TDMOUT_C_MASK0 4284753292 #define EE_AUDIO_TDMOUT_C_MASK1 4284753296 #define SEC_MIPI_DSI_CHAN_STS 4284760072 #define SEC_RO_IMCLK2REF_CNT_L 4284784720 #define SEC_RO_IMCLK2REF_CNT_H 4284784724 #define SEC_AMLUSB_A20 4284702800 #define SEC_AMLUSB_A21 4284702804 #define SEC_AMLUSB_A26 4284702824 #define SEC_AMLUSB_A27 4284702828 #define SEC_AMLUSB_A28 4284702832 #define SEC_AO_SEC_M4_CPU_SRAM_REG0_1 4286579360 #define SEC_AMLUSB_A29 4284702836 #define SEC_AMLUSB_A22 4284702808 #define EE_AUDIO_TODDR_A_STATUS2 4284752152 #define AO_PWM_LOCK_CD 4286586912 #define SEC_AMLUSB_A23 4284702812 #define SEC_AMLUSB_A24 4284702816 #define SEC_AMLUSB_A25 4284702820 #define EE_AUDIO_TODDR_A_STATUS1 4284752148 #define SEC_AMLUSB_A19 4284702796 #define SEC_AMLUSB_A30 4284702840 #define SEC_AMLUSB_A31 4284702844 #define SEC_AED_DRC_EN 4284834208 #define P_PREG_PAD_GPIO1_EN_N 4284695628 #define SEC_AO_SEC_M4_CPU_SRAM_REG0_0 4286579356 #define SEC_PDM_HPF_CTRL 4284743704 #define P_MIPI_DSI_LPOK_TIM 4284760100 #define SEC_AO_CECB_GEN_CNTL 4286579336 #define SEC_AO_I2C_S_SEND_REG 4286603268 #define P_EE_AUDIO_TDMOUT_C_MUTE3 4284753336 #define P_EE_AUDIO_TDMOUT_C_MUTE2 4284753332 #define P_EE_AUDIO_TDMOUT_C_MUTE1 4284753328 #define P_EE_AUDIO_TDMOUT_C_MUTE0 4284753324 #define P_EE_AUDIO_TODDR_B_STATUS1 4284752212 #define P_EE_AUDIO_TODDR_B_STATUS2 4284752216 #define P_RESET1_SEC_REGISTER 4284801028 #define HHI_CDAC_CLK_CNTL 4284728280 #define P_RO_OMCLK2REF_CNT_H 4284784732 #define P_RO_OMCLK2REF_CNT_L 4284784728 #define P_AUD_LOCK_EN 4284784640 #define AO_CEC_INTR_STAT 4286578960 #define P_EFUSE_CLK_A53_CFG2 4284696328 #define SEC_AO_IR_DEC_STATUS 4286611480 #define P_EE_AUDIO_LB_STS 4284752600 #define SEC_EE_AUDIO_MST_F_SCLK_CTRL1 4284751980 #define SEC_PDM_F1_CTRL 4284743692 #define SEC_EE_AUDIO_MST_F_SCLK_CTRL0 4284751976 #define EE_AUDIO_CLK_GATE_EN 4284751872 #define HHI_VIID_CLK_CNTL 4284727596 #define P_AO_CECB_INTR_CLR 4286579348 #define SEC_HHI_GCLK_MPEG0 4284727616 #define EE_AUDIO_TODDR_B_STATUS2 4284752216 #define EE_AUDIO_TODDR_B_STATUS1 4284752212 #define P_AO_SAR_ADC_CHNL23 4286615612 #define SEC_HHI_GCLK_MPEG1 4284727620 #define SEC_HHI_GCLK_MPEG2 4284727624 #define SEC_AED_DRC_AA 4284834216 #define P_EE_AUDIO_TODDR_C_START_ADDRB 4284752284 #define HHI_MEM_PD_REG0 4284727552 #define SEC_AED_DRC_AD 4284834220 #define SEC_AED_DRC_AE 4284834212 #define P_MIPI_ADAPT_DDR_RD0_ST2 4284829724 #define P_MIPI_ADAPT_DDR_RD0_ST1 4284829720 #define P_MIPI_ADAPT_DDR_RD0_ST0 4284829716 #define SEC_AO_CPU_STAT2 4286578896 #define P_RO_REF2IMCLK_CNT_L 4284784704 #define PAD_PULL_UP_EN_REG4 4284695856 #define EE_AUDIO_MCLK_B_CTRL 4284751880 #define PAD_PULL_UP_EN_REG5 4284695860 #define P_RO_REF2IMCLK_CNT_H 4284784708 #define PAD_PULL_UP_EN_REG0 4284695840 #define SEC_HHI_CHECK_CLK_RESULT 4284727312 #define PAD_PULL_UP_EN_REG1 4284695844 #define PAD_PULL_UP_EN_REG2 4284695848 #define SEC_AO_CPU_STAT1 4286578892 #define PAD_PULL_UP_EN_REG3 4284695852 #define SEC_AO_TIMESTAMP_CNTL1 4286578864 #define SEC_AO_TIMESTAMP_CNTL2 4286578844 #define AO_RTI_GEN_PWR_ISO0 4286578924 #define P_AO_SAR_ADC_CHNL01 4286615608 #define SEC_AO_PWM_LOCK_CD 4286586912 #define EE_AUDIO_TDMIN_A_STAT 4284752664 #define EE_AUDIO_TOHDMITX_CTRL0 4284753732 #define PREG_PAD_GPIO0_EN_N 4284695616 #define P_HHI_APICALGDC_CLK_CNTL 4284727660 #define P_EE_AUDIO_FRDDR_B_FINISH_ADDR 4284752396 #define AO_I2C_M_0_WDATA_REG0 4286599184 #define AO_I2C_M_0_WDATA_REG1 4286599188 #define SEC_AMLUSB_B0 4284719104 #define RESET1_SEC_MASK 4284801156 #define HHI_APICALGDC_CLK_CNTL 4284727660 #define SEC_AMLUSB_B3 4284719116 #define SEC_AMLUSB_B4 4284719120 #define SEC_AMLUSB_B1 4284719108 #define SEC_AMLUSB_B2 4284719112 #define SEC_AMLUSB_B7 4284719132 #define SEC_AMLUSB_B8 4284719136 #define SEC_AMLUSB_B5 4284719124 #define SEC_AMLUSB_B6 4284719128 #define SEC_AMLUSB_A8 4284702752 #define SEC_AMLUSB_A9 4284702756 #define SYS_CPUB_CFG4 4284696472 #define SYS_CPUB_CFG3 4284696468 #define SYS_CPUB_CFG2 4284696464 #define SYS_CPUB_CFG1 4284696460 #define SYS_CPUB_CFG0 4284696456 #define SEC_AMLUSB_A2 4284702728 #define SEC_AMLUSB_A3 4284702732 #define SEC_AMLUSB_A0 4284702720 #define SEC_AMLUSB_A1 4284702724 #define SEC_AMLUSB_A6 4284702744 #define SEC_AMLUSB_A7 4284702748 #define SEC_AMLUSB_A4 4284702736 #define SEC_AMLUSB_A5 4284702740 #define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL 4284753612 #define P_AO_MF_IR_DEC_IRQ_CTL 4286611592 #define P_MIPI_OTHER_ST1 4284829996 #define P_MIPI_OTHER_ST0 4284829992 #define SYS_CPUB_CFG9 4284696492 #define SYS_CPUB_CFG8 4284696488 #define SYS_CPUB_CFG7 4284696484 #define SYS_CPUB_CFG6 4284696480 #define SYS_CPUB_CFG5 4284696476 #define SEC_MIPI_DSI_ULPS_CHECK 4284760120 #define P_AO_TIMESTAMP_CNTL2 4286578844 #define HHI_PCIE_PLL_CNTL4 4284727464 #define HHI_PCIE_PLL_CNTL5 4284727468 #define HHI_PCIE_PLL_CNTL2 4284727456 #define P_AO_TIMESTAMP_CNTL1 4286578864 #define HHI_PCIE_PLL_CNTL3 4284727460 #define HHI_PCIE_PLL_CNTL0 4284727448 #define HHI_PCIE_PLL_CNTL1 4284727452 #define SEC_DMA_STS5 4284735540 #define SEC_DMA_STS2 4284735528 #define SEC_DMA_STS1 4284735524 #define SEC_DMA_STS4 4284735536 #define SEC_DMA_STS3 4284735532 #define SEC_DMA_STS0 4284735520 #define SEC_EE_AUDIO_TDMIN_LB_STAT 4284752856 #define SEC_EE_AUDIO_TDMIN_B_SWAP 4284752708 #define P_AO_IR_DEC_LDR_ACTIVE 4286611456 #define SEC_ETH_PHY_DBG_CFG4 4284792856 #define SEC_ETH_PHY_DBG_CFG1 4284792844 #define SEC_ETH_PHY_DBG_CFG0 4284792840 #define SEC_ETH_PHY_DBG_CFG3 4284792852 #define SEC_ETH_PHY_DBG_CFG2 4284792848 #define P_RESET1_SEC_LEVEL 4284801092 #define RNG_SEC_STS 4284678676 #define HHI_VID_CLK_CNTL2 4284727700 #define P_M4_CPU_CNTL3 4286579468 #define P_M4_CPU_CNTL4 4286579472 #define P_M4_CPU_CNTL5 4286579476 #define AO_SEC_JTAG_PWD_SP_3 4286579392 #define AO_SEC_JTAG_PWD_SP_2 4286579388 #define AO_SEC_JTAG_PWD_SP_1 4286579384 #define P_M4_CPU_CNTL2 4286579464 #define P_AO_MF_IR_DEC_LDR_ACTIVE 4286611520 #define AO_SEC_JTAG_PWD_SP_0 4286579380 #define MIPI_DSI_LP_WCHDOG 4284760104 #define P_AO_UART_STATUS 4286590988 #define P_EE_AUDIO_TOHDMITX_CTRL0 4284753732 #define EE_AUDIO_SPDIFOUT_MUTE_VAL 4284753100 #define SEC_AMLUSB_B9 4284719140 #define SEC_AMLUSB_B20 4284719184 #define SEC_AMLUSB_B25 4284719204 #define SEC_AMLUSB_B26 4284719208 #define HHI_SYS_CPUB_CLK_CNTL 4284727816 #define SEC_AMLUSB_B27 4284719212 #define SEC_AMLUSB_B28 4284719216 #define SEC_AMLUSB_B21 4284719188 #define SEC_AMLUSB_B22 4284719192 #define SEC_AMLUSB_B23 4284719196 #define SEC_AMLUSB_B24 4284719200 #define AO_RTI_PINMUX_REG1 4286578712 #define SEC_AMLUSB_B18 4284719176 #define SEC_AMLUSB_B19 4284719180 #define AO_RTI_PINMUX_REG0 4286578708 #define MIPI_ISP_WRARB_UGT 4284842024 #define EE_AUDIO_TODDR_B_START_ADDRB 4284752220 #define EE_AUDIO_FRDDR_B_CTRL0 4284752384 #define EE_AUDIO_RESAMPLE_STATUS1 4284752996 #define SEC_AMLUSB_B30 4284719224 #define SEC_AMLUSB_B31 4284719228 #define EE_AUDIO_FRDDR_B_CTRL1 4284752388 #define SEC_AMLUSB_B29 4284719220 #define P_HHI_ISP_MAX_ADDR_CNTL 4284727764 #define SEC_EE_AUDIO_TDMOUT_B_MASK_VAL 4284753276 #define SEC_EE_AUDIO_TDMOUT_C_MUTE1 4284753328 #define SEC_EE_AUDIO_TDMOUT_C_MUTE2 4284753332 #define SEC_EE_AUDIO_TDMOUT_C_MUTE3 4284753336 #define SEC_EE_AUDIO_TDMOUT_C_MUTE0 4284753324 #define EE_AUDIO_TDMIN_LB_MASK0 4284752840 #define EE_AUDIO_TDMIN_LB_MASK1 4284752844 #define EE_AUDIO_TDMIN_LB_MASK2 4284752848 #define EE_AUDIO_TDMIN_LB_MASK3 4284752852 #define MIPI_ADAPT_IRQ_MASK0 4284830080 #define MIPI_ADAPT_IRQ_MASK1 4284830088 #define SEC_AMLUSB_B14 4284719160 #define SEC_AMLUSB_B15 4284719164 #define SEC_AMLUSB_B16 4284719168 #define P_AO_CPU_CNTL2 4286578748 #define SEC_AMLUSB_B17 4284719172 #define P_AO_CPU_CNTL3 4286578908 #define SEC_AMLUSB_B10 4284719144 #define P_AO_CPU_CNTL4 4286578940 #define SEC_AMLUSB_B11 4284719148 #define P_AO_CPU_CNTL5 4286578964 #define SEC_AMLUSB_B12 4284719152 #define SEC_AMLUSB_B13 4284719156 #define MIPI_ISP_RDARB_WEIGH1_SLV 4284841996 #define SEC_EE_AUDIO_TDMIN_LB_CTRL 4284752832 #define P_AO_CECB_INTR_STAT 4286579352 #define SEC_SYS_CPU_CFG9 4284696172 #define MIPI_ISP_RDARB_UGT 4284842000 #define AO_SEC_SHARED_AHB_SRAM_MASK_1 4286579100 #define AO_SEC_SHARED_AHB_SRAM_MASK_0 4286579096 #define SEC_SYS_CPU_CFG0 4284696136 #define EE_AUDIO_FRDDR_C_INIT_ADDR 4284752484 #define SEC_SYS_CPU_CFG4 4284696152 #define SEC_SYS_CPU_CFG3 4284696148 #define AO_SEC_SHARED_AHB_SRAM_MASK_2 4286579104 #define SEC_SYS_CPU_CFG2 4284696144 #define SEC_SYS_CPU_CFG1 4284696140 #define SEC_SYS_CPU_CFG8 4284696168 #define SEC_SYS_CPU_CFG7 4284696164 #define P_HHI_VID_CLK_CNTL 4284727676 #define SEC_SYS_CPU_CFG6 4284696160 #define SEC_SYS_CPU_CFG5 4284696156 #define P_HHI_SYS_CPUB_CLK_CNTL 4284727816 #define SEC_HHI_SYS_CPU_CLK_CNTL 4284727708 #define EE_AUDIO_TDMIN_A_MUTE_VAL 4284752668 #define SEC_BUS_MON0_DATA 4284696076 #define P_AO_DEBUG_REG2 4286578856 #define P_AO_DEBUG_REG3 4286578860 #define SEC_EE_AUDIO_FRDDR_B_FINISH_ADDR 4284752396 #define P_AO_DEBUG_REG0 4286578848 #define P_AO_DEBUG_REG1 4286578852 #define SEC_HHI_MIPIDSI_PHY_CLK_CNTL 4284727892 #define HHI_CSI_PHY_CNTL3 4284728152 #define SEC_AED_DRC_OFFSET1 4284834240 #define HHI_CSI_PHY_CNTL4 4284728156 #define SEC_AED_DRC_OFFSET0 4284834236 #define HHI_CSI_PHY_CNTL1 4284728144 #define HHI_CSI_PHY_CNTL2 4284728148 #define HHI_CSI_PHY_CNTL5 4284728160 #define HHI_CSI_PHY_CNTL0 4284728140 #define P_AO_SEC_REG0 4286579008 #define SEC_AO_MF_IR_DEC_FRAME_RSV0 4286611580 #define SEC_AO_MF_IR_DEC_FRAME_RSV1 4286611584 #define SEC_HHI_ETH_CLK_CNTL 4284727768 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 4284753568 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 4284753564 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 4284753576 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 4284753572 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 4284753584 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 4284753580 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 4284753592 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 4284753588 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 4284753600 #define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 4284753596 #define P_EE_AUDIO_SPDIFOUT_B_CHSTSA 4284753604 #define P_EE_AUDIO_SPDIFOUT_B_CHSTSB 4284753608 #define AO_CPU_CNTL_NS 4286578756 #define P_SYS_CPUB_POR_CFG1 4284696452 #define P_SYS_CPUB_POR_CFG0 4284696448 #define SEC_HHI_NANOQ_MEM_PD_REG1 4284727568 #define SEC_HHI_NANOQ_MEM_PD_REG0 4284727564 #define AO_TIMERC_REG 4286579676 #define SEC_AO_TIMER_SEC_SCP_CTRL 4286579652 #define AED_NG_CNT 4284834328 #define SEC_PREG_PAD_GPIO2_EN_N 4284695640 #define AUD_LOCK_IMCLK_LAT_INT 4284784664 #define P_AO_RTI_STICKY_REG1 4286578996 #define P_AO_RTI_STICKY_REG0 4286578992 #define P_AO_RTI_STICKY_REG3 4286579004 #define P_AO_RTI_STICKY_REG2 4286579000 #define SEC_AO_SEC_JTAG_SCP_CTRL 4286579416 #define SEC_EE_AUDIO_SPDIFOUT_PREAMB 4284753044 #define HPG_TIMER 4284727356 #define P_AO_CLK_GATE0 4286578764 #define EE_AUDIO_FRDDR_B_FINISH_ADDRB 4284752416 #define SEC_MIPI_DSI_HS_TIM 4284760080 #define HHI_GEN_CLK_CNTL 4284727848 #define SYS_CPU_CFG4 4284696152 #define SYS_CPU_CFG3 4284696148 #define SYS_CPU_CFG6 4284696160 #define SYS_CPU_CFG5 4284696156 #define SYS_CPU_CFG0 4284696136 #define RESET1_SEC_LEVEL 4284801092 #define SYS_CPU_CFG2 4284696144 #define SYS_CPU_CFG1 4284696140 #define PREG_NAND_CFG_KEY0 4284695880 #define M4_CPU_STAT1 4286579488 #define SEC_AO_SEC_M4_CPU_SRAM_REG1_1 4286579368 #define M4_CPU_STAT2 4286579492 #define SEC_AO_SEC_M4_CPU_SRAM_REG1_0 4286579364 #define PREG_NAND_CFG_KEY1 4284695884 #define EE_AUDIO_CLK_SPDIFOUT_CTRL 4284752032 #define SEC_AO_RTI_GEN_PWR_SLEEP0 4286578920 #define AO_PINMUX_LOCK 4286578780 #define SEC_KL_RESP1_1 4284678308 #define SEC_KL_RESP1_0 4284678304 #define P_AUD_LOCK_GCLK_CTRL 4284784688 #define AO_METAL_REVISION 4286578812 #define SYS_CPU_CFG8 4284696168 #define SYS_CPU_CFG7 4284696164 #define SEC_KL_RESP1_3 4284678316 #define SEC_KL_RESP1_2 4284678312 #define SYS_CPU_CFG9 4284696172 #define SEC_EE_AUDIO_TODDR_A_START_ADDR 4284752136 #define SEC_AO_UART2_STATUS 4286595084 #define P_AUD_LOCK_SW_RESET 4284784644 #define P_HHI_VDEC3_CLK_CNTL 4284727784 #define P_BUS_MON1_ADDR 4284696084 #define P_HHI_VPU_CLKC_CNTL 4284727732 #define P_EE_AUDIO_TDMIN_C_MASK1 4284752780 #define P_EE_AUDIO_TDMIN_C_MASK0 4284752776 #define P_EE_AUDIO_TDMIN_C_MASK3 4284752788 #define P_EE_AUDIO_TDMIN_C_MASK2 4284752784 #define AED_NG_CTL 4284834276 #define AO_RTI_PULL_UP_REG 4286578732 #define P_AO_CEC_INTR_STAT 4286578960 #define SEC_AO_CEC_INTR_MASKN 4286578952 #define SEC_HHI_GCLK2_MPEG0 4284727488 #define SEC_PREG_PAD_GPIO5_EN_N 4284695680 #define MIPI_ISP_RDARB_REQEN_SLV 4284841988 #define SEC_HHI_GCLK2_MPEG1 4284727492 #define SEC_HHI_GCLK2_MPEG2 4284727496 #define BUS_MON1_DATA_MSK 4284696092 #define P_SP_HOLD_CTRL 4286578884 #define SEC_EE_AUDIO_FRDDR_C_CTRL1 4284752452 #define SEC_EE_AUDIO_FRDDR_C_CTRL0 4284752448 #define SEC_AO_I2C_M_0_TIMEOUT_TH 4286599200 #define AO_PAD_DS_A 4286578716 #define AO_PAD_DS_B 4286578720 #define SEC_EE_AUDIO_TDMIN_LB_MUTE_VAL 4284752860 #define AUD_LOCK_EN 4284784640 #define MIPI_ADAPT_DDR_RD0_CNTL0 4284829696 #define SEC_PDM_CHAN_CTRL1 4284743712 #define MIPI_ADAPT_DDR_RD0_CNTL1 4284829700 #define MIPI_ADAPT_DDR_RD0_CNTL2 4284829704 #define MIPI_ADAPT_DDR_RD0_CNTL3 4284829708 #define SEC_AO_IR_DEC_LDR_REPEAT 4286611464 #define SEC_SYS_CPUB_POR_CFG0 4284696448 #define AO_TIMERG_HI_REG 4286579704 #define SEC_SYS_CPUB_POR_CFG1 4284696452 #define MIPI_ADAPT_DDR_RD0_CNTL4 4284829712 #define P_AO_TIMERB_CUR_REG 4286579672 #define P_AO_RTI_GEN_PWR_SLEEP0 4286578920 #define AO_PWM_PWM_A 4286607360 #define AO_PWM_PWM_B 4286607364 #define SEC_HHI_FIX_PLL_STS 4284727996 #define AO_PWM_PWM_C 4286586880 #define AO_PWM_PWM_D 4286586884 #define HHI_MALI_CLK_CNTL 4284727728 #define HHI_SYS_PLL_CNTL6 4284728076 #define HHI_SYS_PLL_CNTL5 4284728072 #define HHI_SYS_PLL_CNTL4 4284728068 #define HHI_SYS_PLL_CNTL3 4284728064 #define HHI_SYS_PLL_CNTL2 4284728060 #define HHI_SYS_PLL_CNTL1 4284728056 #define HHI_SYS_PLL_CNTL0 4284728052 #define SEC_HHI_VDEC4_CLK_CNTL 4284727788 #define SEC_MIPI_ADAPT_PIXEL0_ST1 4284829868 #define SEC_AUD_LOCK_REFCLK_LAT_INT 4284784660 #define AO_RTI_PWR_CNTL_REG0 4286578704 #define SEC_EE_AUDIO_TOACODEC_CTRL0 4284753728 #define SEC_MIPI_ADAPT_PIXEL0_ST0 4284829864 #define P_SYS_CPU_MISC 4284696224 #define SEC_EE_AUDIO_TDMOUT_B_MASK1 4284753232 #define SEC_EE_AUDIO_TDMOUT_B_MASK2 4284753236 #define SEC_EE_AUDIO_TDMOUT_B_MASK3 4284753240 #define PREG_PAD_GPIO5_EN_N 4284695680 #define SEC_EE_AUDIO_TDMOUT_B_MASK0 4284753228 #define SEC_EE_AUDIO_RESAMPLE_CTRL3 4284752972 #define SEC_EE_AUDIO_RESAMPLE_CTRL2 4284752968 #define SEC_EE_AUDIO_RESAMPLE_CTRL1 4284752964 #define SEC_EE_AUDIO_RESAMPLE_CTRL0 4284752960 #define P_EE_AUDIO_SW_RESET 4284751908 #define P_AO_TIMERA_REG 4286579660 #define SEC_MIPI_ISP_RDARB_REQEN_SLV 4284841988 #define SEC_HHI_VPU_CLK_CNTL 4284727740 #define SEC_EE_AUDIO_FRDDR_B_START_ADDRB 4284752412 #define SEC_EE_AUDIO_TDMIN_LB_SWAP 4284752836 #define SEC_HHI_HIFI_PLL_STS 4284727540 #define EE_AUDIO_SPDIFOUT_B_GAIN0 4284753540 #define SEC_EE_AUDIO_TODDR_B_INIT_ADDR 4284752228 #define EE_AUDIO_SPDIFOUT_B_GAIN1 4284753544 #define EFUSE_CLK_A73_CFG2 4284696348 #define P_AO_SEC_SHARED_AHB_SRAM_REG5_0 4286579168 #define P_AO_SEC_SHARED_AHB_SRAM_REG5_1 4286579172 #define P_AO_SEC_SHARED_AHB_SRAM_REG5_2 4286579176 #define SEC_EE_AUDIO_CLK_SPDIFOUT_CTRL 4284752032 #define P_AO_CPU_CNTL 4286578744 #define SEC_EE_AUDIO_TDMOUT_A_CTRL1 4284753156 #define MIPI_ISP_WRARB_REQEN_SLV 4284842012 #define AO_FR_EE_WR_ONCE 4286578888 #define AO_CPU_STAT2 4286578896 #define AO_CPU_STAT1 4286578892 #define EE_AUDIO_TDMIN_A_SWAP 4284752644 #define P_EFUSE_RDATA3 4284678188 #define SEC_EE_AUDIO_TDMOUT_A_CTRL0 4284753152 #define P_EFUSE_RDATA2 4284678184 #define P_EFUSE_RDATA1 4284678180 #define P_EFUSE_RDATA0 4284678176 #define P_EE_AUDIO_PAD_CTRL0 4284751900 #define P_EE_AUDIO_PAD_CTRL1 4284751904 #define AO_OSCIN_CNTL 4286578776 #define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDR 4284752460 #define SEC_EE_AUDIO_TDMOUT_C_SWAP 4284753288 #define SEC_HHI_CCI_CLK_CNTL 4284727724 #define SEC_EE_AUDIO_TODDR_A_INIT_ADDR 4284752164 #define SEC_AUD_LOCK_INT_CLR 4284784684 #define SEC_AO_MF_IR_DEC_LDR_ACTIVE 4286611520 #define SEC_MIPI_ISP_WRARB_MODE 4284842008 #define P_MIPI_DSI_CLK_TIM1 4284760112 #define P_RNG_USR_DATA 4284678680 #define SEC_SECE_TIMER_LOW 4284696104 #define EE_AUDIO_TODDR_C_START_ADDRB 4284752284 #define AO_UART_WFIFO 4286590976 #define P_EE_AUDIO_TDMOUT_A_CTRL0 4284753152 #define P_EE_AUDIO_TDMOUT_A_CTRL1 4284753156 #define P_EFUSE_WDATA3 4284678172 #define P_EFUSE_WDATA2 4284678168 #define P_EFUSE_WDATA1 4284678164 #define P_EFUSE_WDATA0 4284678160 #define SEC_EE_AUDIO_POW_DET_VALUE 4284753424 #define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB 4284752352 #define HHI_VID_CLK_CNTL 4284727676 #define SEC_AO_RTI_PINMUX_REG1 4286578712 #define SEC_AO_RTI_PINMUX_REG0 4286578708 #define P_AO_PWM_LOCK_CD 4286586912 #define SEC_AO_TIMERA_CUR_REG 4286579664 #define HHI_MIPIDSI_PHY_CLK_CNTL 4284727892 #define SEC_EFUSE_CLK_A73_CFG2 4284696348 #define MIPI_DSI_CHAN_STS 4284760072 #define SEC_AO_WATCHDOG_RESET 4286578988 #define P_HIU_MAILBOX_STAT_1 4284728340 #define P_HIU_MAILBOX_STAT_0 4284728328 #define AO_PWM_BLINK_CD 4286586908 #define P_EE_AUDIO_TOACODEC_CTRL0 4284753728 #define P_HIU_MAILBOX_STAT_7 4284728412 #define P_EE_AUDIO_TDMOUT_B_STAT 4284753244 #define P_HIU_MAILBOX_STAT_6 4284728400 #define RNG_SEC_CONFIG_REG1 4284678660 #define RNG_SEC_CONFIG_REG2 4284678664 #define P_AO_WATCHDOG_CNTL1 4286578980 #define P_HIU_MAILBOX_STAT_3 4284728364 #define P_HIU_MAILBOX_STAT_2 4284728352 #define P_HIU_MAILBOX_STAT_5 4284728388 #define P_HIU_MAILBOX_STAT_4 4284728376 #define P_EE_AUDIO_TODDR_A_START_ADDR 4284752136 #define SEC_HHI_VDIN_MEAS_CLK_CNTL 4284727888 #define P_RO_IMCLK_PKG_CNT 4284784740 #define SEC_AO_MF_IR_DEC_BIT_0 4286611532 #define SEC_AUD_LOCK_REFCLK_SRC 4284784656 #define MIPI_DSI_TEST_CTRL0 4284760124 #define MIPI_DSI_TEST_CTRL1 4284760128 #define AO_SAR_ADC_CHAN_10_SW 4286615584 #define SEC_EE_AUDIO_TDMIN_B_STAT 4284752728 #define P_TS_PLL_CFG_REG5 4284696596 #define P_TS_PLL_CFG_REG6 4284696600 #define P_TS_PLL_CFG_REG7 4284696604 #define P_TS_PLL_CFG_REG1 4284696580 #define P_TS_PLL_CFG_REG2 4284696584 #define P_TS_PLL_CFG_REG3 4284696588 #define P_TS_PLL_CFG_REG4 4284696592 #define P_MIPI_ISP_RDWR_ARB_STATUS 4284842028 #define SEC_HHI_MEM_PD_REG0 4284727552 #define SEC_HHI_AXI_PIPEL_CNTL 4284728272 #define EE_AUDIO_FRDDR_B_START_ADDR 4284752392 #define PDM_F2_CTRL 4284743696 #define MIPI_ISP_WRARB_MODE 4284842008 #define SEC_AO_I2C_S_RECV_REG 4286603272 #define SEC_EE_AUDIO_TORAM_CTRL0 4284753664 #define SEC_EE_AUDIO_TORAM_CTRL1 4284753668 #define SEC_EE_AUDIO_MST_C_SCLK_CTRL1 4284751956 #define SEC_EE_AUDIO_MST_C_SCLK_CTRL0 4284751952 #define AO_PWM_BLINK_AB 4286607388 #define P_EE_AUDIO_RESAMPLE_CTRL0 4284752960 #define SEC_AO_TIMERC_REG 4286579676 #define P_EE_AUDIO_RESAMPLE_CTRL1 4284752964 #define SEC_AO_SEC_M4_CPU_SRAM_REG2_0 4286579372 #define P_EE_AUDIO_RESAMPLE_CTRL2 4284752968 #define P_EE_AUDIO_RESAMPLE_CTRL3 4284752972 #define SEC_HHI_TS_CLK_CNTL 4284727696 #define SEC_AO_I2C_S_CNTL1_REG 4286603276 #define AO_IR_DEC_DEMOD_CNT0 4286611676 #define P_EE_AUDIO_LB_LB_CH_ID0 4284752592 #define P_EE_AUDIO_LB_LB_CH_ID1 4284752596 #define AO_IR_DEC_DEMOD_CNT1 4286611680 #define SEC_AO_I2C_M_0_TOKEN_LIST1 4286599180 #define SEC_AO_I2C_M_0_TOKEN_LIST0 4286599176 #define SEC_RNG_SEC_CONFIG_REG1 4284678660 #define SEC_RNG_SEC_CONFIG_REG2 4284678664 #define P_AO_PWM_LOCK_AB 4286607392 #define SEC_EE_AUDIO_TORAM_STATUS2 4284753688 #define SEC_EE_AUDIO_TORAM_STATUS1 4284753684 #define SEC_AO_RTI_GEN_PWR_ISO0 4286578924 #define P_AO_SAR_ADC_REG11 4286615596 #define P_AO_SAR_ADC_REG12 4286615600 #define SEC_AO_MF_IR_DEC_FILTE 4286611588 #define P_AO_SAR_ADC_REG13 4286615604 #define BUS_MON0_DATA 4284696076 #define P_HHI_AXI_PIPEL_CNTL2 4284728260 #define AUD_LOCK_REFCLK_SRC 4284784656 #define P_HHI_AXI_PIPEL_CNTL1 4284728268 #define P_ASYNC_FIFO_LOCK_ADR 4284696096 #define PREG_VPU_SECURE0 4284695888 #define PREG_VPU_SECURE1 4284695892 #define SEC_PREG_PAD_GPIO0_EN_N 4284695616 #define P_EE_AUDIO_FRDDR_A_FINISH_ADDR 4284752332 #define P_KL_RAM 4284678400 #define P_AED_EQ_CH2_COEF04 4284834008 #define P_AED_EQ_CH2_COEF02 4284834000 #define P_AED_EQ_CH2_COEF03 4284834004 #define P_AED_EQ_CH2_COEF00 4284833992 #define P_AO_I2C_S_RECV_REG 4286603272 #define P_AED_EQ_CH2_COEF01 4284833996 #define SEC_MIPI_ISP_RDARB_LIMT0 4284842004 #define P_AED_EQ_CH2_COEF10 4284834012 #define P_HHI_VPU_MEM_PD_REG2 4284727604 #define P_HHI_VPU_MEM_PD_REG1 4284727560 #define P_HHI_VPU_MEM_PD_REG0 4284727556 #define P_AO_PAD_DS_B 4286578720 #define EE_AUDIO_TDMOUT_A_SWAP 4284753160 #define P_AED_EQ_CH2_COEF13 4284834024 #define P_AO_PAD_DS_A 4286578716 #define P_AED_EQ_CH2_COEF14 4284834028 #define P_AED_EQ_CH2_COEF11 4284834016 #define P_AED_EQ_CH2_COEF12 4284834020 #define P_MIPI_ADAPT_PIXEL0_CNTL0 4284829824 #define P_MIPI_ADAPT_PIXEL0_CNTL1 4284829828 #define P_AED_EQ_CH2_COEF20 4284834032 #define P_AED_EQ_CH2_COEF21 4284834036 #define AO_PWM_MISC_REG_AB 4286607368 #define P_SECE_TIMER_CTRL 4284696100 #define SEC_AO_GEN_CLK_CNTL 4286578792 #define SEC_EE_AUDIO_TODDR_B_STATUS2 4284752216 #define SEC_EE_AUDIO_TODDR_B_STATUS1 4284752212 #define AO_IR_DEC_STATUS 4286611480 #define P_AO_RTI_STATUS_REG0 4286578688 #define P_AO_RTI_STATUS_REG3 4286578700 #define P_AO_RTI_STATUS_REG2 4286578696 #define P_AO_RTI_STATUS_REG1 4286578692 #define SEC_BUS_MON1_ADDR 4284696084 #define P_HHI_XTAL_DIVN_CNTL 4284727484 #define P_EE_AUDIO_TORAM_INT_ADDR 4284753680 #define SCR_HIU 4284727340 #define P_AED_EQ_CH2_COEF44 4284834088 #define P_EE_AUDIO_TODDR_B_FINISH_ADDRB 4284752224 #define P_AED_EQ_CH2_COEF53 4284834104 #define P_AED_EQ_CH2_COEF54 4284834108 #define P_AED_EQ_CH2_COEF51 4284834096 #define P_AED_EQ_CH2_COEF52 4284834100 #define P_AED_EQ_CH2_COEF50 4284834092 #define P_AED_DRC_AA_1M_H 4284834320 #define P_AO_SEC_SHARED_AHB_SRAM_REG4_1 4286579160 #define P_AO_SEC_SHARED_AHB_SRAM_REG4_2 4286579164 #define P_AO_SEC_SHARED_AHB_SRAM_REG4_0 4286579156 #define P_AUD_LOCK_IMCLK_DS_INT 4284784676 #define P_ETH_PLL_CTL5 4284792920 #define P_AO_CEC_INTR_CLR 4286578956 #define P_ETH_PLL_CTL6 4284792924 #define P_ETH_PLL_CTL3 4284792912 #define P_ETH_PLL_CTL4 4284792916 #define EE_AUDIO_SPDIFOUT_PREAMB 4284753044 #define P_ETH_PLL_CTL7 4284792928 #define AO_MAILBOX_STAT_3 4286619692 #define P_AED_EQ_CH2_COEF64 4284834128 #define P_AED_EQ_CH2_COEF62 4284834120 #define P_AED_EQ_CH2_COEF63 4284834124 #define P_AED_EQ_CH2_COEF60 4284834112 #define P_AED_EQ_CH2_COEF61 4284834116 #define SEC_AO_GPIO_O 4286578740 #define P_AED_EQ_CH2_COEF24 4284834048 #define P_AED_EQ_CH2_COEF22 4284834040 #define P_AED_EQ_CH2_COEF23 4284834044 #define SEC_AO_GPIO_I 4286578728 #define SEC_AO_PWM_BLINK_CD 4286586908 #define AO_MAILBOX_STAT_1 4286619668 #define AO_MAILBOX_STAT_2 4286619680 #define SEC_HHI_VDAC_CNTL1 4284728048 #define SEC_HHI_VDAC_CNTL0 4284728044 #define AO_MAILBOX_STAT_0 4286619656 #define P_ETH_PLL_CTL1 4284792904 #define P_ETH_PLL_CTL2 4284792908 #define P_ETH_PLL_CTL0 4284792900 #define PDM_CHAN_CTRL 4284743708 #define P_AED_EQ_CH2_COEF31 4284834056 #define P_AED_EQ_CH2_COEF32 4284834060 #define AO_SAR_CLK 4286578832 #define P_AED_EQ_CH2_COEF30 4284834052 #define SEC_AO_GPIO_O_EN_N 4286578724 #define P_AED_EQ_CH2_COEF33 4284834064 #define P_AED_EQ_CH2_COEF34 4284834068 #define SEC_M4_CPU_CNTL 4286579456 #define AO_IR_DEC_FRAME 4286611476 #define P_AED_EQ_CH2_COEF42 4284834080 #define P_AED_EQ_CH2_COEF43 4284834084 #define P_AED_EQ_CH2_COEF40 4284834072 #define P_AED_EQ_CH2_COEF41 4284834076 #define SEC_AO_PWM_BLINK_AB 4286607388 #define P_AED_EQ_CH2_COEF90 4284834172 #define P_EE_AUDIO_FRDDR_A_STATUS2 4284752344 #define P_AED_EQ_CH2_COEF93 4284834184 #define P_EE_AUDIO_FRDDR_A_STATUS1 4284752340 #define P_AED_EQ_CH2_COEF94 4284834188 #define P_AED_EQ_CH2_COEF91 4284834176 #define P_AED_EQ_CH2_COEF92 4284834180 #define SEC_AO_TIMERB_CUR_REG 4286579672 #define SEC_AO_SEC_JTAG_PWD_SCP_ADDR2 4286579448 #define SEC_AO_SEC_JTAG_PWD_SCP_ADDR3 4286579452 #define SEC_AO_SEC_JTAG_PWD_SCP_ADDR0 4286579440 #define SEC_AO_SEC_JTAG_PWD_SCP_ADDR1 4286579444 #define MIPI_ISP_WRARB_WEIGH1_SLV 4284842020 #define PDM_STS 4284743728 #define P_HHI_HDMI_PLL_VLOCK_CNTL 4284728132 #define SEC_PDM_HCIC_CTRL2 4284743688 #define SEC_PDM_HCIC_CTRL1 4284743684 #define SEC_EE_AUDIO_SPDIFOUT_STAT 4284753024 #define P_TS_PLL_STAT2 4284696648 #define P_TS_PLL_STAT3 4284696652 #define P_TS_PLL_STAT0 4284696640 #define P_TS_PLL_STAT1 4284696644 #define P_TS_PLL_STAT6 4284696664 #define P_TS_PLL_STAT7 4284696668 #define P_TS_PLL_STAT4 4284696656 #define P_TS_PLL_STAT5 4284696660 #define P_AED_EQ_CH2_COEF73 4284834144 #define P_TS_PLL_STAT8 4284696672 #define P_AED_EQ_CH2_COEF74 4284834148 #define P_TS_PLL_STAT9 4284696676 #define P_AED_EQ_CH2_COEF71 4284834136 #define P_AED_EQ_CH2_COEF72 4284834140 #define P_AED_EQ_CH2_COEF70 4284834132 #define HHI_MIPI_ISP_CLK_CNTL 4284727744 #define P_KL_START1 4284678276 #define P_AO_TIMER_SEC_SCP_CTRL 4286579652 #define P_KL_START0 4284678272 #define HHI_SYS_CPUB_CLK_CNTL1 4284727808 #define P_AED_EQ_CH2_COEF84 4284834168 #define SEC_MIPI_DSI_CLK_TIM1 4284760112 #define P_AED_EQ_CH2_COEF82 4284834160 #define P_AED_EQ_CH2_COEF83 4284834164 #define P_AED_EQ_CH2_COEF80 4284834152 #define P_AED_EQ_CH2_COEF81 4284834156 #define SEC_HHI_ISP_MAX_ADDR_CNTL 4284727764 #define AO_CPU_CNTL 4286578744 #define P_AO_RTI_GEN_PWR_ACK0 4286578928 #define M4_CPU_TIMESTAMP2 4286579484 #define EE_AUDIO_TODDR_C_FINISH_ADDR 4284752268 #define PDM_HPF_CTRL 4284743704 #define AO_SEC_M4_CPU_SRAM_REG0_1 4286579360 #define AO_SEC_M4_CPU_SRAM_REG0_0 4286579356 #define SEC_EE_AUDIO_FRDDR_A_STATUS1 4284752340 #define SEC_EE_AUDIO_FRDDR_A_STATUS2 4284752344 #define P_AO_TIMERA_CUR_REG 4286579664 #define SEC_EE_AUDIO_FRDDR_A_INT_ADDR 4284752336 #define P_RESET2_SEC_LEVEL 4284801096 #define AO_RTI_PWR_SYS_CPUB_CNTL1 4286579532 #define AO_RTI_PWR_SYS_CPUB_CNTL0 4286579528 #define EE_AUDIO_TDMOUT_B_MASK_VAL 4284753276 #define P_AO_IRQ_GPIO_REG 4286578820 #define HHI_VDEC2_CLK_CNTL 4284727780 #define P_EE_AUDIO_TDMIN_B_CTRL 4284752704 #define HHI_HDMI_PHY_STATUS 4284728248 #define AED_NG_STEP 4284834332 #define RO_REFCLK_PKG_CNT 4284784736 #define HHI_GCLK2_MPEG0 4284727488 #define P_EE_AUDIO_FRDDR_B_STATUS2 4284752408 #define HHI_GCLK2_MPEG2 4284727496 #define P_EE_AUDIO_FRDDR_B_STATUS1 4284752404 #define HHI_GCLK2_MPEG1 4284727492 #define EE_AUDIO_TDMIN_B_MUTE3 4284752748 #define EE_AUDIO_TDMIN_B_MUTE0 4284752736 #define EE_AUDIO_TDMIN_B_MUTE1 4284752740 #define EE_AUDIO_TDMIN_B_MUTE2 4284752744 #define EFUSE_CLR 4284678144 #define EFUSE_CLK_NANOQ_CFG01 4284696352 #define P_HHI_ISP_MEM_PD_REG1 4284727576 #define P_HHI_ISP_MEM_PD_REG0 4284727572 #define P_AED_CLIP_THD 4284834260 #define SEC_EE_AUDIO_TDMIN_A_MUTE_VAL 4284752668 #define P_RO_OMCLK_PKG_CNT 4284784744 #define PERIPHS_LOCK_PIN_MUX 4284696252 #define SEC_EE_AUDIO_TDMIN_LB_MUTE1 4284752868 #define SEC_EE_AUDIO_CLK_TDMOUT_A_CTRL 4284752016 #define SEC_EE_AUDIO_TDMIN_LB_MUTE2 4284752872 #define SEC_EE_AUDIO_TDMIN_LB_MUTE0 4284752864 #define SEC_EE_AUDIO_TDMIN_LB_MUTE3 4284752876 #define SEC_EE_AUDIO_SPDIFIN_MUTE_VAL 4284752936 #define EE_AUDIO_CLK_TDMIN_C_CTRL 4284752008 #define SEC_AO_I2C_M_0_SLAVE_ADDR 4286599172 #define SEC_AO_TIMEBASE_CNTL1 4286578772 #define AO_UART_STATUS 4286590988 #define P_AED_NG_THD1 4284834268 #define P_AED_NG_THD0 4284834264 #define HHI_FIX_PLL_STS 4284727996 #define P_AUD_LOCK_REFCLK_LAT_INT 4284784660 #define PDM_COEFF_DATA 4284743720 #define MIPI_ADAPT_PIXEL1_CNTL0 4284829832 #define MIPI_ADAPT_PIXEL1_CNTL1 4284829836 #define P_SYS_CPUB_MISC 4284696544 #define P_HHI_GP0_PLL_CNTL3 4284727372 #define P_HHI_GP0_PLL_CNTL4 4284727376 #define P_HHI_GP0_PLL_CNTL5 4284727380 #define P_EE_AUDIO_SPDIFOUT_B_CTRL0 4284753548 #define P_HHI_GP0_PLL_CNTL6 4284727384 #define P_EE_AUDIO_SPDIFOUT_B_CTRL1 4284753552 #define HHI_SYS1_PLL_STS 4284728220 #define HHI_SD_EMMC_CLK_CNTL 4284727908 #define P_AO_TIMESTAMP_CNTL 4286578868 #define SEC_AO_WATCHDOG_TCNT 4286578984 #define SEC_AED_DRC_AE_1M 4284834224 #define SEC_M4_CPU_TIMESTAMP 4286579480 #define SYS_CPU_CFG10 4284696176 #define P_EE_AUDIO_TDMOUT_B_MASK0 4284753228 #define P_EE_AUDIO_TDMOUT_B_MASK1 4284753232 #define P_AO_RTC_ALT_CLK_CNTL0 4286578836 #define P_AO_RTC_ALT_CLK_CNTL1 4286578840 #define EE_AUDIO_CLK_LOCKER_CTRL 4284752040 #define AO_TIMEBASE_CNTL 4286578788 #define SEC_HHI_GEN_CLK_CNTL 4284727848 #define P_EE_AUDIO_TDMOUT_B_MASK2 4284753236 #define P_EE_AUDIO_TDMOUT_B_MASK3 4284753240 #define HHI_HDMI_PHY_CNTL0 4284728224 #define HHI_HDMI_PHY_CNTL1 4284728228 #define HHI_HDMI_PHY_CNTL2 4284728232 #define P_HHI_GP0_PLL_CNTL0 4284727360 #define HHI_HDMI_PHY_CNTL3 4284728236 #define SEC_AO_CEC_GEN_CNTL 4286578944 #define P_HHI_GP0_PLL_CNTL1 4284727364 #define HHI_HDMI_PHY_CNTL4 4284728240 #define P_HHI_GP0_PLL_CNTL2 4284727368 #define HHI_HDMI_PHY_CNTL5 4284728244 #define SEC_HHI_VID_LOCK_CLK_CNTL 4284728264 #define SEC_EE_AUDIO_TODDR_C_STATUS2 4284752280 #define SEC_EE_AUDIO_TODDR_C_STATUS1 4284752276 #define SEC_EE_AUDIO_CLK_TDMIN_A_CTRL 4284752000 #define EE_AUDIO_SPDIFOUT_GAIN1 4284753032 #define EE_AUDIO_SPDIFOUT_GAIN0 4284753028 #define RESET0_SEC_LEVEL 4284801088 #define EE_AUDIO_TODDR_B_INIT_ADDR 4284752228 #define SEC_EE_AUDIO_MCLK_D_CTRL 4284751888 #define P_RESET2_SEC_MASK 4284801160 #define HHI_MPLL_CNTL4 4284727944 #define HHI_MPLL_CNTL3 4284727940 #define HHI_MPLL_CNTL2 4284727936 #define HHI_MPLL_CNTL1 4284727932 #define ETH_PHY_CNTL0 4284792960 #define HHI_MPLL_CNTL0 4284727928 #define ETH_PHY_CNTL2 4284792968 #define ETH_PHY_CNTL1 4284792964 #define AO_RTI_PWR_SYS_CPUB_MEM_PD1 4286579540 #define HHI_MPLL_CNTL8 4284727960 #define AO_RTI_PWR_SYS_CPUB_MEM_PD0 4286579536 #define HHI_MPLL_CNTL7 4284727956 #define HHI_MPLL_CNTL6 4284727952 #define HHI_MPLL_CNTL5 4284727948 #define AO_PWM_MISC_REG_CD 4286586888 #define P_AO_UART_MISC 4286590992 #define SEC_HHI_WAVE420L_CLK_CNTL 4284727912 #define AO_UART_CONTROL 4286590984 #define P_AED_EQ_CH1_COEF94 4284833988 #define P_AED_EQ_CH1_COEF91 4284833976 #define AO_CPU_TIMESTAMP 4286578900 #define P_AED_EQ_CH1_COEF90 4284833972 #define P_AED_EQ_CH1_COEF93 4284833984 #define P_AED_EQ_CH1_COEF92 4284833980 #define P_HHI_NANOQ_MEM_PD_REG0 4284727564 #define P_HHI_NANOQ_MEM_PD_REG1 4284727568 #define SEC_EE_AUDIO_FRDDR_C_FINISH_ADDRB 4284752480 #define P_AED_EQ_CH1_COEF84 4284833968 #define P_AED_EQ_CH1_COEF83 4284833964 #define P_AED_EQ_CH1_COEF80 4284833952 #define P_AED_EQ_CH1_COEF82 4284833960 #define P_AED_EQ_CH1_COEF81 4284833956 #define AMLUSB_A3 4284702732 #define AMLUSB_A2 4284702728 #define P_AO_MF_IR_DEC_REG0 4286611536 #define AMLUSB_A5 4284702740 #define AMLUSB_A4 4284702736 #define AMLUSB_A7 4284702748 #define AMLUSB_A6 4284702744 #define AMLUSB_A9 4284702756 #define AO_IR_DEC_DEMOD_SUM_CNT0 4286611668 #define AMLUSB_A8 4284702752 #define MIPI_DSI_CLK_TIM1 4284760112 #define EE_AUDIO_TDMOUT_B_STAT 4284753244 #define SEC_MIPI_DSI_ANA_CTRL 4284760108 #define SEC_PDM_COEFF_ADDR 4284743716 #define P_AO_MF_IR_DEC_REG2 4286611552 #define P_PREG_PAD_GPIO3_EN_N 4284695652 #define P_AO_MF_IR_DEC_REG1 4286611548 #define AMLUSB_A1 4284702724 #define P_AO_MF_IR_DEC_REG3 4286611576 #define AMLUSB_A0 4284702720 #define P_AED_EQ_CH1_COEF73 4284833944 #define P_AED_EQ_CH1_COEF72 4284833940 #define SEC_RNG_USR_STS 4284678684 #define P_AED_EQ_CH1_COEF74 4284833948 #define P_AED_EQ_CH1_COEF71 4284833936 #define P_AED_EQ_CH1_COEF70 4284833932 #define SEC_HHI_APICALGDC_CNTL 4284727656 #define P_AED_EQ_CH1_COEF54 4284833908 #define SEC_KL_RAM 4284678400 #define EE_AUDIO_CLK_TDMOUT_C_CTRL 4284752024 #define P_AED_EQ_CH1_COEF62 4284833920 #define P_AED_EQ_CH1_COEF61 4284833916 #define AO_IR_DEC_DEMOD_SUM_CNT1 4286611672 #define P_AED_EQ_CH1_COEF64 4284833928 #define P_AED_EQ_CH1_COEF63 4284833924 #define P_AED_EQ_CH1_COEF60 4284833912 #define RO_AUD_LOCK_INT_STATUS 4284784748 #define AO_CPU_TIMESTAMP2 4286578904 #define SEC_AO_IR_DEC_DEMOD_SUM_CNT0 4286611668 #define EE_AUDIO_TODDR_A_FINISH_ADDRB 4284752160 #define SEC_AO_IR_DEC_DEMOD_SUM_CNT1 4286611672 #define P_AO_SEC_JTAG_PWD_SP_ADDR2 4286579408 #define P_AO_SEC_JTAG_PWD_SP_ADDR3 4286579412 #define SEC_PERIPHS_PIN_MUX_B 4284696300 #define SEC_PERIPHS_PIN_MUX_A 4284696296 #define P_AO_SEC_JTAG_PWD_SP_ADDR0 4286579400 #define P_AO_SEC_JTAG_PWD_SP_ADDR1 4286579404 #define SEC_PERIPHS_PIN_MUX_F 4284696316 #define SEC_PERIPHS_PIN_MUX_E 4284696312 #define SEC_PERIPHS_PIN_MUX_D 4284696308 #define SEC_PERIPHS_PIN_MUX_C 4284696304 #define EE_AUDIO_TODDR_A_INIT_ADDR 4284752164 #define SEC_AO_MSG_INDEX0 4286579072 #define SEC_AO_MSG_INDEX3 4286579084 #define SEC_AO_MSG_INDEX1 4286579076 #define SEC_AO_MSG_INDEX2 4286579080 #define SEC_AO_TIMERG_HI_REG 4286579704 #define AO_I2C_M_0_SLAVE_ADDR 4286599172 #define SEC_EE_AUDIO_MST_A_SCLK_CTRL1 4284751940 #define PDM_CLKG_CTRL 4284743724 #define SEC_EE_AUDIO_MST_A_SCLK_CTRL0 4284751936 #define P_EFUSE_CLK_HEVCB_CFG0 4284696340 #define P_HHI_FIX_PLL_CNTL6 4284727992 #define SEC_PERIPHS_PIN_MUX_2 4284696264 #define P_HHI_FIX_PLL_CNTL5 4284727988 #define SEC_PERIPHS_PIN_MUX_1 4284696260 #define SEC_PERIPHS_PIN_MUX_0 4284696256 #define P_EE_AUDIO_TDMOUT_A_MUTE1 4284753200 #define SEC_PERIPHS_PIN_MUX_6 4284696280 #define P_EE_AUDIO_TDMOUT_A_MUTE0 4284753196 #define SEC_PERIPHS_PIN_MUX_5 4284696276 #define P_EE_AUDIO_TDMOUT_A_MUTE3 4284753208 #define SEC_PERIPHS_PIN_MUX_4 4284696272 #define P_EE_AUDIO_TDMOUT_A_MUTE2 4284753204 #define SEC_PERIPHS_PIN_MUX_3 4284696268 #define SEC_PERIPHS_PIN_MUX_9 4284696292 #define SEC_PERIPHS_PIN_MUX_8 4284696288 #define SEC_PERIPHS_PIN_MUX_7 4284696284 #define HHI_ISP_MEM_PD_REG1 4284727576 #define HHI_ISP_MEM_PD_REG0 4284727572 #define P_EE_AUDIO_CLK_LOCKER_CTRL 4284752040 #define P_HHI_FIX_PLL_CNTL2 4284727976 #define P_HHI_FIX_PLL_CNTL1 4284727972 #define P_HHI_FIX_PLL_CNTL4 4284727984 #define P_HHI_FIX_PLL_CNTL3 4284727980 #define P_HHI_FIX_PLL_CNTL0 4284727968 #define P_AO_SEC_AO_CPU_SRAM_REG1_0 4286579192 #define P_AO_SEC_AO_CPU_SRAM_REG1_1 4286579196 #define SEC_AED_EQ_EN 4284834192 #define SEC_RO_REF2OMCLK_CNT_L 4284784712 #define SEC_RO_REF2OMCLK_CNT_H 4284784716 #define HHI_VPU_CLK_CNTL 4284727740 #define P_DMA_STS1 4284735524 #define P_DMA_STS0 4284735520 #define P_DMA_STS3 4284735532 #define P_DMA_STS2 4284735528 #define P_DMA_STS5 4284735540 #define P_DMA_STS4 4284735536 #define SEC_EE_AUDIO_TODDR_A_INT_ADDR 4284752144 #define P_EE_AUDIO_POW_DET_TH_LO 4284753420 #define SEC_MIPI_ADAPT_PIXEL1_ST0 4284829872 #define SEC_MIPI_ADAPT_PIXEL1_ST1 4284829876 #define SEC_AO_IR_DEC_LDR_IDLE 4286611460 #define P_HHI_SYS_CPU_CLK_CNTL1 4284727644 #define AO_I2C_S_SEND_REG 4286603268 #define SEC_EE_AUDIO_TDMOUT_A_STAT 4284753180 #define HHI_VPU_CLKB_CNTL 4284727820 #define P_EE_AUDIO_FRDDR_B_CTRL1 4284752388 #define P_EE_AUDIO_FRDDR_B_CTRL0 4284752384 #define HHI_HIFI_PLL_STS 4284727540 #define SEC_PDM_F3_CTRL 4284743700 #define AMLUSB_B4 4284719120 #define AMLUSB_B3 4284719116 #define AMLUSB_B6 4284719128 #define AMLUSB_B5 4284719124 #define P_AO_MF_IR_DEC_WIDTH_NEW 4286611600 #define AMLUSB_B8 4284719136 #define AMLUSB_B7 4284719132 #define AMLUSB_B9 4284719140 #define AMLUSB_B0 4284719104 #define AMLUSB_B2 4284719112 #define AMLUSB_B1 4284719108 #define AO_SEC_SD_CFG10 4286579240 #define AO_SEC_SD_CFG11 4286579244 #define AO_SEC_SD_CFG12 4286579248 #define AO_SEC_SD_CFG13 4286579252 #define AO_SEC_SD_CFG14 4286579256 #define AO_SEC_SD_CFG15 4286579260 #define P_EE_AUDIO_TDMOUT_C_GAIN0 4284753312 #define P_EE_AUDIO_TDMOUT_C_GAIN1 4284753316 #define SEC_AUD_LOCK_OMCLK_DS_INT 4284784680 #define P_EE_AUDIO_POW_DET_TH_HI 4284753416 #define EFUSE_CFG_LOCK 4284696320 #define SEC_HHI_WAVE420L_CLK_CNTL2 4284727916 #define AO_MF_IR_DEC_LDR_IDLE 4286611524 #define SEC_EE_AUDIO_SPDIFOUT_B_STAT 4284753536 #define P_EE_AUDIO_TDMIN_B_STAT 4284752728 #define AO_I2C_M_0_CONTROL_REG 4286599168 #define SEC_BUS_MON0_DATA_MSK 4284696080 #define SEC_EE_AUDIO_LB_LB_CH_ID1 4284752596 #define SEC_EE_AUDIO_LB_LB_CH_ID0 4284752592 #define P_AO_SAR_ADC_CHAN_LIST 4286615556 #define EFUSE_CLK_ENCP_CFG0 4284696332 #define SEC_AED_NG_CNT 4284834328 #define P_HHI_VDAC_CNTL1 4284728048 #define P_HHI_VDAC_CNTL0 4284728044 #define P_AO_I2C_M_0_RDATA_REG0 4286599192 #define SEC_HPG_TIMER 4284727356 #define P_AO_I2C_M_0_RDATA_REG1 4286599196 #define BUS_CFG0 4284695552 #define AO_SEC_JTAG_PWD_SCP_CNTL 4286579436 #define BUS_CFG7 4284695580 #define BUS_CFG8 4284695584 #define BUS_CFG5 4284695572 #define BUS_CFG6 4284695576 #define BUS_CFG3 4284695564 #define SEC_AO_WATCHDOG_CNTL1 4286578980 #define BUS_CFG4 4284695568 #define P_EE_AUDIO_SPDIFOUT_MUTE_VAL 4284753100 #define BUS_CFG1 4284695556 #define BUS_CFG2 4284695560 #define SEC_AO_IR_DEC_DEMOD_CNTL1 4286611652 #define SEC_AO_IR_DEC_DEMOD_CNTL0 4286611648 #define BUS_CFG9 4284695588 #define SEC_AED_NG_CTL 4284834276 #define RESET0_SEC_REGISTER 4284801024 #define SEC_AO_MF_IR_DEC_FIFO_CTL 4286611596 #define EE_AUDIO_TDMIN_B_CTRL 4284752704 #define AO_I2C_M_0_TIMEOUT_TH 4286599200 #define P_AO_CEC_CLK_CNTL_REG0 4286578804 #define AO_CECB_CLK_CNTL_REG0 4286579328 #define AO_CECB_CLK_CNTL_REG1 4286579332 #define SEC_MIPI_DSI_LP_TIM 4284760084 #define AO_SAR_ADC_CHNL01 4286615608 #define P_AED_EQ_CH1_COEF04 4284833808 #define P_AED_EQ_CH1_COEF03 4284833804 #define P_AED_EQ_CH1_COEF00 4284833792 #define P_AED_EQ_CH1_COEF02 4284833800 #define P_AED_EQ_CH1_COEF01 4284833796 #define SEC_EFUSE_CLR 4284678144 #define SEC_HHI_SYS_CPU_RESET_CNTL 4284727648 #define SEC_MIPI_ADAPT_ALIG_ST0 4284829928 #define SEC_MIPI_ADAPT_ALIG_ST1 4284829932 #define AO_SAR_ADC_CHNL23 4286615612 #define P_PDM_CLKG_CTRL 4284743724 #define SEC_EE_AUDIO_TODDR_A_FINISH_ADDRB 4284752160 #define P_EE_AUDIO_TODDR_A_INT_ADDR 4284752144 #define EE_AUDIO_TODDR_C_START_ADDR 4284752264 #define P_AED_DRC_K0 4284834252 #define P_HHI_GCLK2_OTHER 4284727504 #define P_AED_DRC_K1 4284834256 #define SEC_AO_SAR_ADC_CHAN_LIST 4286615556 #define AED_ED_CTL 4284834280 #define P_SYS_CPU_CFG10 4284696176 #define SEC_AO_SEC_GP_CFG11 4286579308 #define SEC_AO_SEC_GP_CFG10 4286579304 #define SEC_AO_SEC_GP_CFG13 4286579316 #define SEC_AO_SEC_GP_CFG12 4286579312 #define P_BUS_MON0_DATA_MSK 4284696080 #define P_MIPI_DSI_ANA_CTRL 4284760108 #define SEC_AO_SEC_GP_CFG15 4286579324 #define SEC_AO_SEC_GP_CFG14 4286579320 #define HHI_SYS_CPU_CLK_CNTL1 4284727644 #define MIPI_ISP_RDARB_MODE 4284841984 #define AO_SAR_ADC_CHNL45 4286615616 #define SEC_AO_SEC_AO_CPU_SRAM_REG1_1 4286579196 #define SEC_AO_SEC_AO_CPU_SRAM_REG1_0 4286579192 #define SEC_EE_AUDIO_TDMIN_A_SWAP 4284752644 #define P_AO_TIMERF_REG 4286579692 #define P_EE_AUDIO_FRDDR_C_STATUS2 4284752472 #define P_EE_AUDIO_FRDDR_C_STATUS1 4284752468 #define P_AED_EQ_CH1_COEF44 4284833888 #define AO_SAR_ADC_DELTA_10 4286615592 #define P_AED_EQ_CH1_COEF43 4284833884 #define P_AO_PWM_MISC_REG_CD 4286586888 #define AO_RTI_PWR_SYS_CPU_MEM_PD0 4286578932 #define AO_RTI_PWR_SYS_CPU_MEM_PD1 4286578936 #define P_BUS_MON1_DATA 4284696088 #define HHI_HDMI_PLL_VLOCK_CNTL 4284728132 #define P_AED_EQ_CH1_COEF51 4284833896 #define P_AED_EQ_CH1_COEF50 4284833892 #define P_AED_EQ_CH1_COEF53 4284833904 #define P_AED_EQ_CH1_COEF52 4284833900 #define P_AED_EQ_CH1_COEF33 4284833864 #define P_AED_EQ_CH1_COEF32 4284833860 #define P_EE_AUDIO_SPDIFOUT_B_PREAMB 4284753556 #define P_AED_EQ_CH1_COEF34 4284833868 #define P_AO_SEC_SD_CFG1 4286579204 #define P_AO_SEC_SD_CFG0 4286579200 #define SEC_EE_AUDIO_TDMOUT_C_GAIN1 4284753316 #define P_AO_SEC_SD_CFG5 4286579220 #define P_AO_SEC_SD_CFG4 4286579216 #define P_AO_SEC_SD_CFG3 4286579212 #define SEC_EE_AUDIO_TDMOUT_C_GAIN0 4284753312 #define P_AO_SEC_SD_CFG2 4286579208 #define P_AO_SEC_SD_CFG9 4286579236 #define P_AO_SEC_SD_CFG8 4286579232 #define AO_SAR_ADC_CHNL67 4286615620 #define P_AO_SEC_SD_CFG7 4286579228 #define P_AO_SEC_SD_CFG6 4286579224 #define P_AED_EQ_CH1_COEF40 4284833872 #define P_AED_EQ_CH1_COEF42 4284833880 #define P_AED_EQ_CH1_COEF41 4284833876 #define P_AED_EQ_CH1_COEF22 4284833840 #define P_AED_EQ_CH1_COEF21 4284833836 #define P_AED_EQ_CH1_COEF24 4284833848 #define P_AO_PWM_MISC_REG_AB 4286607368 #define P_AED_EQ_CH1_COEF23 4284833844 #define P_AO_CECB_CLK_CNTL_REG1 4286579332 #define AO_MF_IR_DEC_DURATN2 4286611556 #define AO_MF_IR_DEC_DURATN3 4286611560 #define P_AO_CECB_CLK_CNTL_REG0 4286579328 #define SEC_HHI_GP0_PLL_STS 4284727388 #define P_EE_AUDIO_MST_A_SCLK_CTRL1 4284751940 #define P_EE_AUDIO_MST_A_SCLK_CTRL0 4284751936 #define P_AED_EQ_CH1_COEF31 4284833856 #define P_AED_EQ_CH1_COEF30 4284833852 #define SEC_AO_TIMERB_REG 4286579668 #define P_AED_EQ_CH1_COEF14 4284833828 #define PREG_PAD_GPIO0_O 4284695620 #define P_AED_EQ_CH1_COEF11 4284833816 #define PREG_PAD_GPIO0_I 4284695624 #define P_AED_EQ_CH1_COEF10 4284833812 #define P_AED_EQ_CH1_COEF13 4284833824 #define P_AED_EQ_CH1_COEF12 4284833820 #define SEC_AED_NG_CNT_THD 4284834272 #define EE_AUDIO_FRDDR_C_FINISH_ADDRB 4284752480 #define P_AED_EQ_CH1_COEF20 4284833832 #define P_EE_AUDIO_SPDIFOUT_CHSTSA 4284753092 #define P_EE_AUDIO_SPDIFOUT_CHSTSB 4284753096 #define P_RESET0_SEC_REGISTER 4284801024 #define HHI_SYS_CPU_CLK_CNTL 4284727708 #define SEC_AED_EQ_CH1_COEF01 4284833796 #define P_EE_AUDIO_SPDIFOUT_CHSTS3 4284753064 #define SEC_AED_EQ_CH1_COEF00 4284833792 #define P_EE_AUDIO_SPDIFOUT_CHSTS4 4284753068 #define P_EE_AUDIO_SPDIFOUT_CHSTS1 4284753056 #define P_EE_AUDIO_SPDIFOUT_CHSTS2 4284753060 #define SEC_AED_EQ_CH1_COEF04 4284833808 #define P_EE_AUDIO_SPDIFOUT_CHSTS0 4284753052 #define SEC_AED_EQ_CH1_COEF03 4284833804 #define SEC_AED_EQ_CH1_COEF02 4284833800 #define P_AO_UART2_MISC 4286595088 #define P_EE_AUDIO_SPDIFOUT_CHSTS9 4284753088 #define P_EE_AUDIO_SPDIFOUT_CHSTS7 4284753080 #define P_EE_AUDIO_SPDIFOUT_CHSTS8 4284753084 #define P_EE_AUDIO_SPDIFOUT_CHSTS5 4284753072 #define P_EE_AUDIO_SPDIFOUT_CHSTS6 4284753076 #define SEC_AO_SEC_REG0 4286579008 #define SEC_AED_EQ_CH1_COEF12 4284833820 #define SEC_AED_EQ_CH1_COEF11 4284833816 #define EE_AUDIO_RESAMPLE_CTRL0 4284752960 #define SEC_AED_EQ_CH1_COEF10 4284833812 #define SEC_AED_EQ_CH1_COEF14 4284833828 #define SEC_AED_EQ_CH1_COEF13 4284833824 #define EE_AUDIO_RESAMPLE_CTRL3 4284752972 #define EE_AUDIO_RESAMPLE_CTRL1 4284752964 #define EE_AUDIO_RESAMPLE_CTRL2 4284752968 #define SEC_AO_METAL_REVISION 4286578812 #define SEC_AED_EQ_CH1_COEF30 4284833852 #define SEC_AED_EQ_CH1_COEF23 4284833844 #define SEC_AED_EQ_CH1_COEF22 4284833840 #define SEC_AED_EQ_CH1_COEF21 4284833836 #define SEC_AED_EQ_CH1_COEF20 4284833832 #define SEC_AED_EQ_CH1_COEF24 4284833848 #define EE_AUDIO_SPDIFOUT_CHSTS8 4284753084 #define EE_AUDIO_SPDIFOUT_CHSTS9 4284753088 #define EE_AUDIO_SPDIFOUT_CHSTS4 4284753068 #define EE_AUDIO_SPDIFOUT_CHSTS5 4284753072 #define EE_AUDIO_SPDIFOUT_CHSTS6 4284753076 #define EE_AUDIO_SPDIFOUT_CHSTS7 4284753080 #define P_EE_AUDIO_TODDR_B_START_ADDRB 4284752220 #define EE_AUDIO_SPDIFOUT_CHSTS0 4284753052 #define EE_AUDIO_SPDIFOUT_CHSTS1 4284753056 #define EE_AUDIO_SPDIFOUT_CHSTS2 4284753060 #define EE_AUDIO_SPDIFOUT_CHSTS3 4284753064 #define SEC_AED_EQ_CH1_COEF41 4284833876 #define P_AED_DRC_AE 4284834212 #define SEC_AED_EQ_CH1_COEF40 4284833872 #define SEC_AED_EQ_CH1_COEF34 4284833868 #define SEC_AED_EQ_CH1_COEF33 4284833864 #define SEC_AED_EQ_CH1_COEF32 4284833860 #define SEC_AED_EQ_CH1_COEF31 4284833856 #define AO_SAR_ADC_REG3 4286615564 #define SEC_HHI_FIX_PLL_CNTL0 4284727968 #define SEC_HHI_FIX_PLL_CNTL1 4284727972 #define SEC_HHI_FIX_PLL_CNTL2 4284727976 #define SEC_HHI_FIX_PLL_CNTL3 4284727980 #define SEC_AED_EQ_CH1_COEF52 4284833900 #define SEC_AED_EQ_CH1_COEF51 4284833896 #define AO_SAR_ADC_REG0 4286615552 #define SEC_AED_EQ_CH1_COEF50 4284833892 #define EE_AUDIO_FRDDR_A_CTRL1 4284752324 #define EE_AUDIO_FRDDR_A_CTRL0 4284752320 #define SEC_AED_EQ_CH1_COEF44 4284833888 #define SEC_AED_EQ_CH1_COEF43 4284833884 #define SEC_AED_EQ_CH1_COEF42 4284833880 #define SEC_HHI_FIX_PLL_CNTL4 4284727984 #define SEC_HHI_FIX_PLL_CNTL5 4284727988 #define SEC_HHI_FIX_PLL_CNTL6 4284727992 #define EE_AUDIO_SPDIFOUT_CHSTSA 4284753092 #define EE_AUDIO_SPDIFOUT_CHSTSB 4284753096 #define P_SYS_CPUB_CFG10 4284696496 #define SEC_EE_AUDIO_TDMOUT_B_MUTE3 4284753272 #define SEC_EE_AUDIO_TDMOUT_B_MUTE2 4284753268 #define SEC_EE_AUDIO_TDMOUT_B_MUTE1 4284753264 #define SEC_EE_AUDIO_TDMOUT_B_MUTE0 4284753260 #define SEC_AED_EQ_CH1_COEF63 4284833924 #define SEC_AED_EQ_CH1_COEF62 4284833920 #define SEC_AED_EQ_CH1_COEF61 4284833916 #define SEC_AED_EQ_CH1_COEF60 4284833912 #define P_MIPI_DSI_WAKEUP_TIM 4284760096 #define SEC_HHI_GCLK2_OTHER 4284727504 #define SEC_AED_EQ_CH1_COEF54 4284833908 #define SEC_AED_EQ_CH1_COEF53 4284833904 #define SEC_AO_PWM_TIME_AB 4286607376 #define P_AO_TIMERG_HI_REG 4286579704 #define HHI_VDEC4_CLK_CNTL 4284727788 #define P_EFUSE_CLK_ENCP_CFG0 4284696332 #define SEC_AED_EQ_CH1_COEF70 4284833932 #define P_AO_TIMEBASE_CNTL1 4286578772 #define SEC_AED_EQ_CH1_COEF74 4284833948 #define SEC_AED_EQ_CH1_COEF73 4284833944 #define SEC_AED_EQ_CH1_COEF72 4284833940 #define SEC_AED_EQ_CH1_COEF71 4284833936 #define SEC_AED_EQ_CH1_COEF64 4284833928 #define SEC_AO_IR_DEC_FRAME 4286611476 #define P_DMA_T4 4284735504 #define P_DMA_T5 4284735508 #define P_AO_SAR_ADC_LAST_RD 4286615572 #define P_DMA_T2 4284735496 #define P_DMA_T3 4284735500 #define SEC_AED_EQ_CH1_COEF81 4284833956 #define P_DMA_T0 4284735488 #define SEC_AED_EQ_CH1_COEF80 4284833952 #define P_AED_DRC_EN 4284834208 #define P_DMA_T1 4284735492 #define SEC_AED_EQ_CH1_COEF84 4284833968 #define P_SECE_TIMER_HIG 4284696108 #define SEC_AED_EQ_CH1_COEF83 4284833964 #define SEC_AED_EQ_CH1_COEF82 4284833960 #define PROD_TEST_REG0 4284695936 #define PROD_TEST_REG1 4284695940 #define PROD_TEST_REG2 4284695944 #define SEC_AED_EQ_CH1_COEF92 4284833980 #define SEC_AED_EQ_CH1_COEF91 4284833976 #define SEC_AED_EQ_CH1_COEF90 4284833972 #define PROD_TEST_REG3 4284695948 #define SEC_AED_EQ_CH1_COEF94 4284833988 #define SEC_AED_EQ_CH1_COEF93 4284833984 #define SEC_HHI_HDMI_PHY_CNTL1 4284728228 #define SEC_HHI_HDMI_PHY_CNTL0 4284728224 #define SEC_HHI_HDMI_PHY_CNTL3 4284728236 #define SEC_HHI_HDMI_PHY_CNTL2 4284728232 #define SEC_HHI_HDMI_PHY_CNTL5 4284728244 #define SEC_HHI_HDMI_PHY_CNTL4 4284728240 #define HHI_VID_PLL_CLK_DIV 4284727712 #define P_AO_CEC_CLK_CNTL_REG1 4286578808 #define SEC_EE_AUDIO_TDMIN_A_MUTE1 4284752676 #define SEC_EE_AUDIO_TDMIN_A_MUTE0 4284752672 #define P_AO_CEC_INTR_MASKN 4286578952 #define SEC_EE_AUDIO_TDMIN_A_MUTE3 4284752684 #define SEC_EE_AUDIO_TDMIN_A_MUTE2 4284752680 #define SEC_AO_SEC_SP_CFG12 4286579632 #define SEC_AO_SEC_SP_CFG13 4286579636 #define SEC_AO_SEC_SP_CFG14 4286579640 #define SEC_AO_SEC_SP_CFG15 4286579644 #define AED_EQ_VOLUME_SLEW_CNT 4284834200 #define P_AO_SEC_AO_CPU_SRAM_REG0_0 4286579184 #define P_AO_SEC_AO_CPU_SRAM_REG0_1 4286579188 #define SEC_AO_CECB_RW_REG 4286579340 #define ASYNC_FIFO_LOCK_ADR 4284696096 #define P_AO_SEC_M4_CPU_SRAM_REG2_0 4286579372 #define P_SCR_HIU 4284727340 #define EE_AUDIO_FRDDR_A_INIT_ADDR 4284752356 #define SEC_AO_UART_RFIFO 4286590980 #define AO_CEC_GEN_CNTL 4286578944 #define SEC_AO_SEC_SP_CFG10 4286579624 #define SEC_AO_SEC_SP_CFG11 4286579628 #define SEC_EE_AUDIO_CLK_GATE_EN 4284751872 #define SEC_EE_AUDIO_SPDIFOUT_B_PREAMB 4284753556 #define SEC_AO_PWM_TIME_CD 4286586896 #define P_HHI_GP0_PLL_STS 4284727388 #define P_AED_DRC_AA 4284834216 #define EFUSE_LIC0 4284678192 #define P_AED_DRC_AD 4284834220 #define P_EE_AUDIO_TODDR_B_INT_ADDR 4284752208 #define EFUSE_LIC1 4284678196 #define EFUSE_LIC2 4284678200 #define EFUSE_LIC3 4284678204 #define SEC_AO_SEC_JTAG_PWD_SP_2 4286579388 #define SEC_AO_SEC_JTAG_PWD_SP_3 4286579392 #define SEC_AO_SEC_JTAG_PWD_SP_0 4286579380 #define SEC_AO_SEC_JTAG_PWD_SP_1 4286579384 #define MIPI_ISP_WRARB_WEIGH0_SLV 4284842016 #define SEC_AO_UART_STATUS 4286590988 #define P_HHI_GCLK_SP_MPEG 4284727636 #define SEC_AO_MF_IR_DEC_REPEAT_DET 4286611604 #define SEC_HHI_VID_CLK_CNTL2 4284727700 #define P_AO_I2C_M_0_SLAVE_ADDR 4286599172 #define SEC_AO_MF_IR_DEC_REG0 4286611536 #define SEC_AO_MF_IR_DEC_REG1 4286611548 #define SEC_AO_MF_IR_DEC_REG2 4286611552 #define SEC_AO_MF_IR_DEC_REG3 4286611576 #define AO_IR_DEC_REG0 4286611472 #define AO_IR_DEC_REG1 4286611484 #define AO_I2C_M_0_RDATA_REG0 4286599192 #define AO_I2C_M_0_RDATA_REG1 4286599196 #define P_M4_CPU_TIMESTAMP2 4286579484 #define P_MIPI_ISP_RDARB_MODE 4284841984 #define SEC_AED_EQ_CH2_COEF94 4284834188 #define SEC_AED_EQ_CH2_COEF90 4284834172 #define SEC_AED_EQ_CH2_COEF91 4284834176 #define SEC_AED_EQ_CH2_COEF92 4284834180 #define SEC_AED_EQ_CH2_COEF93 4284834184 #define SEC_EFUSE_CLK_HEVCB_CFG0 4284696340 #define EE_AUDIO_POW_DET_VALUE 4284753424 #define SEC_EE_AUDIO_TODDR_A_FINISH_ADDR 4284752140 #define SEC_AED_EQ_CH2_COEF83 4284834164 #define SEC_AED_EQ_CH2_COEF84 4284834168 #define SEC_AED_EQ_CH2_COEF80 4284834152 #define SEC_AED_EQ_CH2_COEF81 4284834156 #define SEC_AED_EQ_CH2_COEF82 4284834160 #define SEC_AO_IR_DEC_DEMOD_CNT1 4286611680 #define SEC_AO_IR_DEC_DEMOD_CNT0 4286611676 #define SEC_AED_EQ_CH2_COEF72 4284834140 #define SEC_AED_EQ_CH2_COEF73 4284834144 #define SEC_AED_EQ_CH2_COEF74 4284834148 #define M4_CPU_CNTL_NS 4286579460 #define SEC_AED_EQ_CH2_COEF70 4284834132 #define SEC_AED_EQ_CH2_COEF71 4284834136 #define P_EE_AUDIO_SPDIFOUT_B_STAT 4284753536 #define SEC_AO_SEC_GP_CFG1 4286579268 #define SEC_AO_SEC_GP_CFG2 4286579272 #define SEC_AO_SEC_GP_CFG0 4286579264 #define SEC_AO_SEC_GP_CFG5 4286579284 #define SEC_AO_SEC_GP_CFG6 4286579288 #define P_EE_AUDIO_TDMOUT_B_SWAP 4284753224 #define SEC_AO_SEC_GP_CFG3 4286579276 #define SEC_AO_SEC_GP_CFG4 4286579280 #define SEC_AO_SEC_GP_CFG9 4286579300 #define SEC_AO_SEC_GP_CFG7 4286579292 #define SEC_AO_SEC_GP_CFG8 4286579296 #define EE_AUDIO_TODDR_A_CTRL0 4284752128 #define SEC_AO_SEC_SP_CFG7 4286579612 #define SEC_AO_SEC_SP_CFG8 4286579616 #define KL_START0 4284678272 #define SEC_AO_SEC_SP_CFG9 4286579620 #define EE_AUDIO_TODDR_A_CTRL1 4284752132 #define KL_START1 4284678276 #define SEC_AED_EQ_CH2_COEF61 4284834116 #define SEC_AO_SEC_SP_CFG3 4286579596 #define SEC_AED_EQ_CH2_COEF62 4284834120 #define SEC_AO_SEC_SP_CFG4 4286579600 #define SEC_AED_EQ_CH2_COEF63 4284834124 #define SEC_AO_SEC_SP_CFG5 4286579604 #define SEC_AED_EQ_CH2_COEF64 4284834128 #define SEC_AO_SEC_SP_CFG6 4286579608 #define SEC_AO_SEC_SP_CFG0 4286579584 #define SEC_AO_SEC_SP_CFG1 4286579588 #define SEC_AED_EQ_CH2_COEF60 4284834112 #define SEC_AO_SEC_SP_CFG2 4286579592 #define P_HHI_MEM_PD_REG0 4284727552 #define SEC_AED_EQ_CH2_COEF54 4284834108 #define SEC_AO_TIMERF_HI_REG 4286579696 #define P_EE_AUDIO_FRDDR_A_CTRL0 4284752320 #define P_EE_AUDIO_FRDDR_A_CTRL1 4284752324 #define P_HIU_MAILBOX_SET_2 4284728348 #define P_HIU_MAILBOX_SET_3 4284728360 #define P_HIU_MAILBOX_SET_4 4284728372 #define HHI_SYS_PLL_STS 4284728080 #define P_HIU_MAILBOX_SET_5 4284728384 #define P_ETH_PHY_DBG_CTL0 4284792832 #define P_ETH_PHY_DBG_CTL1 4284792836 #define P_HIU_MAILBOX_SET_0 4284728324 #define P_HIU_MAILBOX_SET_1 4284728336 #define SEC_AED_EQ_CH2_COEF50 4284834092 #define SEC_AED_EQ_CH2_COEF51 4284834096 #define SEC_AED_EQ_CH2_COEF52 4284834100 #define SEC_AED_EQ_CH2_COEF53 4284834104 #define P_BUS_STS8 4284695992 #define P_BUS_STS9 4284695996 #define HHI_GCLK_SP_MPEG 4284727636 #define SEC_AED_EQ_CH2_COEF43 4284834084 #define SEC_AED_EQ_CH2_COEF44 4284834088 #define SEC_HHI_HDMI_PLL_CNTL6 4284728120 #define P_BUS_STS0 4284695960 #define SEC_HHI_HDMI_PLL_CNTL5 4284728116 #define P_BUS_STS1 4284695964 #define P_BUS_STS2 4284695968 #define P_BUS_STS3 4284695972 #define SEC_HHI_HDMI_PLL_CNTL2 4284728104 #define P_HIU_MAILBOX_SET_6 4284728396 #define EE_AUDIO_TDMOUT_A_CTRL0 4284753152 #define P_BUS_STS4 4284695976 #define SEC_HHI_HDMI_PLL_CNTL1 4284728100 #define P_HIU_MAILBOX_SET_7 4284728408 #define P_BUS_STS5 4284695980 #define SEC_HHI_HDMI_PLL_CNTL4 4284728112 #define P_BUS_STS6 4284695984 #define SEC_HHI_HDMI_PLL_CNTL3 4284728108 #define EE_AUDIO_TDMOUT_A_CTRL1 4284753156 #define P_BUS_STS7 4284695988 #define SEC_HHI_HDMI_PLL_CNTL0 4284728096 #define SEC_AED_EQ_CH2_COEF40 4284834072 #define SEC_AED_EQ_CH2_COEF41 4284834076 #define P_EE_AUDIO_MCLK_D_CTRL 4284751888 #define SEC_AED_EQ_CH2_COEF42 4284834080 #define ETH_PHY_DBG_CTL0 4284792832 #define DMA_T0 4284735488 #define SEC_AED_EQ_CH2_COEF32 4284834060 #define SEC_AED_EQ_CH2_COEF33 4284834064 #define SEC_AED_EQ_CH2_COEF34 4284834068 #define ETH_PHY_DBG_CTL1 4284792836 #define DMA_T5 4284735508 #define DMA_T4 4284735504 #define DMA_T3 4284735500 #define DMA_T2 4284735496 #define DMA_T1 4284735492 #define SEC_EE_AUDIO_TDMIN_B_CTRL 4284752704 #define SEC_AED_EQ_CH2_COEF30 4284834052 #define P_EE_AUDIO_TODDR_C_CTRL1 4284752260 #define SEC_AED_EQ_CH2_COEF31 4284834056 #define P_EE_AUDIO_TODDR_C_CTRL0 4284752256 #define DDR_RD1_LBUF_STATUS 4284830020 #define SEC_HHI_MPLL_CNTL7 4284727956 #define AED_MUTE 4284834204 #define SEC_HHI_MPLL_CNTL8 4284727960 #define SEC_AED_EQ_CH2_COEF21 4284834036 #define SEC_AED_EQ_CH2_COEF22 4284834040 #define SEC_AED_EQ_CH2_COEF23 4284834044 #define SEC_AED_EQ_CH2_COEF24 4284834048 #define SEC_BUS_MON1_DATA_MSK 4284696092 #define SEC_HHI_MPLL_CNTL1 4284727932 #define SEC_HHI_MPLL_CNTL2 4284727936 #define SEC_HHI_MPLL_CNTL0 4284727928 #define SEC_AED_EQ_CH2_COEF20 4284834032 #define SEC_HHI_MPLL_CNTL5 4284727948 #define SEC_HHI_MPLL_CNTL6 4284727952 #define SEC_HHI_MPLL_CNTL3 4284727940 #define SEC_HHI_MPLL_CNTL4 4284727944 #define SEC_AED_EQ_CH2_COEF14 4284834028 #define SEC_AED_EQ_CH2_COEF10 4284834012 #define SEC_AED_EQ_CH2_COEF11 4284834016 #define SEC_AED_EQ_CH2_COEF12 4284834020 #define SEC_AED_EQ_CH2_COEF13 4284834024 #define SEC_EE_AUDIO_TDMOUT_A_MUTE3 4284753208 #define SEC_EE_AUDIO_TDMOUT_A_MUTE2 4284753204 #define SEC_EE_AUDIO_TDMOUT_A_MUTE1 4284753200 #define SEC_EE_AUDIO_TDMOUT_A_MUTE0 4284753196 #define P_AO_MF_IR_DEC_LDR_IDLE 4286611524 #define SEC_AED_EQ_CH2_COEF03 4284834004 #define SEC_AED_EQ_CH2_COEF04 4284834008 #define SEC_AED_EQ_CH2_COEF00 4284833992 #define SEC_AED_EQ_CH2_COEF01 4284833996 #define SEC_AED_EQ_CH2_COEF02 4284834000 #define SEC_EFUSE_CLK_NANOQ_CFG01 4284696352 #define EE_AUDIO_TODDR_C_CTRL1 4284752260 #define EE_AUDIO_TODDR_C_CTRL0 4284752256 #define P_HHI_VID_LOCK_CLK_CNTL 4284728264 #define HHI_GP0_PLL_CNTL3 4284727372 #define HHI_GP0_PLL_CNTL2 4284727368 #define HHI_GP0_PLL_CNTL1 4284727364 #define HHI_GP0_PLL_CNTL0 4284727360 #define HHI_GP0_PLL_CNTL6 4284727384 #define HHI_GP0_PLL_CNTL5 4284727380 #define HHI_GP0_PLL_CNTL4 4284727376 #define P_KL_RESP1_0 4284678304 #define P_KL_RESP1_2 4284678312 #define P_KL_RESP1_1 4284678308 #define P_EE_AUDIO_POW_DET_VALUE 4284753424 #define P_KL_RESP1_3 4284678316 #define EE_AUDIO_TDMOUT_C_CTRL0 4284753280 #define P_MIPI_DSI_TURN_WCHDOG 4284760116 #define P_AUD_LOCK_IMCLK_LAT_INT 4284784664 #define AO_UART2_WFIFO 4286595072 #define EE_AUDIO_TDMOUT_B_CTRL1 4284753220 #define SEC_HHI_SYS1_PLL_STS 4284728220 #define EE_AUDIO_TDMOUT_B_CTRL0 4284753216 #define SEC_HHI_HDCP22_CLK_CNTL 4284727792 #define P_EE_AUDIO_MST_E_SCLK_CTRL1 4284751972 #define P_EE_AUDIO_MST_E_SCLK_CTRL0 4284751968 #define AO_UART2_MISC 4286595088 #define EE_AUDIO_TDMOUT_C_CTRL1 4284753284 #define P_EE_AUDIO_MCLK_A_CTRL 4284751876 #define P_EE_AUDIO_TDMIN_A_MASK0 4284752648 #define P_EE_AUDIO_TDMIN_A_MASK1 4284752652 #define P_EE_AUDIO_TDMIN_A_MASK2 4284752656 #define P_EE_AUDIO_TDMIN_A_MASK3 4284752660 #define SEC_RO_OMCLK_PKG_CNT 4284784744 #define EE_AUDIO_TODDR_B_CTRL1 4284752196 #define EE_AUDIO_TODDR_B_CTRL0 4284752192 #define P_EE_AUDIO_TODDR_A_FINISH_ADDR 4284752140 #define SEC_SYS_CPU_STATUS0 4284696192 #define SEC_SYS_CPU_STATUS2 4284696200 #define SEC_SYS_CPU_STATUS1 4284696196 #define SEC_SYS_CPU_STATUS4 4284696208 #define SEC_SYS_CPU_STATUS3 4284696204 #define SEC_AO_TIMESTAMP_CNTL 4286578868 #define P_HHI_VPU_CLK_CNTL 4284727740 #define M4_CPU_CNTL 4286579456 #define P_EE_AUDIO_SPDIFIN_STAT2 4284752932 #define SEC_SYS_CPU_STATUS5 4284696212 #define P_EE_AUDIO_SPDIFIN_STAT1 4284752928 #define EE_AUDIO_SPDIFOUT_B_STAT 4284753536 #define P_EE_AUDIO_SPDIFIN_STAT0 4284752924 #define EE_AUDIO_TODDR_C_INIT_ADDR 4284752292 #define P_AO_MF_IR_DEC_REPEAT_DET 4286611604 #define P_AO_RTI_PWR_CNTL_REG0 4286578704 #define SEC_HHI_GP0_PLL_CNTL0 4284727360 #define SEC_HHI_GP0_PLL_CNTL1 4284727364 #define SEC_HHI_GP0_PLL_CNTL6 4284727384 #define EE_AUDIO_LB_STS 4284752600 #define SEC_HHI_GP0_PLL_CNTL4 4284727376 #define SEC_HHI_GP0_PLL_CNTL5 4284727380 #define SEC_HHI_GP0_PLL_CNTL2 4284727368 #define SEC_HHI_GP0_PLL_CNTL3 4284727372 #define EE_AUDIO_FRDDR_A_INT_ADDR 4284752336 #define AO_SEC_SHARED_AHB_SRAM_REG0_0 4286579108 #define AO_SEC_SHARED_AHB_SRAM_REG0_1 4286579112 #define EE_AUDIO_POW_DET_TH_LO 4284753420 #define P_AO_MF_IR_DEC_FILTE 4286611588 #define P_AO_SEC_GP_CFG0 4286579264 #define P_AO_SEC_GP_CFG1 4286579268 #define P_AO_SEC_GP_CFG4 4286579280 #define SEC_AO_CPU_TIMESTAMP 4286578900 #define P_AO_SEC_GP_CFG5 4286579284 #define P_AO_SEC_GP_CFG2 4286579272 #define P_AO_SEC_GP_CFG3 4286579276 #define P_AO_SEC_GP_CFG8 4286579296 #define P_AO_SEC_GP_CFG9 4286579300 #define P_AO_SEC_GP_CFG6 4286579288 #define P_AO_SEC_GP_CFG7 4286579292 #define SEC_AO_UART_WFIFO 4286590976 #define SEC_EE_AUDIO_CLK_LOCKER_CTRL 4284752040 #define P_AO_TIMERC_REG 4286579676 #define SEC_EE_AUDIO_FRDDR_C_STATUS2 4284752472 #define SEC_EE_AUDIO_FRDDR_C_STATUS1 4284752468 #define SEC_AO_MF_IR_DEC_FRAME1 4286611564 #define MIPI_ADAPT_PIXEL1_ST1 4284829876 #define MIPI_ADAPT_PIXEL1_ST0 4284829872 #define EE_AUDIO_TDMIN_C_MUTE0 4284752800 #define EE_AUDIO_TDMIN_C_MUTE1 4284752804 #define SEC_AO_TIMERE_REG 4286579684 #define AO_SEC_SHARED_AHB_SRAM_REG0_2 4286579116 #define EE_AUDIO_TDMIN_C_MUTE2 4284752808 #define EE_AUDIO_TDMIN_C_MUTE3 4284752812 #define SEC_MIPI_ADAPT_PIXEL1_CNTL1 4284829836 #define SEC_MIPI_ADAPT_PIXEL1_CNTL0 4284829832 #define SEC_EE_AUDIO_TODDR_C_INT_ADDR 4284752272 #define SEC_AO_RTI_PWR_SYS_CPU_MEM_PD0 4286578932 #define SEC_AO_RTI_PWR_SYS_CPU_MEM_PD1 4286578936 #define SEC_EE_AUDIO_CLK_TDMIN_LB_CTRL 4284752012 #define P_EE_AUDIO_CLK_TDMOUT_A_CTRL 4284752016 #define HHI_HDMI_CLK_CNTL 4284727756 #define SEC_AED_CLIP_THD 4284834260 #define EE_AUDIO_FRDDR_B_INT_ADDR 4284752400 #define P_EE_AUDIO_CLK_TDMIN_A_CTRL 4284752000 #define HHI_VID_LOCK_CLK_CNTL 4284728264 #define P_EE_AUDIO_TDMIN_A_MUTE_VAL 4284752668 #define EE_AUDIO_POW_DET_TH_HI 4284753416 #define AMLUSB_A12 4284702768 #define AMLUSB_A11 4284702764 #define P_EE_AUDIO_TODDR_B_CTRL0 4284752192 #define AMLUSB_A10 4284702760 #define AMLUSB_A16 4284702784 #define EE_AUDIO_SPDIFIN_MUTE_VAL 4284752936 #define P_AO_WRITE_ONCE0 4286579056 #define P_EE_AUDIO_TODDR_B_CTRL1 4284752196 #define AMLUSB_A15 4284702780 #define AMLUSB_A14 4284702776 #define P_AO_WRITE_ONCE2 4286579064 #define AMLUSB_A13 4284702772 #define P_AO_WRITE_ONCE1 4286579060 #define SEC_MIPI_ADAPT_DDR_RD0_CNTL1 4284829700 #define SEC_MIPI_ADAPT_DDR_RD0_CNTL0 4284829696 #define AMLUSB_A19 4284702796 #define AMLUSB_A18 4284702792 #define AMLUSB_A17 4284702788 #define SEC_MIPI_ADAPT_DDR_RD0_CNTL4 4284829712 #define SEC_MIPI_ADAPT_DDR_RD0_CNTL3 4284829708 #define SEC_MIPI_ADAPT_DDR_RD0_CNTL2 4284829704 #define SEC_EE_AUDIO_LB_DAT_CH_ID0 4284752584 #define SEC_EE_AUDIO_LB_DAT_CH_ID1 4284752588 #define AMLUSB_A23 4284702812 #define AMLUSB_A22 4284702808 #define AMLUSB_A21 4284702804 #define AMLUSB_A20 4284702800 #define AMLUSB_A27 4284702828 #define AMLUSB_A26 4284702824 #define AMLUSB_A25 4284702820 #define AMLUSB_A24 4284702816 #define AMLUSB_A29 4284702836 #define SEC_AO_OSCIN_CNTL 4286578776 #define AMLUSB_A28 4284702832 #define SEC_AO_RTI_PWR_CNTL_REG0 4286578704 #define AMLUSB_A30 4284702840 #define AMLUSB_A31 4284702844 #define SEC_AO_CECB_INTR_CLR 4286579348 #define AO_MF_IR_DEC_BIT_0 4286611532 #define P_AO_PINMUX_LOCK 4286578780 #define EE_AUDIO_CLK_SPDIFIN_CTRL 4284752028 #define P_EE_AUDIO_SPDIFOUT_SWAP 4284753048 #define P_EFUSE_CLK_A73_CFG2 4284696348 #define P_HHI_PCIE_PLL_STS 4284727472 #define P_PREG_VPU_SECURE0 4284695888 #define P_PREG_VPU_SECURE1 4284695892 #define P_AO_I2C_M_0_CONTROL_REG 4286599168 #define SEC_EE_AUDIO_SPDIFOUT_B_CTRL0 4284753548 #define HHI_WAVE420L_CLK_CNTL 4284727912 #define P_AO_I2C_S_SEND_REG 4286603268 #define SEC_EE_AUDIO_SPDIFOUT_B_CTRL1 4284753552 #define SEC_M4_CPU_TIMESTAMP2 4286579484 #define P_HHI_CHECK_CLK_RESULT 4284727312 #define P_RO_AUD_LOCK_INT_STATUS 4284784748 #define P_AO_IR_DEC_DEMOD_CNT0 4286611676 #define P_EE_AUDIO_CLK_GATE_EN 4284751872 #define P_AO_IR_DEC_DEMOD_CNT1 4286611680 #define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB 4284752480 #define SEC_AO_SEC_JTAG_PWD_SP_ADDR3 4286579412 #define SEC_AO_SEC_JTAG_PWD_SP_ADDR1 4286579404 #define SEC_AO_SEC_JTAG_PWD_SP_ADDR2 4286579408 #define P_HPG_TIMER 4284727356 #define SEC_AO_SEC_JTAG_PWD_SP_ADDR0 4286579400 #define SEC_AO_CLK_GATE0 4286578764 #define P_HHI_MIPI_ISP_CLK_CNTL 4284727744 #define P_EE_AUDIO_TDMIN_B_SWAP 4284752708 #define EE_AUDIO_FRDDR_C_START_ADDR 4284752456 #define P_AO_WATCHDOG_RESET 4286578988 #define SEC_EE_AUDIO_CLK_TDMOUT_C_CTRL 4284752024 #define P_PDM_F2_CTRL 4284743696 #define SEC_AO_MF_IR_DEC_IRQ_CTL 4286611592 #define AO_TIMERA_CUR_REG 4286579664 #define SEC_AUD_LOCK_OMCLK_LAT_INT 4284784668 #define SEC_AO_RTC_ALT_CLK_CNTL0 4286578836 #define AO_UART2_RFIFO 4286595076 #define SEC_AO_RTC_ALT_CLK_CNTL1 4286578840 #define P_PERIPHS_LOCK_PIN_MUX 4284696252 #define AUD_LOCK_IMCLK_DS_INT 4284784676 #define PREG_PAD_GPIO3_EN_N 4284695652 #define P_EE_AUDIO_TDMOUT_B_GAIN0 4284753248 #define SEC_EE_AUDIO_LB_STS 4284752600 #define P_EE_AUDIO_TDMOUT_B_GAIN1 4284753252 #define SEC_MIPI_DSI_TEST_CTRL1 4284760128 #define P_PREG_PAD_GPIO1_O 4284695632 #define SEC_MIPI_DSI_TEST_CTRL0 4284760124 #define P_PREG_PAD_GPIO1_I 4284695636 #define P_AO_IR_DEC_DEMOD_SUM_CNT0 4286611668 #define P_AO_IR_DEC_DEMOD_SUM_CNT1 4286611672 #define AO_MF_IR_DEC_REG0 4286611536 #define AO_MF_IR_DEC_REG1 4286611548 #define EE_AUDIO_SECURITY_CTRL 4284753484 #define SEC_HHI_SYS_PLL_CNTL6 4284728076 #define SEC_HHI_SYS_PLL_CNTL4 4284728068 #define SEC_HHI_SYS_PLL_CNTL5 4284728072 #define SEC_HHI_SYS_PLL_CNTL2 4284728060 #define SEC_HHI_SYS_PLL_CNTL3 4284728064 #define EE_AUDIO_SPDIFOUT_B_SWAP 4284753560 #define SEC_HHI_SYS_PLL_CNTL0 4284728052 #define SEC_HHI_SYS_PLL_CNTL1 4284728056 #define AO_MF_IR_DEC_REG2 4286611552 #define AO_MF_IR_DEC_REG3 4286611576 #define AED_EQ_CH1_COEF62 4284833920 #define AED_EQ_CH1_COEF63 4284833924 #define AED_EQ_CH1_COEF64 4284833928 #define SEC_AO_I2C_M_0_RDATA_REG1 4286599196 #define SEC_AO_I2C_M_0_RDATA_REG0 4286599192 #define AED_EQ_CH1_COEF60 4284833912 #define AED_EQ_CH1_COEF61 4284833916 #define AO_CEC_RW_REG 4286578948 #define AED_EQ_CH1_COEF73 4284833944 #define AED_EQ_CH1_COEF74 4284833948 #define AED_EQ_CH1_COEF70 4284833932 #define AED_EQ_CH1_COEF71 4284833936 #define AED_EQ_CH1_COEF72 4284833940 #define AED_EQ_CH1_COEF44 4284833888 #define P_MIPI_ADAPT_PIXEL1_CNTL1 4284829836 #define P_MIPI_ADAPT_PIXEL1_CNTL0 4284829832 #define SEC_HHI_PCIE_PLL_CNTL4 4284727464 #define SEC_HHI_PCIE_PLL_CNTL5 4284727468 #define SEC_HHI_PCIE_PLL_CNTL2 4284727456 #define SEC_HHI_PCIE_PLL_CNTL3 4284727460 #define AED_EQ_CH1_COEF40 4284833872 #define SEC_HHI_PCIE_PLL_CNTL0 4284727448 #define AED_EQ_CH1_COEF41 4284833876 #define SEC_HHI_PCIE_PLL_CNTL1 4284727452 #define AED_EQ_CH1_COEF42 4284833880 #define AED_EQ_CH1_COEF43 4284833884 #define SEC_SECE_TIMER_HIG 4284696108 #define P_HHI_SPICC_CLK_CNTL 4284728284 #define SEC_KL_RESP0_2 4284678296 #define SEC_KL_RESP0_1 4284678292 #define SEC_KL_RESP0_0 4284678288 #define SEC_EE_AUDIO_MCLK_F_CTRL 4284751896 #define AED_EQ_CH1_COEF51 4284833896 #define RESET0_SEC_MASK 4284801152 #define AED_EQ_CH1_COEF52 4284833900 #define AED_EQ_CH1_COEF53 4284833904 #define P_HHI_VDEC4_CLK_CNTL 4284727788 #define AED_EQ_CH1_COEF54 4284833908 #define AED_EQ_CH1_COEF50 4284833892 #define SEC_KL_RESP0_3 4284678300 #define P_AO_SEC_TMODE_PWD0 4286579040 #define P_AO_SEC_TMODE_PWD2 4286579048 #define P_AO_SEC_TMODE_PWD1 4286579044 #define P_AO_SEC_TMODE_PWD3 4286579052 #define P_EE_AUDIO_TODDR_A_INIT_ADDR 4284752164 #define P_HHI_VID_CLK_DIV 4284727652 #define SEC_EE_AUDIO_TDMIN_B_MUTE3 4284752748 #define SEC_EE_AUDIO_TDMIN_B_MUTE1 4284752740 #define SEC_EE_AUDIO_TDMIN_B_MUTE2 4284752744 #define SEC_EE_AUDIO_TDMIN_B_MUTE0 4284752736 #define P_PDM_CHAN_CTRL1 4284743712 #define P_BUS_CFG0 4284695552 #define P_BUS_CFG1 4284695556 #define P_AO_MF_IR_DEC_BIT_0 4286611532 #define EE_AUDIO_FRDDR_A_START_ADDRB 4284752348 #define SEC_ETH_PLL_STS 4284792896 #define SEC_AO_RTI_STATUS_REG1 4286578692 #define SEC_AO_RTI_STATUS_REG0 4286578688 #define SEC_AO_RTI_STATUS_REG3 4286578700 #define SEC_AO_RTI_STATUS_REG2 4286578696 #define SEC_MIPI_ISP_WRARB_WEIGH1_SLV 4284842020 #define AED_EQ_CH1_COEF84 4284833968 #define AED_EQ_CH1_COEF80 4284833952 #define AED_EQ_CH1_COEF81 4284833956 #define AED_EQ_CH1_COEF82 4284833960 #define AED_EQ_CH1_COEF83 4284833964 #define P_AO_SEC_JTAG_PWD_SCP_ADDR0 4286579440 #define SEC_EE_AUDIO_TDMIN_C_MASK3 4284752788 #define P_AO_SEC_JTAG_PWD_SCP_ADDR3 4286579452 #define P_AO_SEC_JTAG_PWD_SCP_ADDR2 4286579448 #define P_AO_SEC_JTAG_PWD_SCP_ADDR1 4286579444 #define SEC_EE_AUDIO_TDMIN_C_MASK2 4284752784 #define SEC_EE_AUDIO_TDMIN_C_MASK1 4284752780 #define SEC_PREG_PAD_GPIO3_EN_N 4284695652 #define SEC_EE_AUDIO_TDMIN_C_MASK0 4284752776 #define AED_EQ_CH1_COEF90 4284833972 #define AED_EQ_CH1_COEF91 4284833976 #define AED_EQ_CH1_COEF92 4284833980 #define AED_EQ_CH1_COEF93 4284833984 #define AED_EQ_CH1_COEF94 4284833988 #define P_AED_EQ_EN 4284834192 #define AO_SEC_SP_CFG15 4286579644 #define AO_IR_DEC_DEMOD_IIR_THD 4286611656 #define AO_SEC_SP_CFG14 4286579640 #define P_AO_SAR_ADC_CHNL67 4286615620 #define SEC_EE_AUDIO_TDMOUT_B_GAIN0 4284753248 #define SEC_EE_AUDIO_TDMOUT_B_GAIN1 4284753252 #define EE_AUDIO_FRDDR_C_STATUS2 4284752472 #define EE_AUDIO_FRDDR_C_STATUS1 4284752468 #define SEC_SYS_CPUB_CFG0 4284696456 #define SEC_SYS_CPUB_CFG2 4284696464 #define SEC_SYS_CPUB_CFG1 4284696460 #define PDM_CTRL 4284743680 #define SEC_HHI_MIPI_CNTL2 4284727304 #define SEC_HHI_MIPI_CNTL1 4284727300 #define SEC_HHI_MIPI_CNTL0 4284727296 #define SEC_AO_CECB_CLK_CNTL_REG1 4286579332 #define SEC_AO_CECB_CLK_CNTL_REG0 4286579328 #define SEC_SYS_CPUB_CFG8 4284696488 #define SEC_SYS_CPUB_CFG7 4284696484 #define SEC_SYS_CPUB_CFG9 4284696492 #define SEC_SYS_CPUB_CFG4 4284696472 #define SEC_SYS_CPUB_CFG3 4284696468 #define SEC_SYS_CPUB_CFG6 4284696480 #define SEC_SYS_CPUB_CFG5 4284696476 #define P_HHI_HIFI_PLL_CNTL3 4284727524 #define P_HHI_HIFI_PLL_CNTL2 4284727520 #define P_HHI_HIFI_PLL_CNTL1 4284727516 #define P_HHI_HIFI_PLL_CNTL0 4284727512 #define SEC_AO_SEC_SCRATCH 4286579068 #define P_AO_SAR_ADC_CHNL45 4286615616 #define EE_AUDIO_LB_LB_CH_ID0 4284752592 #define P_HHI_HIFI_PLL_CNTL6 4284727536 #define P_HHI_HIFI_PLL_CNTL5 4284727532 #define P_HHI_HIFI_PLL_CNTL4 4284727528 #define P_BUS_CFG2 4284695560 #define P_BUS_CFG3 4284695564 #define EE_AUDIO_TDMIN_C_MUTE_VAL 4284752796 #define P_BUS_CFG4 4284695568 #define P_BUS_CFG5 4284695572 #define P_BUS_CFG6 4284695576 #define EE_AUDIO_LB_LB_CH_ID1 4284752596 #define P_BUS_CFG7 4284695580 #define P_BUS_CFG8 4284695584 #define MIPI_DSI_TURN_WCHDOG 4284760116 #define P_BUS_CFG9 4284695588 #define AMLUSB_B11 4284719148 #define P_EE_AUDIO_TDMIN_LB_CTRL 4284752832 #define AMLUSB_B10 4284719144 #define AO_SAR_ADC_LAST_RD 4286615572 #define AMLUSB_B15 4284719164 #define AMLUSB_B14 4284719160 #define AMLUSB_B13 4284719156 #define AMLUSB_B12 4284719152 #define P_EE_AUDIO_TODDR_A_STATUS2 4284752152 #define AMLUSB_B19 4284719180 #define P_EE_AUDIO_TODDR_A_STATUS1 4284752148 #define AMLUSB_B18 4284719176 #define AMLUSB_B17 4284719172 #define AMLUSB_B16 4284719168 #define AO_SEC_SP_CFG13 4286579636 #define AO_SEC_SP_CFG12 4286579632 #define AO_SEC_SP_CFG11 4286579628 #define AO_SEC_SP_CFG10 4286579624 #define BUS_MON0_DATA_MSK 4284696080 #define P_AO_SEC_SP_CFG14 4286579640 #define P_AO_SEC_SP_CFG13 4286579636 #define P_AO_SEC_SP_CFG15 4286579644 #define AED_EQ_CH1_COEF22 4284833840 #define AED_EQ_CH1_COEF23 4284833844 #define AED_EQ_CH1_COEF24 4284833848 #define P_KL_RESP0_1 4284678292 #define P_KL_RESP0_0 4284678288 #define P_KL_RESP0_3 4284678300 #define P_KL_RESP0_2 4284678296 #define EE_AUDIO_LB_CTRL1 4284752580 #define EE_AUDIO_LB_CTRL0 4284752576 #define DMA_CFG 4284735552 #define AED_EQ_CH1_COEF20 4284833832 #define AED_EQ_CH1_COEF21 4284833836 #define P_AO_SEC_SP_CFG10 4286579624 #define P_AO_SEC_SP_CFG12 4286579632 #define P_AO_SEC_SP_CFG11 4286579628 #define AED_EQ_CH1_COEF33 4284833864 #define P_EE_AUDIO_TORAM_CTRL1 4284753668 #define AED_EQ_CH1_COEF34 4284833868 #define P_EE_AUDIO_TORAM_CTRL0 4284753664 #define EE_AUDIO_TORAM_START_ADDR 4284753672 #define AED_EQ_CH1_COEF30 4284833852 #define AED_EQ_CH1_COEF31 4284833856 #define AED_EQ_CH1_COEF32 4284833860 #define P_HHI_BT656_CLK_CNTL 4284728276 #define AED_CLIP_THD 4284834260 #define AED_EQ_CH1_COEF04 4284833808 #define AED_EQ_CH1_COEF00 4284833792 #define AED_EQ_CH1_COEF01 4284833796 #define AED_EQ_CH1_COEF02 4284833800 #define AED_EQ_CH1_COEF03 4284833804 #define SEC_MIPI_ADAPT_IRQ_PENDING1 4284830092 #define AUD_LOCK_REFCLK_LAT_INT 4284784660 #define SEC_MIPI_ADAPT_IRQ_PENDING0 4284830084 #define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDR 4284752332 #define EE_AUDIO_MCLK_D_CTRL 4284751888 #define SEC_TS_DDR_STAT9 4284697700 #define SEC_TS_DDR_STAT8 4284697696 #define SEC_TS_DDR_STAT7 4284697692 #define SEC_TS_DDR_STAT6 4284697688 #define SEC_TS_DDR_STAT5 4284697684 #define SEC_TS_DDR_STAT4 4284697680 #define SEC_EE_AUDIO_PAD_CTRL0 4284751900 #define SEC_TS_DDR_STAT3 4284697676 #define SEC_TS_DDR_STAT2 4284697672 #define SEC_TS_DDR_STAT1 4284697668 #define SEC_EE_AUDIO_PAD_CTRL1 4284751904 #define SEC_TS_DDR_STAT0 4284697664 #define AED_EQ_CH1_COEF11 4284833816 #define AED_EQ_CH1_COEF12 4284833820 #define AED_EQ_CH1_COEF13 4284833824 #define AED_EQ_CH1_COEF14 4284833828 #define AO_SEC_JTAG_PWD_SP_ADDR0 4286579400 #define AO_SEC_JTAG_PWD_SP_ADDR3 4286579412 #define AO_SEC_JTAG_PWD_SP_ADDR1 4286579404 #define AO_SEC_JTAG_PWD_SP_ADDR2 4286579408 #define AED_EQ_CH1_COEF10 4284833812 #define HHI_GCLK_OTHER 4284727632 #define P_ETH_PHY_CNTL2 4284792968 #define EE_AUDIO_TDMOUT_B_MASK2 4284753236 #define EE_AUDIO_TDMOUT_B_MASK1 4284753232 #define EE_AUDIO_TDMOUT_B_MASK0 4284753228 #define SEC_HHI_GCLK_LOCK 4284727612 #define P_ETH_PHY_CNTL0 4284792960 #define P_ETH_PHY_CNTL1 4284792964 #define SEC_EE_AUDIO_SPDIFOUT_MUTE_VAL 4284753100 #define EE_AUDIO_TDMOUT_B_MASK3 4284753240 #define SEC_PERIPHS_LOCK_PIN_MUX 4284696252 #define AO_CLK_GATE0 4286578764 #define P_EE_AUDIO_TODDR_A_FINISH_ADDRB 4284752160 #define EE_AUDIO_TORAM_STATUS2 4284753688 #define SEC_AED_DRC_AA_1M 4284834228 #define SEC_EE_AUDIO_TDMOUT_A_SWAP 4284753160 #define P_HHI_VID_PLL_CLK_DIV 4284727712 #define AO_CECB_GEN_CNTL 4286579336 #define P_EE_AUDIO_SPDIFOUT_CTRL1 4284753040 #define P_EE_AUDIO_SPDIFOUT_CTRL0 4284753036 #define P_PERIPHS_PIN_MUX_A 4284696296 #define P_PERIPHS_PIN_MUX_B 4284696300 #define P_PERIPHS_PIN_MUX_C 4284696304 #define SEC_EE_AUDIO_TODDR_C_INIT_ADDR 4284752292 #define SEC_HIU_MAILBOX_SET_7 4284728408 #define AMLUSB_B22 4284719192 #define AMLUSB_B21 4284719188 #define SEC_HIU_MAILBOX_SET_5 4284728384 #define AMLUSB_B20 4284719184 #define SEC_HIU_MAILBOX_SET_6 4284728396 #define P_PERIPHS_PIN_MUX_D 4284696308 #define AMLUSB_B26 4284719208 #define P_PERIPHS_PIN_MUX_E 4284696312 #define AMLUSB_B25 4284719204 #define P_PERIPHS_PIN_MUX_F 4284696316 #define AMLUSB_B24 4284719200 #define AMLUSB_B23 4284719196 #define EE_AUDIO_FRDDR_A_STATUS1 4284752340 #define SEC_HIU_MAILBOX_SET_0 4284728324 #define AMLUSB_B29 4284719220 #define EE_AUDIO_FRDDR_A_STATUS2 4284752344 #define AMLUSB_B28 4284719216 #define AMLUSB_B27 4284719212 #define SEC_HIU_MAILBOX_SET_3 4284728360 #define SEC_HIU_MAILBOX_SET_4 4284728372 #define SEC_HIU_MAILBOX_SET_1 4284728336 #define SEC_HIU_MAILBOX_SET_2 4284728348 #define P_AO_SEC_GP_CFG12 4286579312 #define P_AO_SEC_GP_CFG11 4286579308 #define P_AO_SEC_GP_CFG10 4286579304 #define P_AO_SEC_GP_CFG15 4286579324 #define P_EE_AUDIO_POW_DET_CTRL0 4284753408 #define P_AO_SEC_GP_CFG14 4286579320 #define P_EE_AUDIO_POW_DET_CTRL1 4284753412 #define SEC_EE_AUDIO_TODDR_B_INT_ADDR 4284752208 #define P_AO_SEC_GP_CFG13 4286579316 #define EE_AUDIO_FRDDR_C_INT_ADDR 4284752464 #define AMLUSB_B31 4284719228 #define AMLUSB_B30 4284719224 #define AED_DRC_OFFSET0 4284834236 #define AED_DRC_OFFSET1 4284834240 #define P_PERIPHS_PIN_MUX_0 4284696256 #define P_PERIPHS_PIN_MUX_1 4284696260 #define P_PERIPHS_PIN_MUX_2 4284696264 #define P_PERIPHS_PIN_MUX_3 4284696268 #define P_PERIPHS_PIN_MUX_8 4284696288 #define P_PERIPHS_PIN_MUX_9 4284696292 #define P_PERIPHS_PIN_MUX_4 4284696272 #define P_PERIPHS_PIN_MUX_5 4284696276 #define P_PERIPHS_PIN_MUX_6 4284696280 #define P_PERIPHS_PIN_MUX_7 4284696284 #define AO_SEC_TMODE_PWD0 4286579040 #define AO_SEC_TMODE_PWD1 4286579044 #define AO_SEC_TMODE_PWD2 4286579048 #define AO_SEC_TMODE_PWD3 4286579052 #define P_MIPI_ADAPT_ALIG_ST0 4284829928 #define P_MIPI_ADAPT_ALIG_ST1 4284829932 #define SEC_ACODEC_4 4284686352 #define SEC_ACODEC_5 4284686356 #define SEC_ACODEC_6 4284686360 #define SEC_ACODEC_7 4284686364 #define SEC_ACODEC_0 4284686336 #define SEC_ACODEC_1 4284686340 #define SEC_ACODEC_2 4284686344 #define SEC_ACODEC_3 4284686348 #define SEC_AUD_LOCK_EN 4284784640 #define P_SYS_CPU_STATUS1 4284696196 #define P_SYS_CPU_STATUS0 4284696192 #define P_SYS_CPU_STATUS5 4284696212 #define P_SYS_CPU_STATUS4 4284696208 #define P_SYS_CPU_STATUS3 4284696204 #define P_SYS_CPU_STATUS2 4284696200 #define P_EE_AUDIO_FRDDR_B_START_ADDRB 4284752412 #define SEC_EFUSE_CLK_MALI_CFG0 4284696336 #define P_EE_AUDIO_SPDIFIN_CTRL6 4284752920 #define P_PDM_HCIC_CTRL2 4284743688 #define P_AO_SAR_ADC_DELTA_10 4286615592 #define P_PDM_HCIC_CTRL1 4284743684 #define P_EE_AUDIO_SPDIFIN_CTRL0 4284752896 #define P_EE_AUDIO_SPDIFIN_CTRL1 4284752900 #define P_EE_AUDIO_SPDIFIN_CTRL4 4284752912 #define P_EE_AUDIO_SPDIFIN_CTRL5 4284752916 #define P_EE_AUDIO_SPDIFIN_CTRL2 4284752904 #define P_EE_AUDIO_SPDIFIN_CTRL3 4284752908 #define DMA_STS5 4284735540 #define DMA_STS4 4284735536 #define DMA_STS3 4284735532 #define DMA_STS2 4284735528 #define DMA_STS1 4284735524 #define DMA_STS0 4284735520 #define P_ETH_PLL_STS 4284792896 #define SEC_EE_AUDIO_CLK_SPDIFOUT_B_CTRL 4284752052 #define P_HHI_VIPNANOQ_CNTL 4284727748 #define EE_AUDIO_SPDIFOUT_STAT 4284753024 #define SEC_HHI_SYS_CPUB_CLK_CNTL1 4284727808 #define ETH_PHY_DBG_CFG1 4284792844 #define SYS_CPU_STATUS3 4284696204 #define ETH_PHY_DBG_CFG0 4284792840 #define SYS_CPU_STATUS4 4284696208 #define SYS_CPU_STATUS5 4284696212 #define ETH_PHY_DBG_CFG4 4284792856 #define SYS_CPU_STATUS0 4284696192 #define ETH_PHY_DBG_CFG3 4284792852 #define SYS_CPU_STATUS1 4284696196 #define ETH_PHY_DBG_CFG2 4284792848 #define SYS_CPU_STATUS2 4284696200 #define MIPI_DSI_HS_TIM 4284760080 #define AO_TIMERF_HI_REG 4286579696 #define EFUSE_CLK_HEVCB_CFG0 4284696340 #define P_AED_NG_CTL 4284834276 #define P_PREG_PAD_GPIO0_O 4284695620 #define P_PREG_PAD_GPIO0_I 4284695624 #define SEC_AO_RTI_PULL_UP_REG 4286578732 #define SEC_AO_CEC_CLK_CNTL_REG0 4286578804 #define SEC_AO_CEC_CLK_CNTL_REG1 4286578808 #define P_AO_I2C_M_0_TIMEOUT_TH 4286599200 #define EE_AUDIO_TDMIN_B_MUTE_VAL 4284752732 #define AO_CEC_INTR_MASKN 4286578952 #define P_HHI_SYS1_PLL_STS 4284728220 #define AO_MF_IR_DEC_FILTE 4286611588 #define P_EE_AUDIO_MST_C_SCLK_CTRL0 4284751952 #define P_EE_AUDIO_MST_C_SCLK_CTRL1 4284751956 #define P_AUD_LOCK_REFCLK_DS_INT 4284784672 #define SEC_EE_AUDIO_SPDIFOUT_CTRL0 4284753036 #define SEC_EE_AUDIO_SPDIFOUT_CTRL1 4284753040 #define EE_AUDIO_TODDR_A_START_ADDRB 4284752156 #define SEC_AO_I2C_M_0_WDATA_REG0 4286599184 #define SEC_HHI_VPU_CLKC_CNTL 4284727732 #define MIPI_OTHER_CNTL0 4284829952 #define MIPI_OTHER_CNTL1 4284829956 #define MIPI_OTHER_CNTL2 4284829960 #define MIPI_OTHER_CNTL3 4284829964 #define MIPI_OTHER_CNTL4 4284829968 #define P_AO_MF_IR_DEC_LDR_REPEAT 4286611528 #define AO_SAR_ADC_CHAN_LIST 4286615556 #define SEC_AO_DEBUG_REG0 4286578848 #define SEC_AO_DEBUG_REG3 4286578860 #define SEC_AO_DEBUG_REG2 4286578856 #define SEC_AO_DEBUG_REG1 4286578852 #define P_MIPI_DSI_LP_TIM 4284760084 #define P_AED_DRC_OFFSET0 4284834236 #define SEC_HHI_SYS_CPU_CLK_CNTL1 4284727644 #define P_AED_DRC_OFFSET1 4284834240 #define P_EFUSE_CLK_NANOQ_CFG01 4284696352 #define P_AED_NG_CNT 4284834328 #define MIPI_OTHER_ST0 4284829992 #define MIPI_OTHER_ST1 4284829996 #define P_AO_MAILBOX_CLR_0 4286619660 #define P_AED_DEBUG6 4284834308 #define P_AED_DEBUG5 4284834304 #define P_AO_MAILBOX_CLR_2 4286619684 #define P_AO_MAILBOX_CLR_1 4286619672 #define P_AED_DEBUG2 4284834292 #define P_AO_MAILBOX_CLR_3 4286619696 #define P_AED_DEBUG1 4284834288 #define P_AED_DEBUG4 4284834300 #define P_AED_DEBUG3 4284834296 #define EE_AUDIO_SPDIFOUT_B_PREAMB 4284753556 #define P_EFUSE_CLK_MALI_CFG0 4284696336 #define AO_TIMEBASE_CNTL1 4286578772 #define P_AED_DEBUG0 4284834284 #define AO_IR_DEC_DEMOD_CNTL0 4286611648 #define AO_IR_DEC_DEMOD_CNTL1 4286611652 #define P_EE_AUDIO_TDMOUT_C_MASK0 4284753292 #define P_AUD_LOCK_OMCLK_DS_INT 4284784680 #define P_EE_AUDIO_TDMIN_B_MUTE_VAL 4284752732 #define P_BUS_MON1_DATA_MSK 4284696092 #define SEC_RESET1_SEC_LEVEL 4284801092 #define P_EE_AUDIO_TDMOUT_C_MASK1 4284753296 #define P_EE_AUDIO_TDMOUT_C_MASK2 4284753300 #define P_EE_AUDIO_TDMOUT_C_MASK3 4284753304 #define EE_AUDIO_TDMIN_B_STAT 4284752728 #define SEC_HHI_VID_CLK_DIV 4284727652 #define P_AED_MUTE 4284834204 #define SEC_AO_I2C_M_0_WDATA_REG1 4286599188 #define SEC_EE_AUDIO_FRDDR_A_INIT_ADDR 4284752356 #define HHI_HIFI_PLL_CNTL2 4284727520 #define RO_OMCLK_PKG_CNT 4284784744 #define HHI_HIFI_PLL_CNTL1 4284727516 #define HHI_HIFI_PLL_CNTL0 4284727512 #define MIPI_ISP_RDARB_WEIGH0_SLV 4284841992 #define HHI_BT656_CLK_CNTL 4284728276 #define SEC_AO_MAILBOX_STAT_2 4286619680 #define HHI_HIFI_PLL_CNTL6 4284727536 #define SEC_AO_MAILBOX_STAT_1 4286619668 #define HHI_HIFI_PLL_CNTL5 4284727532 #define HHI_HIFI_PLL_CNTL4 4284727528 #define SEC_AO_MAILBOX_STAT_3 4286619692 #define HHI_HIFI_PLL_CNTL3 4284727524 #define SEC_AO_MAILBOX_STAT_0 4286619656 #define SEC_EE_AUDIO_MCLK_A_CTRL 4284751876 #define AO_TIMERF_REG 4286579692 #define SEC_AO_CPU_TIMESTAMP2 4286578904 #define P_DDR_RD1_LBUF_STATUS 4284830020 #define SYS_CPUB_POR_CFG0 4284696448 #define HIU_MAILBOX_CLR_5 4284728392 #define HIU_MAILBOX_CLR_4 4284728380 #define HIU_MAILBOX_CLR_7 4284728416 #define HIU_MAILBOX_CLR_6 4284728404 #define HIU_MAILBOX_CLR_1 4284728344 #define HIU_MAILBOX_CLR_0 4284728332 #define HIU_MAILBOX_CLR_3 4284728368 #define SYS_CPUB_POR_CFG1 4284696452 #define HIU_MAILBOX_CLR_2 4284728356 #define RESET2_SEC_LEVEL 4284801096 #define AO_I2C_M_0_TOKEN_LIST0 4286599176 #define AO_I2C_M_0_TOKEN_LIST1 4286599180 #define SEC_ETH_PHY_DBG_CTL0 4284792832 #define SEC_ETH_PHY_DBG_CTL1 4284792836 #define SEC_AED_DEBUG0 4284834284 #define SEC_AED_DEBUG1 4284834288 #define DMA_SEC 4284735556 #define SEC_AO_MF_IR_DEC_LDR_REPEAT 4286611528 #define SEC_AED_DEBUG4 4284834300 #define SEC_AED_DEBUG5 4284834304 #define SEC_AED_DEBUG2 4284834292 #define SEC_AED_DEBUG3 4284834296 #define SEC_AED_DEBUG6 4284834308 #define SEC_HHI_GCLK_SP_MPEG 4284727636 #define SEC_AO_SEC_AO_CPU_SRAM_REG0_1 4286579188 #define SEC_AO_SEC_AO_CPU_SRAM_REG0_0 4286579184 #define AED_DRC_AD_1M_H 4284834324 #define P_HHI_HIFI_PLL_STS 4284727540 #define EE_AUDIO_TORAM_STATUS1 4284753684 #define P_HHI_SYS_CPU_CLK_CNTL 4284727708 #define EE_AUDIO_FRDDR_A_START_ADDR 4284752328 #define EE_AUDIO_CLK_TDMIN_LB_CTRL 4284752012 #define SEC_MIPI_ISP_WRARB_UGT 4284842024 #define P_PDM_CHAN_CTRL 4284743708 #define SEC_AO_MF_IR_DEC_LDR_IDLE 4286611524 #define P_PREG_PAD_GPIO3_O 4284695656 #define P_AO_GEN_CLK_CNTL 4286578792 #define PREG_PAD_GPIO4_EN_N 4284695664 #define SEC_MIPI_DSI_CLK_TIM 4284760076 #define SEC_PREG_ETH_REG0 4284695872 #define SEC_PREG_ETH_REG2 4284695896 #define SEC_PREG_ETH_REG1 4284695876 #define SEC_PREG_ETH_REG4 4284695904 #define SEC_PREG_ETH_REG3 4284695900 #define RESET2_SEC_MASK 4284801160 #define SEC_PREG_PAD_GPIO2_O 4284695644 #define SEC_PREG_PAD_GPIO2_I 4284695648 #define TS_PLL_STAT1 4284696644 #define TS_PLL_STAT2 4284696648 #define TS_PLL_STAT0 4284696640 #define TS_PLL_STAT5 4284696660 #define TS_PLL_STAT6 4284696664 #define TS_PLL_STAT3 4284696652 #define TS_PLL_STAT4 4284696656 #define TS_PLL_STAT9 4284696676 #define TS_PLL_STAT7 4284696668 #define TS_PLL_STAT8 4284696672 #define P_PREG_PAD_GPIO3_I 4284695660 #define P_PDM_F3_CTRL 4284743700 #define AO_TIMESTAMP_CNTL1 4286578864 #define AO_TIMESTAMP_CNTL2 4286578844 #define SEC_EE_AUDIO_FRDDR_A_FINISH_ADDRB 4284752352 #define PDM_MUTE_VALUE 4284743732 #define P_EE_AUDIO_TDMOUT_C_MASK_VAL 4284753340 #define SEC_EE_AUDIO_TDMOUT_C_MASK3 4284753304 #define SEC_EE_AUDIO_TDMOUT_C_MASK2 4284753300 #define SEC_EE_AUDIO_TDMOUT_C_MASK1 4284753296 #define SEC_EE_AUDIO_TDMOUT_C_MASK0 4284753292 #define AED_DRC_THD1 4284834248 #define EE_AUDIO_FRDDR_C_CTRL1 4284752452 #define EE_AUDIO_FRDDR_C_CTRL0 4284752448 #define AED_DRC_THD0 4284834244 #define PREG_PAD_GPIO4_I 4284695672 #define AO_SEC_SHARED_AHB_SRAM_REG2_0 4286579132 #define AO_SEC_SHARED_AHB_SRAM_REG2_1 4286579136 #define AO_SEC_SHARED_AHB_SRAM_REG2_2 4286579140 #define AO_WATCHDOG_CNTL1 4286578980 #define PREG_PAD_GPIO4_O 4284695668 #define SEC_HHI_SYS1_PLL_CNTL6 4284728216 #define SEC_HHI_SYS1_PLL_CNTL5 4284728212 #define SEC_HHI_SYS1_PLL_CNTL2 4284728200 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_2 4286579128 #define SEC_HHI_SYS1_PLL_CNTL1 4284728196 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_1 4286579124 #define SEC_HHI_SYS1_PLL_CNTL4 4284728208 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG1_0 4286579120 #define SEC_HHI_SYS1_PLL_CNTL3 4284728204 #define HHI_VDIN_MEAS_CLK_CNTL 4284727888 #define SEC_HHI_SYS1_PLL_CNTL0 4284728192 #define AED_EQ_CH2_COEF64 4284834128 #define AED_EQ_CH2_COEF63 4284834124 #define AO_WATCHDOG_CNTL 4286578976 #define AED_EQ_CH2_COEF60 4284834112 #define EE_AUDIO_SW_RESET 4284751908 #define AED_EQ_CH2_COEF62 4284834120 #define AED_EQ_CH2_COEF61 4284834116 #define P_RNG_SEC_CONFIG_REG1 4284678660 #define P_RNG_SEC_CONFIG_REG2 4284678664 #define AED_EQ_CH2_COEF53 4284834104 #define AED_EQ_CH2_COEF52 4284834100 #define AED_EQ_CH2_COEF54 4284834108 #define AED_EQ_CH2_COEF51 4284834096 #define AED_EQ_CH2_COEF50 4284834092 #define SEC_EE_AUDIO_TODDR_C_START_ADDRB 4284752284 #define P_AO_UART2_REG5 4286595092 #define AED_EQ_CH2_COEF80 4284834152 #define SEC_MIPI_ISP_ARB_DBG_STAT 4284842036 #define EE_AUDIO_FRDDR_B_START_ADDRB 4284752412 #define AED_EQ_CH2_COEF82 4284834160 #define AED_EQ_CH2_COEF81 4284834156 #define AED_EQ_CH2_COEF84 4284834168 #define AED_EQ_CH2_COEF83 4284834164 #define AED_DRC_AD_1M 4284834232 #define SEC_EFUSE_CLK_ENCP_CFG0 4284696332 #define P_EE_AUDIO_TDMIN_C_MUTE1 4284752804 #define AO_SEC_GP_CFG14 4286579320 #define SEC_EE_AUDIO_MCLK_C_CTRL 4284751884 #define P_EE_AUDIO_TDMIN_C_MUTE2 4284752808 #define AO_SEC_GP_CFG15 4286579324 #define P_EE_AUDIO_TDMIN_C_MUTE0 4284752800 #define AO_SEC_GP_CFG10 4286579304 #define AO_SEC_GP_CFG11 4286579308 #define P_EE_AUDIO_TDMIN_C_MUTE3 4284752812 #define AO_SEC_GP_CFG12 4286579312 #define AO_SEC_GP_CFG13 4286579316 #define AED_EQ_CH2_COEF74 4284834148 #define AED_EQ_CH2_COEF71 4284834136 #define SEC_PAD_DS_REG0A 4284696384 #define AED_EQ_CH2_COEF70 4284834132 #define AED_EQ_CH2_COEF73 4284834144 #define AED_EQ_CH2_COEF72 4284834140 #define MIPI_DSI_ANA_UP_TIM 4284760088 #define SEC_HHI_MIPI_CSI_PHY_CLK_CNTL 4284728128 #define SEC_PAD_DS_REG1A 4284696388 #define HHI_XTAL_DIVN_CNTL 4284727484 #define P_PREG_ETH_REG0 4284695872 #define P_PREG_ETH_REG1 4284695876 #define P_PREG_ETH_REG4 4284695904 #define P_PREG_ETH_REG2 4284695896 #define P_PREG_ETH_REG3 4284695900 #define P_AO_MF_IR_DEC_STATUS1 4286611568 #define P_AO_MF_IR_DEC_STATUS2 4286611572 #define AED_EQ_CH2_COEF91 4284834176 #define AED_EQ_CH2_COEF90 4284834172 #define P_HHI_SYS_CPUB_RESET_CNTL 4284727812 #define SEC_PAD_DS_REG2B 4284696396 #define SEC_HHI_AXI_PIPEL_CNTL1 4284728268 #define AED_EQ_CH2_COEF93 4284834184 #define SEC_HHI_AXI_PIPEL_CNTL2 4284728260 #define AED_EQ_CH2_COEF92 4284834180 #define SEC_PAD_DS_REG2A 4284696392 #define AED_EQ_CH2_COEF94 4284834188 #define AO_SEC_AO_CPU_SRAM_REG0_1 4286579188 #define AO_SEC_AO_CPU_SRAM_REG0_0 4286579184 #define SEC_PAD_DS_REG3A 4284696400 #define SEC_PAD_DS_REG4A 4284696404 #define AED_EQ_VOLUME 4284834196 #define SEC_EFUSE_CLK_A73_CFG01 4284696344 #define SEC_MIPI_DSI_WAKEUP_TIM 4284760096 #define P_AO_MF_IR_DEC_FIFO_CTL 4286611596 #define SEC_EE_AUDIO_TODDR_B_FINISH_ADDR 4284752204 #define P_AO_SEC_JTAG_PWD_SP_CNTL 4286579396 #define P_AO_PWM_PWM_C 4286586880 #define P_AO_PWM_PWM_B 4286607364 #define P_AO_PWM_PWM_A 4286607360 #define P_AO_PWM_PWM_D 4286586884 #define AO_CEC_STICKY_DATA2 4286579504 #define AO_CEC_STICKY_DATA1 4286579500 #define AO_CEC_STICKY_DATA4 4286579512 #define AO_CEC_STICKY_DATA3 4286579508 #define AO_CEC_STICKY_DATA0 4286579496 #define P_AED_EQ_VOLUME_SLEW_CNT 4284834200 #define AO_CEC_STICKY_DATA6 4286579520 #define AO_CEC_STICKY_DATA5 4286579516 #define AO_CEC_STICKY_DATA7 4286579524 #define P_PREG_NAND_CFG_KEY1 4284695884 #define P_PREG_NAND_CFG_KEY0 4284695880 #define P_HHI_VIPNANOQ_CLK_CNTL 4284727752 #define SEC_RESET0_SEC_REGISTER 4284801024 #define EE_AUDIO_TDMIN_LB_CTRL 4284752832 #define SEC_EE_AUDIO_TODDR_C_FINISH_ADDRB 4284752288 #define EE_AUDIO_FRDDR_A_FINISH_ADDRB 4284752352 #define SEC_EE_AUDIO_TDMIN_A_CTRL 4284752640 #define P_PREG_PAD_GPIO5_EN_N 4284695680 #define SEC_AUD_LOCK_SW_LATCH 4284784648 #define PERIPHS_PIN_MUX_A 4284696296 #define PERIPHS_PIN_MUX_B 4284696300 #define PERIPHS_PIN_MUX_C 4284696304 #define PERIPHS_PIN_MUX_D 4284696308 #define PERIPHS_PIN_MUX_E 4284696312 #define PERIPHS_PIN_MUX_F 4284696316 #define PERIPHS_PIN_MUX_1 4284696260 #define PERIPHS_PIN_MUX_2 4284696264 #define PERIPHS_PIN_MUX_3 4284696268 #define PERIPHS_PIN_MUX_4 4284696272 #define PERIPHS_PIN_MUX_0 4284696256 #define PERIPHS_PIN_MUX_9 4284696292 #define PERIPHS_PIN_MUX_5 4284696276 #define PERIPHS_PIN_MUX_6 4284696280 #define PERIPHS_PIN_MUX_7 4284696284 #define PERIPHS_PIN_MUX_8 4284696288 #define P_PDM_COEFF_ADDR 4284743716 #define PREG_ETH_REG2 4284695896 #define PREG_ETH_REG1 4284695876 #define PREG_ETH_REG0 4284695872 #define PREG_ETH_REG4 4284695904 #define PREG_ETH_REG3 4284695900 #define P_PDM_CTRL 4284743680 #define SEC_HHI_PCIE_PLL_STS 4284727472 #define SEC_HHI_SYS_CPUB_RESET_CNTL 4284727812 #define SEC_EE_AUDIO_TDMOUT_C_MASK_VAL 4284753340 #define PAD_PULL_UP_REG4 4284695800 #define PAD_PULL_UP_REG5 4284695804 #define PAD_PULL_UP_REG2 4284695792 #define P_M4_CPU_CNTL 4286579456 #define PAD_PULL_UP_REG3 4284695796 #define PAD_PULL_UP_REG0 4284695784 #define PAD_PULL_UP_REG1 4284695788 #define P_HHI_HDMI_CLK_CNTL 4284727756 #define SEC_EE_AUDIO_TDMIN_LB_MASK2 4284752848 #define SEC_EE_AUDIO_TDMIN_LB_MASK3 4284752852 #define P_EE_AUDIO_LB_CTRL1 4284752580 #define SEC_KL_START1 4284678276 #define SEC_KL_START0 4284678272 #define P_EE_AUDIO_LB_CTRL0 4284752576 #define MIPI_ADAPT_DDR_RD1_CNTL3 4284829772 #define SEC_EE_AUDIO_TDMIN_LB_MASK0 4284752840 #define MIPI_ADAPT_DDR_RD1_CNTL4 4284829776 #define SEC_EE_AUDIO_TDMIN_LB_MASK1 4284752844 #define P_AO_FR_EE_WR_ONCE 4286578888 #define SEC_MIPI_ISP_WRARB_WEIGH0_SLV 4284842016 #define P_MIPI_ISP_RDARB_UGT 4284842000 #define P_MIPI_DSI_CHAN_STS 4284760072 #define MIPI_ADAPT_DDR_RD1_CNTL1 4284829764 #define SEC_AUD_LOCK_INT_CTRL 4284784692 #define MIPI_ADAPT_DDR_RD1_CNTL2 4284829768 #define SEC_SYS_CPUB_CFG10 4284696496 #define MIPI_ADAPT_DDR_RD1_CNTL0 4284829760 #define ETH_PLL_CTL0 4284792900 #define ETH_PLL_CTL1 4284792904 #define AUD_LOCK_GCLK_CTRL 4284784688 #define ETH_PLL_CTL4 4284792916 #define ETH_PLL_CTL5 4284792920 #define ETH_PLL_CTL2 4284792908 #define P_HHI_VAPBCLK_CNTL 4284727796 #define P_HHI_CCI_CLK_CNTL 4284727724 #define ETH_PLL_CTL3 4284792912 #define ETH_PLL_CTL6 4284792924 #define ETH_PLL_CTL7 4284792928 #define SEC_AO_PAD_DS_A 4286578716 #define SEC_AO_PAD_DS_B 4286578720 #define P_PREG_STICKY_REG8 4284696032 #define P_PREG_STICKY_REG9 4284696036 #define P_PREG_STICKY_REG6 4284696024 #define P_PREG_STICKY_REG7 4284696028 #define SEC_AO_SAR_ADC_DELTA_10 4286615592 #define P_EE_AUDIO_FRDDR_B_INIT_ADDR 4284752420 #define EE_AUDIO_TDMIN_B_SWAP 4284752708 #define SEC_HHI_ISP_MEM_PD_REG0 4284727572 #define SEC_HHI_ISP_MEM_PD_REG1 4284727576 #define P_AUD_LOCK_SW_LATCH 4284784648 #define P_EE_AUDIO_SPDIFOUT_B_SWAP 4284753560 #define P_AUD_LOCK_INT_CTRL 4284784692 #define P_ETH_PHY_STS2 4284792988 #define P_PREG_STICKY_REG0 4284696000 #define EE_AUDIO_CLK_TDMIN_B_CTRL 4284752004 #define P_ETH_PHY_STS1 4284792984 #define P_PREG_STICKY_REG1 4284696004 #define P_ETH_PHY_STS0 4284792980 #define SEC_MIPI_ISP_RDARB_MODE 4284841984 #define P_PREG_STICKY_REG4 4284696016 #define P_PREG_STICKY_REG5 4284696020 #define P_PREG_STICKY_REG2 4284696008 #define P_PREG_STICKY_REG3 4284696012 #define P_AO_RTI_PULL_UP_REG 4286578732 #define SEC_EFUSE_CLK_A53_CFG2 4284696328 #define P_HHI_SYS1_PLL_CNTL4 4284728208 #define P_EE_AUDIO_FRDDR_A_INIT_ADDR 4284752356 #define P_HHI_SYS1_PLL_CNTL5 4284728212 #define P_HHI_SYS1_PLL_CNTL6 4284728216 #define P_HHI_SYS1_PLL_CNTL0 4284728192 #define P_HHI_SYS1_PLL_CNTL1 4284728196 #define P_HHI_SYS1_PLL_CNTL2 4284728200 #define P_HHI_SYS1_PLL_CNTL3 4284728204 #define P_RNG_USR_STS 4284678684 #define EE_AUDIO_TDMIN_LB_MUTE2 4284752872 #define EE_AUDIO_TDMIN_LB_MUTE1 4284752868 #define EE_AUDIO_TDMIN_LB_MUTE3 4284752876 #define EE_AUDIO_TDMIN_LB_MUTE0 4284752864 #define P_MIPI_ADAPT_DDR_RD0_CNTL0 4284829696 #define P_MIPI_ADAPT_DDR_RD0_CNTL3 4284829708 #define P_AO_UART_CONTROL 4286590984 #define P_MIPI_ADAPT_DDR_RD0_CNTL4 4284829712 #define P_MIPI_ADAPT_DDR_RD0_CNTL1 4284829700 #define P_MIPI_ADAPT_DDR_RD0_CNTL2 4284829704 #define P_RNG_SEC_DATA 4284678672 #define SEC_EE_AUDIO_TDMIN_B_MUTE_VAL 4284752732 #define SEC_EE_AUDIO_TDMOUT_A_GAIN0 4284753184 #define SEC_EE_AUDIO_TDMOUT_A_GAIN1 4284753188 #define EFUSE_CLK_MALI_CFG0 4284696336 #define P_MIPI_DSI_CLK_TIM 4284760076 #define SEC_HIU_MAILBOX_STAT_1 4284728340 #define SEC_HIU_MAILBOX_STAT_2 4284728352 #define SEC_HIU_MAILBOX_STAT_0 4284728328 #define SEC_HHI_VIID_CLK_DIV 4284727592 #define AO_SEC_SHARED_AHB_SRAM_REG1_1 4286579124 #define AO_SEC_SHARED_AHB_SRAM_REG1_2 4286579128 #define PREG_PAD_GPIO3_I 4284695660 #define P_MIPI_ADAPT_PIXEL1_ST0 4284829872 #define P_PREG_PAD_GPIO2_O 4284695644 #define P_PREG_PAD_GPIO2_I 4284695648 #define P_MIPI_ADAPT_PIXEL1_ST1 4284829876 #define SEC_HIU_MAILBOX_STAT_7 4284728412 #define SEC_HIU_MAILBOX_STAT_5 4284728388 #define SEC_HIU_MAILBOX_STAT_6 4284728400 #define PREG_PAD_GPIO3_O 4284695656 #define SEC_AO_SEC_JTAG_PWD_SP_CNTL 4286579396 #define SEC_HIU_MAILBOX_STAT_3 4284728364 #define SEC_HIU_MAILBOX_STAT_4 4284728376 #define P_AO_SEC_SD_CFG15 4286579260 #define P_AO_SEC_SD_CFG13 4286579252 #define P_AO_SEC_SD_CFG14 4286579256 #define P_AO_SEC_SD_CFG11 4286579244 #define P_AUD_LOCK_INT_CLR 4284784684 #define P_AO_SEC_SD_CFG12 4286579248 #define P_AO_SEC_SD_CFG10 4286579240 #define SEC_HHI_MIPI_ISP_CLK_CNTL 4284727744 #define P_EE_AUDIO_FRDDR_C_INIT_ADDR 4284752484 #define P_MIPI_DSI_TEST_CTRL1 4284760128 #define P_MIPI_DSI_TEST_CTRL0 4284760124 #define P_EE_AUDIO_SPDIFIN_MUTE_VAL 4284752936 #define SEC_PREG_PAD_GPIO1_I 4284695636 #define SEC_PREG_PAD_GPIO1_O 4284695632 #define SEC_PREG_STICKY_REG0 4284696000 #define AO_TIMERG_REG 4286579700 #define HHI_VDEC_CLK_CNTL 4284727776 #define SEC_PREG_STICKY_REG2 4284696008 #define SEC_PREG_STICKY_REG1 4284696004 #define SEC_PREG_STICKY_REG4 4284696016 #define SEC_PREG_STICKY_REG3 4284696012 #define SEC_PREG_STICKY_REG6 4284696024 #define SEC_PREG_STICKY_REG5 4284696020 #define P_EFUSE_CFG_LOCK 4284696320 #define P_AO_UART2_RFIFO 4286595076 #define SEC_PDM_COEFF_DATA 4284743720 #define P_HHI_HDMI_PHY_STATUS 4284728248 #define SEC_PREG_STICKY_REG8 4284696032 #define SEC_PREG_STICKY_REG7 4284696028 #define P_EE_AUDIO_TDMIN_LB_STAT 4284752856 #define P_AO_CECB_RW_REG 4286579340 #define SEC_PREG_STICKY_REG9 4284696036 #define P_SECE_TIMER_LOW 4284696104 #define P_AO_PWM_TIME_CD 4286586896 #define SEC_HHI_MALI_CLK_CNTL 4284727728 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_2 4286579116 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_1 4286579112 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG0_0 4286579108 #define SEC_AO_SAR_ADC_CHAN_10_SW 4286615584 #define AO_SEC_SHARED_AHB_SRAM_REG1_0 4286579120 #define SEC_TS_DDR_CFG_REG6 4284697624 #define SEC_TS_DDR_CFG_REG7 4284697628 #define EE_AUDIO_TORAM_CTRL0 4284753664 #define EE_AUDIO_TORAM_CTRL1 4284753668 #define P_HHI_WAVE420L_CLK_CNTL 4284727912 #define SEC_TS_DDR_CFG_REG1 4284697604 #define SEC_TS_DDR_CFG_REG4 4284697616 #define SEC_TS_DDR_CFG_REG5 4284697620 #define SEC_TS_DDR_CFG_REG2 4284697608 #define SEC_TS_DDR_CFG_REG3 4284697612 #define EE_AUDIO_SPDIFIN_STAT1 4284752928 #define EE_AUDIO_SPDIFIN_STAT0 4284752924 #define EE_AUDIO_SPDIFIN_STAT2 4284752932 #define AO_RTC_ALT_CLK_CNTL0 4286578836 #define P_EE_AUDIO_FRDDR_C_START_ADDRB 4284752476 #define AO_RTC_ALT_CLK_CNTL1 4286578840 #define P_HHI_TS_CLK_CNTL 4284727696 #define SEC_MIPI_DSI_PHY_CTRL 4284760064 #define AO_MF_IR_DEC_LDR_ACTIVE 4286611520 #define P_HHI_PCIE_PLL_CNTL5 4284727468 #define P_HHI_PCIE_PLL_CNTL3 4284727460 #define P_HHI_PCIE_PLL_CNTL4 4284727464 #define P_HHI_PCIE_PLL_CNTL1 4284727452 #define P_HHI_PCIE_PLL_CNTL2 4284727456 #define P_HHI_PCIE_PLL_CNTL0 4284727448 #define AO_MF_IR_DEC_WIDTH_NEW 4286611600 #define SEC_AUD_LOCK_GCLK_CTRL 4284784688 #define AO_RTI_PWR_SYS_CPU_CNTL0 4286578912 #define AO_RTI_PWR_SYS_CPU_CNTL1 4286578916 #define PREG_PAD_GPIO1_EN_N 4284695628 #define AO_UART2_CONTROL 4286595080 #define AO_IR_DEC_DEMOD_THD1 4286611664 #define AO_IR_DEC_DEMOD_THD0 4286611660 #define P_AED_DRC_AA_1M 4284834228 #define HHI_MPEG_CLK_CNTL 4284727668 #define AM_RING_OSC_REG0 4284696060 #define SEC_MALI_CFG0 4284695612 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS9 4284753600 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS5 4284753584 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS6 4284753588 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS7 4284753592 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS8 4284753596 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS1 4284753568 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS2 4284753572 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS3 4284753576 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS4 4284753580 #define AO_RTI_GEN_CNTL_REG0 4286578752 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTSA 4284753604 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTSB 4284753608 #define SEC_AO_IR_BLASTER_ADDR3 4286579032 #define SEC_AO_IR_BLASTER_ADDR2 4286579028 #define SEC_RO_IMCLK_PKG_CNT 4284784740 #define TS_DDR_STAT6 4284697688 #define SEC_HHI_VDEC3_CLK_CNTL 4284727784 #define TS_DDR_STAT5 4284697684 #define TS_DDR_STAT8 4284697696 #define SEC_EE_AUDIO_SPDIFOUT_B_CHSTS0 4284753564 #define TS_DDR_STAT7 4284697692 #define TS_DDR_STAT9 4284697700 #define SEC_AO_IR_BLASTER_ADDR1 4286579024 #define TS_DDR_STAT0 4284697664 #define SEC_AO_IR_BLASTER_ADDR0 4286579020 #define TS_DDR_STAT2 4284697672 #define TS_DDR_STAT1 4284697668 #define TS_DDR_STAT4 4284697680 #define TS_DDR_STAT3 4284697676 #define AO_TIMER_SEC_SP_CTRL 4286579656 #define AED_TOP_REQ_CTL 4284834340 #define P_HHI_GEN_CLK_CNTL 4284727848 #define P_AO_IR_DEC_DEMOD_IIR_THD 4286611656 #define SEC_ETH_PLL_CTL0 4284792900 #define SEC_ETH_PLL_CTL1 4284792904 #define SEC_ETH_PLL_CTL2 4284792908 #define P_EE_AUDIO_TDMIN_LB_MUTE_VAL 4284752860 #define SEC_ETH_PLL_CTL3 4284792912 #define P_MIPI_ADAPT_IRQ_PENDING1 4284830092 #define P_MIPI_ADAPT_IRQ_PENDING0 4284830084 #define SEC_HHI_VPU_CLKB_CNTL 4284727820 #define EE_AUDIO_TOACODEC_CTRL0 4284753728 #define P_AO_SAR_ADC_REG0 4286615552 #define RO_OMCLK2REF_CNT_H 4284784732 #define P_AO_SAR_ADC_REG3 4286615564 #define RO_REF2IMCLK_CNT_H 4284784708 #define RO_OMCLK2REF_CNT_L 4284784728 #define EE_AUDIO_FRDDR_B_FINISH_ADDR 4284752396 #define P_AO_MAILBOX_STAT_1 4286619668 #define P_AO_MAILBOX_STAT_0 4286619656 #define RO_REF2IMCLK_CNT_L 4284784704 #define EFUSE_CLK_A53_CFG2 4284696328 #define P_EE_AUDIO_TDMIN_B_MASK3 4284752724 #define P_AO_MAILBOX_STAT_3 4286619692 #define P_AO_MAILBOX_STAT_2 4286619680 #define SEC_ETH_PLL_CTL4 4284792916 #define SEC_ETH_PLL_CTL5 4284792920 #define SEC_ETH_PLL_CTL6 4284792924 #define SEC_ETH_PLL_CTL7 4284792928 #define P_EE_AUDIO_TDMIN_B_MASK1 4284752716 #define P_EE_AUDIO_TDMIN_B_MASK2 4284752720 #define P_EE_AUDIO_TDMIN_B_MASK0 4284752712 #define HHI_FIX_PLL_CNTL6 4284727992 #define AED_EQ_CH2_COEF02 4284834000 #define AED_EQ_CH2_COEF01 4284833996 #define AED_EQ_CH2_COEF04 4284834008 #define AED_EQ_CH2_COEF03 4284834004 #define PDM_HCIC_CTRL1 4284743684 #define PDM_HCIC_CTRL2 4284743688 #define EE_AUDIO_TDMIN_LB_STAT 4284752856 #define AED_EQ_CH2_COEF00 4284833992 #define SP_HOLD_CTRL 4286578884 #define AED_EQ_CH2_COEF24 4284834048 #define HHI_VAPBCLK_CNTL 4284727796 #define AED_EQ_CH2_COEF23 4284834044 #define P_AO_MF_IR_DEC_DURATN3 4286611560 #define P_EE_AUDIO_TDMIN_LB_MASK1 4284752844 #define P_EE_AUDIO_TDMIN_LB_MASK2 4284752848 #define P_AO_MF_IR_DEC_DURATN2 4286611556 #define P_EE_AUDIO_TDMIN_LB_MASK0 4284752840 #define P_EE_AUDIO_TDMIN_LB_MASK3 4284752852 #define HHI_VPU_MEM_PD_REG2 4284727604 #define HHI_VPU_MEM_PD_REG1 4284727560 #define SEC_HHI_VIPNANOQ_CNTL 4284727748 #define AED_EQ_CH2_COEF20 4284834032 #define AED_EQ_CH2_COEF22 4284834040 #define AED_EQ_CH2_COEF21 4284834036 #define AED_EQ_CH2_COEF13 4284834024 #define AED_EQ_CH2_COEF12 4284834020 #define AED_EQ_CH2_COEF14 4284834028 #define EE_AUDIO_TODDR_B_INT_ADDR 4284752208 #define EE_AUDIO_TDMOUT_C_STAT 4284753308 #define P_HIU_MAILBOX_CLR_7 4284728416 #define P_HIU_MAILBOX_CLR_5 4284728392 #define P_HIU_MAILBOX_CLR_6 4284728404 #define P_HIU_MAILBOX_CLR_3 4284728368 #define AED_EQ_CH2_COEF11 4284834016 #define P_HIU_MAILBOX_CLR_4 4284728380 #define SEC_AED_DRC_AA_H 4284834312 #define AED_EQ_CH2_COEF10 4284834012 #define P_HIU_MAILBOX_CLR_1 4284728344 #define P_HIU_MAILBOX_CLR_2 4284728356 #define P_HIU_MAILBOX_CLR_0 4284728332 #define P_AO_WATCHDOG_CNTL 4286578976 #define P_AO_CPU_TIMESTAMP2 4286578904 #define ACODEC_4 4284686352 #define ACODEC_5 4284686356 #define ACODEC_2 4284686344 #define ACODEC_3 4284686348 #define ACODEC_0 4284686336 #define ACODEC_1 4284686340 #define ACODEC_6 4284686360 #define P_AED_EQ_VOLUME 4284834196 #define ACODEC_7 4284686364 #define HHI_FIX_PLL_CNTL3 4284727980 #define AED_EQ_CH2_COEF42 4284834080 #define HHI_FIX_PLL_CNTL2 4284727976 #define AED_EQ_CH2_COEF41 4284834076 #define HHI_FIX_PLL_CNTL5 4284727988 #define AED_EQ_CH2_COEF44 4284834088 #define HHI_FIX_PLL_CNTL4 4284727984 #define AED_EQ_CH2_COEF43 4284834084 #define HHI_FIX_PLL_CNTL1 4284727972 #define P_AO_RTI_PWR_SYS_CPU_MEM_PD0 4286578932 #define AED_EQ_CH2_COEF40 4284834072 #define HHI_FIX_PLL_CNTL0 4284727968 #define P_AO_RTI_PWR_SYS_CPU_MEM_PD1 4286578936 #define AED_EQ_CH2_COEF34 4284834068 #define MIPI_ADAPT_IRQ_PENDING0 4284830084 #define HHI_VPU_MEM_PD_REG0 4284727556 #define AO_TIMERE_HI_REG 4286579688 #define MIPI_ADAPT_IRQ_PENDING1 4284830092 #define SEC_RESET1_SEC_REGISTER 4284801028 #define AED_EQ_CH2_COEF31 4284834056 #define AED_EQ_CH2_COEF30 4284834052 #define AED_EQ_CH2_COEF33 4284834064 #define AED_EQ_CH2_COEF32 4284834060 #define SEC_SP_HOLD_CTRL 4286578884 #define P_AO_PWM_TIME_AB 4286607376 #define EE_AUDIO_TDMOUT_B_SWAP 4284753224 #define SEC_BUS_MONITOR_CNTL 4284696068 #define AO_TIMESTAMP_CNTL 4286578868 #define SEC_EE_AUDIO_TORAM_INIT_ADDR 4284753692 #define AO_TIMESTAMP_RD0 4286578872 #define P_MIPI_ISP_RDARB_WEIGH1_SLV 4284841996 #define AO_TIMESTAMP_RD1 4286578876 #define P_EE_AUDIO_RESAMPLE_STATUS1 4284752996 #define EE_AUDIO_TDMIN_C_CTRL 4284752768 #define AO_METAL_REVISION_1 4286578760 #define P_EE_AUDIO_TDMIN_C_CTRL 4284752768 #define SEC_AED_NG_STEP 4284834332 #define SEC_EE_AUDIO_SPDIFOUT_B_SWAP 4284753560 #define SEC_RESET2_SEC_LEVEL 4284801096 #define EE_AUDIO_FRDDR_C_START_ADDRB 4284752476 #define P_AO_CEC_RW_REG 4286578948 #define P_EFUSE_CLR 4284678144 #define P_EE_AUDIO_TODDR_A_CTRL0 4284752128 #define P_EE_AUDIO_TODDR_A_CTRL1 4284752132 #define SEC_EE_AUDIO_TODDR_B_FINISH_ADDRB 4284752224 #define EE_AUDIO_MST_E_SCLK_CTRL0 4284751968 #define EE_AUDIO_MST_E_SCLK_CTRL1 4284751972 #define P_AO_TIMER_CTRL 4286579648 #define P_AO_SEC_SP_CFG7 4286579612 #define P_AO_SEC_SP_CFG6 4286579608 #define P_AO_SEC_SP_CFG9 4286579620 #define P_AO_SEC_SP_CFG8 4286579616 #define EE_AUDIO_TODDR_A_FINISH_ADDR 4284752140 #define P_AO_SEC_SP_CFG3 4286579596 #define SEC_AO_MAILBOX_CLR_0 4286619660 #define P_AO_SEC_SP_CFG2 4286579592 #define SEC_AO_MAILBOX_CLR_1 4286619672 #define P_AO_SEC_SP_CFG5 4286579604 #define SEC_AO_MAILBOX_CLR_2 4286619684 #define P_AO_SEC_SP_CFG4 4286579600 #define SEC_AO_MAILBOX_CLR_3 4286619696 #define P_MIPI_ISP_RDARB_LIMT0 4284842004 #define P_AO_SEC_SP_CFG1 4286579588 #define P_AO_SEC_SP_CFG0 4286579584 #define P_EE_AUDIO_TDMOUT_C_STAT 4284753308 #define HHI_ISP_MAX_ADDR_CNTL 4284727764 #define KL_RAM 4284678400 #define SEC_TS_PLL_STAT9 4284696676 #define SEC_AO_SAR_ADC_AUX_SW 4286615580 #define SEC_TS_PLL_STAT1 4284696644 #define SEC_TS_PLL_STAT2 4284696648 #define SEC_TS_PLL_STAT3 4284696652 #define SEC_TS_PLL_STAT4 4284696656 #define HHI_SPICC_CLK_CNTL 4284728284 #define SEC_TS_PLL_STAT5 4284696660 #define SEC_TS_PLL_STAT6 4284696664 #define SEC_TS_PLL_STAT7 4284696668 #define SEC_TS_PLL_STAT8 4284696672 #define SEC_TS_PLL_STAT0 4284696640 #define EE_AUDIO_ARB_CTRL 4284752512 #define P_HHI_NAND_CLK_CNTL 4284727900 #define AO_GPIO_O_EN_N 4286578724 #define P_PDM_STS 4284743728 #define SEC_SECE_TIMER_CTRL 4284696100 #define AO_MF_IR_DEC_FRAME_RSV0 4286611580 #define AO_MF_IR_DEC_FRAME_RSV1 4286611584 #define SEC_AO_CECB_INTR_MASKN 4286579344 #define P_AO_CECB_GEN_CNTL 4286579336 #define HIU_MAILBOX_STAT_0 4284728328 #define SEC_AO_TIMER_CTRL 4286579648 #define HIU_MAILBOX_STAT_6 4284728400 #define HIU_MAILBOX_STAT_5 4284728388 #define AO_DEBUG_REG3 4286578860 #define HIU_MAILBOX_STAT_7 4284728412 #define HIU_MAILBOX_STAT_2 4284728352 #define HIU_MAILBOX_STAT_1 4284728340 #define HIU_MAILBOX_STAT_4 4284728376 #define HIU_MAILBOX_STAT_3 4284728364 #define AO_DEBUG_REG0 4286578848 #define AO_DEBUG_REG2 4286578856 #define AO_TIMERA_REG 4286579660 #define MIPI_DSI_PHY_CTRL 4284760064 #define AO_DEBUG_REG1 4286578852 #define P_HHI_VID_CLK_CNTL2 4284727700 #define P_EE_AUDIO_TDMIN_LB_SWAP 4284752836 #define MIPI_DSI_CLK_TIM 4284760076 #define PREG_PAD_GPIO2_I 4284695648 #define TS_PLL_CFG_REG4 4284696592 #define TS_PLL_CFG_REG5 4284696596 #define TS_PLL_CFG_REG2 4284696584 #define TS_PLL_CFG_REG3 4284696588 #define TS_PLL_CFG_REG1 4284696580 #define SEC_ETH_PHY_DBG_REG 4284792992 #define PREG_PAD_GPIO2_O 4284695644 #define TS_PLL_CFG_REG6 4284696600 #define TS_PLL_CFG_REG7 4284696604 #define P_PREG_PAD_GPIO5_O 4284695684 #define AO_SEC_SP_CFG0 4286579584 #define AO_SEC_SP_CFG2 4286579592 #define AO_SEC_SP_CFG1 4286579588 #define AO_SEC_SP_CFG4 4286579600 #define AO_SEC_SP_CFG3 4286579596 #define AO_SEC_SP_CFG6 4286579608 #define AO_SEC_SP_CFG5 4286579604 #define AO_SEC_SP_CFG8 4286579616 #define AO_SEC_SP_CFG7 4286579612 #define AO_SEC_SP_CFG9 4286579620 #define SEC_MIPI_DSI_CHAN_CTRL 4284760068 #define P_AUD_LOCK_OMCLK_LAT_INT 4284784668 #define SEC_PREG_PAD_GPIO0_I 4284695624 #define SEC_PREG_PAD_GPIO0_O 4284695620 #define HIU_MAILBOX_SET_2 4284728348 #define HIU_MAILBOX_SET_1 4284728336 #define HIU_MAILBOX_SET_0 4284728324 #define HIU_MAILBOX_SET_6 4284728396 #define HIU_MAILBOX_SET_5 4284728384 #define HIU_MAILBOX_SET_4 4284728372 #define HIU_MAILBOX_SET_3 4284728360 #define P_EE_AUDIO_TDMOUT_C_SWAP 4284753288 #define EE_AUDIO_TDMIN_B_MASK3 4284752724 #define EE_AUDIO_TDMIN_B_MASK2 4284752720 #define SEC_AO_PWM_A2 4286607380 #define EE_AUDIO_TDMIN_B_MASK1 4284752716 #define EE_AUDIO_TDMIN_B_MASK0 4284752712 #define P_PREG_PAD_GPIO5_I 4284695688 #define AO_IR_DEC_LDR_ACTIVE 4286611456 #define SEC_AO_PWM_B2 4286607384 #define P_AO_PWM_BLINK_CD 4286586908 #define P_PAD_PULL_UP_REG0 4284695784 #define P_PAD_PULL_UP_REG2 4284695792 #define P_PAD_PULL_UP_REG1 4284695788 #define P_PAD_PULL_UP_REG4 4284695800 #define AO_MF_IR_DEC_IRQ_CTL 4286611592 #define P_PAD_PULL_UP_REG3 4284695796 #define P_PAD_PULL_UP_REG5 4284695804 #define P_AMLUSB_B0 4284719104 #define P_AMLUSB_B1 4284719108 #define SEC_AO_PWM_C2 4286586900 #define SEC_AO_PINMUX_LOCK 4286578780 #define P_AMLUSB_B4 4284719120 #define P_AMLUSB_B5 4284719124 #define P_EE_AUDIO_FRDDR_C_CTRL0 4284752448 #define P_AMLUSB_B2 4284719112 #define P_AMLUSB_B3 4284719116 #define P_AMLUSB_B8 4284719136 #define P_EE_AUDIO_FRDDR_C_CTRL1 4284752452 #define P_AMLUSB_B9 4284719140 #define P_AMLUSB_B6 4284719128 #define P_AMLUSB_B7 4284719132 #define P_AMLUSB_A9 4284702756 #define HIU_MAILBOX_SET_7 4284728408 #define P_AMLUSB_A0 4284702720 #define SEC_AO_PWM_D2 4286586904 #define P_AMLUSB_A3 4284702732 #define P_AMLUSB_A4 4284702736 #define EE_AUDIO_TODDR_B_FINISH_ADDRB 4284752224 #define P_AMLUSB_A1 4284702724 #define P_AMLUSB_A2 4284702728 #define P_AMLUSB_A7 4284702748 #define P_AMLUSB_A8 4284702752 #define P_AMLUSB_A5 4284702740 #define SEC_EE_AUDIO_TODDR_B_START_ADDRB 4284752220 #define SEC_AO_RTI_PULL_UP_EN_REG 4286578736 #define P_AMLUSB_A6 4284702744 #define P_AO_I2C_S_CONTROL_REG 4286603264 #define SEC_HHI_BT656_CLK_CNTL 4284728276 #define SEC_AO_SAR_ADC_DELAY 4286615568 #define SEC_EE_AUDIO_SPDIFOUT_B_MUTE_VAL 4284753612 #define P_SYS_CPUB_CFG8 4284696488 #define P_SYS_CPUB_CFG9 4284696492 #define P_SYS_CPUB_CFG6 4284696480 #define P_SYS_CPUB_CFG7 4284696484 #define P_SYS_CPUB_CFG4 4284696472 #define P_SYS_CPUB_CFG5 4284696476 #define P_SYS_CPUB_CFG2 4284696464 #define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL 4284752052 #define P_SYS_CPUB_CFG3 4284696468 #define P_AO_SEC_M4_CPU_SRAM_REG1_0 4286579364 #define P_SYS_CPUB_CFG0 4284696456 #define P_SYS_CPUB_CFG1 4284696460 #define SEC_AO_TIMERG_REG 4286579700 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_0 4286579144 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_2 4286579152 #define P_AO_GPIO_I 4286578728 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG3_1 4286579148 #define P_EE_AUDIO_MCLK_B_CTRL 4284751880 #define P_AO_GPIO_O 4286578740 #define AO_CEC_CLK_CNTL_REG1 4286578808 #define AO_CEC_CLK_CNTL_REG0 4286578804 #define SEC_AO_RTI_PWR_SYS_CPUB_MEM_PD0 4286579536 #define SEC_AO_RTI_PWR_SYS_CPUB_MEM_PD1 4286579540 #define P_MIPI_ISP_WRARB_UGT 4284842024 #define SEC_HHI_SPICC_CLK_CNTL 4284728284 #define AO_SEC_SCRATCH 4286579068 #define P_AO_CEC_GEN_CNTL 4286578944 #define P_MIPI_ISP_WRARB_WEIGH1_SLV 4284842020 #define AO_SAR_ADC_DETECT_IDLE_SW 4286615588 #define EFUSE_CLK_A53_CFG01 4284696324 #define SEC_MIPI_OTHER_CNTL0 4284829952 #define SEC_MIPI_OTHER_CNTL1 4284829956 #define SEC_MIPI_OTHER_CNTL4 4284829968 #define SEC_MIPI_OTHER_CNTL2 4284829960 #define SEC_MIPI_OTHER_CNTL3 4284829964 #define P_EE_AUDIO_CLK_TDMOUT_C_CTRL 4284752024 #define SEC_HHI_HDMI_CLK_CNTL 4284727756 #define SEC_AO_RTI_GEN_PWR_ACK0 4286578928 #define SEC_EE_AUDIO_LB_CTRL1 4284752580 #define SEC_EE_AUDIO_LB_CTRL0 4284752576 #define SEC_AO_SAR_ADC_REG11 4286615596 #define P_HHI_VPU_CLKB_CNTL 4284727820 #define SEC_AO_SAR_ADC_REG13 4286615604 #define SEC_AO_SAR_ADC_REG12 4286615600 #define PDM_CHAN_CTRL1 4284743712 #define EE_AUDIO_TDMOUT_A_MASK1 4284753168 #define EE_AUDIO_TDMOUT_A_MASK0 4284753164 #define EE_AUDIO_TDMOUT_A_MASK3 4284753176 #define EE_AUDIO_TDMOUT_A_MASK2 4284753172 #define P_MIPI_ADAPT_IRQ_MASK0 4284830080 #define P_MIPI_ADAPT_IRQ_MASK1 4284830088 #define SEC_BUS_MON0_ADDR 4284696072 #define SEC_EE_AUDIO_MST_E_SCLK_CTRL0 4284751968 #define SEC_EE_AUDIO_MST_E_SCLK_CTRL1 4284751972 #define P_AO_SEC_M4_CPU_SRAM_REG1_1 4286579368 #define SEC_EE_AUDIO_FRDDR_B_START_ADDR 4284752392 #define M4_CPU_CNTL2 4286579464 #define M4_CPU_CNTL3 4286579468 #define M4_CPU_CNTL4 4286579472 #define M4_CPU_CNTL5 4286579476 #define SEC_AO_SEC_TMODE_PWD0 4286579040 #define P_EE_AUDIO_TDMOUT_C_CTRL0 4284753280 #define SEC_AO_SEC_TMODE_PWD1 4286579044 #define P_EE_AUDIO_TDMOUT_C_CTRL1 4284753284 #define SEC_AO_SEC_TMODE_PWD2 4286579048 #define SEC_AO_SEC_TMODE_PWD3 4286579052 #define AO_MF_IR_DEC_FIFO_CTL 4286611596 #define P_HHI_GCLK_OTHER 4284727632 #define SEC_AM_RING_OSC_REG0 4284696060 #define SEC_M4_CPU_CNTL2 4286579464 #define SEC_M4_CPU_CNTL3 4286579468 #define SEC_M4_CPU_CNTL4 4286579472 #define SEC_M4_CPU_CNTL5 4286579476 #define P_EE_AUDIO_CLK_TDMIN_LB_CTRL 4284752012 #define P_EE_AUDIO_TDMOUT_B_MUTE3 4284753272 #define P_EE_AUDIO_TDMOUT_B_MUTE2 4284753268 #define P_EE_AUDIO_TDMOUT_B_MUTE1 4284753264 #define P_EE_AUDIO_TDMOUT_B_MUTE0 4284753260 #define P_AO_PWM_BLINK_AB 4286607388 #define P_EE_AUDIO_MST_D_SCLK_CTRL0 4284751960 #define P_EE_AUDIO_MST_D_SCLK_CTRL1 4284751964 #define SEC_AO_UART2_RFIFO 4286595076 #define AED_DRC_AA_H 4284834312 #define SEC_HHI_HIFI_PLL_CNTL5 4284727532 #define SEC_HHI_HIFI_PLL_CNTL6 4284727536 #define P_AO_MAILBOX_SET_3 4286619688 #define P_AO_MAILBOX_SET_2 4286619676 #define P_AO_MAILBOX_SET_1 4286619664 #define P_AO_MAILBOX_SET_0 4286619652 #define SEC_RO_OMCLK2REF_CNT_H 4284784732 #define SEC_RO_OMCLK2REF_CNT_L 4284784728 #define P_AO_SEC_SCRATCH 4286579068 #define SEC_HHI_HIFI_PLL_CNTL0 4284727512 #define SEC_HHI_HIFI_PLL_CNTL1 4284727516 #define SEC_HHI_HIFI_PLL_CNTL2 4284727520 #define SEC_HHI_HIFI_PLL_CNTL3 4284727524 #define SEC_HHI_HIFI_PLL_CNTL4 4284727528 #define SEC_AO_SAR_ADC_FIFO_RD 4286615576 #define P_AED_DRC_AD_H 4284834316 #define SEC_AO_UART2_CONTROL 4286595080 #define P_AO_TIMERE_REG 4286579684 #define AO_SEC_SHARED_AHB_SRAM_REG5_1 4286579172 #define AO_SEC_SHARED_AHB_SRAM_REG5_2 4286579176 #define AO_SEC_SHARED_AHB_SRAM_REG5_0 4286579168 #define AO_RTI_GEN_PWR_ACK0 4286578928 #define P_AO_CLK_GATE0_SP 4286578768 #define AED_DEBUG1 4284834288 #define AED_DEBUG0 4284834284 #define AED_DEBUG3 4284834296 #define HHI_VDEC3_CLK_CNTL 4284727784 #define EFUSE_START 4284678148 #define AED_DEBUG2 4284834292 #define AED_DEBUG5 4284834304 #define AED_DEBUG4 4284834300 #define AED_DEBUG6 4284834308 #define HHI_PCIE_PLL_STS 4284727472 #define P_EE_AUDIO_TORAM_INIT_ADDR 4284753692 #define P_EE_AUDIO_TDMIN_C_STAT 4284752792 #define P_HHI_MIPI_CNTL2 4284727304 #define P_HHI_MIPI_CNTL0 4284727296 #define P_HHI_MIPI_CNTL1 4284727300 #define AO_SEC_SD_CFG8 4286579232 #define AO_SEC_SD_CFG7 4286579228 #define AO_SEC_SD_CFG6 4286579224 #define AO_SEC_SD_CFG5 4286579220 #define AO_SEC_SD_CFG4 4286579216 #define AO_SEC_SD_CFG3 4286579212 #define AO_SEC_SD_CFG2 4286579208 #define AO_SEC_SD_CFG1 4286579204 #define AO_SEC_SD_CFG9 4286579236 #define SEC_EE_AUDIO_FRDDR_A_CTRL1 4284752324 #define SEC_EE_AUDIO_FRDDR_A_CTRL0 4284752320 #define SEC_MIPI_ADAPT_DDR_RD0_ST1 4284829720 #define SEC_MIPI_ADAPT_DDR_RD0_ST0 4284829716 #define SEC_MIPI_ADAPT_DDR_RD0_ST2 4284829724 #define P_MIPI_ADAPT_DDR_RD1_CNTL4 4284829776 #define AO_CEC_INTR_CLR 4286578956 #define MIPI_DSI_LPOK_TIM 4284760100 #define P_ETH_PHY_DBG_CFG3 4284792852 #define P_ETH_PHY_DBG_CFG4 4284792856 #define P_MIPI_ADAPT_DDR_RD1_CNTL0 4284829760 #define P_ETH_PHY_DBG_CFG1 4284792844 #define P_MIPI_ADAPT_DDR_RD1_CNTL1 4284829764 #define P_ETH_PHY_DBG_CFG2 4284792848 #define P_HHI_MIPI_STS 4284727308 #define P_MIPI_ADAPT_DDR_RD1_CNTL2 4284829768 #define P_MIPI_ADAPT_DDR_RD1_CNTL3 4284829772 #define P_ETH_PHY_DBG_CFG0 4284792840 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS6 4284753076 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS7 4284753080 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS8 4284753084 #define EE_AUDIO_TORAM_FINISH_ADDR 4284753676 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS9 4284753088 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS0 4284753052 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS1 4284753056 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS2 4284753060 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS3 4284753064 #define SECE_TIMER_LOW 4284696104 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS4 4284753068 #define SEC_EE_AUDIO_SPDIFOUT_CHSTS5 4284753072 #define P_AO_SEC_JTAG_PWD_SCP_CNTL 4286579436 #define SEC_EE_AUDIO_SPDIFOUT_CHSTSA 4284753092 #define SEC_EE_AUDIO_SPDIFOUT_CHSTSB 4284753096 #define AO_SEC_AO_CPU_SRAM_REG1_1 4286579196 #define AO_SEC_AO_CPU_SRAM_REG1_0 4286579192 #define HHI_HDMI_PLL_STS 4284728124 #define SEC_AED_TOP_REQ_CTL 4284834340 #define SEC_AED_DRC_THD0 4284834244 #define P_AO_CPU_TIMESTAMP 4286578900 #define SEC_AED_DRC_THD1 4284834248 #define SEC_SCR_HIU 4284727340 #define AO_CECB_INTR_MASKN 4286579344 #define P_EE_AUDIO_SPDIFOUT_STAT 4284753024 #define SEC_EE_AUDIO_TDMOUT_C_CTRL1 4284753284 #define P_PREG_PAD_GPIO4_O 4284695668 #define SEC_EE_AUDIO_TDMOUT_C_CTRL0 4284753280 #define P_AUD_LOCK_REFCLK_SRC 4284784656 #define P_EE_AUDIO_TODDR_A_START_ADDRB 4284752156 #define AO_CECB_INTR_STAT 4286579352 #define SEC_ASYNC_FIFO_LOCK_ADR 4284696096 #define P_AO_I2C_M_0_TOKEN_LIST0 4286599176 #define P_AO_I2C_M_0_TOKEN_LIST1 4286599180 #define P_AO_SEC_JTAG_SCP_CTRL 4286579416 #define AO_SEC_SD_CFG0 4286579200 #define AO_SEC_SHARED_AHB_SRAM_REG3_0 4286579144 #define P_HHI_VDEC2_CLK_CNTL 4284727780 #define AO_SEC_SHARED_AHB_SRAM_REG3_1 4286579148 #define AO_SEC_SHARED_AHB_SRAM_REG3_2 4286579152 #define SEC_AED_EQ_VOLUME 4284834196 #define P_MIPI_ISP_WRARB_MODE 4284842008 #define SEC_EE_AUDIO_TDMIN_C_SWAP 4284752772 #define SEC_HHI_SYS_PLL_STS 4284728080 #define P_EE_AUDIO_SECURITY_CTRL 4284753484 #define P_PREG_PAD_GPIO4_I 4284695672 #define P_MIPI_ISP_ARB_DBG_STAT 4284842036 #define P_EE_AUDIO_TODDR_B_FINISH_ADDR 4284752204 #define EE_AUDIO_SPDIFIN_CTRL5 4284752916 #define EE_AUDIO_SPDIFIN_CTRL6 4284752920 #define SEC_DDR_RD0_LBUF_STATUS 4284830016 #define EE_AUDIO_SPDIFIN_CTRL0 4284752896 #define EE_AUDIO_SPDIFIN_CTRL3 4284752908 #define EE_AUDIO_SPDIFIN_CTRL4 4284752912 #define EE_AUDIO_SPDIFIN_CTRL1 4284752900 #define EE_AUDIO_SPDIFIN_CTRL2 4284752904 #define SEC_AO_IR_DEC_REG1 4286611484 #define SEC_AO_IR_DEC_REG0 4286611472 #define EE_AUDIO_MCLK_A_CTRL 4284751876 #define P_HHI_SYS_PLL_CNTL0 4284728052 #define MIPI_DSI_WAKEUP_TIM 4284760096 #define P_HHI_SYS_PLL_CNTL1 4284728056 #define P_HHI_SYS_PLL_CNTL2 4284728060 #define P_HHI_SYS_PLL_CNTL3 4284728064 #define P_HHI_SYS_PLL_CNTL4 4284728068 #define P_PREG_PAD_GPIO0_EN_N 4284695616 #define P_HHI_SYS_PLL_CNTL5 4284728072 #define P_HHI_SYS_PLL_CNTL6 4284728076 #define HHI_CHECK_CLK_RESULT 4284727312 #define P_EE_AUDIO_TDMOUT_A_GAIN1 4284753188 #define SEC_EE_AUDIO_TODDR_C_START_ADDR 4284752264 #define P_EE_AUDIO_TDMOUT_A_GAIN0 4284753184 #define P_AO_RTI_GEN_PWR_ISO0 4286578924 #define EE_AUDIO_TDMOUT_C_MUTE2 4284753332 #define EE_AUDIO_TDMOUT_C_MUTE1 4284753328 #define EE_AUDIO_TDMOUT_C_MUTE0 4284753324 #define EE_AUDIO_TDMOUT_C_MUTE3 4284753336 #define P_HHI_ETH_CLK_CNTL 4284727768 #define HHI_HDMI_PLL_CNTL3 4284728108 #define HHI_HDMI_PLL_CNTL4 4284728112 #define HHI_HDMI_PLL_CNTL5 4284728116 #define HHI_HDMI_PLL_CNTL6 4284728120 #define HHI_HDMI_PLL_CNTL0 4284728096 #define HHI_HDMI_PLL_CNTL1 4284728100 #define HHI_HDMI_PLL_CNTL2 4284728104 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_1 4286579136 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_0 4286579132 #define SEC_AO_SEC_SHARED_AHB_SRAM_REG2_2 4286579140 #define AO_SEC_GP_CFG9 4286579300 #define AO_SEC_GP_CFG0 4286579264 #define P_BUS_MON0_ADDR 4284696072 #define AO_SEC_GP_CFG7 4286579292 #define AO_SEC_GP_CFG8 4286579296 #define AO_SEC_GP_CFG5 4286579284 #define AO_SEC_GP_CFG6 4286579288 #define AO_SEC_GP_CFG3 4286579276 #define P_M4_CPU_CNTL_NS 4286579460 #define AO_SEC_GP_CFG4 4286579280 #define AO_SEC_GP_CFG1 4286579268 #define AO_SEC_GP_CFG2 4286579272 #define P_AO_UART2_STATUS 4286595084 #define P_MIPI_DSI_LP_WCHDOG 4284760104 #define SEC_AO_TIMERE_HI_REG 4286579688 #define P_RESET2_SEC_REGISTER 4284801032 #define PREG_STICKY_REG4 4284696016 #define PREG_STICKY_REG3 4284696012 #define PREG_STICKY_REG2 4284696008 #define PREG_STICKY_REG1 4284696004 #define PREG_STICKY_REG0 4284696000 #define HHI_NANOQ_MEM_PD_REG1 4284727568 #define SEC_PREG_PAD_GPIO1_EN_N 4284695628 #define HHI_NANOQ_MEM_PD_REG0 4284727564 #define PREG_STICKY_REG9 4284696036 #define PREG_STICKY_REG8 4284696032 #define PREG_STICKY_REG7 4284696028 #define PREG_STICKY_REG6 4284696024 #define PREG_STICKY_REG5 4284696020 #define SEC_AO_CEC_RW_REG 4286578948 #define SEC_HHI_APICALGDC_CLK_CNTL 4284727660 #define SEC_HHI_MPLL_STS 4284727964 #define EE_AUDIO_FRDDR_C_FINISH_ADDR 4284752460 #define P_HHI_CDAC_CLK_CNTL 4284728280 #define HHI_HDCP22_CLK_CNTL 4284727792 #define SEC_AO_WRITE_ONCE1 4286579060 #define SEC_AO_WRITE_ONCE0 4286579056 #define SEC_AO_WRITE_ONCE2 4286579064 #define AED_DRC_AA_1M_H 4284834320 #define SEC_EE_AUDIO_TODDR_C_FINISH_ADDR 4284752268 #define AO_PWM_TIME_AB 4286607376 #define P_AO_SEC_JTAG_PWD_SP_1 4286579384 #define P_AO_SEC_JTAG_PWD_SP_2 4286579388 #define P_AO_SEC_JTAG_PWD_SP_3 4286579392 #define P_AO_SEC_JTAG_PWD_SP_0 4286579380 #define P_AO_IR_DEC_DEMOD_CNTL1 4286611652 #define HHI_GCLK_MPEG0 4284727616 #define P_AO_IR_DEC_DEMOD_CNTL0 4286611648 #define HHI_GCLK_MPEG1 4284727620 #define HHI_GCLK_MPEG2 4284727624 #define AO_PWM_A2 4286607380 #define SEC_AED_NG_THD0 4284834264 #define SEC_AED_NG_THD1 4284834268 #define P_AED_ED_CTL 4284834280 #define P_PROD_TEST_REG1 4284695940 #define P_PROD_TEST_REG0 4284695936 #define P_PROD_TEST_REG3 4284695948 #define P_PROD_TEST_REG2 4284695944 #define P_AO_UART2_WFIFO 4286595072 #define SEC_TS_PLL_CFG_REG7 4284696604 #define SEC_TS_PLL_CFG_REG6 4284696600 #define SEC_TS_PLL_CFG_REG5 4284696596 #define BUS_MON1_DATA 4284696088 #define EE_AUDIO_TODDR_A_START_ADDR 4284752136 #define SEC_TS_PLL_CFG_REG4 4284696592 #define AO_PWM_TIME_CD 4286586896 #define SEC_TS_PLL_CFG_REG3 4284696588 #define SEC_TS_PLL_CFG_REG2 4284696584 #define SEC_TS_PLL_CFG_REG1 4284696580 #define SEC_AED_ED_CTL 4284834280 #define SEC_MIPI_DSI_TURN_WCHDOG 4284760116 #define AO_PWM_C2 4286586900 #define BUS_STS9 4284695996 #define PDM_F1_CTRL 4284743692 #define BUS_STS7 4284695988 #define BUS_STS8 4284695992 #define BUS_STS5 4284695980 #define BUS_STS6 4284695984 #define BUS_STS3 4284695972 #define BUS_STS4 4284695976 #define BUS_STS1 4284695964 #define BUS_STS2 4284695968 #define BUS_STS0 4284695960 #define P_EE_AUDIO_TORAM_STATUS1 4284753684 #define P_EE_AUDIO_TORAM_STATUS2 4284753688 #define SEC_EE_AUDIO_TDMOUT_A_MASK_VAL 4284753212 #define AO_PWM_B2 4286607384 #define P_EE_AUDIO_CLK_TDMIN_C_CTRL 4284752008 #define P_AO_SEC_M4_CPU_SRAM_REG0_1 4286579360 #define P_AO_SEC_M4_CPU_SRAM_REG0_0 4286579356 #define AO_PWM_DELTA_SIGMA_CD 4286586892 #define P_HHI_MALI_CLK_CNTL 4284727728 #define P_EE_AUDIO_TODDR_C_INT_ADDR 4284752272 #define SEC_EE_AUDIO_TDMIN_A_STAT 4284752664 #define SEC_PDM_STS 4284743728 #define SEC_AO_SEC_JTAG_PWD_SCP_CNTL 4286579436 #define SECE_TIMER_CTRL 4284696100 #define AO_MAILBOX_CLR_2 4286619684 #define AO_MAILBOX_CLR_3 4286619696 #define AO_MAILBOX_CLR_0 4286619660 #define AO_MAILBOX_CLR_1 4286619672 #define EE_AUDIO_TDMOUT_B_GAIN1 4284753252 #define EE_AUDIO_TDMOUT_B_GAIN0 4284753248 #define AUD_LOCK_REFCLK_DS_INT 4284784672 #define AO_PWM_D2 4286586904 #define SEC_MIPI_ADAPT_DDR_RD1_CNTL0 4284829760 #define SEC_MIPI_ADAPT_DDR_RD1_CNTL2 4284829768 #define SEC_MIPI_ADAPT_DDR_RD1_CNTL1 4284829764 #define SEC_MIPI_ADAPT_DDR_RD1_CNTL4 4284829776 #define SEC_MIPI_ADAPT_DDR_RD1_CNTL3 4284829772 #define EE_AUDIO_MCLK_F_CTRL 4284751896 #define AUD_LOCK_HW_LATCH 4284784652 #define HHI_MPLL_STS 4284727964 #define EE_AUDIO_CLK_PDMIN_CTRL1 4284752048 #define SEC_HHI_NAND_CLK_CNTL 4284727900 #define EE_AUDIO_CLK_PDMIN_CTRL0 4284752044 #define P_EE_AUDIO_TODDR_C_START_ADDR 4284752264 #define P_HHI_FIX_PLL_STS 4284727996 #define EE_AUDIO_RESAMPLE_COEF2 4284752984 #define EE_AUDIO_RESAMPLE_COEF1 4284752980 #define EE_AUDIO_RESAMPLE_COEF0 4284752976 #define EE_AUDIO_RESAMPLE_COEF4 4284752992 #define EE_AUDIO_RESAMPLE_COEF3 4284752988 #define AO_SEC_SHARED_AHB_SRAM_REG4_2 4286579164 #define P_AO_IR_DEC_FRAME 4286611476 #define SEC_DMA_T1 4284735492 #define SEC_HIU_MAILBOX_CLR_6 4284728404 #define SEC_DMA_T2 4284735496 #define SEC_HIU_MAILBOX_CLR_7 4284728416 #define AO_SEC_SHARED_AHB_SRAM_REG4_0 4286579156 #define AO_SEC_SHARED_AHB_SRAM_REG4_1 4286579160 #define SEC_DMA_T0 4284735488 #define SEC_DMA_T5 4284735508 #define SEC_HIU_MAILBOX_CLR_2 4284728356 #define SEC_HIU_MAILBOX_CLR_3 4284728368 #define SEC_DMA_T3 4284735500 #define SEC_HIU_MAILBOX_CLR_4 4284728380 #define SEC_DMA_T4 4284735504 #define SEC_HIU_MAILBOX_CLR_5 4284728392 #define P_AO_MF_IR_DEC_FRAME 4286611540 #define EE_AUDIO_POW_DET_CTRL0 4284753408 #define P_EE_AUDIO_FRDDR_B_START_ADDR 4284752392 #define SEC_HIU_MAILBOX_CLR_0 4284728332 #define EE_AUDIO_POW_DET_CTRL1 4284753412 #define SEC_HIU_MAILBOX_CLR_1 4284728344 #define AUD_LOCK_SW_RESET 4284784644 #define EE_AUDIO_MST_B_SCLK_CTRL0 4284751944 #define SEC_EE_AUDIO_TDMOUT_B_STAT 4284753244 #define MIPI_ADAPT_DDR_RD1_ST1 4284829784 #define MIPI_ADAPT_DDR_RD1_ST2 4284829788 #define SEC_AO_CPU_CNTL_NS 4286578756 #define EE_AUDIO_MST_B_SCLK_CTRL1 4284751948 #define AO_IRQ_GPIO_REG 4286578820 #define PREG_PAD_GPIO1_O 4284695632 #define HHI_VPU_CLKC_CNTL 4284727732 #define MIPI_ADAPT_DDR_RD1_ST0 4284829780 #define PREG_PAD_GPIO1_I 4284695636 #define SEC_AED_TOP_CTL 4284834336 #define P_HHI_GCLK2_MPEG2 4284727496 #define P_HHI_GCLK2_MPEG0 4284727488 #define P_HHI_GCLK2_MPEG1 4284727492 #define AUD_LOCK_OMCLK_DS_INT 4284784680 #define BUS_MONITOR_CNTL 4284696068 #define P_AO_METAL_REVISION 4286578812 #define SEC_AO_TIMESTAMP_RD1 4286578876 #define SEC_AO_TIMESTAMP_RD0 4286578872 #define P_AO_SAR_ADC_AUX_SW 4286615580 #define SEC_HHI_VPU_MEM_PD_REG1 4284727560 #define SEC_HHI_VPU_MEM_PD_REG2 4284727604 #define SEC_HHI_VPU_MEM_PD_REG0 4284727556 #define P_AO_TIMERF_HI_REG 4286579696 undefined1 * FUN_fffa1078(void) { memset(&DAT_fffb1000,0,0x1d0); DAT_fffb1010 = &DAT_fffb1120; DAT_fffb1002 = 0x50; DAT_fffb1122 = 0x58; DAT_fffb10ca = 0x58; DAT_fffb1000 = 3; DAT_fffb1008 = &DAT_fffb1080; DAT_fffb1018 = &DAT_fffb1098; DAT_fffb1028 = &DAT_fffb10b0; DAT_fffb1001 = 1; DAT_fffb1080 = 2; DAT_fffb1081 = 1; DAT_fffb1082 = 0x18; DAT_fffb1120 = 1; DAT_fffb1121 = 1; DAT_fffb1098 = 2; DAT_fffb1099 = 1; DAT_fffb109a = 0x18; DAT_fffb1020 = &DAT_fffb10c8; DAT_fffb10c8 = 1; DAT_fffb10c9 = 1; DAT_fffb10b0 = 2; DAT_fffb10b1 = 1; DAT_fffb10b2 = 0x18; DAT_fffb1030 = &DAT_fffb1050; DAT_fffb1050 = 2; DAT_fffb1051 = 1; DAT_fffb1004 = 0; DAT_fffb1084 = 0; DAT_fffb1124 = 0; DAT_fffb109c = 0; DAT_fffb10cc = 0; DAT_fffb10e0 = 0; DAT_fffb10b4 = 0; DAT_fffb1052 = 0x18; DAT_fffb1069 = 1; DAT_fffb1054 = 0; DAT_fffb1038 = &DAT_fffb1068; DAT_fffb1068 = 2; DAT_fffb106a = 0x18; DAT_fffb106c = 0; return &DAT_fffb1000; } undefined * FUN_fffa1180(void) { DAT_fffb1198 = 0xf1e2d3c4b5a6978; return &DAT_fffb1178; } void bl2_early_platform_setup(void) { uint uVar1; uVar1 = FUN_fffac56c(); FUN_fffac6a0(1); FUN_fffa5d80(); uVar1 = uVar1 >> 8 & 0xff; if (uVar1 != 10) { uVar1 = 0xb; } /* uVar1 == 0xb on librecomputer-alta? G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;0. bl2_stage_init 0x0b bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 */ stage_init__ns(uVar1); stage_init__ns(1); /* s_i 0x81, 0xc1 */ FUN_fffa5ee4(); stage_init__ns(2); tzram.total_base = &DAT_fffa0000; tzram.total_size = 0x40000; tzram.free_base = &DAT_fffb0000; tzram.free_size = 0x30000; tzram.attr__unk = 0xe939e2e8cf8effd; tzram.next = 0; return; } void boot_prep(void) { undefined8 ret; storage_init(&DAT_fffb1c40); ret = secureboot__ns(); if ((int)ret != 0) { loop_forever2(); } FUN_fffa63c8_dos(); return; } void FUN_fffa1260(void) { FUN_fffac958((ulong)&DAT_fffb1000,0x1d0); return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void bl2_plat_arch_setup(void) { uint uVar1; if (_DAT_ff80007c == 0x11111111) { uVar1 = 0xa00; } else if (_DAT_ff80007c == 0x11111113) { uVar1 = 0xb00; } else { uVar1 = 0xc00; } DAT_fffb2198 = _DAT_ff800220 & 0xf | _DAT_ffd0814c << 0x18 | uVar1 | (DAT_fffe7c10 & 0xff) << 0x10 ; return; } void FUN_fffa12f8(undefined8 param_1,long param_2) { *(uint *)(param_2 + 4) = *(uint *)(param_2 + 4) & 0xfffffffe; *(undefined8 *)(param_2 + 0x10) = 0x3cd; return; } void FUN_fffa1310(undefined8 param_1,long param_2) { *(undefined8 *)(param_2 + 0x10) = 0; *(uint *)(param_2 + 4) = *(uint *)(param_2 + 4) & 0xfffffffe; return; } void FUN_fffa1324(undefined8 param_1,long param_2) { int iVar1; ulong uVar2; uVar2 = FUN_fffac9f8(); iVar1 = 2; if ((uVar2 >> 8 & 0xf) == 0) { iVar1 = 1; } *(ulong *)(param_2 + 0x10) = (ulong)(iVar1 << 2 | 0x3c1); *(uint *)(param_2 + 4) = *(uint *)(param_2 + 4) | 1; return; } void FUN_fffa1368(int param_1,uint param_2) { char *s; if (param_2 < 8) { if (param_1 != 0) { *(int *)((ulong)(param_2 * 0xc) + 0xff63c404) = param_1; return; } s = s_Error__mailbox_try_to_send_zero_v_fffaca80; } else { s = s_Error__Use_the_error_port_num__fffaca60; } puts(s); return; } undefined4 FUN_fffa13a4(uint param_1) { undefined4 uVar1; if (param_1 < 8) { uVar1 = *(undefined4 *)((ulong)(param_1 * 0xc) + 0xff63c408); } else { puts(s_Error__Use_the_error_port_num__fffaca60); uVar1 = 0; } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa13e4(long param_1,uint param_2,int param_3) { long lVar1; int iVar2; uint uVar3; long lVar4; int local_40 [4]; undefined4 *local_30; undefined4 local_28; undefined4 local_24; undefined4 local_20; uint *local_18; uint local_10; undefined4 local_c [3]; local_40[0] = 0xd3; local_30 = local_c; local_28 = 0xd2; local_18 = &local_10; local_c[0] = 0xfffd0000; local_40[1] = 3; local_40[2] = 3; local_24 = 3; local_20 = 3; uVar3 = 0x59; if ((param_3 == 0x1000) && (param_2 < 0x10c01)) { local_10 = param_2; FUN_fffa61ac((long)&DAT_fffd0000_ddr_params,param_1,param_2); FUN_fffa61ac(0xfffe1800,param_1,0x1000); if (((_DAT_ff800200 & 3) == 3) || (loop_forever1(), (_DAT_ff800200 & 3) == 3)) { lVar4 = 0; do { DAT_fffe7a00 = **(undefined4 **)((long)&local_30 + lVar4); lVar1 = lVar4 + 0x18; FUN_fffa1368(*(int *)((long)local_40 + lVar4),*(uint *)((long)local_40 + lVar4 + 4)); loop_forever1(); iVar2 = FUN_fffa13a4(*(uint *)((long)local_40 + lVar4 + 8)); if (iVar2 != 0) { return 0x85; } lVar4 = lVar1; } while (lVar1 != 0x30); iVar2 = 600; do { loop_forever1(); iVar2 = iVar2 + -1; if (iVar2 == 0) { return 0x92; } } while ((_DAT_ff800200 & 3) == 3); iVar2 = 600; while (uVar3 = _DAT_ff800200 & 3, uVar3 != 0) { if ((uVar3 != 1) || (iVar2 = iVar2 + -1, iVar2 == 0)) { return 0x9b; } loop_forever1(); } } else { uVar3 = 0x6f; } } return uVar3; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa1590(undefined4 param_1) { _DAT_ffd0f0d8 = param_1; _DAT_ffd0f0dc = 0; _DAT_ffd0f0d0 = 0x3645dbf; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa15dc(void) { _DAT_ffd0f0dc = 0; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa15ec(void) { _DAT_ffd0f0d0 = _DAT_ffd0f0d0 & 0xfdfbffff; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void loop_forever2(void) { int iVar1; loop_forever1(); do { iVar1 = 100; do { iVar1 = iVar1 + -1; } while (iVar1 != 0); } while( true ); } void FUN_fffa1678(long param_1,long param_2,long param_3) { memcpy(param_3,param_1 + 0xfffe7c00,param_2); return; } uint FUN_fffa1694(void) { uint uVar1; uint local_10; uint local_c [3]; local_c[0] = 0; local_10 = 0; memcpy((long)&local_10,0xfffe7c11,1); memcpy((long)local_c,0xfffe7c13,1); uVar1 = local_10 & 0x40; if ((local_10 >> 6 & 1) != 0) { uVar1 = local_c[0] & 0x3f | 0x10000; } local_c[0] = uVar1; return local_c[0]; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint is_verified_boot_enabled(void) { return _EFUSE_LIC0_ff630030 & 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa1710(void) { return _EFUSE_LIC0_ff630030 >> 1 & 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa1724(void) { return _EFUSE_LIC0_ff630030 >> 6 & 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa1738(void) { return _DAT_ff800224 >> 0xb & 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa174c(void) { return _DAT_ff800224 >> 10 & 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint get_print_or_not_fffa1760(void) { return _EFUSE_LIC0_ff630030 >> 0x16 & 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa1774(int param_1) { uint uVar1; uVar1 = _DAT_ff63c174 & 0x7fff8e00; if (param_1 == 0) { _DAT_ff63c174 = uVar1 | 0x82; puts(s_Set_clk81_to_24M_fffacadb); _DAT_ff63c174 = _DAT_ff63c174 & 0xfffffeff; } else { puts(s_CLK81__166_6M_fffacacc); _DAT_ff63c174 = uVar1 | 0x5182; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa1818(int param_1) { uint uVar1; if ((int)_DAT_ff63c1ac < 0) { uVar1 = 0x100; if (param_1 != 0) { uVar1 = 0x900; } _DAT_ff63c1ac = uVar1 | _DAT_ff63c1ac & 0x7ffff180; } else { uVar1 = 0x81000000; if (param_1 != 0) { uVar1 = 0x89000000; } _DAT_ff63c1ac = uVar1 | _DAT_ff63c1ac & 0xf180ffff; } return; } void FUN_fffa1878(ulong param_1,uint param_2) { uint uVar1; uint uVar2; uint uVar3; uint uVar4; do { uVar4 = *(uint *)(param_1 & 0xffffffff); uVar1 = uVar4 & 0x10000000; } while ((uVar4 >> 0x1c & 1) != 0); if (param_2 == 1) { uVar4 = uVar4 | 0x4000800; goto LAB_fffa194c; } if (param_2 == 500) { uVar1 = 1; uVar3 = uVar1; uVar2 = uVar1; } else if (param_2 < 0x1f5) { if (param_2 == 0xfa) { uVar1 = 3; uVar2 = 1; LAB_fffa1908: uVar3 = 1; } else { uVar1 = 1; if (param_2 == 0x14d) goto LAB_fffa18f4; LAB_fffa18dc: uVar1 = 0; uVar3 = uVar1; uVar2 = uVar1; } } else { if (param_2 != 0x29b) { uVar2 = uVar1; if (param_2 != 1000) goto LAB_fffa18dc; goto LAB_fffa1908; } LAB_fffa18f4: uVar3 = 2; uVar2 = uVar1; } if ((uVar4 >> 10 & 1) == 0) { uVar4 = uVar4 & 0xfc08fbff | 0x4000400 | uVar1 << 0x14 | uVar2 << 0x12 | uVar3 << 0x10; } else { uVar4 = uVar4 & 0xfffff808 | 0x4000000 | uVar3 | uVar1 << 4 | uVar2 << 2; } uVar4 = uVar4 & 0xfffff7ff; LAB_fffa194c: *(uint *)(param_1 & 0xffffffff) = uVar4; return; } void FUN_fffa1954(char *param_1,char param_2) { char *s; puts(param_1); puts(s__pll_lock_check_fffacaed); if (param_2 == '\0') { s = s_pass_fffacafe; } else { s = s_retry_fffacb04; } puts(s); return; } undefined8 FUN_fffa1998(char *param_1,int param_2,uint param_3,uint param_4,uint param_5) { bool bVar1; int iVar2; uint *puVar3; puVar3 = (uint *)(ulong)param_3; if (param_2 != 0) { return 0; } FUN_fffa1954(param_1,'\x01'); puts(s_try_t0____fffacb0b); bVar1 = true; do { if (!bVar1) { FUN_fffa1954(param_1,'\x01'); puts(s_Stop_here____fffacb21); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } iVar2 = 100; do { iVar2 = iVar2 + -1; *(uint *)(ulong)param_4 = *(uint *)(ulong)param_4 | 0x80000000; loop_forever1(); *puVar3 = *puVar3 & 0xdfffffff; loop_forever1(); if ((int)*puVar3 < 0) { if (iVar2 != 0) { return 0; } break; } } while (iVar2 != 0); FUN_fffa1954(param_1,'\x01'); puts(s_try_t1____fffacb16); *(undefined4 *)(ulong)param_5 = 0x55540000; bVar1 = false; } while( true ); } int FUN_fffa1a80(int param_1,uint param_2) { uint *puVar1; puVar1 = (uint *)(ulong)param_2; do { *puVar1 = DAT_fffadbd8; param_1 = param_1 + -1; *(undefined4 *)(ulong)(param_2 + 4) = DAT_fffadbdc; *(undefined4 *)(ulong)(param_2 + 8) = DAT_fffadbe0; *(undefined4 *)(ulong)(param_2 + 0xc) = DAT_fffadbe4; *(undefined4 *)(ulong)(param_2 + 0x10) = DAT_fffadbe8; *(undefined4 *)(ulong)(param_2 + 0x14) = DAT_fffadbec; *(undefined4 *)(ulong)(param_2 + 0x18) = DAT_fffadbf0; loop_forever1(); *puVar1 = *puVar1 & 0xdfffffff; loop_forever1(); if ((int)*puVar1 < 0) { return param_1; } } while (param_1 != 0); return 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa1b48(char *param_1) { uint uVar1; uint uVar2; uint uVar3; uVar2 = 0; if ((_DAT_ff63c2f4 >> 10 & 0x1f) != 0) { uVar2 = 0x18 / (_DAT_ff63c2f4 >> 10 & 0x1f); } uVar1 = _DAT_ff63c2f4 & 0x1ff; uVar3 = _DAT_ff63c2f4 >> 0x10; puts(param_1); puts(s_d2pll_clk__fffad170 + 5); put_dec((ulong)(uVar2 * uVar1 >> ((ulong)uVar3 & 3))); puts(&DAT_fffacb2f); return; } uint FUN_fffa1ba8(uint param_1) { uint uVar1; uint uVar2; if (param_1 < 0x168) { puts(s_CPU_clk_minimum__360MHz_fffacb35); param_1 = 0x168; LAB_fffa1bf0: uVar1 = param_1 / 3; uVar2 = 0x30400; } else { if (param_1 < 0x7d1) { if (param_1 < 0x2ef) goto LAB_fffa1bf0; if (param_1 < 0x5dd) { uVar1 = param_1 / 6; uVar2 = 0x20400; goto LAB_fffa1c30; } } else { puts(s_CPU_clk_minimum__2000MHz_fffacb4e); param_1 = 0x7c8; } uVar1 = param_1 / 0xc; uVar2 = 0x10400; } LAB_fffa1c30: return uVar1 | uVar2; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 pll_init(void) { uint uVar1; int iVar2; long lVar3; long lVar4; if (*(short *)(*(long *)(DAT_fffb1c30 + 0x10) + 2) == 0) { puts(s_Set_A53_clk_to_24M_fffacb67); FUN_fffa1878((ulong)&DAT_ff63c19c,0); puts(s_Set_A73_clk_to_24M_fffacb7b); FUN_fffa1878((ulong)&DAT_ff63c208,0); FUN_fffa1774(0); FUN_fffa1818(0); if (*(int *)(*(long *)(DAT_fffb1c30 + 0x10) + 0x20) != 0) { puts(s_Use_user_sys_pll_config_fffacba0); lVar4 = *(long *)(DAT_fffb1c30 + 0x10); lVar3 = 0; do { *(undefined4 *)((long)&DAT_fffadbd8 + lVar3) = *(undefined4 *)(lVar4 + lVar3 + 0x20); lVar3 = lVar3 + 4; } while (lVar3 != 0x1c); } uVar1 = FUN_fffa1ba8((uint)**(ushort **)(DAT_fffb1c30 + 0x10)); DAT_fffadbd8 = uVar1 | 0x38000000; iVar2 = FUN_fffa1a80(100,0xff63c2f4); FUN_fffa1998(&DAT_fffacb8f,iVar2,0xff63c2f4,0xff63c300,0xff63c30c); iVar2 = FUN_fffa1a80(100,0xff63c380); FUN_fffa1998(&DAT_fffacb93,iVar2,0xff63c380,0xff63c38c,0xff63c398); FUN_fffa1b48(&DAT_fffacb98); FUN_fffa1b48(&DAT_fffacb9c); do { } while ((_DAT_ff63c19c >> 0x1c & 1) != 0); _DAT_ff63c19c = _DAT_ff63c19c | 0x4000800; do { } while ((_DAT_ff63c208 >> 0x1c & 1) != 0); _DAT_ff63c208 = _DAT_ff63c208 | 0x4000800; if (*(int *)(*(long *)(DAT_fffb1c30 + 0x10) + 0x60) != 0) { puts(s_Use_user_fix_pll_config_fffacbb9); lVar4 = *(long *)(DAT_fffb1c30 + 0x10); lVar3 = 0; do { *(undefined4 *)((long)&DAT_fffadbb8 + lVar3) = *(undefined4 *)(lVar4 + lVar3 + 0x60); lVar3 = lVar3 + 4; } while (lVar3 != 0x1c); } iVar2 = 100; do { _DAT_ff63c2a0 = DAT_fffadbb8; _DAT_ff63c2a4 = DAT_fffadbbc; _DAT_ff63c2a8 = DAT_fffadbc0; _DAT_ff63c2ac = DAT_fffadbc4; _DAT_ff63c2b0 = DAT_fffadbc8; _DAT_ff63c2b4 = DAT_fffadbcc; _DAT_ff63c2b8 = DAT_fffadbd0; loop_forever1(); _DAT_ff63c2a0 = _DAT_ff63c2a0 & 0xdfffffff; loop_forever1(); iVar2 = iVar2 + -1; if ((int)_DAT_ff63c2a0 < 0) break; } while (iVar2 != 0); FUN_fffa1998(&DAT_fffacbd2,iVar2,0xff63c2a0,0xff63c2ac,0xff63c2b8); FUN_fffa1774(1); FUN_fffa1818(1); } return 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa1f6c(void) { _DAT_ff80902c = _DAT_ff80902c & 0xffffff9f | 0x2000; _DAT_ff80900c = _DAT_ff80900c | 0x200000; loop_forever1(); _DAT_ff800090 = _DAT_ff800090 | 0x100; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ ulong saradc_ch1_get(void) { uint uVar1; ulong uVar2; _DAT_ff809000 = 0x84004040; _DAT_ff809004 = 0; _DAT_ff809008 = 0; _DAT_ff80900c = 0x9388000a; _DAT_ff809010 = 0x10a000a; _DAT_ff80901c = 0x3eb1a0c; _DAT_ff809020 = 0x8c000c; _DAT_ff809024 = 0xc000c; _DAT_ff80902c = 0x2c2003; _DAT_ff809034 = 0x2000; uVar1 = FUN_fffa1694(); if ((uVar1 >> 0x10 & 1) != 0) { _DAT_ff809034 = (uVar1 & 0x3f) << 8 | _DAT_ff809034 & 0xffffc0ff; } _DAT_ff80900c = _DAT_ff80900c | 0x8000000; _DAT_ff80902c = _DAT_ff80902c | 1; _DAT_ff800090 = _DAT_ff800090 & 0xffffff00 | 0x9f; FUN_fffa1f6c(); loop_forever1(); _DAT_ff809004 = 1; _DAT_ff809024 = 0x8c008c; uVar2 = 0; do { if ((_DAT_ff809000 & 0x70000000) == 0) { if ((uint)uVar2 < 10000) { _DAT_ff809000 = (_DAT_ff809000 | 5) & 0xfffffffe; uVar1 = _DAT_ff809018 >> 2 & 0x3ff; goto LAB_fffa2230; } break; } uVar1 = (uint)uVar2 + 1; uVar2 = (ulong)(ushort)uVar1; } while ((uVar1 & 0xffff) != 0x2711); _DAT_ff809000 = _DAT_ff809000 | 5; puts(s__Get_saradc_sample_Error__Cnt__fffacbd6); put_dec(uVar2); puts(s__fffadb47 + 1); uVar1 = 0xffffffff; LAB_fffa2230: _DAT_ff800090 = _DAT_ff800090 & 0xfffffeff; _DAT_ff80900c = _DAT_ff80900c & 0xffdfffff; uVar2 = 0; do { if (uVar1 <= (uint)(&DAT_fffacc08)[uVar2]) break; uVar2 = uVar2 + 1; } while (uVar2 != 0xd); uVar2 = uVar2 & 0xffffffff; _AO_SEC_GP_CFG0_ff800240 = _AO_SEC_GP_CFG0_ff800240 & 0xffff00ff | (int)uVar2 << 8; puts(s_Board_ID___fffacbf5); put_dec(uVar2); puts(s__fffadb47 + 1); return uVar2; } /* WARNING: Removing unreachable block (ram,0xfffa2340) */ /* WARNING: Removing unreachable block (ram,0xfffa23d4) */ /* WARNING: Removing unreachable block (ram,0xfffa2344) */ /* WARNING: Removing unreachable block (ram,0xfffa23c4) */ /* WARNING: Removing unreachable block (ram,0xfffa23e4) */ bool FUN_fffa22e4(void) { /* WARNING: Do nothing block with infinite loop */ do { } while( true ); } /* WARNING: Removing unreachable block (ram,0xfffa2520) */ /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa23f4(long param_1,int param_2,int param_3) { if (PTR_DAT_fffadbf8[0xc] == '\x04') { _DAT_ffd14008 = _DAT_ffd14008 | 0x100000; } else if (PTR_DAT_fffadbf8[0xc] == '\x02') { _DAT_ffd14008 = _DAT_ffd14008 | 0x4000; } else { _DAT_ffd14008 = _DAT_ffd14008 & 0xffefbfff; } if (param_3 < 1) { return; } do { } while( true ); } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined4 spi_nand_init(int param_1,undefined *param_2) { undefined uVar1; undefined *puVar2; bool bVar3; int iVar4; ulong uVar5; FUN_fffa5a34(); if (param_1 == 0) { _DAT_ffd14008 = 0xa949; } else { _DAT_ffd14008 = 0xa101; } _DAT_ffd14008 = _DAT_ffd14008 | 0x220000; memset(&DAT_fffe7000,0,0x200); memset(&DAT_fffe7200,0,0x100); uVar5 = 0x20; do { puts(s_SPI_NAND__spi_nand_read_info_fffacc40); puts(s_page___0x_fffacc5e); put_hex(uVar5,0x40); puts(s__fffadb47 + 1); bVar3 = FUN_fffa22e4(); if (!bVar3) { FUN_fffa23f4((long)PTR_DAT_fffadbf8,(uint)bVar3,0x200); iVar4 = FUN_fffac604((long)PTR_DAT_fffadbf8,(long)s_AMLIFPG_fffacc68); if (iVar4 == 0) { puts(s_SNIP_Vr__bl2_0x_fffacc70); put_hex(1,8); puts(s__bl33_0x_fffacc80); put_hex((ulong)(byte)PTR_DAT_fffadbf8[8],8); puts(s__fffadb47 + 1); puts(s__page_size_0x_fffacc89); put_hex((ulong)*(uint *)(PTR_DAT_fffadbf8 + 0x18),0x20); puts(s__fffadb47 + 1); puVar2 = PTR_DAT_fffadbf8; *param_2 = PTR_DAT_fffadbf8[0xb]; uVar1 = puVar2[10]; param_2[2] = 0; param_2[1] = uVar1; param_2[3] = puVar2[9]; puts(s_SPI_NAND__read_info_page_success_fffacc97); return 0; } } uVar5 = uVar5 + 0x80; } while (uVar5 != 0x420); puts(s_SPI_NAND__no_valid_info_page_fffaccb9); return 1; } /* WARNING: Removing unreachable block (ram,0xfffa27cc) */ /* WARNING: Removing unreachable block (ram,0xfffa27e8) */ /* WARNING: Removing unreachable block (ram,0xfffa2804) */ /* WARNING: Removing unreachable block (ram,0xfffa281c) */ /* WARNING: Removing unreachable block (ram,0xfffa2828) */ /* WARNING: Removing unreachable block (ram,0xfffa283c) */ /* WARNING: Removing unreachable block (ram,0xfffa2858) */ /* WARNING: Removing unreachable block (ram,0xfffa2868) */ /* WARNING: Removing unreachable block (ram,0xfffa2880) */ /* WARNING: Removing unreachable block (ram,0xfffa289c) */ /* WARNING: Removing unreachable block (ram,0xfffa28a4) */ /* WARNING: Removing unreachable block (ram,0xfffa28c8) */ /* WARNING: Removing unreachable block (ram,0xfffa28b8) */ /* WARNING: Removing unreachable block (ram,0xfffa28d4) */ /* WARNING: Removing unreachable block (ram,0xfffa29a4) */ /* WARNING: Removing unreachable block (ram,0xfffa28e8) */ /* WARNING: Removing unreachable block (ram,0xfffa28fc) */ /* WARNING: Removing unreachable block (ram,0xfffa2908) */ /* WARNING: Removing unreachable block (ram,0xfffa291c) */ /* WARNING: Removing unreachable block (ram,0xfffa2924) */ /* WARNING: Removing unreachable block (ram,0xfffa292c) */ /* WARNING: Removing unreachable block (ram,0xfffa2930) */ /* WARNING: Removing unreachable block (ram,0xfffa293c) */ /* WARNING: Removing unreachable block (ram,0xfffa2948) */ /* WARNING: Removing unreachable block (ram,0xfffa2954) */ /* WARNING: Removing unreachable block (ram,0xfffa2988) */ /* WARNING: Removing unreachable block (ram,0xfffa298c) */ /* WARNING: Removing unreachable block (ram,0xfffa29e0) */ /* WARNING: Removing unreachable block (ram,0xfffa29b8) */ /* WARNING: Removing unreachable block (ram,0xfffa29c8) */ /* WARNING: Removing unreachable block (ram,0xfffa29ec) */ /* WARNING: Removing unreachable block (ram,0xfffa29fc) */ /* WARNING: Removing unreachable block (ram,0xfffa2a04) */ /* WARNING: Removing unreachable block (ram,0xfffa29d4) */ /* WARNING: Removing unreachable block (ram,0xfffa29dc) */ /* WARNING: Removing unreachable block (ram,0xfffa29e8) */ /* WARNING: Removing unreachable block (ram,0xfffa295c) */ /* WARNING: Removing unreachable block (ram,0xfffa296c) */ /* WARNING: Removing unreachable block (ram,0xfffa297c) */ /* WARNING: Removing unreachable block (ram,0xfffa2984) */ /* WARNING: Removing unreachable block (ram,0xfffa2998) */ /* WARNING: Removing unreachable block (ram,0xfffa29ac) */ /* WARNING: Removing unreachable block (ram,0xfffa29b0) */ /* WARNING: Removing unreachable block (ram,0xfffa2a28) */ /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ bool FUN_fffa271c(ulong param_1,ulong param_2,long param_3,ulong param_4,int param_5) { FUN_fffa5a34(); do { } while( true ); } undefined FUN_fffa2a44(void) { return DAT_fffb1bd6; } void FUN_fffa2a50(byte param_1) { if (param_1 < 4) { DAT_fffb1bd6 = param_1; } return; } void FUN_fffa2a68(void) { return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa2a6c(uint param_1) { _DAT_ff800248 = (param_1 & 7) << 0x16 | _DAT_ff800248 & 0xfe3fffff; return; } long nf_load(undefined8 param_1,uint param_2,uint param_3,ulong param_4,int param_5) { int iVar1; iVar1 = FUN_fffa4df4(param_1,param_2,param_3,param_4,param_5); if (iVar1 != 0) { puts(s_nf_load_img_fail_fffacd40); } return (long)iVar1; } uint FUN_fffa2ac8(uint param_1,uint param_2,ulong param_3) { uint uVar1; uVar1 = (uint)((param_1 & 0xff) != 0) | (param_1 >> 8 & 1) << 1 | (param_1 >> 9 & 1) << 2 | (param_1 >> 10 & 1) << 3 | (param_1 >> 0xb & 1) << 4; if ((param_1 >> 0xc & 1) == 0) { if (uVar1 == 0) { return 0; } } else { uVar1 = uVar1 | 0x20; } if ((param_2 != 0x13) && (param_2 != 0x15)) { puts(s_sd_emmc_cmd_fffacd52); put_dec((ulong)param_2); puts(s__arg_0x_fffacd5f); put_hex(param_3 & 0xffffffff,0x20); puts(s__status_fffacd67); put_hex((ulong)param_1,0x20); puts(s__fffadb47 + 1); } return uVar1; } uint FUN_fffa2b94(long param_1,uint param_2,ulong param_3,undefined4 param_4,undefined4 *param_5) { uint uVar1; if (param_1 == 0) { uVar1 = 0x40; } else { *(undefined4 *)(param_1 + 0x48) = 0x3fff; *(uint *)(param_1 + 0x50) = param_2; *(undefined4 *)(param_1 + 0x58) = param_4; *(int *)(param_1 + 0x54) = (int)param_3; do { } while ((*(uint *)(param_1 + 0x48) >> 0xd & 1) == 0); uVar1 = FUN_fffa2ac8(*(uint *)(param_1 + 0x48),param_2 >> 0x18 & 0x3f,param_3); if ((param_5 != (undefined4 *)0x0) && (*param_5 = *(undefined4 *)(param_1 + 0x5c), (param_2 >> 0x15 & 1) != 0)) { *param_5 = *(undefined4 *)(param_1 + 0x68); param_5[1] = *(undefined4 *)(param_1 + 100); param_5[2] = *(undefined4 *)(param_1 + 0x60); param_5[3] = *(undefined4 *)(param_1 + 0x5c); } } return uVar1; } uint FUN_fffa2c2c(long param_1,undefined4 *param_2) { uint uVar1; uVar1 = FUN_fffa2b94(param_1,0x8c00cc00,0,0,param_2); return uVar1; } uint FUN_fffa2c44(long param_1,ulong param_2,long param_3,ulong param_4,long param_5) { uint uVar1; long lVar2; int iVar3; ulong uVar4; int iVar5; if (param_1 == 0) { uVar1 = 0x40; } else { iVar5 = 0x200; if (param_5 != 0) { iVar5 = 1; } *(undefined4 *)(param_1 + 0x50) = 0x1104c201; uVar4 = 0; while (iVar3 = (int)uVar4, uVar4 < param_4 >> 9) { lVar2 = param_1 + 0x400; if ((uVar4 & 1) != 0) { lVar2 = param_1 + 0x600; } *(int *)(param_1 + 0x58) = (int)lVar2; uVar1 = iVar5 * (iVar3 + (int)(param_2 >> 9)); *(uint *)(param_1 + 0x54) = uVar1; if (iVar3 != 0) { lVar2 = param_1 + 0x600; if ((uVar4 & 1) != 0) { lVar2 = param_1 + 0x400; } memcpy((ulong)(iVar3 * 0x200 - 0x200) + param_3,lVar2,0x200); } if ((*(uint *)(param_1 + 0x50) >> 0x1e & 1) != 0) { uVar1 = FUN_fffa2ac8(*(uint *)(param_1 + 0x48),0x11,(ulong)uVar1); return uVar1; } uVar1 = *(uint *)(param_1 + 0x5c) & 0xfcf80000; if (uVar1 != 0) { return uVar1; } uVar4 = (ulong)(iVar3 + 1); } lVar2 = param_1 + 0x400; if (iVar3 != 1) { lVar2 = param_1 + 0x600; } memcpy((ulong)(iVar3 * 0x200 - 0x200) + param_3,lVar2,0x200); uVar1 = 0; } return uVar1; } uint FUN_fffa2d70(long param_1,ulong param_2,uint param_3,ulong param_4,ulong param_5) { uint uVar1; uint uVar2; ulong uVar3; undefined4 auStack_10 [4]; if ((param_5 & 0x1ff) == 0) { uVar3 = param_2 & 0xffffffff; uVar1 = (uint)param_4 & 0x1ff; } else { uVar3 = param_2 >> 9; uVar1 = (uint)(param_4 >> 9) & 0x1ff | 0x200; } uVar1 = FUN_fffa2b94(param_1,uVar1 | 0x9204c800,uVar3,param_3 & 0xfffffffe,(undefined4 *)0x0); uVar2 = FUN_fffa2c2c(param_1,auStack_10); return uVar2 | uVar1; } long sdio_read_blks(long param_1,long param_2,long param_3,long param_4) { ulong uVar1; ulong uVar2; uint uVar3; ulong uVar4; ulong uVar5; ulong uVar6; long lVar7; if (param_1 == 1) { uVar5 = 0x7000; } else { if (param_1 != 4) { puts(s_sd_emmc_boot_device_error_fffacd70); return 0x40; } uVar5 = 0x5000; } uVar6 = (ulong)((uint)(DAT_ff800244 >> 7) | DAT_ff800245 >> 1 & 1); uVar4 = param_4 + 0x1ffU & 0xfffffffffffffe00; lVar7 = param_2 - param_3; while( true ) { uVar1 = lVar7 + param_3; if (param_3 - 0xfffa0000U < 0x48001) { uVar2 = uVar4; if (0x10000 < uVar4) { uVar2 = 0x10000; } uVar3 = FUN_fffa2c44(uVar5 | 0xffe00000,uVar1,param_3,uVar2,uVar6); } else { uVar2 = uVar4; if (0x10000 < uVar4) { uVar2 = 0x10000; } uVar3 = FUN_fffa2d70(uVar5 | 0xffe00000,uVar1,(uint)param_3,uVar2,uVar6); } if (uVar3 != 0) break; if (uVar4 < 0x10001) { return 0; } param_3 = param_3 + 0x10000; uVar4 = uVar4 - 0x10000; } return (long)(int)uVar3; } long sdio_load(long param_1,long param_2,long param_3,long param_4,uint param_5) { uint uVar1; uint uVar2; long lVar3; char *s; if (DAT_fffadc08 == 0xffffffff) { DAT_fffadc08 = (uint)DAT_fffb1c42; } uVar1 = DAT_fffadc08; if ((DAT_fffadc08 == param_5) || (uVar2 = FUN_fffa53c4(param_1,param_5), uVar1 = param_5, uVar2 == 0)) { DAT_fffadc08 = uVar1; lVar3 = sdio_read_blks(param_1,param_2,param_3,param_4); uVar2 = (uint)lVar3; if (uVar2 == 0) goto LAB_fffa2fa0; s = s_sdio_read_data_fail_fffacda3; } else { puts(s_emmc_swith_fffacd8b); put_dec((ulong)param_5); s = s__part_fail_fffacd97; } puts(s); LAB_fffa2fa0: return (long)(int)uVar2; } undefined8 FUN_fffa2fb8(void) { int *piVar1; byte bVar2; byte bVar3; undefined8 uVar4; long lVar5; int iVar6; uint uVar7; uint uVar8; bVar3 = DAT_fffb1c42; bVar2 = DAT_fffb1c40; uVar8 = (uint)DAT_fffb1bd7; uVar4 = 0; if (DAT_fffb1bd7 == 0) { while( true ) { if ((uint)bVar2 <= (uVar8 & 0xff)) break; iVar6 = 0; uVar7 = (uint)bVar2; if (bVar2 != 0) { iVar6 = (int)(uVar8 + bVar3) / (int)uVar7; } lVar5 = sdio_load(DAT_bootdev__ns_fffb1e50,0,(long)&DAT_fffb1c50,0x200, (uVar8 + bVar3) - iVar6 * uVar7); if ((((lVar5 == 0) && (DAT_fffb1e4c != 0)) && (DAT_fffb1c50 == 1)) && ((ulong)(uint)(DAT_fffb1c60 + DAT_fffb1c54) - 0x16000 < 0x6001)) { iVar6 = 0; lVar5 = 0; do { piVar1 = (int *)((long)&DAT_fffb1c50 + lVar5); lVar5 = lVar5 + 4; iVar6 = iVar6 + *piVar1; } while (lVar5 != 0x1fc); if ((iVar6 != 0) && (iVar6 == DAT_fffb1e4c)) { if ((uVar8 & 0xff) < uVar7) { DAT_fffb1bd7 = 1; return 0; } break; } } uVar8 = uVar8 + 1; } uVar4 = 0xffffffff; } return uVar4; } long storage_load(ulong src,ulong dst,ulong len,char *name,uint part) { bool bVar1; uint ret; long fun_ret; undefined8 uVar2; char *s; if ((DAT_bootdev__ns_fffb1e50 < 8) && ((uint)DAT_bootdev__ns_fffb1e50 < 8)) { switch(DAT_bootdev__ns_fffb1e50 & 0xffffffff) { case 0: /* Magical inexistant storage device known as "Rsv" ;) */ s = s_Rsv_fffacdb8; break; case 1: /* eMMC */ src = src + 0x200; s = s_eMMC_fffacdbc; break; case 2: /* NAND */ s = s_SPINAND_fffacdc8 + 3; break; case 3: /* SPI */ s = s_SPI_fffacdc1; break; case 4: /* SD */ src = src + 0x200; s = s_SD_fffacdc5; break; default: /* USB download mode */ s = s_USB_fffacdd0; break; case 6: /* SPINAND */ s = s_SPINAND_fffacdc8; } } else { s = s_UNKNOWN_fffacdd4; } if (name != (char *)0x0) { /* printf("Load %s from %s, src: 0x%x, des: 0x%x, size: 0x%x, part: %d\n", name, s, src, dst, len, part); */ puts(s_Load_fffacddc); puts(name); puts(s__from_fffacde2); puts(s); puts(s___src__0x_fffacde9); put_hex(src,0x20); puts(s___des__0x_fffacdf3); put_hex(dst,0x20); puts(s___size__0x_fffacdfd); put_hex(len,32); puts(s___part__ffface08); put_dec((ulong)part); puts(s__fffadb47 + 1); } if (6 < DAT_bootdev__ns_fffb1e50 - 1) { switchD_fffa324c_caseD_2: ret = 1; goto storage_error; } switch(DAT_bootdev__ns_fffb1e50 - 1 & 0xffffffff) { case 0: /* eMMC goes to SD */ fun_ret = 1; goto sd_boot; case 1: fun_ret = nf_load(2,(uint)src,(uint)dst,len,part); ret = (uint)fun_ret; break; default: goto switchD_fffa324c_caseD_2; case 3: fun_ret = 4; part = 0; sd_boot: /* eMMC and SD */ fun_ret = sdio_load(fun_ret,src,dst,len,part); ret = (uint)fun_ret; break; case 4: case 6: uVar2 = FUN_fffac46c(src,dst,len); ret = (uint)uVar2; break; case 5: bVar1 = FUN_fffa271c((ulong)(*(short *)(*(long *)(DAT_fffb1c30 + 0x10) + 2) != 0),src,dst,len, part); ret = (uint)bVar1; } storage_error: return (long)(int)ret; } ulong load_ddr_params(ulong dst,ulong len) { uint uVar1; ulong tmp_var; undefined8 uVar2; if (DAT_bootdev__ns_fffb1e50 == 2) { /* NAND stuff? */ uVar1 = FUN_fffa4770(dst,len); return (ulong)uVar1; } tmp_var = 0; if (DAT_bootdev__ns_fffb1e50 == 1) { /* eMMC? */ uVar2 = FUN_fffa2fb8(); if ((int)uVar2 == 0) { tmp_var = (ulong)(uint)(DAT_fffb1c60 + DAT_fffb1c54); } else { /* alta -> " NO find ddr boot_info from eMMC" */ puts(s__NO_find_ddr_boot_info_from_eMMC_ffface11); tmp_var = 0x16000; } /* On librecomputer-alta, this outputs: ddr saved addr:00016000 */ print_str_hex(tmp_var,s_ddr_saved_addr__ffface33); /* Offset, in that case, is 0x02c00000 Weird. */ tmp_var = storage_load((tmp_var - 1) * 0x200,dst,len,s_ddr_parameter_ffface43,0); } return tmp_var; } bool FUN_fffa33ac(long param_1,long param_2) { byte bVar1; sdio_read_blks(param_1,0x200,(long)&DAT_fffe7200,0x200); puts(&DAT_ffface51); bVar1 = FUN_fffac5b0(param_2,(long)&DAT_fffe7200,0x200); if (bVar1 == 0) { puts(s__steps_fffad3b7 + 5); } else { puts(&DAT_ffface56); } return bVar1 != 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa3428(long param_1) { byte bVar1; bool bVar2; uint uVar3; undefined4 local_10; if (param_1 == 1) { sdio_read_blks(1,0x200,(long)&DAT_fffe7000,0x200); uVar3 = FUN_fffa52bc(0xffe07000,1,0xffffffb7,2); if (uVar3 == 0) { bVar1 = (byte)_DAT_ffe07044; uVar3 = _DAT_ffe07044 & 0xfffffffc; local_10 = uVar3 | 2; _DAT_ffe07044 = local_10; bVar2 = FUN_fffa33ac(1,(long)&DAT_fffe7000); if (bVar2) { FUN_fffa52bc(0xffe07000,1,0xffffffb7,0); local_10 = CONCAT31((int3)(uVar3 >> 8),(byte)local_10 & 0xfc | bVar1 & 3); _DAT_ffe07044 = local_10; } } } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint get_boot_device(void) { uint uVar1; uVar1 = 7; if ((_AO_UNK_ff80000c >> 0xc & 0xf) != 2) { uVar1 = _AO_SEC_GP_CFG0_ff800240 & 0xf; } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 storage_init(undefined *param_1) { uint uVar1; undefined8 uVar2; if (param_1 == (undefined *)0x0) { uVar2 = 1; } else { if (DAT_fffb1bd4 == '\0') { uVar1 = _DAT_ff800248 >> 0x1a & 7; DAT_fffb1bd5 = (undefined)uVar1; _DAT_ff800248 = _DAT_ff800248 & 0xe1ffffff | uVar1 << 0x19; DAT_fffb1bd4 = '\x01'; } *param_1 = 1; param_1[1] = 1; param_1[2] = 0; param_1[3] = 0; uVar1 = get_boot_device(); DAT_bootdev__ns_fffb1e50 = (ulong)uVar1; if (DAT_bootdev__ns_fffb1e50 == 2) { puts(s_SPI_NAND_init_ffface66 + 4); nand_init(param_1); if ((param_1[3] & 1) == 0) { uVar1 = FUN_fffa174c(); if (uVar1 == 0) { param_1[2] = DAT_fffb1bd5; } } else { param_1[2] = 0; } } else if (DAT_bootdev__ns_fffb1e50 == 6) { puts(s_SPI_NAND_init_ffface66); spi_nand_init((uint)(*(short *)(*(long *)(DAT_fffb1c30 + 0x10) + 2) != 0),param_1); } else if (DAT_bootdev__ns_fffb1e50 == 1) { *param_1 = 3; param_1[1] = 3; uVar1 = FUN_fffa1738(); if (uVar1 == 0) { param_1[2] = DAT_fffb1bd5; } FUN_fffa2a50(param_1[2]); puts(s_eMMC_boot___ffface59); put_dec((ulong)DAT_fffb1bd6); puts(s__fffadb47 + 1); FUN_fffa3428(DAT_bootdev__ns_fffb1e50); } puts(s_storage_init_finish_ffface75); uVar2 = 0; } return uVar2; } ulong FUN_fffa36a8(ulong param_1) { uint uVar1; uint uVar2; uint uVar3; int iVar4; if (DAT_fffb11d4 == 0) { return param_1; } uVar1 = DAT_fffb11d8 >> 1; uVar2 = 0; uVar3 = (uint)param_1; if (uVar1 != 0) { uVar2 = uVar3 / uVar1; } if (DAT_fffb11d4 == 6) { iVar4 = uVar3 - uVar2 * uVar1; param_1 = 0; if (iVar4 == 0) goto LAB_fffa375c; LAB_fffa3704: param_1 = (ulong)(iVar4 * 2 - 1); } else { if (DAT_fffb11d4 < 10) { uVar3 = uVar3 - uVar2 * uVar1; param_1 = (ulong)uVar3; if (uVar3 < 2) goto LAB_fffa375c; if ((uVar3 & 1) != 0) { iVar4 = uVar3 + 0x7fffffff; goto LAB_fffa3704; } iVar4 = uVar3 + 0x7fffffff; } else { if (DAT_fffb11d4 != 0x28) { if (((int)DAT_fffb11d4 < 0) && ((DAT_fffb11d4 & 0xff) == 0x32)) { uVar3 = uVar3 - uVar2 * uVar1; param_1 = (ulong)uVar3; if (3 < uVar3) { if ((uVar3 & 1) == 0) { param_1 = (ulong)(uVar3 * 2 - 4); } else { param_1 = (ulong)(uVar3 * 2 - 5); } } } goto LAB_fffa375c; } iVar4 = uVar3 - uVar2 * uVar1; } param_1 = (ulong)(uint)(iVar4 << 1); } LAB_fffa375c: return (ulong)((int)param_1 + uVar2 * DAT_fffb11d8); } void print_str_hex(ulong hex,char *s) { puts(s); put_hex(hex & 0xffffffff,0x20); puts(s__fffadb47 + 1); return; } /* WARNING: Removing unreachable block (ram,0xfffa3860) */ /* WARNING: Removing unreachable block (ram,0xfffa3864) */ /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined4 FUN_fffa379c(void) { _DAT_ffe07800 = 0x33800; return 0; } void FUN_fffa387c(uint param_1,undefined4 *param_2) { uint uVar1; int iVar2; ulong uVar3; uint uVar4; ulong uVar5; long lVar6; byte local_20 [4]; undefined local_1c; undefined local_1b; undefined local_1a; undefined local_19; undefined local_18; undefined local_17; undefined local_16; undefined local_15; undefined local_14; undefined local_13; undefined local_12; undefined local_11; undefined local_10; undefined local_f; undefined local_e; undefined local_d; undefined local_c; undefined local_b; undefined local_a; undefined local_9; undefined local_8; undefined local_7; undefined local_6; undefined local_5; undefined local_4; undefined local_3; undefined local_2; undefined local_1; local_1a = 0x78; local_19 = 0x78; local_17 = 0x76; local_e = 0x76; local_b = 0x76; local_20[0] = 4; local_20[1] = 4; local_16 = 0x74; local_14 = 8; local_13 = 8; local_d = 0x74; local_9 = 0x70; local_20[2] = 0x7c; local_20[3] = 0x7e; local_1c = 0; local_1b = 0x7c; local_18 = 0x7c; local_15 = 0x72; local_12 = 0; local_11 = 0; local_10 = 0xb; local_f = 0x7e; local_c = 0x10; local_a = 0x72; local_8 = 2; local_7 = 0; local_6 = 0x7e; local_5 = 0x7c; local_4 = 0; local_3 = 0; local_2 = 0; local_1 = 0; uVar1 = param_1; if (param_1 == 7) { param_1 = 0xff; LAB_fffa3990: uVar3 = 0; } else { if (param_1 == 0xff) { uVar1 = 7; goto LAB_fffa3990; } uVar4 = 0; if (7 < param_1) goto LAB_fffa3af8; if (param_1 == 0) { *param_2 = 0x1785c; param_2[1] = 0x178c5; param_2[2] = 0x33800; uVar3 = 3; } else { uVar3 = 0; } } lVar6 = 0; uVar5 = uVar3; do { param_2[uVar5] = 0x17855; iVar2 = (int)uVar5; param_2[iVar2 + 1] = 0x33802; param_2[iVar2 + 2] = (int)lVar6 + 4U | 0x1b800; param_2[iVar2 + 3] = 0x33802; param_2[iVar2 + 4] = local_20[uVar1 * 4 + (int)lVar6] | 0x13800; lVar6 = lVar6 + 1; param_2[iVar2 + 5] = 0x33800; uVar5 = (ulong)(iVar2 + 6); } while (lVar6 != 4); iVar2 = (int)uVar3; param_2[iVar2 + 0x18] = 0x17855; param_2[iVar2 + 0x19] = 0x33802; param_2[iVar2 + 0x1a] = 0x1b80d; param_2[iVar2 + 0x1b] = 0x33802; param_2[iVar2 + 0x1c] = 0x13800; uVar1 = iVar2 + 0x1e; param_2[iVar2 + 0x1d] = 0x33800; if (param_1 == 6) { param_2[uVar1] = 0x178b3; uVar1 = iVar2 + 0x20; param_2[iVar2 + 0x1f] = 0x33800; } else if (param_1 == 0xff) { param_2[uVar1] = 0x178ff; param_2[iVar2 + 0x1f] = 0x33802; param_2[iVar2 + 0x20] = 0x17870; param_2[iVar2 + 0x21] = 0x33802; uVar4 = iVar2 + 0x23; param_2[iVar2 + 0x22] = 0x142c0d; goto LAB_fffa3af8; } param_2[uVar1] = 0x17826; param_2[uVar1 + 1] = 0x1785d; uVar4 = uVar1 + 3; param_2[uVar1 + 2] = 0x33800; LAB_fffa3af8: param_2[uVar4] = 0; return; } void FUN_fffa3b58(uint param_1,undefined4 *param_2) { undefined4 *puVar1; long lVar2; uint uVar3; byte abStack_40 [64]; memcpy((long)abStack_40,(long)&DAT_ffface90,0x3f); if (param_1 == 0x15) { LAB_fffa3cc4: *param_2 = 0x1783b; param_2[1] = 0x178b9; param_2[2] = 0x17854; param_2[3] = 0x1b804; param_2[4] = 0x13800; param_2[5] = 0x17854; param_2[6] = 0x1b805; param_2[7] = 0x13800; param_2[8] = 0x17854; param_2[9] = 0x1b807; param_2[10] = 0x13800; uVar3 = 0x78d6; } else { if (param_1 == 0) { *param_2 = 0x1783b; param_2[1] = 0x178b9; uVar3 = 4; puVar1 = param_2 + 2; do { *puVar1 = 0x17854; puVar1[1] = uVar3 | 0x1b800; uVar3 = uVar3 + 1; puVar1[2] = 0x13800; puVar1 = puVar1 + 3; } while (uVar3 != 0xd); param_2[0x1d] = 0x178b6; lVar2 = 0x1e; goto LAB_fffa3d58; } if (0x14 < param_1) { lVar2 = 0; if (param_1 != 0xff) goto LAB_fffa3d58; goto LAB_fffa3cc4; } *param_2 = 0x1783b; param_2[1] = 0x178b9; param_2[2] = 0x17854; uVar3 = param_1 * 3; param_2[3] = 0x1b804; param_2[4] = abStack_40[uVar3] | 0x13800; param_2[5] = 0x17854; param_2[6] = 0x1b805; param_2[7] = abStack_40[uVar3 + 1] | 0x13800; param_2[8] = 0x17854; param_2[9] = 0x1b807; param_2[10] = abStack_40[uVar3 + 2] | 0x13800; uVar3 = 0x78b6; } param_2[0xb] = uVar3 | 0x10000; lVar2 = 0xc; LAB_fffa3d58: param_2[lVar2] = 0; return; } void FUN_fffa3d68(uint param_1,undefined4 *param_2) { long lVar1; if (param_1 == 0xff) { param_1 = 0; } else { lVar1 = 0; if (7 < param_1) goto LAB_fffa3e10; } *param_2 = 0x178ef; param_2[1] = 0x1b889; param_2[2] = 0x33803; param_2[3] = param_1 | 0x13800; param_2[4] = 0x13800; param_2[5] = 0x13800; param_2[6] = 0x13800; param_2[7] = 0x33802; param_2[8] = 0x17870; param_2[9] = 0x33802; param_2[10] = 0x142c0d; lVar1 = 0xb; LAB_fffa3e10: param_2[lVar1] = 0; return; } void FUN_fffa3e18(uint param_1,undefined4 *param_2) { long lVar1; undefined4 *puVar2; byte local_50 [64]; byte local_10 [16]; local_10[0] = 0xa7; local_10[1] = 0xa4; local_10[2] = 0xa5; local_10[3] = 0xa6; memcpy((long)local_50,(long)&DAT_fffaced0,0x3c); if (param_1 == 0xff) { param_1 = 0; } else { lVar1 = 0; if (0xe < param_1) goto LAB_fffa3f04; } lVar1 = 0; puVar2 = param_2; do { *puVar2 = 0x178a1; puVar2[1] = 0x1b800; puVar2[2] = local_10[lVar1] | 0x1b800; puVar2[3] = 0x33802; puVar2[4] = local_50[param_1 * 4 + (int)lVar1] | 0x13800; lVar1 = lVar1 + 1; puVar2[5] = 0x33808; puVar2 = puVar2 + 6; } while (lVar1 != 4); lVar1 = 0x18; LAB_fffa3f04: param_2[lVar1] = 0; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa3f14(void) { uint *puVar1; uint uVar2; long lVar3; uint local_200 [128]; memset(local_200,0,0x200); if (DAT_fffb1f5e != 0) { if (DAT_fffb1f5c == 0x45) { FUN_fffa3b58(DAT_fffb1720,local_200); } else if (DAT_fffb1f5c < 0x46) { if (DAT_fffb1f5c == 0x2c) { FUN_fffa3d68(DAT_fffb1720,local_200); } } else if (DAT_fffb1f5c == 0x98) { FUN_fffa387c(DAT_fffb1720,local_200); } else if (DAT_fffb1f5c == 0xec) { FUN_fffa3e18(DAT_fffb1720,local_200); } DAT_fffb1720 = DAT_fffb1720 + 1; if (DAT_fffb1f5e <= DAT_fffb1720) { DAT_fffb1720 = 0; } lVar3 = 0; uVar2 = _DAT_ffe07800; do { _DAT_ffe07800 = uVar2; if ((_DAT_ffe07800 >> 0x16 & 0x1f) == 0x1f) { return; } puVar1 = (uint *)((long)local_200 + lVar3); lVar3 = lVar3 + 4; uVar2 = *puVar1; } while (*puVar1 != 0); } return; } void FUN_fffa4030(void) { undefined4 auStack_200 [128]; if ((DAT_fffb1f5e != 0) && (DAT_fffb1f5c == 0x2c)) { FUN_fffa3d68(0,auStack_200); } return; } int FUN_fffa4070(void) { int iVar1; uint uVar2; iVar1 = 0x180; uVar2 = (uint)((ulong)DAT_fffb1f58 & 0x3fffff); if ((uVar2 >> 0xd & 1) == 0) { iVar1 = 0x400; if (((uint)(((ulong)DAT_fffb1f58 & 0x3fffff) >> 0xe) & 7) < 2) { iVar1 = 0x200; } iVar1 = iVar1 * (uVar2 & 0x3f); } return iVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined4 FUN_fffa40a4(undefined8 param_1,undefined4 param_2) { uint uVar1; uint uVar2; uint uVar3; uint uVar4; undefined4 *puVar5; uVar1 = DAT_fffb1f58; _DAT_ffe07804 = 0x80004064; uVar2 = FUN_fffa4070(); uVar1 = uVar1 & 0x3f; uVar3 = 0; if (uVar1 != 0) { uVar3 = uVar2 / uVar1; } do { } while ((_DAT_ffe07800 >> 0x16 & 0x1f) != 0); _DAT_ffe0780c = 0xfffb1e58; _DAT_ffe07800 = 0x33800; _DAT_ffe07808 = param_2; for (uVar2 = 0; uVar2 < uVar1; uVar2 = uVar2 + 1) { uVar4 = 0; do { while ((_DAT_ffe07818 >> 0xb & 1) == 0) { if ((_DAT_ffe07800 >> 0x1b & 1) != 0) { _DAT_ffe07800 = 0x80000000; return 0x81; } } puVar5 = (undefined4 *)(ulong)_DAT_ffe0781c; *puVar5 = _DAT_ffe07820; uVar4 = uVar4 + 1; puVar5[1] = _DAT_ffe07824; } while (uVar4 < (uVar3 >> 3) + 1); } uVar3 = 0; while( true ) { if (uVar1 <= uVar3) { _DAT_ffe07804 = (DAT_fffb1f58 >> 0x1b & 3) << 10 | 0x80000064; return 0; } uVar2 = *(uint *)(ulong)(uVar3 * 8 - 0x4e1a8); if ((uVar2 >> 0x18 & 0x3f) == 0x3f) break; uVar3 = uVar3 + 1; } if (9 < (uVar2 >> 0x10 & 0x3f)) { return 0x82; } return 0x85; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined4 FUN_fffa43c8(undefined8 param_1,undefined8 param_2,long param_3) { uint uVar1; long lVar2; uint uVar3; ulong uVar4; undefined4 local_8; uVar1 = DAT_fffb1f58 & 0x3f; memset((void *)0x1b00200,0,(ulong)uVar1 << 3); lVar2 = (ulong)uVar1 << 3; FUN_fffac958(0x1b00200,lVar2); do { } while ((_DAT_ffe07800 >> 0x16 & 0x1f) != 0); _DAT_ffe07800 = 0x33800; do { FUN_fffac98c(0x1b00200,lVar2); } while (*(long *)((ulong)(uVar1 - 1) * 8 + 0x1b00200) == 0); uVar4 = 0; while( true ) { uVar3 = (uint)uVar4; if (uVar1 <= uVar3) { return 0; } local_8 = *(uint *)(ulong)((uVar3 + 0x360040) * 8); if ((local_8 >> 0x18 & 0x3f) == 0x3f) break; if (param_3 == 0) { if ((uVar3 == 0) && ((local_8 & 0xc000ffff) != 0xc000aa55)) { return 0x83; } } else if (uVar3 < 8) { memcpy(param_3 + (uVar4 & 0x7fffffff) * 2,(long)&local_8,2); } uVar4 = (ulong)(uVar3 + 1); } if ((DAT_fffb1f58 & 0x1000000) != 0) { FUN_fffa379c(); } if (9 < (local_8._2_2_ & 0x3f)) { return 0x82; } return 0x85; } undefined4 FUN_fffa4770(ulong param_1,ulong param_2) { uint uVar1; undefined4 uVar2; undefined auStack_10 [16]; uVar1 = DAT_fffb171c; print_str_hex((ulong)DAT_fffb171c,s_ddr_saved_page__fffacf10); if (((param_2 < 0x801) && ((uint)((DAT_fffb11d8 + 0x80) * 8) <= uVar1)) && (uVar1 <= DAT_fffb11d8 * 0x30 + 0x400U)) { if (param_1 - 0xfffa0000 < 0x48001) { uVar2 = FUN_fffa40a4((ulong)uVar1,(int)param_1); } else { uVar2 = FUN_fffa43c8((ulong)uVar1,param_1 & 0xffffffff,(long)auStack_10); } } else { uVar2 = 0xffffffff; } return uVar2; } int FUN_fffa4824(uint param_1,uint param_2,uint param_3,long param_4,int param_5,int param_6) { uint uVar1; uint uVar2; uint uVar3; int iVar4; int iVar5; ulong uVar6; int iVar7; uint uVar8; ulong uVar9; uVar3 = DAT_fffb1f58 >> 0xd; uVar9 = (ulong)param_2; iVar4 = FUN_fffa4070(); FUN_fffac958(uVar9,(ulong)param_3); do { uVar8 = DAT_fffb11d8; iVar5 = DAT_fffb11d4; iVar7 = (int)uVar9; if (param_3 <= iVar7 - param_2) { return 0; } uVar1 = DAT_fffb11d8 >> 1; while( true ) { uVar6 = FUN_fffa36a8((ulong)param_1); uVar6 = uVar6 & 0xffffffff; if ((uVar3 & 1) != 0) break; uVar2 = 0; if (uVar8 != 0) { uVar2 = (uint)uVar6 / uVar8; } if ((&DAT_fffb1f60)[uVar2] == '\0') { if (param_5 == 0) break; param_5 = param_5 + -1; } uVar2 = uVar8; if (iVar5 != 0) { uVar2 = uVar1; } param_1 = param_1 + uVar2; } uVar8 = 0; while( true ) { if (param_6 == 0) { iVar5 = FUN_fffa43c8(uVar6,uVar9,param_4); } else { iVar5 = FUN_fffa40a4(uVar6,iVar7); } if (iVar5 != 0x82) break; if (DAT_fffb1f5e <= uVar8) { if (uVar8 != 0) { FUN_fffa4030(); } print_str_hex(uVar6,s_read_page_addr__fffacf21); return 0x82; } uVar8 = uVar8 + 1; FUN_fffa3f14(); } uVar9 = (ulong)(uint)(iVar7 + iVar4); if (iVar5 != 0) { return iVar5; } param_1 = param_1 + 1; } while( true ); } short FUN_fffa499c(uint param_1,int param_2) { uint uVar1; uint uVar2; int iVar3; uint uVar4; ulong uVar5; short sVar6; int iVar7; uint uVar8; uVar4 = DAT_fffb11d8; iVar3 = DAT_fffb11d4; iVar7 = 0; if ((DAT_fffb1718 & 1) != 0) { iVar7 = DAT_fffb11d8 * 0x30 + 0x400; } uVar1 = DAT_fffb11d8 >> 1; sVar6 = 0; for (uVar8 = iVar7 + param_2; uVar8 < param_1; uVar8 = uVar8 + uVar2) { uVar5 = FUN_fffa36a8((ulong)uVar8); uVar2 = 0; if (uVar4 != 0) { uVar2 = (uint)uVar5 / uVar4; } if ((&DAT_fffb1f60)[uVar2] != '\0') { sVar6 = sVar6 + 1; } uVar2 = uVar4; if (iVar3 != 0) { uVar2 = uVar1; } } uVar5 = FUN_fffa36a8((ulong)param_1); uVar8 = 0; if (uVar4 != 0) { uVar8 = (uint)uVar5 / uVar4; } if (((&DAT_fffb1f60)[uVar8] != '\0') && (sVar6 != 0)) { sVar6 = sVar6 + -1; } return sVar6; } int FUN_fffa4a7c(uint param_1,uint param_2,undefined8 param_3,undefined8 param_4,int param_5, undefined8 param_6) { uint uVar1; ushort uVar2; int iVar3; undefined auStack_30 [16]; undefined8 local_20; undefined8 local_18; undefined8 local_10; local_20 = param_3; local_18 = param_4; local_10 = param_6; uVar2 = FUN_fffa499c(param_1,param_5); uVar1 = param_1 - (int)local_18; if ((DAT_fffb1718 & 1) == 0) { uVar1 = param_1 + 1; } iVar3 = FUN_fffa4824(uVar1,param_2,(uint)local_20,(long)auStack_30,(uint)uVar2,(int)local_10); return iVar3; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa4ae8(uint *param_1,int param_2) { uint uVar1; uint uVar2; uVar2 = 0xc; if (param_2 == 0) { uVar2 = 1; } *param_1 = uVar2 | (uint)(param_2 != 0) << 6 | 0x90000200; uVar2 = (DAT_fffb1f58._3_1_ >> 3 & 3) << 10; uVar1 = uVar2 | 0x80004064; if ((DAT_fffb1724 & 0x40) == 0) { uVar1 = uVar2 | 0x80000064; } _DAT_ffe07804 = uVar1 | 0x20000; if ((DAT_fffb1724 & 0x60) != 0x20) { _DAT_ffe07804 = uVar1; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ int nand_init(undefined *param_1) { int iVar1; uint uVar2; FUN_fffa59a8(); FUN_fffa4ae8((uint *)0xffe07000,1); iVar1 = FUN_fffa379c(); if (iVar1 != 0) { return iVar1; } DAT_fffb1f58 = DAT_fffe7000 & 0x87ffffff; _DAT_ffe07800 = 0x33800; DAT_fffb1f5c = (ushort)(byte)_DAT_ffe07810; if ((_DAT_ffe07810 & 0xff) == 0x45) { DAT_fffb1f5e = 0x16; goto LAB_fffa4d10; } if ((_DAT_ffe07810 & 0xff) < 0x46) { uVar2 = _DAT_ffe07810 & 0xff; if (((uVar2 == 7) || (uVar2 < 8)) || ((uVar2 == 0x20 || (uVar2 != 0x2c)))) { LAB_fffa4d08: DAT_fffb1f5e = 0; goto LAB_fffa4d10; } } else { uVar2 = _DAT_ffe07810 & 0xff; if (uVar2 != 0x98) { if (((0x98 < uVar2) && (uVar2 != 0xad)) && (DAT_fffb1f5e = 0xf, uVar2 == 0xec)) goto LAB_fffa4d10; goto LAB_fffa4d08; } } DAT_fffb1f5e = 8; LAB_fffa4d10: DAT_fffb11d4 = DAT_fffe705c; DAT_fffb11d8 = DAT_fffe7060; DAT_fffb11e4 = DAT_fffe706c; DAT_fffb11e8 = DAT_fffe7070; DAT_fffb171c = DAT_fffe7084; if (DAT_fffe707c != 0) { DAT_fffb1728 = DAT_fffe7080; DAT_fffb1718 = (uint)DAT_fffe707e; } memset(&DAT_fffb1f60,0,0x100); *param_1 = (char)DAT_fffb11e4; param_1[3] = (char)DAT_fffb1718; return 0; } int FUN_fffa4df4(undefined8 param_1,uint param_2,uint param_3,ulong param_4,int param_5) { uint uVar1; uint uVar2; uint uVar3; int iVar4; uint uVar5; uVar5 = DAT_fffb11e8; iVar4 = DAT_fffb11d4; uVar3 = FUN_fffa4070(); uVar1 = 0; if (uVar3 != 0) { uVar1 = param_2 / uVar3; } if (param_2 == uVar1 * uVar3) { if ((iVar4 - 1U < 9) || (iVar4 == 0x28)) { uVar5 = uVar5 >> 1; } uVar2 = 0; if (uVar3 != 0) { uVar2 = (uVar3 + 0xffff) / uVar3; } iVar4 = FUN_fffa4a7c(uVar1 + DAT_fffb1728 + uVar5 * param_5,param_3,param_4 & 0xffffffff, (ulong)uVar2,uVar5 * param_5,(ulong)(param_3 + 0x60000 < 0x48001)); return iVar4; } return 0x86; } uint FUN_fffa4eb8(int param_1) { uint uVar1; undefined8 local_20; undefined8 uStack_18; ulong local_10; uVar1 = 0x80000001; if (param_1 == 0) { uVar1 = 1; } local_20 = 0; uStack_18 = 0; uVar1 = FUN_fffa2b94(0xffe07000,0x9700c800,(ulong)uVar1,0,(undefined4 *)&local_20); local_10 = (ulong)uVar1; if (uVar1 == 0) { uVar1 = FUN_fffa2b94(0xffe07000,0x990ccc00,local_10,0x1b00000,(undefined4 *)&local_20); } else { puts(s__s_mmc_set_blockcount___fffacf70); put_dec((long)(int)local_10); puts(s__fffadb47 + 1); uVar1 = 1; } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa4f48(ushort param_1) { ushort uVar1; uint uVar2; char *pcVar3; undefined8 local_10; undefined8 uStack_8; local_10 = 0; uStack_8 = 0; uVar2 = FUN_fffa2b94(0xffe07000,0x9700c800,1,0,(undefined4 *)&local_10); if (uVar2 != 0) { puts(s__s_mmc_set_blockcount___fffacf70); LAB_fffa4ff0: put_dec((long)(int)uVar2); puts(s__fffadb47 + 1); return 0xffffffff; } FUN_fffa2b94(0xffe07000,0x9204c800,(ulong)uVar2,0x1b00000,(undefined4 *)&local_10); uVar1 = _DAT_01b001fc; if (((_DAT_01b001fe & 0xff) << 8 | (uint)(_DAT_01b001fe >> 8)) != (uint)param_1) { puts(s_response__fffacf88); uVar2 = (_DAT_01b001fe & 0xff) << 8 | (uint)(_DAT_01b001fe >> 8); goto LAB_fffa4ff0; } uVar2 = (_DAT_01b001fc & 0xff) << 8 | (uint)(_DAT_01b001fc >> 8); if (uVar2 == 0) { return 0; } switch(_DAT_01b001fc >> 8 & 7) { case 1: pcVar3 = s_General_failure_fffacf93; break; case 2: pcVar3 = s_Authentication_failure_fffacfa3; break; case 3: pcVar3 = s_Counter_failure_fffacfba; break; case 4: pcVar3 = s_Address_failure_fffacfca; break; case 5: pcVar3 = s_Write_failure_fffacfda; break; case 6: pcVar3 = s_Read_failure_fffacfe8; break; case 7: pcVar3 = s_Authentication_key_not_yet_progr_fffacff5; break; default: goto switchD_fffa5040_caseD_7; } puts(pcVar3); switchD_fffa5040_caseD_7: if ((short)uVar1 < 0) { pcVar3 = s_Write_counter_expired_fffad01b; } else { pcVar3 = s__fffadb47 + 2; } puts(pcVar3); puts(s__fffadb47 + 1); return uVar2; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa50d4(ushort param_1) { uint uVar1; memset((void *)0x1b00000,0,0x200); _DAT_01b001fe = 0x500; uVar1 = FUN_fffa4eb8(0); if (uVar1 == 0) { uVar1 = FUN_fffa4f48(param_1); return uVar1; } return uVar1; } uint FUN_fffa5128(long param_1,long param_2) { uint uVar1; *(undefined4 *)(param_1 + 0x50) = 0x804c201; *(int *)(param_1 + 0x58) = (int)(param_1 + 0x400); *(undefined4 *)(param_1 + 0x54) = 0; uVar1 = 0; if ((*(uint *)(param_1 + 0x50) >> 0x1e & 1) != 0) { uVar1 = *(uint *)(param_1 + 0x48); } uVar1 = FUN_fffa2ac8(uVar1,8,0); put_hex((long)(int)uVar1,0x20); puts(s__fffadb47 + 1); if (uVar1 == 0) { memcpy(param_2,param_1 + 0x400,0x200); } return uVar1; } uint FUN_fffa51b8(long param_1,uint param_2) { uint uVar1; uVar1 = FUN_fffa2b94(param_1,0x8804c800,0,param_2 & 0xfffffffe,(undefined4 *)0x0); return uVar1; } uint FUN_fffa51d0(long param_1,long param_2) { uint uVar1; if (param_2 - 0xfffa0000U < 0x48001) { uVar1 = FUN_fffa5128(param_1,param_2); return uVar1; } uVar1 = FUN_fffa51b8(param_1,(uint)param_2); return uVar1; } uint FUN_fffa51ec(long param_1,ulong param_2) { uint uVar1; if ((int)(param_2 & 0xffffffff) == 0) { uVar1 = 0x8701c800; } else { uVar1 = 0x8700c800; } uVar1 = FUN_fffa2b94(param_1,uVar1,param_2 & 0xffffffff,0,(undefined4 *)0x0); return uVar1; } uint FUN_fffa5210(void) { uint uVar1; FUN_fffa51ec(0xffe07000,0); FUN_fffa2b94(0xffe07000,0x8a20c800,0x10000,0,&DAT_fffb11f8); uVar1 = FUN_fffa51ec(0xffe07000,0x10000); return uVar1; } uint FUN_fffa5260(long param_1,undefined4 *param_2) { uint uVar1; if (param_1 == 1) { uVar1 = FUN_fffa51d0(0xffe07000,0x1b00000); if (uVar1 == 0) { *param_2 = *(undefined4 *)(&DAT_fffacf40 + (ulong)DAT_01b000c0 * 4); } } else { uVar1 = 0xffffffff; } return uVar1; } uint FUN_fffa52bc(long param_1,undefined8 param_2,uint param_3,uint param_4) { uint uVar1; int iVar2; int iVar3; uint local_20 [4]; undefined4 auStack_10 [4]; uVar1 = FUN_fffa2b94(param_1,0x8600cc00, (ulong)((param_4 & 0xff) << 8 | 0x3000000 | (param_3 & 0xff) << 0x10),0, auStack_10); if (uVar1 == 0) { iVar3 = 5; iVar2 = 1000; do { uVar1 = FUN_fffa2b94(param_1,0x8d00c800,0x10000,0,local_20); if (uVar1 == 0) { if (((local_20[0] >> 8 & 1) != 0) && ((local_20[0] & 0x1e00) != 0xe00)) { if (iVar2 != 0) { if ((local_20[0] & 0x80) == 0) { return 0; } return 0xffffffeb; } break; } if ((local_20[0] & 0xfdf94080) != 0) { puts(s_Status_Error__0x_fffad031); put_hex((ulong)local_20[0],0x20); puts(s__fffadb47 + 1); return 0xffffffee; } } else { iVar3 = iVar3 + -1; if (iVar3 < 0) { return uVar1; } } loop_forever1(); iVar2 = iVar2 + -1; } while (iVar2 != -1); puts(s_Timeout_waiting_card_ready_fffad042); uVar1 = 0xffffffed; } return uVar1; } uint FUN_fffa53c4(long param_1,uint param_2) { uint uVar1; if ((param_1 == 1) && (param_2 < 4)) { uVar1 = FUN_fffa51d0(0xffe07000,(long)&DAT_fffe7000); if (uVar1 == 0) { uVar1 = FUN_fffa52bc(0xffe07000,1,0xffffffb3,param_2 | DAT_fffe70b3 & 0xfffffff8); puts(s_emmc_switch_fffad05e); put_dec((long)(int)param_2); if (uVar1 == 0) { puts(&DAT_fffad06b); FUN_fffa2a50((byte)param_2); } else { puts(s_sdio_read_data_fail_fffacda3 + 0xe); } } } else { uVar1 = 0xffffffff; } return uVar1; } void FUN_fffa5480(long param_1,int param_2,long param_3,uint param_4,long param_5) { byte bVar1; long lVar2; undefined auStack_160 [172]; undefined auStack_b4 [52]; byte local_80 [64]; byte local_40 [64]; FUN_fffac160((long)auStack_160,0x100); lVar2 = 0; while( true ) { if (param_2 <= (int)lVar2) break; bVar1 = *(byte *)(param_1 + lVar2); local_40[lVar2] = bVar1 ^ 0x36; local_80[lVar2] = bVar1 ^ 0x5c; lVar2 = lVar2 + 1; } if (param_2 < 0) { param_2 = 0; } for (; param_2 != 0x40; param_2 = param_2 + 1) { local_40[param_2] = 0x36; local_80[param_2] = 0x5c; } FUN_fffac1a0((long)auStack_160,(long)local_40,0x40); FUN_fffac1a0((long)auStack_160,param_3,param_4); FUN_fffac2b4((long)auStack_160); memcpy(param_5,(long)auStack_b4,0x20); FUN_fffac160((long)auStack_160,0x100); FUN_fffac1a0((long)auStack_160,(long)local_80,0x40); FUN_fffac1a0((long)auStack_160,param_5,0x20); FUN_fffac2b4((long)auStack_160); memcpy(param_5,(long)auStack_b4,0x20); return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa55a4(long param_1,uint *param_2) { uint uVar1; uint uVar2; if (param_1 == 1) { memset((void *)0x1b00000,0,0x200); _DAT_01b001fe = 0x200; uVar2 = FUN_fffa4eb8(0); if ((uVar2 == 0) && (uVar2 = FUN_fffa4f48(0x200), uVar2 == 0)) { uVar1 = (_DAT_01b001f4 & 0xff00ff00) >> 8 | (_DAT_01b001f4 & 0xff00ff) << 8; *param_2 = uVar1 >> 0x10 | uVar1 << 0x10; } } else { uVar2 = 0xffffffff; } return uVar2; } uint FUN_fffa5618(long param_1) { uint uVar1; uint uVar2; uint local_10 [4]; local_10[0] = 0; uVar1 = FUN_fffa2a44(); FUN_fffa53c4(param_1,3); uVar2 = FUN_fffa55a4(param_1,local_10); if (uVar2 == 0) { puts(s_BL2__rpmb_counter__0x_fffad08a); put_hex((ulong)local_10[0],0x20); puts(s__fffadb47 + 1); uVar2 = 1; } else { puts(s_get_rpmb_counter_error_0x_fffad070); put_hex((long)(int)uVar2,0x20); puts(s__fffadb47 + 1); } FUN_fffa53c4(param_1,uVar1 & 0xff); return uVar2; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa56c4(long param_1,long param_2) { uint uVar1; if (param_1 == 1) { memset((void *)0x1b00000,0,0x200); _DAT_01b001fe = 0x100; memcpy(0x1b000c4,param_2,0x20); uVar1 = FUN_fffa4eb8(1); if (uVar1 == 0) { uVar1 = FUN_fffa50d4(0x100); return uVar1; } } else { uVar1 = 0xffffffff; } return uVar1; } uint FUN_fffa5748(long param_1) { uint uVar1; uint local_10 [4]; uVar1 = FUN_fffa5260(param_1,local_10); if (local_10[0] < 0x10429) { uVar1 = 0xfffffffe; } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa5778(void) { uint uVar1; uint uVar2; uint uVar3; uint uVar4; ulong uVar5; long lVar6; undefined auStack_20 [16]; undefined auStack_10 [16]; uVar2 = get_boot_device(); if ((uVar2 == 1) && (uVar2 = FUN_fffa5748(1), uVar2 == 0)) { uVar2 = FUN_fffa5618(1); if (uVar2 != 1) { _DAT_ff80025c = _DAT_ff80025c & 0xffbfffff; } else { _DAT_ff80025c = _DAT_ff80025c | 0x400000; } uVar1 = _AO_UNK_ff80000c & 0x7f; if ((uVar1 == 9) || (uVar3 = FUN_fffa1724(), uVar3 != 0)) { uVar3 = 0; if (uVar2 != 1) { uVar2 = FUN_fffa2a44(); uVar3 = FUN_fffac54c(0); uVar5 = 0xd0; if ((uVar3 & 0xfffffffd) != 0x25) { uVar4 = 0x40; if (uVar3 < 0x28) { uVar4 = 0x70; } uVar5 = (ulong)uVar4; } FUN_fffa1678(uVar5,0x10,(long)&DAT_fffb1228); FUN_fffa5210(); lVar6 = 0; DAT_fffb1200 = DAT_fffb1200 & 0xff00ffff; do { uVar3 = (*(uint *)((long)&DAT_fffb11f8 + lVar6) & 0xff00ff00) >> 8 | (*(uint *)((long)&DAT_fffb11f8 + lVar6) & 0xff00ff) << 8; *(uint *)((long)&DAT_fffb11f8 + lVar6) = uVar3 >> 0x10 | uVar3 << 0x10; lVar6 = lVar6 + 4; } while (lVar6 != 0x10); memcpy((long)auStack_20,(long)&DAT_fffb11f8,0x10); memcpy((long)auStack_10,(long)s_rpmbhmac_fffacf60,9); FUN_fffa5480((long)&DAT_fffb1228,0x10,(long)auStack_20,0x19,(long)&DAT_fffb1208); FUN_fffa53c4(1,3); uVar3 = FUN_fffa56c4(1,(long)&DAT_fffb1208); puts(s_BL2__rpmb_set_key__0x_fffad0d5); put_hex((long)(int)uVar3,0x20); puts(s__fffadb47 + 1); memset(&DAT_fffb1208,0,0x20); memset(&DAT_fffb1228,0,0x10); FUN_fffa53c4(1,uVar2 & 0xff); if (uVar3 == 0) { _DAT_ff80025c = _DAT_ff80025c | 0x400000; } } if (uVar1 == 9) { _AO_UNK_ff80000c = _AO_UNK_ff80000c & 0xffffff80; } } else { uVar3 = 0; } } else { uVar3 = 0xffffffff; } return uVar3; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa59a8(void) { uint uVar1; uVar1 = FUN_fffac56c(); _DAT_ff634520 = 0x1fff; _DAT_ff6344e8 = 0x1f00; _DAT_ff6346c0 = 0x11111111; uVar1 = uVar1 >> 8 & 0xff; _DAT_ff6346c4 = 0x22122222; if (uVar1 == 10) { _DAT_ff634740 = 0x55555555; } else if (uVar1 == 0xb) { _DAT_ff634740 = 0xffffffff; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa5a34(void) { _DAT_ff6346c0 = 0x33333000; _DAT_ff6346c4 = 0x3000000; return; } /* WARNING: Removing unreachable block (ram,0xfffa5a80) */ void loop_forever1(void) { /* WARNING: Do nothing block with infinite loop */ do { } while( true ); } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void pinmux_init(void) { uint uVar1; uint uVar2; uint uVar3; uint uVar4; uint uVar5; uint uVar6; char *s; uVar5 = _DAT_ff6346e4; uVar4 = FUN_fffac56c(); if (uVar4 >> 0x18 == 0x29) { _DAT_ff800020 = _DAT_ff800020 | 0x3f; } _DAT_ff634740 = 0xffffffff; _DAT_ff634744 = 0xffff; uVar4 = _DAT_ff63444c | 0x40; uVar1 = _DAT_ff6344ec | 0x40; uVar2 = _DAT_ff634524 | 0x40; uVar3 = _DAT_ff6346e4 & 0xf0ffffff; if ((_DAT_ff634454 >> 6 & 1) == 0) { _DAT_ff63444c = _DAT_ff63444c | 0x48; _DAT_ff634524 = _DAT_ff634524 | 0x48; _DAT_ff6344ec = _DAT_ff6344ec | 0x48; if ((_DAT_ff634454 >> 3 & 1) == 0) { _DAT_ff800014 = _DAT_ff800014 & 0xffffff00; _DAT_ff6346e4 = _DAT_ff6346e4 & 0xf0ff00ff | 0x2200; uVar5 = get_boot_device(); if (uVar5 == 4) { _DAT_ff6346e4 = _DAT_ff6346e4 & 0xff00fff0 | 0x110001; } s = s__sdio_debug_board_detected_fffad104; } else { _DAT_ff6346e4 = _DAT_ff6346e4 & 0xf0ff0fff; uVar6 = get_boot_device(); uVar4 = _DAT_ff63444c; uVar1 = _DAT_ff6344ec; uVar2 = _DAT_ff634524; uVar3 = _DAT_ff6346e4; if (uVar6 != 4) goto LAB_fffa5a84; s = s__no_sdio_debug_board_detected_fffad120; _DAT_ff6346e4 = uVar5; } puts(s); uVar4 = _DAT_ff63444c; uVar1 = _DAT_ff6344ec; uVar2 = _DAT_ff634524; uVar3 = _DAT_ff6346e4; } LAB_fffa5a84: _DAT_ff6346e4 = uVar3; _DAT_ff634524 = uVar2; _DAT_ff6344ec = uVar1; _DAT_ff63444c = uVar4; serial_print(s__L0__fffad0eb,_EFUSE_LIC0_ff630030,0,s__fffadb47 + 1); serial_print(s_L1__fffad0f0,_DAT_ff630034,0,s__fffadb47 + 1); serial_print(s_L2__fffad0f4,_DAT_ff630038,0,s__fffadb47 + 1); serial_print(s_L3__fffad0f8,_DAT_ff63003c,0,s__fffadb47 + 1); serial_print(s_B2__fffad0fc,_DAT_ff800224,0,s__fffadb47 + 1); serial_print(s_B1__fffad100,_DAT_ff800228,0,s__fffadb47 + 1); return; } void Empty_fffa5d7c(void) { return; } void FUN_fffa5d80(void) { acs_set_t *acs_l; DAT_fffb1c30 = &DAT_fffb1be0; acs_l = (acs_set_t *)(ulong)acs_; DAT_fffb1be0 = acs_l->ddr_set_addr; DAT_fffb1c00 = (uint)acs_l->ddr_set_length; DAT_fffb1c04 = DAT_fffb1c00 / 0x498; DAT_fffb1c08 = (uint)acs_l->ddr_set_version; DAT_fffb1be8 = acs_l->ddr_reg_addr; DAT_fffb1c0c = (uint)acs_l->ddr_reg_length; DAT_fffb1c10 = (uint)(acs_l->ddr_reg_length >> 4); DAT_fffb1c14 = (uint)acs_l->ddr_reg_version; DAT_fffb1bf0 = acs_l->pll_set_addr; DAT_fffb1c18 = (uint)acs_l->pll_set_length; DAT_fffb1c1c = (uint)(acs_l->pll_set_length >> 7); DAT_fffb1c20 = (uint)acs_l->pll_set_version; DAT_fffb1bf8 = acs_l->bl2_regs_addr; DAT_fffb1c24 = (uint)acs_l->bl2_regs_length; DAT_fffb1c28 = (uint)(acs_l->bl2_regs_length >> 4); DAT_fffb1c2c = (uint)acs_l->bl2_regs_version; puts(s__fffadb47 + 1); return; } void stage_init__ns(uint stage_init) { int iVar1; uint *puVar2; int iVar3; iVar1 = *(int *)(DAT_fffb1c30 + 0x48); puVar2 = *(uint **)(DAT_fffb1c30 + 0x18); loop_forever1(); puts(s_bl2_stage_init_fffad160); /* "0x" */ puts(s_SNIP_Vr__bl2_0x_fffacc70 + 0xc); put_hex((ulong)stage_init,8); /* "\n" */ puts(s__fffadb47 + 1); for (iVar3 = 0; iVar3 != iVar1; iVar3 = iVar3 + 1) { if (*(byte *)((long)puVar2 + 0xe) == stage_init) { *(uint *)(ulong)*puVar2 = *(uint *)(ulong)*puVar2 & (puVar2[2] ^ 0xffffffff) | puVar2[1]; loop_forever1(); } puVar2 = puVar2 + 4; } return; } void FUN_fffa5ee4(void) { int iVar1; uint pwm_id; uint *puVar2_pwm; uint hw_id; int i; puVar2_pwm = *(uint **)(DAT_fffb1c30 + 0x18); iVar1 = *(int *)(DAT_fffb1c30 + 0x48); hw_id = 0; stage_init__ns(0x81); /* I guess just prints some info? */ i = 0; do { if (i == iVar1) { pwm_id = 0xffffffff; LAB_fffa5f78: puts(s_hw_id__0x_fffad146); put_hex((ulong)hw_id,0x10); puts(s____pwm_id_0x_fffad150); put_hex((ulong)pwm_id,8); puts(s__fffadb47 + 1); stage_init__ns(pwm_id | 0xc0); return; } if (*(char *)((long)puVar2_pwm + 0xe) == -0x7e) { hw_id = *(uint *)(ulong)*puVar2_pwm >> (ulong)(puVar2_pwm[1] & 0x1f) & 1 | hw_id << 1; loop_forever1(); } if ((*(char *)((long)puVar2_pwm + 0xe) == -0x7d) && (hw_id == *puVar2_pwm)) { pwm_id = puVar2_pwm[1]; goto LAB_fffa5f78; } i = i + 1; puVar2_pwm = puVar2_pwm + 4; } while( true ); } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa5fc8(void) { if ((DAT_fffb1240 != 0) || (DAT_fffb1248 != 0)) { _DAT_ff639004 = ((int)DAT_fffb1240 + (int)DAT_fffb1248) - 1U & 0xffff0000 | (uint)((ulong)DAT_fffb1240 >> 0x10) & 0xffff; _DAT_ff639040 = 0x1f00001; _DAT_ff639140 = 0x1f00001; _DAT_ff639000 = _DAT_ff639000 | 0x10001; } if ((DAT_fffb1268 != 0) || (DAT_fffb1270 != 0)) { _DAT_ff639008 = ((int)DAT_fffb1268 + (int)DAT_fffb1270) - 1U & 0xffff0000 | (uint)((ulong)DAT_fffb1268 >> 0x10) & 0xffff; _DAT_ff639050 = 0x1f00001; _DAT_ff639150 = 0x1f00001; _DAT_ff639000 = _DAT_ff639000 | 0x20002; } _DAT_ff639130 = 0x1ffffff; _DAT_ff639230 = 0x1ffffff; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void thunk_FUN_fffa5fc8(void) { if ((DAT_fffb1240 != 0) || (DAT_fffb1248 != 0)) { _DAT_ff639004 = ((int)DAT_fffb1240 + (int)DAT_fffb1248) - 1U & 0xffff0000 | (uint)((ulong)DAT_fffb1240 >> 0x10) & 0xffff; _DAT_ff639040 = 0x1f00001; _DAT_ff639140 = 0x1f00001; _DAT_ff639000 = _DAT_ff639000 | 0x10001; } if ((DAT_fffb1268 != 0) || (DAT_fffb1270 != 0)) { _DAT_ff639008 = ((int)DAT_fffb1268 + (int)DAT_fffb1270) - 1U & 0xffff0000 | (uint)((ulong)DAT_fffb1268 >> 0x10) & 0xffff; _DAT_ff639050 = 0x1f00001; _DAT_ff639150 = 0x1f00001; _DAT_ff639000 = _DAT_ff639000 | 0x20002; } _DAT_ff639130 = 0x1ffffff; _DAT_ff639230 = 0x1ffffff; return; } void FUN_fffa60f8(undefined8 *param_1,ulong param_2) { undefined8 uVar1; uVar1 = param_1[1]; (&DAT_fffb1240)[(param_2 & 0xffffffff) * 5] = *param_1; (&DAT_fffb1248)[(param_2 & 0xffffffff) * 5] = uVar1; FUN_fffa5fc8(); return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa6124(void) { if ((DAT_fffb1240 != 0) || (DAT_fffb1248 != 0)) { _DAT_ff639040 = 0x400001; _DAT_ff639140 = 0x400001; } if ((DAT_fffb1268 != 0) || (DAT_fffb1270 != 0)) { _DAT_ff639050 = 0x800001; _DAT_ff639150 = 0x800001; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ long FUN_fffa61ac(long param_1,long param_2,uint param_3) { long *plVar1; long local_40; long local_38; uint local_30; undefined4 local_2c; long local_28; long local_20; uint local_18; uint local_10; undefined4 local_c; undefined4 local_8; memset(&local_40,0,0x30); local_40 = param_2; local_38 = param_1; if (param_3 < 0x201) { local_30 = param_3; } else { local_30 = param_3 >> 9; local_2c = 1; local_28 = (int)(param_3 & 0xfffffe00) + param_2; local_20 = (int)(param_3 & 0xfffffe00) + param_1; local_18 = param_3 & 0x1ff; } for (plVar1 = &local_40; plVar1 != (long *)&local_10; plVar1 = plVar1 + 3) { local_c = (int)*plVar1; local_8 = (int)plVar1[1]; local_10 = *(uint *)(plVar1 + 2) & 0x1ffff; local_10 = CONCAT13((char)((*(uint *)((long)plVar1 + 0x14) & 1) << 5), (int3)(*(uint *)(plVar1 + 2) & 0x1ffff)) | 0x80040000; _DAT_ff63e028 = 0xf; _DAT_ff63e008 = (uint)&local_10 | 2; } return param_1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa62bc(void) { undefined local_30 [48]; _DAT_ff63e028 = 0xf; _DAT_ff63e008 = (uint)local_30 | 2; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa63c8_dos(void) { _DOS_SECURE_CTL_INDEX = 0; _DOS_SECURE_CTL_DATA = 0x3f82; return; } char FUN_fffa6424(long param_1) { long lVar1; char cVar2; FUN_fffa1678(4,0xc,(long)&DAT_fffb2060); lVar1 = 0; cVar2 = '\0'; do { if ((&DAT_fffb2060)[lVar1] != *(char *)(param_1 + lVar1)) { cVar2 = cVar2 + '\x01'; } lVar1 = lVar1 + 1; } while (lVar1 != 0xc); return cVar2; } void FUN_fffa6488(astruct *param_1) { undefined4 uVar1; long lVar2; undefined8 uVar3; param_1->field594_0x268 = 0xff6345c0; lVar2 = DAT_fffb1c30; uVar3 = *(undefined8 *)(DAT_fffb1c30 + 0x10); param_1->field170_0xb8 = DAT_fffb1c30; uVar1 = *(undefined4 *)(lVar2 + 0x24); param_1->field169_0xb0 = uVar3; param_1->field208_0xe6 = (char)uVar1; param_1->field168_0xa8 = &DAT_fffadcb8; param_1->field207_0xe4 = 0x10; memset(¶m_1->field_0xf0,0xffffffff,0xa0); return; } void FUN_fffa64d4(long param_1) { *(undefined **)(param_1 + 0x48) = &DAT_fffc8000; *(undefined **)(param_1 + 0x50) = &DAT_fffc8000; *(undefined **)(param_1 + 0x58) = &DAT_fffc8000; *(undefined **)(param_1 + 0x60) = &DAT_fffc8000; *(undefined **)(param_1 + 0x68) = &DAT_fffc8000; *(undefined **)(param_1 + 0x70) = &DAT_fffc8000; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa6520(ddr_set_t *param_1) { int iVar1; uint uVar2; undefined4 uVar3; byte bVar4; undefined uVar5; uint uVar6; uint *puVar7; long ddr_clk__ns; uint *puVar8; uint uVar9; uint uVar10; uint i; ddr_clk__ns = *(long *)(param_1->dfi_pinmux + 0x10); param_1->soc_bit_vref[0x18] = '\x01'; param_1->retraining[4] = '\x02'; *(undefined *)((long)param_1->write_dq_bit_delay + 0x4d) = 0; bVar4 = *(byte *)(ddr_clk__ns + 7); if (((bVar4 & 0xc0) != 0) && ((byte)(*(char *)(ddr_clk__ns + 4) - 1U) < 0xfe)) { *(byte *)(param_1->write_dq_bit_delay + 0x2e) = bVar4 & 0x3f; param_1->retraining[5] = '\x01'; } if ((_AO_UNK_ff80000c & 15) != 0) { uVar10 = *(uint *)(param_1->retraining + 8); param_1[1].magic = *(uint *)(ulong)(uVar10 + 0x20); puVar7 = (uint *)(ulong)uVar10; DAT_fffb172c = *puVar7 & 0xffff; if ((*puVar7 >> 0x14 == 0xf13) || (*puVar7 >> 0x14 == 0xf12)) { i = *(uint *)(ulong)(uVar10 + 4); uVar10 = *(uint *)(ulong)(uVar10 + 8); serial_print(s_d2pll_clk__fffad170,i,1,s__fffadb47 + 1); param_1->retraining[0xc] = '\x01'; } else { uVar10 = 0; i = 0; } ddr_clk__ns = *(long *)(param_1->dfi_pinmux + 0x10); if ((*(byte *)(ddr_clk__ns + 0x78) >> 2 & 1) != 0) { *(undefined *)(param_1->write_dq_bit_delay + 0x30) = 1; } if (uVar10 != 0) { if ((uVar10 & 0xfffffffd) == 1) { *(undefined *)(param_1->write_dq_bit_delay + 0x30) = 1; *(undefined4 *)(param_1->dram_bit_vref + 0x1c) = *(undefined4 *)(ulong)(*(int *)(param_1->retraining + 8) + 0xc); } else if (uVar10 == 4) { uVar2 = *(uint *)(ulong)(*(int *)(param_1->retraining + 8) + 0xc); uVar6 = uVar2 & 0xff; *(char *)(param_1->read_dqs_gate_delay + 5) = (char)uVar6; if (uVar6 != 0) { *(char *)(ddr_clk__ns + 0x11) = (char)uVar2; } } if (uVar10 - 2 < 2) { iVar1 = *(int *)(param_1->retraining + 8); puVar7 = (uint *)(ulong)(iVar1 + 0x10); uVar9 = *(uint *)(ulong)(iVar1 + 0xc) & 0xff; *(char *)((long)param_1->write_dq_bit_delay + 0x61) = (char)uVar9; uVar2 = *puVar7; *(char *)(param_1->write_dq_bit_delay + 0x31) = (char)(uVar2 >> 0x18); *(uint *)(param_1->write_dq_bit_delay + 0x32) = *puVar7 >> 0x10 & 0xff; uVar6 = *puVar7; puVar8 = (uint *)(ulong)(iVar1 + 0x14); *(uint *)(param_1->write_dq_bit_delay + 0x34) = uVar6 & 0xffff; puVar7 = (uint *)(ulong)(iVar1 + 0x18); *(char *)(param_1->write_dq_bit_delay + 0x36) = (char)(*puVar8 >> 0x18); *(uint *)(param_1->write_dq_bit_delay + 0x38) = *puVar8 >> 0x10 & 0xff; *(uint *)(param_1->write_dq_bit_delay + 0x3a) = *puVar8 & 0xffff; *(char *)(param_1->write_dq_bit_delay + 0x3c) = (char)(*puVar7 >> 0x18); *(uint *)(param_1->write_dq_bit_delay + 0x3e) = *puVar7 >> 0x10 & 0xff; *(uint *)(param_1->write_dq_bit_delay + 0x40) = *puVar7 & 0xffff; if (uVar9 == 0) { if (uVar2 >> 0x18 == 0x11) { FUN_fffa8334(uVar6 & 0xffff); } if (*(char *)(param_1->write_dq_bit_delay + 0x36) == '\x11') { FUN_fffa8334(*(uint *)(param_1->write_dq_bit_delay + 0x3a)); } if (*(char *)(param_1->write_dq_bit_delay + 0x3c) == '\x11') { FUN_fffa8334(*(uint *)(param_1->write_dq_bit_delay + 0x40)); } } } if (uVar10 - 0x31 < 2) { if (uVar10 == 0x32) { uVar5 = 2; } else { uVar5 = 1; } *(undefined *)(param_1->write_dq_bit_delay + 0x42) = uVar5; iVar1 = *(int *)(param_1->retraining + 8); *(uint *)(param_1->write_dq_bit_delay + 0x44) = *(uint *)(ulong)(iVar1 + 0xc) & 0xffff; *(uint *)(param_1->write_dq_bit_delay + 0x46) = *(uint *)(ulong)(iVar1 + 0x10) & 0xffff; *(uint *)param_1->read_dqs_gate_delay = *(uint *)(ulong)(iVar1 + 0x14) & 0xffff; *(uint *)(param_1->read_dqs_gate_delay + 2) = *(uint *)(ulong)(iVar1 + 0x18) & 0xffff; param_1->retraining[6] = (uchar)*(undefined4 *)(ulong)(iVar1 + 0x1c); *(undefined4 *)(param_1->dram_bit_vref + 0x1c) = *(undefined4 *)(ulong)(iVar1 + 0x20); } if (uVar10 - 0x11 < 2) { iVar1 = *(int *)(param_1->retraining + 8); *(char *)(param_1->write_dq_bit_delay + 0x2e) = (char)*(undefined4 *)(ulong)(iVar1 + 0xc); *(undefined4 *)(param_1->write_dq_bit_delay + 0x28) = *(undefined4 *)(ulong)(iVar1 + 0x10); *(undefined4 *)(param_1->write_dq_bit_delay + 0x2a) = *(undefined4 *)(ulong)(iVar1 + 0x14); puVar7 = (uint *)(ulong)(iVar1 + 0x18); *(uint *)(param_1->write_dq_bit_delay + 0x2c) = *puVar7 & 0xff; *(char *)((long)param_1->write_dq_bit_delay + 0x5d) = (char)*(undefined4 *)(ulong)(iVar1 + 0x1c); param_1->write_dq_bit_delay[0x2f] = (ushort)*(undefined4 *)(ulong)(iVar1 + 0x20); *(undefined4 *)(param_1->soc_bit_vref + 0x1c) = *(undefined4 *)(ulong)(iVar1 + 0x24); param_1->soc_bit_vref[0x19] = (byte)(*puVar7 >> 0x1c) & 1; uVar2 = *puVar7 >> 0x18 & 1; param_1->soc_bit_vref[0x1a] = (uchar)uVar2; param_1->dram_bit_vref[0x18] = (byte)(*puVar7 >> 0x14) & 1; param_1->dram_bit_vref[0x19] = (byte)(*puVar7 >> 0x15) & 1; if (uVar2 != 0) { param_1->soc_bit_vref[0x18] = '\0'; } param_1->retraining[3] = (byte)(*puVar7 >> 0x19) & 1; param_1->dram_bit_vref[0x1a] = (byte)(*puVar7 >> 0x16) & 1; param_1->retraining[5] = '\x01'; } } if (uVar10 - 0x41 < 4) { iVar1 = *(int *)(param_1->retraining + 8); *(char *)(param_1->read_dqs_gate_delay + 6) = (char)*(undefined4 *)(ulong)(iVar1 + 0xc); puVar7 = (uint *)(ulong)(iVar1 + 0x10); *(char *)((long)param_1->read_dqs_gate_delay + 0xd) = (char)*puVar7; *(uint *)(param_1->read_dqs_gate_delay + 8) = *puVar7 >> 8 & 0xff; *(char *)(param_1->read_dqs_gate_delay + 0xf) = (char)(*puVar7 >> 0x10); *(char *)((long)param_1->read_dqs_gate_delay + 0x1f) = (char)(*puVar7 >> 0x18); puVar7 = (uint *)(ulong)(iVar1 + 0x14); *(char *)(param_1->read_dqs_gate_delay + 10) = (char)*puVar7; *(uint *)(param_1->read_dqs_gate_delay + 0xc) = *puVar7 >> 8 & 0xff; param_1->soc_bit_vref[0] = (uchar)(*puVar7 >> 0x10); param_1->soc_bit_vref[1] = (uchar)(*puVar7 >> 0x18); *(char *)(param_1->read_dqs_gate_delay + 0xe) = (char)*(undefined4 *)(ulong)(iVar1 + 0x18); *(char *)((long)param_1->read_dqs_gate_delay + 0x1d) = (char)*(undefined4 *)(ulong)(iVar1 + 0x1c); *(undefined4 *)(param_1->soc_bit_vref + 4) = *(undefined4 *)(ulong)(iVar1 + 0x20); uVar3 = *(undefined4 *)(ulong)(iVar1 + 0x24); param_1->soc_bit_vref[0x18] = '\0'; param_1->soc_bit_vref[8] = (uchar)uVar3; param_1->soc_bit_vref[0x1a] = '\x01'; } if (*(char *)(*(long *)(param_1->dfi_pinmux + 0x10) + 0x78) < '\0') { param_1->soc_bit_vref[9] = '\x01'; } if (uVar10 == 0x51) { param_1->soc_bit_vref[9] = '\x03'; *(undefined4 *)(param_1->soc_bit_vref + 0xc) = *(undefined4 *)(ulong)(*(int *)(param_1->retraining + 8) + 0xc); } param_1->dram_bit_vref[0x14] = '\0'; if ((uVar10 == 0x42) || (uVar10 == 0x12)) { *(uint *)(ulong)*(uint *)(param_1->retraining + 8) = *(uint *)(ulong)*(uint *)(param_1->retraining + 8) & 0xffff | 0x20180000; *(undefined4 *)(ulong)(*(int *)(param_1->retraining + 8) + 4) = 1; } FUN_fffa7d38((long)param_1); if (i != 0) { *(short *)(*(long *)(param_1->dfi_pinmux + 0x10) + (ulong)*(byte *)((long)param_1->write_dq_bit_delay + 0x4d) * 2 + 0x38) = (short)i; } } return; } void FUN_fffa69d8(long param_1) { if (*(uint *)(ulong)*(uint *)(param_1 + 0x268) >> 0x14 == 0xf13) { *(uint *)(ulong)*(uint *)(param_1 + 0x268) = 0; *(undefined4 *)(ulong)(*(int *)(param_1 + 0x268) + 4) = 0; *(undefined4 *)(ulong)(*(int *)(param_1 + 0x268) + 8) = 0; } puts(s_boot_times_fffad17c); put_dec((ulong)DAT_fffb172c); DAT_fffb172c = DAT_fffb172c + 1; *(uint *)(ulong)*(uint *)(param_1 + 0x268) = *(uint *)(ulong)*(uint *)(param_1 + 0x268) & 0xffff0000 | DAT_fffb172c; return; } /* WARNING: Unknown calling convention -- yet parameter storage is locked */ undefined8 FUN_fffa6a60(ddr_set_t **param_1) { undefined *puVar1; char *s; ddr_set_t *pdVar2; uchar ddr_type; puVar1 = PTR_DAT_fffadcb0; ddr_type = param_1[20]->dram_rank_config; *(uchar *)(param_1 + 0x37) = ddr_type; pdVar2 = *(ddr_set_t **)(puVar1 + 0x28); param_1[3] = (ddr_set_t *)0x0; param_1[5] = pdVar2; param_1[6] = *(ddr_set_t **)(puVar1 + 0x30); param_1[7] = (ddr_set_t *)FUN_fffa81b8; *param_1 = *(ddr_set_t **)(puVar1 + 0x38); if (ddr_type == 0) { /* #define CONFIG_DDR_TYPE_DDR3 0 */ puts(s_LPDDR3_probe_fffad188 + 2); pdVar2 = *(ddr_set_t **)PTR_DAT_fffadcb0; *(undefined *)(param_1 + 0x1d) = 0; param_1[3] = pdVar2; *(undefined *)((long)param_1 + 0xea) = 0; param_1[0x13] = param_1[0xf]; param_1[0x34] = (ddr_set_t *)&DAT_fffadc50; param_1[0x35] = (ddr_set_t *)&DAT_fffadc70; param_1[0x32] = (ddr_set_t *)(param_1 + 0x22); param_1[0x33] = (ddr_set_t *)0x0; } else { if (ddr_type == 1) { /* #define CONFIG_DDR_TYPE_DDR4 1 */ puts(s_LPDDR4_probe_fffad196 + 2); pdVar2 = *(ddr_set_t **)(PTR_DAT_fffadcb0 + 8); *(undefined *)(param_1 + 0x1d) = 1; param_1[3] = pdVar2; *(undefined *)((long)param_1 + 0xea) = 0; param_1[0x13] = param_1[0x10]; param_1[0x34] = (ddr_set_t *)&DAT_fffadc30; param_1[0x35] = (ddr_set_t *)&DAT_fffade80; param_1[0x32] = (ddr_set_t *)(param_1 + 0x24); pdVar2 = (ddr_set_t *)(param_1 + 0x26); } else { if (ddr_type == 3) { /* #define CONFIG_DDR_TYPE_LPDDR3 3 */ pdVar2 = *(ddr_set_t **)(puVar1 + 0x10); *(undefined *)(param_1 + 0x1d) = 0; param_1[3] = pdVar2; *(undefined *)((long)param_1 + 0xea) = 0; param_1[0x13] = param_1[0x11]; param_1[0x34] = (ddr_set_t *)&DAT_fffadc90; param_1[0x36] = (ddr_set_t *)&DAT_fffadc10; param_1[0x32] = (ddr_set_t *)(param_1 + 0x28); param_1[0x33] = (ddr_set_t *)0x0; puts(s_LPDDR3_probe_fffad188); goto LAB_fffa6c20; } if (ddr_type != 2) { s = s_Unsupport_ddr_type_fffad1a4; goto fail; } /* #define CONFIG_DDR_TYPE_LPDDR4 2 */ puts(s_LPDDR4_probe_fffad196); pdVar2 = *(ddr_set_t **)(PTR_DAT_fffadcb0 + 0x18); *(undefined *)((long)param_1 + 0xea) = 0; param_1[3] = pdVar2; param_1[0x13] = param_1[0x12]; param_1[0x34] = (ddr_set_t *)&DAT_fffade40; param_1[0x36] = (ddr_set_t *)&DAT_fffade60; *(undefined *)(param_1 + 0x1d) = 1; param_1[0x32] = (ddr_set_t *)(param_1 + 0x2a); pdVar2 = (ddr_set_t *)(param_1 + 0x2c); } param_1[0x33] = pdVar2; } LAB_fffa6c20: if (*(int *)param_1[0x32]->fast_boot != -1) { if (*(char *)((long)¶m_1[0x14]->imem_load_addr + 1) != -1) { return 0; } *(undefined *)((long)param_1 + 0x205) = 0xff; return 0; } s = s_Firmware_does_not_exist__fffad1b8; fail: puts(s); return 0xff; } undefined8 ddr_run_driver_init(long aml_ddr_fw__ns) { undefined8 uVar1; if (*(code **)(aml_ddr_fw__ns + 0x18) == (code *)0x0) { puts(s_Error__Driver_init_failed__fffad1d2); uVar1 = 0xff; } else { uVar1 = (**(code **)(aml_ddr_fw__ns + 0x18))(); } return uVar1; } void FUN_fffa6ca0(void) { puts(s_result_report_fffad1ee); return; } undefined8 ddr_parse_fw(long *data) { uint32_t uVar1; long *plVar2; uint uVar3; long *ddr_fip_hdr_copy; struct_ddrfw_toc_entry *entry; short i; short ddrfw_count; uint fw_name; ddr_fip_hdr_copy = (long *)data[24]; if (ddr_fip_hdr_copy == (long *)0x0) { puts(s_fip_hdr_data_lost__reset____fffad1fd); loop_forever1(); loop_forever2(); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } ddrfw_count = *(short *)((long)ddr_fip_hdr_copy + 0x1794); entry = (struct_ddrfw_toc_entry *)(ddr_fip_hdr_copy + 0x2f4); i = 0; do { /* Looks like it fails once, on librecomputer-alta. The following is printed over UART: Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 Get wrong ddr fw magic! Error!! fw parse done Maybe just fallthrough? As for fw_name, this was already reversed as part of gxlimg: if(!memcmp(fw_identifier, "d444", 4)) strcpy(fw_name, "ddr4_1d.fw"); else if(!memcmp(fw_identifier, "d422", 4)) strcpy(fw_name, "ddr4_2d.fw"); else if(!memcmp(fw_identifier, "d333", 4)) strcpy(fw_name, "ddr3_1d.fw"); else if(!memcmp(fw_identifier, "eaea", 4)) strcpy(fw_name, "piei.fw"); else if(!memcmp(fw_identifier, "dl44", 4)) strcpy(fw_name, "lpddr4_1d.fw"); else if(!memcmp(fw_identifier, "dl40", 4)) strcpy(fw_name, "lpddr4_2d.fw"); else if(!memcmp(fw_identifier, "ddg1", 4)) strcpy(fw_name, "diag_lpddr4.fw"); else if(!memcmp(fw_identifier, "AML0", 4)) strcpy(fw_name, "aml_ddr.fw"); else if(!memcmp(fw_identifier, "dl33", 4)) strcpy(fw_name, "lpddr3_1d.fw"); else snprintf(fw_name, sizeof(fw_name), "ddrfw_%u.bin", i); */ if (i == ddrfw_count) { puts(s_fw_parse_done_fffad23b); return 0; } fw_name = *(uint *)(entry->props + 4); if (fw_name == 0x33333364) { plVar2 = data + 0x22; LAB_fffa6dfc: /* ??? */ *(uint32_t *)plVar2 = entry->offset; uVar1 = entry->size; plVar2[1] = (long)entry; *(uint32_t *)((long)plVar2 + 4) = uVar1; } else { if (fw_name < 0x33333365) { if (fw_name == 0x304c4d41) { plVar2 = data + 0x1e; } else if (fw_name == 0x32323464) { plVar2 = data + 0x26; } else { if (fw_name != 0x30346c64) goto fail_to_get_magic; plVar2 = data + 0x2c; } goto LAB_fffa6dfc; } if (fw_name == 0x34343464) { plVar2 = data + 0x24; goto LAB_fffa6dfc; } if (fw_name < 0x34343465) { uVar3 = 0x33336c64; plVar2 = data + 0x28; } else { if (fw_name == 0x34346c64) { plVar2 = data + 0x2a; goto LAB_fffa6dfc; } uVar3 = 0x61656165; plVar2 = data + 0x20; } if (fw_name == uVar3) goto LAB_fffa6dfc; fail_to_get_magic: puts(s_Get_wrong_ddr_fw_magic__Error___fffad21a); } i = i + 1; entry = entry + 1; } while( true ); } void FUN_fffa6e38(void) { return; } uint FUN_fffa6e3c(long param_1) { uint uVar1; char cVar2; char *s; long lVar3; uint uVar4; uint uVar5; ulong uVar6; uVar1 = acs_; uVar5 = (uint)*(byte *)(param_1 + 0xe7); FUN_fffa1590(5000); uVar6 = (ulong)uVar1; if (*(char *)(*(long *)(DAT_fffb1c30 + 0x10) + 0x1b) == '\0') { *(undefined *)(param_1 + 0xe6) = 0xc; } do { if (*(byte *)(param_1 + 0xe6) <= uVar5) { LAB_fffa6fb4: if (uVar5 == *(byte *)(param_1 + 0xe6)) { puts(s_All_ddr_config_failed____fffad29a); uVar5 = 0xff; } else if (*(char *)(*(long *)(DAT_fffb1c30 + 0x10) + 0x1b) == '\0') { memset(&DAT_fffb1730,0,0x498); memcpy((long)&DAT_fffb1730,*(long *)(param_1 + 0xa0), (ulong)*(ushort *)(uVar6 + (ulong)uVar5 * 2 + 0x7c)); *(undefined **)(param_1 + 0xa0) = &DAT_fffb1730; } return uVar5; } puts(s_Cfg_max__fffad24a); uVar1 = uVar5 + 1; put_dec((ulong)*(byte *)(param_1 + 0xe6)); puts(s___cur__fffad254); put_dec((ulong)*(byte *)(param_1 + 0xe7) + 1); puts(&DAT_fffad25c); lVar3 = DAT_fffb1c30; *(char *)(param_1 + 0xe7) = (char)uVar1; if (*(char *)(*(long *)(lVar3 + 0x10) + 0x1b) == '\0') { uVar4 = *(uint *)*(long **)(param_1 + 0xb8); lVar3 = 0; if (uVar5 != 0) { while (lVar3 = lVar3 + 1, (uint)lVar3 < uVar1) { uVar4 = uVar4 + *(ushort *)(uVar6 + lVar3 * 2 + 0x7a); } } *(ulong *)(param_1 + 0xa0) = (ulong)uVar4; *(undefined *)((ulong)uVar4 + 0xc) = *(undefined *)(uVar6 + uVar5 + 0x70); } else { *(ulong *)(param_1 + 0xa0) = **(long **)(param_1 + 0xb8) + (ulong)uVar5 * 0x498; } puts(s_Board_id__fffad25f); put_dec((ulong)*(byte *)(*(long *)(param_1 + 0xa0) + 0xc)); cVar2 = *(char *)(*(long *)(param_1 + 0xa0) + 0xc); if (*(char *)(param_1 + 0xe9) == cVar2) { s = s___match_fffad26a; LAB_fffa6f98: puts(s); goto LAB_fffa6fb4; } if (cVar2 == -1) { s = s___Force_loop_cfg_fffad273; goto LAB_fffa6f98; } puts(s___not_match__skip___fffad285); uVar5 = uVar1; } while( true ); } undefined8 FUN_fffa702c(long param_1) { uint ret; ret = FUN_fffa6e3c(param_1); if (ret == 0xff) { puts(s_Reset____fffad2b4); FUN_fffa69d8(param_1); loop_forever2(); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } FUN_fffa64d4(param_1); FUN_fffa6520((ddr_set_t *)param_1); FUN_fffa8a20(param_1); FUN_fffa9020(); return 0; } void load_ddr_fwhdr(long *firmware) { int iVar1; byte bVar2; byte bVar3; uint tmp_; uint tmp__; uint uVar4; int iVar5; undefined uVar6; uint tmp; bVar3 = DAT_fffb1c42; bVar2 = DAT_fffb1c40; tmp__ = 0; iVar5 = 0; uVar6 = 0; tmp = 0; uVar4 = (uint)DAT_fffb1c40; do { tmp_ = (uint)bVar2; if (uVar4 < (tmp__ & 0xff) || tmp_ == (tmp__ & 0xff)) goto LAB_fffa7144; iVar1 = 0; if (tmp_ != 0) { iVar1 = (int)(tmp__ + bVar3) / (int)tmp_; } tmp = (tmp__ + bVar3) - iVar1 * tmp_; firmware[24] = 0; if (tmp__ == uVar4 - 1) { iVar5 = 1; } uVar6 = (undefined)tmp; storage_load(0x10000,(ulong)&DAT_fffd0000_ddr_params,0x4000,s_FIP_HDR_DDR_fffad2be,tmp); tmp_ = fip_hdr_check__ns((undefined8 *)&DAT_fffd0000_ddr_params,(ulong)&DAT_fffdc000,iVar5); tmp = tmp_ & 0xff; tmp__ = tmp__ + 1; } while ((tmp_ & 0xff) != 0); firmware[24] = (long)&DAT_fffdc000; LAB_fffa7144: DAT_fffb1c42 = uVar6; if (tmp != 0) { puts(s_All_fw_copies_fiphdr_error_fffad2ca); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } return; } void load_ddr_fw(long *ddrfw) { char cVar1; byte bVar2; byte bVar3; int iVar4; long lVar5; char *s; long *plVar6; undefined8 *puVar7; uint uVar8; bVar2 = DAT_fffb1c40; do { bVar3 = DAT_fffb1c42; cVar1 = *(char *)((long)ddrfw + 0xea); if (cVar1 == '\x0f') { plVar6 = ddrfw + 0x1e; puVar7 = &DAT_fffb4000; } else if (cVar1 == '\0') { plVar6 = ddrfw + 0x20; puVar7 = (undefined8 *)&DAT_fffcc000; } else { if (cVar1 == '\x01') { plVar6 = (long *)ddrfw[0x32]; } else { if (cVar1 != '\x02') { puts(s_Error__Unsupport_fw_load_step__fffad2e6); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } plVar6 = (long *)ddrfw[0x33]; } *(char *)((long)ddrfw + 0x25d) = cVar1; if (plVar6 == (long *)0x0) { puts(s_Error__FW_doesn_t_exit__fffad305); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } puVar7 = (undefined8 *)0xfffc0000; } /* storage_load(ulong src,ulong dst,ulong len,char *name,uint part) */ lVar5 = storage_load((ulong)(*(int *)plVar6 + 0x10000),(ulong)&DAT_fffd0000_ddr_params, (ulong)*(uint *)((long)plVar6 + 4),(char *)0x0,(uint)bVar3); s = s_Error__DDR_fw_load_fail__fffad31d; if (((int)lVar5 == 0) && (iVar4 = check_fw__ns((long)&DAT_fffd0000_ddr_params,(long)puVar7,plVar6[1]), s = s_Error__DDR_fw_check_fail__fffad337, iVar4 == 0)) { return; } /* Prints error regardless if it succeeded or not? */ puts(s); cVar1 = '\0'; uVar8 = bVar3 + 1 & 0xff; if (bVar2 != 0) { cVar1 = (char)(uVar8 / bVar2); } DAT_fffb1c42 = (char)uVar8 - cVar1 * bVar2; load_ddr_fwhdr(ddrfw); ddr_parse_fw(ddrfw); } while( true ); } void PIEI_prepare_(long param_1) { uint uVar1; undefined *puVar2; for (puVar2 = &DAT_fffcc008; (int)puVar2 + 0x33ff8U < *(uint *)(param_1 + 0x104); puVar2 = puVar2 + 8) { uVar1 = *(uint *)(puVar2 + -8); if (uVar1 == 0x33336c64) { if (*(short *)(puVar2 + -4) == -0x113) { *(undefined **)(param_1 + 0x88) = puVar2; } } else if (uVar1 < 0x33336c65) { if ((uVar1 == 0x33333364) && (*(short *)(puVar2 + -4) == -0x113)) { *(undefined **)(param_1 + 0x78) = puVar2; } } else if (uVar1 == 0x34343464) { if (*(short *)(puVar2 + -4) == -0x113) { *(undefined **)(param_1 + 0x80) = puVar2; } } else if ((uVar1 == 0x34346c64) && (*(short *)(puVar2 + -4) == -0x113)) { *(undefined **)(param_1 + 0x90) = puVar2; } } puts(s_PIEI_prepare_done_fffad352); return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 aml_ddr_load(long *ddr_fw) { char cVar1; byte bVar2; byte bVar3; uint uVar4; int iVar5; undefined8 uVar6; ulong uVar7; long lVar8; load_ddr_fwhdr(ddr_fw); ddr_parse_fw(ddr_fw); *(undefined *)((long)ddr_fw + 0xea) = 0xf; load_ddr_fw(ddr_fw); *(undefined *)((long)ddr_fw + 0xea) = 0; load_ddr_fw(ddr_fw); PIEI_prepare_((long)ddr_fw); ddr_fw[0x14] = *(long *)ddr_fw[0x17] + (ulong)*(byte *)((long)ddr_fw + 0xe6) * 0x498 + L'\xfffffb68'; load_ddr_params((ulong)&DAT_fffd0000_ddr_params,0x1000); bVar2 = ddr_fw_data_verify__ns((long)&DAT_fffd0000_ddr_params); uVar7 = (ulong)bVar2; if (DAT_fffadea0 != '\0') { puts(s_fastboot_data_verify_fffad365); puts(s_result__fffad37b); /* uVar7 == 255 */ put_dec(uVar7); puts(s__fffadb47 + 1); } if (bVar2 == 0) { lVar8 = 0xfffd0020; } else { /* bVar2 != 0 */ lVar8 = *(long *)ddr_fw[0x17]; } if ((*(uint *)(lVar8 + 8) >> 0x1e & 1) == 0) { if (bVar2 == 0) goto LAB_fffa7484; } else { bVar3 = FUN_fffa6424(0xfffd04b8); uVar7 = (ulong)((uint)bVar2 + (uint)bVar3); if ((uint)bVar2 + (uint)bVar3 == 0) { LAB_fffa7484: if (0xfc < *(byte *)(lVar8 + 4)) { memcpy((long)&DAT_fffb1730,0xfffd0020,0x498); cVar1 = DAT_fffadea0; ddr_fw[0x14] = (long)&DAT_fffb1730; if (cVar1 != '\0') { puts(s_enable_fast_boot_fffad384); if ((*(byte *)(ddr_fw[0x14] + 5) & 0xf) != 0) { puts(s_dmc_margin_rx___fffad396); put_dec((ulong)*(byte *)(ddr_fw[0x14] + 5) & 0xf); } if (*(byte *)(ddr_fw[0x14] + 5) >> 4 != 0) { puts(s__dmc_margin_tx___fffad3a6); put_dec((ulong)(*(byte *)(ddr_fw[0x14] + 5) >> 4)); } puts(s__steps_fffad3b7); } FUN_fffa64d4(ddr_fw); FUN_fffa6520((ddr_set_t *)ddr_fw); *(undefined *)((long)ddr_fw + 0x264) = 0xff; uVar6 = FUN_fffa6a60((ddr_set_t **)ddr_fw); if ((int)uVar6 == 0) { (*(code *)*ddr_fw)(ddr_fw); (*(code *)ddr_fw[7])(ddr_fw); iVar5 = (*(code *)ddr_fw[5])(ddr_fw); if (iVar5 == 0) goto LAB_fffa758c; } } uVar7 = 0; } } LAB_fffa75c4: do { uVar4 = FUN_fffa6e3c((long)ddr_fw); if (uVar4 == 0xff) { puts(s_Reset____fffad2b4); FUN_fffa69d8((long)ddr_fw); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } FUN_fffa64d4(ddr_fw); FUN_fffa6520((ddr_set_t *)ddr_fw); uVar6 = FUN_fffa6a60((ddr_set_t **)ddr_fw); if (((int)uVar6 != 0xff) && (iVar5 = (*(code *)*ddr_fw)(ddr_fw), iVar5 != 0xf)) { if (*(byte *)(ddr_fw[0x14] + 4) < 0xfd) { FUN_fffa7e58(); *(undefined *)((long)ddr_fw + 0xea) = 1; load_ddr_fw(ddr_fw); uVar7 = ddr_run_driver_init((long)ddr_fw); uVar7 = uVar7 & 0xffffffff; puts(s_1D_training_fffad3bf); if ((int)uVar7 != 0) { LAB_fffa76b8: puts(s_failed_fffad3cc); goto LAB_fffa75c4; } puts(s_1D_init_succeed_fffad79b + 8); if (*(char *)(ddr_fw + 0x1d) != '\0') { *(undefined *)((long)ddr_fw + 0xea) = 2; load_ddr_fw(ddr_fw); uVar7 = ddr_run_driver_init((long)ddr_fw); uVar7 = uVar7 & 0xffffffff; puts(s_2D_training_fffad3d4); if ((int)uVar7 != 0) goto LAB_fffa76b8; puts(s_1D_init_succeed_fffad79b + 8); } } else { (*(code *)ddr_fw[7])(ddr_fw); } uVar7 = (*(code *)ddr_fw[5])(ddr_fw); uVar7 = uVar7 & 0xffffffff; } } while ((int)uVar7 != 0); LAB_fffa758c: (*(code *)ddr_fw[6])(ddr_fw); if (*(char *)((long)ddr_fw + 0x234) != '\0') { FUN_fffa83c4((long)ddr_fw); } _DAT_ff638630 = 0x900; if (*(char *)(ddr_fw[0x14] + 0xe) == '\0') { _DAT_ff638630 = 0x1d00; } puts(s__100bdlr_step_size_ps___fffad3e1); uVar4 = FUN_fffa7f38((long)ddr_fw); put_dec((ulong)uVar4); puts(s__fffadb47 + 1); if (*(char *)(ddr_fw[0x14] + 0xe) == '\x02') { _DAT_ff63865c = 0xc10186a0; } *(undefined4 *)(ulong)(*(int *)(ddr_fw + 0x4d) + 0x20) = *(undefined4 *)(ddr_fw + 0x4e); return 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void ddr_init(void) { uint BoardID; BoardID = get_board_id(); /* BoardID == 1 (alta) */ puts(s_board_id__fffad3fa); put_dec((ulong)BoardID); puts(s__fffadb47 + 1); DAT_BoardID_fffb1379 = (undefined)BoardID; /* Fill 0xfffb4000 (up to +0xc000) with 0's */ memset(&DAT_fffb4000,0,0xc000); /* ??????????? */ FUN_fffa6488((astruct *)&DAT_fffb1290_); _DAT_ff63c100 = _DAT_ff63c100 & 0xfffcffff; if (DAT_bootdev__ns_fffb1e50 == 5) { /* USB? */ FUN_fffa702c((long)&DAT_fffb1290_); } else { aml_ddr_load(&DAT_fffb1290_); } puts(s_result_report_fffad1ee); FUN_fffa69d8((long)&DAT_fffb1290_); FUN_fffa794c((long)&DAT_fffb1290_); puts(s_Enable_ddr_reg_access_fffad405); _DAT_ff63936c = 0x88888; if (*(short *)(DAT_fffb1340 + 2) != 0) { _DAT_ff80025c = _DAT_ff80025c | 0x40000000; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined4 FUN_fffa7894(void) { do { } while (_DAT_ff630214 == 0); return _DAT_ff630210; } uint FUN_fffa78b4(uint param_1) { uint uVar1; uint uVar2; uint uVar3; uint uVar4; uVar2 = (param_1 & 0xfffff) >> 0x10 & 7; uVar3 = 2; if ((((uVar2 != 0) && (uVar3 = 3, uVar2 != 1)) && (uVar3 = 4, uVar2 != 2)) && ((uVar3 = 6, uVar2 != 3 && (uVar3 = 8, uVar2 != 4)))) { uVar3 = 0xfff; } uVar4 = (param_1 & 0xfffff) >> 10 & 0x1f; uVar2 = 0; if (uVar4 != 0) { uVar1 = 0; if (uVar4 != 0) { uVar1 = ((param_1 & 0x1ff) * 0x18) / uVar4; } uVar4 = 2; if ((param_1 & 0x80000) == 0) { uVar4 = 1; } uVar2 = 0; if (uVar3 != 0) { uVar2 = ((uVar1 >> (ulong)uVar4) << 1) / uVar3; } } return uVar2; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint get_board_id(void) { return _AO_SEC_GP_CFG0_ff800240 >> 8 & 0xff; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa794c(long param_1) { long lVar1; undefined4 *puVar2; undefined4 *puVar3; long lVar4; if ((_AO_UNK_ff80000c & 0xf) == 0) { puVar2 = (undefined4 *)&DAT_ff638800; do { puVar3 = puVar2 + 1; *puVar2 = 0; puVar2 = puVar3; } while (puVar3 != (undefined4 *)0xff638900); } if ((_DAT_ff638800 & 0xffff) != 0x2222) { lVar4 = *(long *)(param_1 + 0xa0); lVar1 = 0; do { *(undefined4 *)(&DAT_ff638800 + lVar1) = *(undefined4 *)(lVar1 + lVar4); lVar1 = lVar1 + 4; } while (lVar1 != 0x100); } return; } uint FUN_fffa79c4(ushort param_1,byte param_2) { uint uVar1; uint uVar2; uint uVar3; uint uVar4; uVar3 = (uint)param_2; uVar1 = (uint)param_1; uVar2 = (int)uVar1 >> 2; if (param_2 == 0) { if (uVar1 < 0x641) { if (0x4b0 < param_1) { uVar3 = 1; uVar2 = (int)uVar1 >> 3; uVar4 = 2; goto LAB_fffa7aec; } if (800 < param_1) { uVar2 = uVar1 / 6; uVar4 = 2; goto LAB_fffa7ab0; } uVar3 = 3; if (uVar1 < 0x259) { if (uVar1 < 0x191) { if (0x168 < uVar1) goto LAB_fffa7ac4; uVar2 = (uVar1 << 4) / 0x18; uVar4 = 3; } else { uVar2 = uVar1 / 3; uVar4 = 2; } LAB_fffa7ad8: uVar3 = 4; goto LAB_fffa7aec; } } else { uVar2 = uVar1 / 0xc; uVar3 = (uint)param_2; } uVar4 = 2; } else { if (param_2 != 1) { uVar4 = 0; uVar3 = 0; uVar2 = 0; goto LAB_fffa7aec; } if (799 < uVar1) { uVar2 = uVar1 / 6; uVar4 = 3; uVar3 = 0; goto LAB_fffa7aec; } if (599 < uVar1) { uVar4 = 3; goto LAB_fffa7aec; } uVar4 = 3; if (uVar1 < 400) { if (299 < uVar1) { LAB_fffa7ac4: uVar3 = 3; uVar2 = (int)uVar1 >> 1; uVar4 = uVar3; goto LAB_fffa7aec; } uVar2 = (uVar1 << 4) / 0x18; goto LAB_fffa7ad8; } uVar2 = uVar1 / 3; LAB_fffa7ab0: uVar3 = 2; } LAB_fffa7aec: return uVar2 | 0x400 | uVar3 << 0x10 | uVar4 << 0x13; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffa7afc(long param_1) { uint uVar1; uint uVar2; long lVar3; int iVar4; if (DAT_fffadea4 == 0x12345678) { puts(s__fffadb47 + 1); puts(s_LPDDR4_PHY_V_0_1_27_fffad57d); puts(&DAT_fffad591); puts(s_Built___05_09_43__Jul_8_2023__g1_fffaca08); puts(s__fffadb47 + 1); DAT_fffadea4 = -0x5a5aa5a6; } if (*(byte *)(*(long *)(param_1 + 0xa0) + 0x11) < 10) { FUN_fffa15ec(); } lVar3 = *(long *)(param_1 + 0xa0) + (ulong)*(byte *)(param_1 + 0x1b9) * 2; uVar1 = FUN_fffa79c4(*(ushort *)(lVar3 + 0x38), (byte)((int)(uint)*(byte *)(*(long *)(param_1 + 0xa0) + 0x40) >> (*(byte *)(param_1 + 0x1b9) & 0x1f)) & 1); uVar2 = FUN_fffa78b4(uVar1); *(short *)(lVar3 + 0x38) = (short)uVar2; if (*(char *)(param_1 + 0x1ba) == '\0') { puts(s_ddr_clk_to_fffad593); put_dec((ulong)uVar2); puts(&DAT_fffacb30); } lVar3 = *(long *)(param_1 + 0xb0); if ((*(int *)(lVar3 + 0x44) == 0) && (*(int *)(lVar3 + 0x4c) == 0)) { *(undefined4 *)(lVar3 + 0x48) = 0; *(undefined4 *)(lVar3 + 0x4c) = 0x8691c00; *(undefined4 *)(lVar3 + 0x50) = 0x88770290; *(undefined4 *)(lVar3 + 0x40) = 0x18110400; *(undefined4 *)(lVar3 + 0x54) = 0x3927200a; *(undefined4 *)(lVar3 + 0x44) = 4; *(undefined4 *)(lVar3 + 0x58) = 0x50540000; } iVar4 = 100; do { lVar3 = *(long *)(param_1 + 0xb0); _DAT_ff638c18 = *(undefined4 *)(lVar3 + 0x58); _DAT_ff638c14 = *(undefined4 *)(lVar3 + 0x54); _DAT_ff638c10 = *(undefined4 *)(lVar3 + 0x50); _DAT_ff638c0c = *(undefined4 *)(lVar3 + 0x4c); _DAT_ff638c08 = *(undefined4 *)(lVar3 + 0x48); _DAT_ff638c04 = *(undefined4 *)(lVar3 + 0x44); loop_forever1(); _DAT_ff638c00 = uVar1 | 0x1c000000; loop_forever1(); _DAT_ff638c00 = uVar1 | 0x3c000000; loop_forever1(); _DAT_ff638c00 = uVar1 | 0x1c000000; loop_forever1(); if ((int)_DAT_ff638c00 < 0) { if (iVar4 != 0) { return 0; } puts(s_DDR_pll_lock_failed__fffad59f); return 0xf; } iVar4 = iVar4 + -1; } while (iVar4 != -1); return 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa7d38(long param_1) { long lVar1; undefined4 *puVar2; long lVar4; undefined4 *puVar3; if ((*(uint *)(ulong)*(uint *)(param_1 + 0x268) & 0xffff0000) == 0x20180000) { if (*(int *)(ulong)(*(uint *)(param_1 + 0x268) + 4) == 1) { puts(s_D2PLL_flow_fffad5b5); *(undefined *)(param_1 + 0x1ba) = 1; *(undefined2 *)(*(long *)(param_1 + 0xa0) + 0x38) = 0x198; FUN_fffa7afc(param_1); _DAT_ff638c20 = 0xb0000007; _DAT_ff638004 = 0xffffffff; _DAT_ff638008 = 0xffffffff; _DAT_ff63800c = 0xffffffff; lVar4 = *(long *)(param_1 + 0xa0); *(undefined *)(param_1 + 0x1ba) = 0; lVar1 = 0; do { *(undefined4 *)(lVar1 + lVar4) = *(undefined4 *)(&DAT_ff638800 + lVar1); lVar1 = lVar1 + 4; } while (lVar1 != 0x100); puVar2 = (undefined4 *)(lVar4 + 0x100); do { puVar3 = puVar2 + 1; *puVar2 = 0; puVar2 = puVar3; } while (puVar3 != (undefined4 *)(lVar4 + 0x498)); } else { puts(s_Unsupport_sticky_cmd_fffad5c1); } *(uint *)(ulong)*(uint *)(param_1 + 0x268) = *(uint *)(ulong)*(uint *)(param_1 + 0x268) & 0xffff ; *(undefined4 *)(ulong)(*(int *)(param_1 + 0x268) + 4) = 0; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffa7e58(void) { _DAT_ff638c20 = 0xb0000007; _DAT_ff638004 = 0xffffffff; _DAT_ff638008 = 0xffffffff; _DAT_ff63800c = 0xffffffff; loop_forever1(); _DAT_ff638004 = 0; _DAT_ff638008 = 0; _DAT_ff63800c = 0; loop_forever1(); _DAT_ff638004 = 0xffffffff; _DAT_ff638008 = 0xffffffff; _DAT_ff63800c = 0xffffffff; _DAT_ff638c24 = 0x1f; return 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffa7f38(long param_1) { uint uVar1; uint uVar2; _DAT_fe0401c6 = 0xc00; uVar2 = (uint)*(ushort *)(*(long *)(param_1 + 0xa0) + (((ulong)_DAT_ff63864c & 1) + 0x18) * 2 + 8) ; uVar1 = 0; if (uVar2 != 0) { uVar1 = 100000000 / (uVar2 << 1); } uVar2 = 0; if ((_DAT_fe0401c8 & 0x3ff) != 0) { uVar2 = uVar1 / (_DAT_fe0401c8 & 0x3ff); } return uVar2; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa7f90(void) { if ((_DAT_ff638c24 >> 4 & 1) != 0) { _DAT_ff638650 = 2; loop_forever1(); _DAT_ff638628 = 0x3e; loop_forever1(); _DAT_ff638628 = 0x3f; loop_forever1(); _DAT_ff638628 = 0x3e; loop_forever1(); _DAT_ff638c24 = 0xf; loop_forever1(); _DAT_ff638c24 = 0; loop_forever1(); return; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa8048(void) { _DAT_ff638c20 = 0xb0000007; _DAT_ff638004 = 0xffffffff; _DAT_ff638008 = 0xffffffff; _DAT_ff63800c = 0xffffffff; loop_forever1(); _DAT_ff638004 = 0; _DAT_ff638008 = 0; _DAT_ff63800c = 0; loop_forever1(); _DAT_ff638004 = 0xffffffff; _DAT_ff638008 = 0xffffffff; _DAT_ff63800c = 0xffffffff; loop_forever1(); _DAT_ff638c24 = 3; loop_forever1(); _DAT_ff638c24 = 1; loop_forever1(); _DAT_ff638628 = 0; _DAT_ff638c24 = 0; loop_forever1(); _DAT_ff638c24 = 0x10; loop_forever1(); _DAT_ff638c24 = 0x12; loop_forever1(); _DAT_ff638c24 = 0x13; loop_forever1(); _DAT_fe1a0000 = 0; _DAT_fe120050 = 0; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffa81b8(long param_1) { byte bVar1; undefined uVar2; uint uVar3; if (*(char *)(param_1 + 0x266) == '\0') { uVar2 = 0xff; } else { *(undefined *)(*(long *)(param_1 + 0xa0) + 4) = 0; uVar2 = 2; } *(undefined *)(param_1 + 0x264) = uVar2; if ((*(char *)(param_1 + 0x1f0) == '\0') && ((*(byte *)(*(long *)(param_1 + 0xa0) + 0x78) & 1) == 0)) { FUN_fffa7f90(); } FUN_fffa8048(); *(undefined *)(param_1 + 0xea) = 1; _DAT_fe1a0000 = 0; if (((*(char *)(param_1 + 0x264) == -1) && ((*(uint *)(*(long *)(param_1 + 0xa0) + 8) >> 0x1b & 1) == 0)) && (*(char *)(param_1 + 0x25d) != '\x01')) { load_ddr_fw((long *)param_1); } if (*(char *)(param_1 + 0x264) == '\x02') { load_ddr_fw((long *)param_1); } ddr_run_driver_init(param_1); if ((*(char *)(param_1 + 0xe8) != '\0') && (*(char *)(param_1 + 0x264) == '\x02')) { *(undefined *)(param_1 + 0xea) = 2; load_ddr_fw((long *)param_1); ddr_run_driver_init(param_1); } bVar1 = *(byte *)(param_1 + 0x208); if ((bVar1 != 0) && (*(char *)(param_1 + 0x1c9) != '\0')) { if (((bVar1 & 0xfb) == 3) || ((bVar1 == 5 || ((byte)(bVar1 - 0xc) < 3)))) { FUN_fffa8574(param_1); } if ((*(char *)(param_1 + 0x208) == '\x04') || (*(char *)(param_1 + 0x208) == '\x02')) { FUN_fffa87b8((uint)*(byte *)(param_1 + 0x233),(ushort)*(byte *)(param_1 + 0x232),0,param_1); } } uVar3 = 0; if (*(char *)(param_1 + 0x236) == '\0') { uVar3 = 2; } _DAT_ff639254 = uVar3 | _DAT_ff639254; return 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa8334(uint param_1) { uint uVar1; ulong uVar2; undefined *puVar3; uint uVar4; puVar3 = &DAT_fffad420; uVar4 = 0x1c; while( true ) { uVar1 = uVar4 - 1; uVar2 = (ulong)uVar1; if ((*(uint *)(uVar2 * 8 + 0xfffad424) < param_1) && (param_1 <= *(uint *)(puVar3 + 0xe4))) break; puVar3 = puVar3 + -8; uVar4 = uVar1; if (uVar1 == 0) { LAB_fffa837c: if (((int)uVar2 != 0) && (param_1 != 0)) { _DAT_ff807004 = *(undefined4 *)(&DAT_fffad420 + uVar2 * 8); serial_print(s__DDR_overide_EE_voltage____fffad5e5, *(uint *)((ulong)((int)uVar2 - 1) * 8 + 0xfffad424),1,s__mv_fffad600); return; } return; } } uVar2 = (ulong)uVar4; goto LAB_fffa837c; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa83c4(long param_1) { uint uVar1; uint uVar2; char *pcVar3; puts(s__fffadb47 + 1); uVar2 = *(uint *)(*(long *)(param_1 + 0xa0) + 8); uVar1 = uVar2 & 0x800; if ((uVar2 >> 0xb & 1) == 0) { pcVar3 = s_non_sec_scramble_use_zero_key_fffad67f; _DAT_ff639240 = uVar1; _DAT_ff639244 = uVar1; } else { _DAT_ff639240 = FUN_fffa7894(); _DAT_ff639244 = FUN_fffa7894(); pcVar3 = s_non_sec_scramble_use_random_key_fffad65e; } puts(pcVar3); _DAT_ff639248 = FUN_fffa7894(); _DAT_ff63924c = FUN_fffa7894(); if ((*(short *)(*(long *)(param_1 + 0xb0) + 2) == 0) && (*(byte *)(param_1 + 0x234) != 0)) { _DAT_ff639254 = (uint)*(byte *)(param_1 + 0x234) << 1; pcVar3 = s_ddr_scramble_enabled_fffad69e; } else { _DAT_ff639254 = 0; pcVar3 = s_ddr_scramble_disabled_fffad6b4; } puts(pcVar3); return; } byte ddr_fw_data_verify__ns(long param_1) { byte bVar1; undefined8 local_20; undefined8 uStack_18; undefined8 local_10; undefined8 uStack_8; local_20 = 0; uStack_18 = 0; local_10 = 0; uStack_8 = 0; FUN_fffac334(param_1 + 0x20,0x498,(long)&local_20,0); FUN_fffa6e38(); bVar1 = FUN_fffac5b0((long)&local_20,param_1,0x20); if (bVar1 != 0) { bVar1 = 255; } return bVar1; } void FUN_fffa8518(undefined8 param_1,undefined8 param_2,undefined2 param_3,byte param_4,char param_5 ) { uint uVar1; uVar1 = 0x40; if (param_5 != '\0') { uVar1 = 0x30; } *(undefined2 *) ((ulong)(((uint)param_4 % 0x24) % 9 << 8 | ((uint)param_4 % 0x24) / 9 << 0xc | 0x10000 | uVar1) * 2 + 0xfe000000) = param_3; return; } void FUN_fffa8574(long param_1) { uint uVar1; uint uVar2; bool bVar3; byte bVar4; int iVar5; if (*(byte *)(param_1 + 0x1c9) != 0) { uVar2 = *(byte *)(param_1 + 0x1c9) - 1; bVar3 = *(char *)(param_1 + 0x208) == '\f'; if ((*(char *)(param_1 + 0x208) == '\x03') || (bVar3)) { uVar1 = uVar2 >> 1; iVar5 = 0; do { FUN_fffa8518((ulong)*(byte *)(*(long *)(param_1 + 0xa0) + 0xe), (ulong)*(byte *)(param_1 + 0x233),(ushort)*(byte *)(param_1 + 0x232), (char)uVar1 + (char)(uVar1 << 3) + (char)iVar5,bVar3); iVar5 = iVar5 + 1; } while (iVar5 != 9); } bVar4 = (byte)uVar2; if ((*(byte *)(param_1 + 0x208) & 0xf7) == 5) { FUN_fffa8518((ulong)*(byte *)(*(long *)(param_1 + 0xa0) + 0xe), (ulong)*(byte *)(param_1 + 0x233),(ushort)*(byte *)(param_1 + 0x232),bVar4,bVar3) ; } if ((*(char *)(param_1 + 0x208) == '\x0e') || (*(char *)(param_1 + 0x208) == '\a')) { FUN_fffa8518((ulong)*(byte *)(*(long *)(param_1 + 0xa0) + 0xe), (ulong)*(byte *)(param_1 + 0x233),(ushort)*(byte *)(param_1 + 0x232),bVar4,bVar3) ; return; } } return; } /* WARNING: Removing unreachable block (ram,0xfffa8780) */ /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa8674(byte param_1,byte param_2,ushort param_3,long param_4) { char cVar1; uint uVar2; _DAT_ff6394e8 = 0xa000a; cVar1 = *(char *)(param_4 + 0x1b8); if ((cVar1 == '\x03') || (uVar2 = (uint)(cVar1 == '\0'), cVar1 == '\0')) { uVar2 = (uint)param_2; } if (cVar1 == '\x01') { uVar2 = param_2 & 3 | (param_2 >> 2 & 3) << 3; } else if (cVar1 == '\x02') { uVar2 = (uint)param_2; } if (*(char *)(param_4 + 0x262) != '\0') { do { } while( true ); } _DAT_ff638664 = param_3 | 0x80000000 | uVar2 << 0x10; do { } while ((int)_DAT_ff638664 < 0); return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa87b8(int param_1,ushort param_2,undefined8 param_3,long param_4) { ushort uVar1; byte bVar2; ushort uVar3; if (*(char *)(param_4 + 0x1b8) == '\x02') { uVar3 = param_2 | (ushort)(param_1 << 6); bVar2 = 0xe; } else if (*(char *)(param_4 + 0x1b8) == '\x01') { uVar3 = param_2 | (ushort)(param_1 << 6) | (((ushort)*(undefined4 *)(*(long *)(param_4 + 0xa8) + 0x50) & 0xff) - 4) * 0x400; bVar2 = 6; } else { bVar2 = 6; uVar3 = 0; } _DAT_ff638650 = 1; loop_forever1(); do { } while ((_DAT_ff638654 >> 4 & 0xf) != 1); if (*(char *)(param_4 + 0x1b8) == '\x01') { uVar1 = uVar3 | 0x80; FUN_fffa8674(0,bVar2,uVar1,param_4); uVar3 = uVar3 & 0xff7f; FUN_fffa8674(0,bVar2,uVar1,param_4); FUN_fffa8674(0,bVar2,uVar3,param_4); if (*(short *)(*(long *)(param_4 + 0xa0) + 0x2a) != 0) { FUN_fffa8674(1,bVar2,uVar1,param_4); FUN_fffa8674(1,bVar2,uVar1,param_4); FUN_fffa8674(1,6,uVar3,param_4); } } if (*(char *)(param_4 + 0x1b8) == '\x02') { FUN_fffa8674(0,bVar2,uVar3,param_4); if (*(short *)(*(long *)(param_4 + 0xa0) + 0x2a) != 0) { FUN_fffa8674(1,bVar2,uVar3,param_4); } } _DAT_ff638650 = 4; loop_forever1(); do { } while ((_DAT_ff638654 >> 4 & 0xf) != 2); loop_forever1(); return; } void FUN_fffa8970(long param_1) { if (DAT_fffb1372 == 0x2000) { puts(s_Data_req_end_fffad6d8); *(undefined *)(param_1 + 0x15) = 1; } else { if ((((DAT_fffb1372 >> 4 & 1) == 0) && (DAT_fffb1372 != 0xf)) && (DAT_fffb1372 != 0x20)) { memcpy(param_1,0xfffb1358,0x18); return; } puts(s_Exit_data_request_loop___Err0x_fffad6e6); put_hex((ulong)DAT_fffb1372,0x20); puts(s__fffadb47 + 1); *(char *)(param_1 + 0x15) = (char)DAT_fffb1372; DAT_fffb1372 = 0x3000; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined2 FUN_fffa8a20(long param_1) { ushort uVar1; undefined2 uVar2; int iVar3; int iVar4; uVar1 = *(ushort *)(param_1 + 0xe2); if (uVar1 == 0) { LAB_fffa8a98: *(undefined4 *)(param_1 + 0xcc) = 0xfffd0000; *(undefined4 *)(param_1 + 0xd0) = 0x10000; *(undefined4 *)(param_1 + 0xd4) = 0x4000; uVar2 = 0x2001; } else if (uVar1 == 0x1004) { *(undefined4 *)(param_1 + 0xcc) = 0xfffd0000; iVar3 = **(int **)(param_1 + 0x198); *(int *)(param_1 + 0xd4) = (*(int **)(param_1 + 0x198))[1]; *(int *)(param_1 + 0xd0) = iVar3 + 0x10000; uVar2 = 0x2004; } else if (uVar1 < 0x1005) { if (uVar1 == 0x1002) { *(undefined4 *)(param_1 + 0xcc) = 0xfffd0000; iVar3 = **(int **)(param_1 + 400); *(int *)(param_1 + 0xd4) = (*(int **)(param_1 + 400))[1]; *(int *)(param_1 + 0xd0) = iVar3 + 0x10000; uVar2 = 0x2002; } else { if (uVar1 < 0x1003) { if (uVar1 != 0x1001) goto LAB_fffa8b84; goto LAB_fffa8a98; } *(undefined4 *)(param_1 + 0xcc) = 0xfffd0000; *(int *)(param_1 + 0xd0) = *(int *)(param_1 + 0x100) + 0x10000; *(undefined4 *)(param_1 + 0xd4) = *(undefined4 *)(param_1 + 0x104); uVar2 = 0x2003; } } else if (uVar1 == 0x1006) { iVar3 = (int)_DAT_014000a8; iVar4 = (int)_DAT_014000b0; *(undefined4 *)(param_1 + 0xcc) = 0x1704000; *(undefined4 *)(param_1 + 0xd0) = 0x14000; *(int *)(param_1 + 0xd4) = iVar4 + iVar3 + -0x4000; uVar2 = 0x2006; } else if (uVar1 < 0x1006) { *(undefined4 *)(param_1 + 0xcc) = 0x1700000; *(undefined4 *)(param_1 + 0xd0) = 0x10000; *(undefined4 *)(param_1 + 0xd4) = 0x4000; uVar2 = 0x2005; } else { if (uVar1 != 0x1103) goto LAB_fffa8b84; *(undefined4 *)(param_1 + 0xcc) = 0xfffd0000; *(int *)(param_1 + 0xd0) = *(int *)(param_1 + 0xf0) + 0x10000; *(undefined4 *)(param_1 + 0xd4) = *(undefined4 *)(param_1 + 0xf4); uVar2 = 0x2103; } *(undefined2 *)(param_1 + 0xe2) = uVar2; LAB_fffa8b84: return *(undefined2 *)(param_1 + 0xe2); } uint FUN_fffa8b8c(uint param_1,uint param_2) { uint uVar1; uVar1 = fip_hdr_check__ns((undefined8 *)(ulong)param_1,(ulong)param_2,0); return uVar1; } undefined2 FUN_fffa8b9c(void) { bool bVar1; short sVar2; undefined2 uVar3; int iVar4; uint uVar5; undefined8 uVar6; char *s; if (DAT_fffb1372 == 0x2000) { puts(s_RUN_bl2_usb_boot_fffad705); uVar6 = FUN_fffaaeac(); if (((int)uVar6 != 0) && (sVar2 = DAT_fffb1374 + -1, bVar1 = DAT_fffb1374 != 0, DAT_fffb1374 = sVar2, bVar1)) { DAT_fffb1372 = 0x1006; } } else { if (DAT_fffb1372 == 0x2004) { iVar4 = check_fw__ns((long)&DAT_fffd0000_ddr_params,0xfffc0000,*(long *)(DAT_fffb1428 + 8)); if ((iVar4 != 0) && (sVar2 = DAT_fffb1374 + -1, bVar1 = DAT_fffb1374 != 0, DAT_fffb1374 = sVar2, bVar1)) { puts(s_2D_fw_check_fail__retry__fffad7cb); LAB_fffa8e14: DAT_fffb1372 = 0x1004; goto aml_ddr_fw_load_done; } DAT_fffb137a = 2; DAT_fffb14ed = 2; uVar6 = ddr_run_driver_init((long)&DAT_fffb1290_); if ((int)uVar6 == 0) { s = s_2D_init_succeed_fffad7e5; LAB_fffa8e40: puts(s); DAT_fffb1372 = 0x1f08; goto aml_ddr_fw_load_done; } LAB_fffa8e4c: DAT_fffb1372 = 0x1f09; goto aml_ddr_fw_load_done; } if (DAT_fffb1372 < 0x2005) { if (DAT_fffb1372 == 0x2002) { iVar4 = check_fw__ns((long)&DAT_fffd0000_ddr_params,0xfffc0000,*(long *)(DAT_fffb1420 + 8)); if ((iVar4 == 0) || (sVar2 = DAT_fffb1374 + -1, bVar1 = DAT_fffb1374 == 0, DAT_fffb1374 = sVar2, bVar1)) { DAT_fffb137a = 1; DAT_fffb14ed = 1; uVar6 = ddr_run_driver_init((long)&DAT_fffb1290_); if ((int)uVar6 == 0) { puts(s_1D_init_succeed_fffad79b); if (DAT_fffb1378 == '\0') { s = s_need_2d_0__skip_2d_fw_load____fffad7ac; goto LAB_fffa8e40; } goto LAB_fffa8e14; } goto LAB_fffa8e4c; } puts(s_1D_fw_check_fail__retry__fffad781); } else { if (DAT_fffb1372 < 0x2003) { if (DAT_fffb1372 == 0x2001) { iVar4 = FUN_fffa8b8c(0xfffd0000,0xfffdc000); if ((iVar4 != 0) && (sVar2 = DAT_fffb1374 + -1, bVar1 = DAT_fffb1374 != 0, DAT_fffb1374 = sVar2, bVar1)) { puts(s_FIP_hdr_check_fail__retry__fffad717); DAT_fffb1372 = 0x1001; goto aml_ddr_fw_load_done; } DAT_fffb1350 = &DAT_fffdc000; ddr_parse_fw((long *)&DAT_fffb1290_); LAB_fffa8cc4: DAT_fffb1372 = 0x1103; goto aml_ddr_fw_load_done; } goto LAB_fffa8e9c; } iVar4 = check_fw__ns((long)&DAT_fffd0000_ddr_params,(long)&DAT_fffcc000,DAT_fffb1398); if ((iVar4 != 0) && (sVar2 = DAT_fffb1374 + -1, bVar1 = DAT_fffb1374 != 0, DAT_fffb1374 = sVar2, bVar1)) { puts(s_PIEI_check_fail__retry__fffad768); DAT_fffb1372 = 0x1003; goto aml_ddr_fw_load_done; } PIEI_prepare_((long)&DAT_fffb1290_); uVar6 = FUN_fffa6a60((ddr_set_t **)&DAT_fffb1290_); if (((int)uVar6 == 0xff) || (iVar4 = (*DAT_fffb1290_)(&DAT_fffb1290_), iVar4 == 0xf)) goto LAB_fffa8e4c; FUN_fffa7e58(); } DAT_fffb1372 = 0x1002; goto aml_ddr_fw_load_done; } if (DAT_fffb1372 == 0x2006) { DAT_fffb1372 = 0x2000; goto aml_ddr_fw_load_done; } if (DAT_fffb1372 < 0x2006) { iVar4 = FUN_fffa8b8c(0x1700000,0x1400000); if ((iVar4 == 0) || (sVar2 = DAT_fffb1374 + -1, bVar1 = DAT_fffb1374 == 0, DAT_fffb1374 = sVar2, bVar1)) { DAT_fffb1372 = 0x1006; } else { puts(s_DDR_fip_hdr_check_fail__retry__fffad7f6); DAT_fffb1372 = 0x1005; } goto aml_ddr_fw_load_done; } if (DAT_fffb1372 == 0x2103) { iVar4 = check_fw__ns((long)&DAT_fffd0000_ddr_params,(long)&DAT_fffb4000,DAT_fffb1388); if ((iVar4 == 0) || (sVar2 = DAT_fffb1374 + -1, bVar1 = DAT_fffb1374 == 0, DAT_fffb1374 = sVar2, bVar1)) { DAT_fffb1372 = 0x1003; puts(s_AML_DDR_FW_load_done_fffad752); goto aml_ddr_fw_load_done; } puts(s_AML_DDR_FW_check_fail__retry__fffad733); goto LAB_fffa8cc4; } } LAB_fffa8e9c: puts(s_ddr_usb_sub_error_status_fffad816); DAT_fffb1372 = 0xf; aml_ddr_fw_load_done: if (DAT_fffb1372 == 0x1f08) { puts(s_ddr_init_done__boot_next_stage_fffad830); FUN_fffa6ca0(); iVar4 = (*DAT_fffb12b8)(&DAT_fffb1290_); if (iVar4 == 0) { if (*(char *)(DAT_fffb1330 + 7) < '\0') { (*DAT_fffb12c0)(&DAT_fffb1290_); } DAT_fffb1372 = 0x1005; } else { DAT_fffb1372 = 0x1f09; } } if (DAT_fffb1372 == 0x1f09) { uVar5 = FUN_fffa6e3c((long)&DAT_fffb1290_); if (uVar5 == 0xff) { puts(s_Try_next_cfg_fffad850); DAT_fffb1372 = 0x20; return 0x20; } FUN_fffa64d4(&DAT_fffb1290_); FUN_fffa6520((ddr_set_t *)&DAT_fffb1290_); puts(s_ddr_probe_id_done_fffad85e); DAT_fffb1372 = 0; } if (DAT_fffb1374 == 0) { puts(s_DDR_fw_retry_times_end_fffad871); DAT_fffb1372 = DAT_fffb1372 | 0x10; } uVar3 = FUN_fffa8a20((long)&DAT_fffb1290_); return uVar3; } void FUN_fffa8fb8(void) { if (DAT_fffb1372 != 0x3000) { puts(s_DATA_transfer_complete____fffad889); FUN_fffa15ec(); FUN_fffa8b9c(); FUN_fffa1590(5000); return; } return; } void FUN_fffa900c(void) { FUN_fffa9cbc(); FUN_fffa9ccc(); return; } undefined8 FUN_fffa9020(void) { int iVar1; FUN_fffa900c(); do { FUN_fffa15dc(); iVar1 = thunk_FUN_fffa9604(); } while (iVar1 == 0); return 0; } int thunk_FUN_fffa9604(void) { int iVar1; undefined8 uVar2; iVar1 = FUN_fffaa334(); uVar2 = FUN_fffaa368(); return iVar1 + (int)uVar2; } void FUN_fffa9048(long param_1) { uint uVar1; *(undefined *)(param_1 + 0x39) = 1; uVar1 = 2; if (*(char *)(param_1 + 0x38) == '\0') { uVar1 = 1; } FUN_fffa977c(param_1,uVar1); return; } void FUN_fffa9064(void) { return; } void FUN_fffa9068(long param_1,char *param_2) { char cVar1; ushort uVar2; uint uVar3; cVar1 = param_2[1]; uVar2 = *(ushort *)(param_2 + 6); if ((cVar1 == 'P') || (cVar1 == '`')) { if (*param_2 == '@') { *(undefined8 *)(param_1 + 0x10) = 0; *(undefined4 *)(param_1 + 0x18) = 0; *(byte *)(param_1 + 0x3b) = *(byte *)(param_1 + 0x3b) | 1; } } else if (cVar1 == ' ') { DAT_fffb1508 = 0; DAT_fffb1509 = 0; DAT_fffb150a = 1; DAT_fffb150b = 8; DAT_fffb150c = 0; DAT_fffb150d = 1; DAT_fffb150e = 0; DAT_fffb150f = 0; *(undefined **)(param_1 + 0x10) = &DAT_fffb1508; uVar3 = (uint)uVar2; if (8 < uVar2) { uVar3 = 8; } *(uint *)(param_1 + 0x18) = uVar3; } return; } void FUN_fffa90f8(long param_1,long param_2) { int iVar1; uint uVar2; ulong uVar3; if (*(char *)(param_2 + 1) == 'P') { if (DAT_fffb1bcc != 0) { return; } FUN_fffa8970((long)&DAT_fffb2080); DAT_fffb2098 = 0x434c4d41; DAT_fffb209c = DAT_fffb1bc8; DAT_fffb20a0 = DAT_fffb208c; DAT_fffb20a4 = DAT_fffb2088; DAT_fffb20a8 = DAT_fffb2094; DAT_fffb20a9 = DAT_fffb2095; DAT_fffb1bc8 = DAT_fffb1bc8 + 1; memset(&DAT_fffb1508,0,0x200); memcpy((long)&DAT_fffb1508,(long)&DAT_fffb2098,0x14); *(undefined *)(param_1 + 0x38) = 0; *(undefined1 **)(param_1 + 0x20) = &DAT_fffb1508; *(undefined4 *)(param_1 + 0x30) = 0x200; } else { if (*(char *)(param_2 + 1) != '`') { return; } if (DAT_fffb1bcc != 1) { return; } if (DAT_fffb2090 < DAT_fffb208c) { uVar2 = (uint)*(ushort *)(param_2 + 2) * 0x200; if (uVar2 != DAT_fffb2090) { DAT_fffb1bcc = 0; return; } iVar1 = *(ushort *)(param_2 + 4) + 1; if (DAT_fffb208c < iVar1 + uVar2) { DAT_fffb1bcc = 0; return; } uVar3 = (ulong)DAT_fffb2084; *(int *)(param_1 + 0x2c) = (int)(*(ushort *)(param_2 + 4) + 0x1000) >> 0xc; *(ulong *)(param_1 + 0x20) = uVar3 + (long)(int)uVar2; *(int *)(param_1 + 0x30) = iVar1; DAT_fffb1bcc = 2; } else { DAT_fffb1bcc = 3; *(undefined1 **)(param_1 + 0x20) = &DAT_fffb1508; *(undefined4 *)(param_1 + 0x30) = 0x200; } *(undefined *)(param_1 + 0x38) = 1; } FUN_fffa9048(param_1); return; } void FUN_fffa929c(long param_1) { int iVar1; int iVar2; ulong uVar3; uint uVar4; if (*(char *)(param_1 + 1) == 'P') { if (DAT_fffb1bcc != 0) { DAT_fffb1bcc = 0; return; } if (*(char *)(param_1 + 0x38) == '\0') { *(undefined *)(param_1 + 0x3a) = 1; memset(&DAT_fffb1508,0,0x10); *(undefined4 *)(param_1 + 0x30) = 0x10; *(undefined *)(param_1 + 0x38) = 1; *(undefined1 **)(param_1 + 0x20) = &DAT_fffb1508; FUN_fffa9048(param_1); if (DAT_fffb20a9 != '\0') { DAT_fffb20b0 = DAT_fffb2080; DAT_fffb20b4 = 1; FUN_fffa8fb8(); return; } return; } return; } if (*(char *)(param_1 + 1) != '`') { return; } if (DAT_fffb1bcc == 2) { *(undefined *)(param_1 + 0x39) = 0; if (*(int *)(param_1 + 0x2c) < 1) { DAT_fffb1bcc = 0; return; } iVar2 = *(int *)(param_1 + 0x34); iVar1 = *(int *)(param_1 + 0x2c) + -1; *(int *)(param_1 + 0x2c) = iVar1; if ((*(int *)(param_1 + 0x30) < iVar2) || (DAT_fffb208c <= DAT_fffb2090)) { DAT_fffb1bcc = 0; return; } uVar3 = *(ulong *)(param_1 + 0x20); if (uVar3 < DAT_fffb2084) { DAT_fffb1bcc = 0; return; } if ((ulong)DAT_fffb2084 + (ulong)DAT_fffb208c < uVar3) { DAT_fffb1bcc = 0; return; } DAT_fffb2090 = iVar2 + DAT_fffb2090; *(int *)(param_1 + 0x30) = *(int *)(param_1 + 0x30) - iVar2; if (iVar1 != 0) { *(ulong *)(param_1 + 0x20) = uVar3 + (long)iVar2; *(undefined *)(param_1 + 0x38) = 1; goto LAB_fffa953c; } memset(&DAT_fffb1508,0,0x10); memcpy((long)&DAT_fffb1508,(long)s_OKAY_fffad8a4,4); *(undefined *)(param_1 + 0x3a) = 1; *(undefined *)(param_1 + 0x38) = 0; *(undefined1 **)(param_1 + 0x20) = &DAT_fffb1508; } else { if ((DAT_fffb1bcc != 3) || (**(int **)(param_1 + 0x20) != 0x534c4d41)) { DAT_fffb1bcc = 0; return; } *(undefined *)(param_1 + 0x3a) = 1; memcpy(0xfffb2070,(long)*(int **)(param_1 + 0x20),0x10); uVar4 = (uint)(DAT_fffb2074 == DAT_fffb209c); if (((DAT_fffb20a8 & 1) == 0) && (iVar2 = FUN_fffac4a0((int *)(ulong)DAT_fffb2084,DAT_fffb208c), DAT_fffb2078 != iVar2)) { uVar4 = 0; } DAT_fffb20b4 = uVar4; memset(&DAT_fffb1508,0,0x10); if (uVar4 == 0) { memcpy((long)&DAT_fffb1508,(long)s_FAIL_fffad8a9,4); } else { memcpy((long)&DAT_fffb1508,(long)s_OKAY_fffad8a4,4); DAT_fffb20b0 = DAT_fffb2080; FUN_fffa8fb8(); } *(undefined *)(param_1 + 0x38) = 0; *(undefined1 **)(param_1 + 0x20) = &DAT_fffb1508; } *(undefined4 *)(param_1 + 0x30) = 0x10; LAB_fffa953c: FUN_fffa9048(param_1); return; } void FUN_fffa9568(long param_1) { uint uVar1; *(undefined *)(param_1 + 0x3a) = 0; if (*(char *)(param_1 + 1) == 'P') { if (DAT_fffb1bcc == 0) { if ((*(char *)(param_1 + 0x38) != '\0') && (uVar1 = FUN_fffac64c(*(long *)(param_1 + 0x20),(long)s_OKAY_fffad8a4,4), uVar1 == 0)) { DAT_fffb1bcc = 1; } } else { DAT_fffb1bcc = 0; } } else if (*(char *)(param_1 + 1) == '`') { if (DAT_fffb1bcc == 2) { DAT_fffb1bcc = 1; } else { DAT_fffb1bcc = 0; } } return; } int FUN_fffa9604(void) { int iVar1; undefined8 uVar2; iVar1 = FUN_fffaa334(); uVar2 = FUN_fffaa368(); return iVar1 + (int)uVar2; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa962c(uint param_1) { int iVar1; _DAT_ff400010 = (param_1 & 0x1f) << 6 | 0x20; iVar1 = 0x2711; do { iVar1 = iVar1 + -1; } while (iVar1 != 0); loop_forever1(); return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa9664(byte *param_1) { uint uVar1; byte bVar2; uint uVar3; uint uVar4; int iVar5; uint uVar6; uint uVar7; uVar7 = *(uint *)(param_1 + 0x18) & 0x7ffff; bVar2 = param_1[1]; *(uint *)(param_1 + 0x20) = *(uint *)(param_1 + 0x20) & 0xfff80000 | *(uint *)(param_1 + 0x18) & 0x7ffff; uVar6 = *(ushort *)(param_1 + 2) >> 4 & 0x7ff; if ((bVar2 & 1) == 0) { iVar5 = *param_1 + 0x58; } else { iVar5 = *param_1 + 0x48; } uVar3 = iVar5 * 0x20; uVar1 = *(uint *)((ulong)(uVar3 + 0x10) + 0xff400000); if (uVar7 == 0) { if ((bVar2 & 1) != 0) { uVar6 = 0; } uVar6 = uVar1 & 0xe0000000 | uVar6 | 0x80000; } else { uVar4 = 0; if ((*(ushort *)(param_1 + 2) >> 4 & 0x7ff) != 0) { uVar4 = (int)(uVar7 + (uVar6 - 1)) / (int)uVar6; } if (((bVar2 & 1) == 0) || (uVar6 <= uVar7)) { uVar7 = uVar7 - (*(uint *)(param_1 + 0x1c) & 0x7ffff); } uVar6 = uVar1 & 0xe0000000 | (uVar4 & 0x3ff) << 0x13 | uVar7 & 0x7ffff; } *(uint *)((ulong)(uVar3 + 0x10) + 0xff400000) = uVar6; *(uint *)((ulong)uVar3 + 0xff400000) = *(uint *)((ulong)uVar3 + 0xff400000) | 0x84000000; if ((bVar2 & 1) != 0) { _DAT_ff400014 = _DAT_ff400014 & 0xffffffdf; _DAT_ff400018 = _DAT_ff400018 | 0x20; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffa977c(long param_1,uint param_2) { int iVar1; uint uVar2; byte bVar3; undefined8 uVar4; uint uVar5; long lVar6; long lVar7; uint local_10; lVar6 = (long)(int)param_2; lVar7 = lVar6 * 0x28; (&DAT_fffb20f8)[lVar7] = (char)param_2; if (param_2 == 0) { if (*(int *)(param_1 + 8) != 2) { if (*(int *)(param_1 + 8) != 3) { return 0xffffffff; } if (((*(byte *)(param_1 + 0x3b) & 1) != 0) || (*(int *)(param_1 + 0x18) == 0)) { (&DAT_fffb20f9)[lVar7] = (&DAT_fffb20f9)[lVar7] | 1; *(undefined4 *)(param_1 + 8) = 4; } } uVar4 = *(undefined8 *)(param_1 + 0x10); uVar5 = *(uint *)(param_1 + 0x18); (&DAT_fffb2100)[lVar6 * 5] = uVar4; (&DAT_fffb2108)[lVar6 * 5] = uVar4; uVar5 = uVar5 & 0x7ffff; (&DAT_fffb2110)[lVar6 * 10] = (&DAT_fffb2110)[lVar6 * 10] & 0xfff80000 | uVar5; uVar2 = (&DAT_fffb2114)[lVar6 * 10]; (&DAT_fffb2114)[lVar6 * 10] = uVar2 & 0xfff80000; *(byte *)((long)&DAT_fffb2114 + lVar7 + 2) = (byte)((uVar2 & 0xfff80000) >> 0x10) & 0xf7; bVar3 = *(byte *)(&DAT_fffb20fa + lVar6 * 0x14); (&DAT_fffb2118)[lVar6 * 10] = (&DAT_fffb2118)[lVar6 * 10] & 0xfff80000 | uVar5; *(byte *)(&DAT_fffb20fa + lVar6 * 0x14) = bVar3 & 0xf; *(byte *)((long)&DAT_fffb20fa + lVar7 + 1) = *(byte *)((long)&DAT_fffb20fa + lVar7 + 1) & 0x80 | 4; } else { uVar4 = *(undefined8 *)(param_1 + 0x20); uVar5 = *(uint *)(param_1 + 0x30); (&DAT_fffb2100)[lVar6 * 5] = uVar4; (&DAT_fffb2108)[lVar6 * 5] = uVar4; if (0x1000 < (int)uVar5) { uVar5 = 0x1000; } (&DAT_fffb2110)[lVar6 * 10] = (&DAT_fffb2110)[lVar6 * 10] & 0xfff80000 | uVar5 & 0x7ffff; uVar2 = (&DAT_fffb2114)[lVar6 * 10]; (&DAT_fffb2114)[lVar6 * 10] = uVar2 & 0xfff80000; *(byte *)((long)&DAT_fffb2114 + lVar7 + 2) = (byte)((uVar2 & 0xfff80000) >> 0x10) & 0xf7; (&DAT_fffb2118)[lVar6 * 10] = (&DAT_fffb2118)[lVar6 * 10] & 0xfff80000 | uVar5 & 0x7ffff; *(byte *)(&DAT_fffb20fa + lVar6 * 0x14) = *(byte *)(&DAT_fffb20fa + lVar6 * 0x14) & 0xf; *(byte *)((long)&DAT_fffb20fa + lVar7 + 1) = *(byte *)((long)&DAT_fffb20fa + lVar7 + 1) & 0x80 | 0x20; (&DAT_fffb20f9)[lVar7] = (&DAT_fffb20f9)[lVar7] & 0xfe | param_2 == 1; if (param_2 == 1) { iVar1 = (param_2 & 0xff) + 0x48; uVar5 = 2; } else { iVar1 = (param_2 & 0xff) + 0x58; uVar5 = 0x40000; } local_10 = iVar1 * 0x20; uVar2 = *(uint *)((ulong)local_10 + 0xff400000); if ((uVar2 >> 0xf & 1) == 0) { *(uint *)((ulong)local_10 + 0xff400000) = uVar2 & 0xfc300000 | uVar2 & 0x3f800 | 0x80200 | 0x10008000; } _DAT_ff40081c = uVar5 | _DAT_ff40081c; } FUN_fffa9664(&DAT_fffb20f8 + lVar7); return 0; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa9960(void) { _DAT_ff400b10 = 0x60080018; _DAT_ff400b00 = 0x80008000; return; } void FUN_fffa99a0(int *param_1) { if (*param_1 != 5) { *param_1 = 4; DAT_fffb2110 = DAT_fffb2110 & 0xfff80000; DAT_fffb2114 = DAT_fffb2114 & 0xfff80000; DAT_fffb20f9 = DAT_fffb20f9 | 1; FUN_fffa9664(&DAT_fffb20f8); FUN_fffa9960(); return; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffa99fc(void) { if (DAT_fffb20c0 == 4) { DAT_fffb2100 = 0; DAT_fffb2110 = DAT_fffb2110 & 0xfff80000; DAT_fffb2108 = 0; } else { if ((DAT_fffb2110 & 0x7ffff) != 0) { if ((DAT_fffb20f9 & 1) == 0) { FUN_fffa99a0(&DAT_fffb20c0); } else if (((_DAT_ff400910 & 0x7f) == 0) && (DAT_fffb20c0 != 5)) { DAT_fffb20c0 = 4; DAT_fffb2110 = DAT_fffb2110 & 0xfff80000; DAT_fffb20f9 = DAT_fffb20f9 & 0xfe; DAT_fffb2114 = DAT_fffb2114 & 0xfff80000; FUN_fffa9664(&DAT_fffb20f8); FUN_fffa9960(); } return 0; } DAT_fffb2114 = DAT_fffb2114 & 0xfff80000 | 0x80000; FUN_fffa9664(&DAT_fffb20f8); } return 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa9ad8(void) { ulong uVar1; byte bVar2; undefined8 local_10; bVar2 = DAT_fffb20f3; switch(DAT_fffb20c0) { case 1: local_10 = DAT_fffb20b8; uVar1 = local_10; bVar2 = DAT_fffb20f3 & 0xfe; if ((DAT_fffb20f3 >> 1 & 1) != 0) { DAT_fffb20f3 = DAT_fffb20f3 & 0xfc; local_10._0_1_ = (char)DAT_fffb20b8; DAT_fffb20c4 = 0; if ((char)local_10 < '\0') { DAT_fffb20f9 = DAT_fffb20f9 | 1; DAT_fffb20c0 = 2; } else { DAT_fffb20f9 = DAT_fffb20f9 & 0xfe; DAT_fffb20c0 = 3; } local_10 = uVar1; if ((DAT_fffb20b8 & 0x60) == 0) { local_10._1_1_ = (undefined)(DAT_fffb20b8 >> 8); switch(local_10._1_1_) { case 0: DAT_fffb20c8 = &DAT_fffb20c4; DAT_fffb20c4 = 0; DAT_fffb20d0 = 2; break; case 5: if ((char)local_10 != '\0') { DAT_fffb20c4 = 0; return; } local_10._2_2_ = (ushort)(DAT_fffb20b8 >> 0x10); _DAT_ff400800 = (local_10._2_2_ & 0x7f) << 4 | _DAT_ff400800; FUN_fffa99a0(&DAT_fffb20c0); return; case 9: case 0xb: DAT_fffb20f3 = DAT_fffb20f3 | 1; default: FUN_fffa9064(); } } else { FUN_fffa9068((long)&DAT_fffb20b8,(char *)&local_10); } FUN_fffa977c((long)&DAT_fffb20b8,0); bVar2 = DAT_fffb20f3; } break; case 2: if ((DAT_fffb2118 & 0x7ffff) <= (DAT_fffb2114 & 0x7ffff)) { FUN_fffa99fc(); bVar2 = DAT_fffb20f3; } break; case 3: FUN_fffa99fc(); FUN_fffa90f8((long)&DAT_fffb20b8,(long)&DAT_fffb20b8); bVar2 = DAT_fffb20f3; break; case 4: FUN_fffa99fc(); FUN_fffa90f8((long)&DAT_fffb20b8,(long)&DAT_fffb20b8); DAT_fffb20c0 = 1; DAT_fffb20f9 = DAT_fffb20f9 & 0xfe | 4; bVar2 = DAT_fffb20f3; } DAT_fffb20f3 = bVar2; return; } void FUN_fffa9cbc(void) { DAT_fffb20c0 = 1; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa9ccc(void) { if ((_DAT_ff400920 >> 0xf & 1) == 0) { _DAT_ff400920 = _DAT_ff400920 & 0xfc300000 | _DAT_ff400920 & 0x3f800 | 0x80200 | 0x10008000; } if ((_DAT_ff400b40 >> 0xf & 1) == 0) { _DAT_ff400b40 = _DAT_ff400b40 & 0xfc300000 | _DAT_ff400b40 & 0x3f800 | 0x80200 | 0x10008000; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa9d40(ulong param_1,ushort param_2) { ulong uVar1; uint uVar2; uVar1 = param_1 & 3; if (uVar1 == 0) { for (; (int)uVar1 < (int)(uint)param_2; uVar1 = uVar1 + 4) { *(uint *)(param_1 + uVar1) = _DAT_ff401000; } } else { uVar2 = 0; for (uVar1 = 0; (int)uVar1 < (int)(uint)param_2; uVar1 = uVar1 + 1) { if ((uVar1 & 3) == 0) { uVar2 = _DAT_ff401000; } *(char *)(param_1 + uVar1) = (char)uVar2; uVar2 = uVar2 >> 8; } } return; } void FUN_fffa9da4(byte *param_1) { byte *pbVar1; byte *pbVar2; byte *pbVar3; uint uVar4; byte bVar5; byte *pbVar6; uint uVar7; byte *pbVar8; uint local_c; pbVar8 = *(byte **)(param_1 + 0x10); if ((*(uint *)(param_1 + 0x1c) & 0x7ffff) < (*(uint *)(param_1 + 0x18) & 0x7ffff)) { uVar7 = (*(uint *)(param_1 + 0x18) & 0x7ffff) - (*(uint *)(param_1 + 0x1c) & 0x7ffff); uVar4 = *(ushort *)(param_1 + 2) >> 4 & 0x7ff; if ((int)uVar7 < (int)uVar4) { uVar4 = uVar7; } bVar5 = *param_1; pbVar6 = pbVar8; for (uVar7 = 0; local_c = (bVar5 + 1) * 0x1000, uVar7 != uVar4 + 3 >> 2; uVar7 = uVar7 + 1) { pbVar1 = pbVar6 + 2; pbVar2 = pbVar6 + 1; bVar5 = *pbVar6; pbVar3 = pbVar6 + 3; pbVar6 = pbVar6 + 4; *(uint *)((ulong)local_c + 0xff400000) = (uint)*pbVar1 << 0x10 | (uint)*pbVar2 << 8 | (uint)bVar5 | (uint)*pbVar3 << 0x18; bVar5 = *param_1; } *(uint *)(param_1 + 0x1c) = *(uint *)(param_1 + 0x1c) & 0xfff80000 | uVar4 + (*(uint *)(param_1 + 0x1c) & 0x7ffff) & 0x7ffff; *(byte **)(param_1 + 0x10) = pbVar8 + uVar4; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffa9e78(undefined4 *param_1) { *param_1 = _DAT_ff401000; param_1[1] = _DAT_ff401000; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffa9e9c(void) { bool bVar1; uint uVar2; undefined *puVar3; uint uVar4; uint uVar5; undefined auStack_10 [16]; uVar5 = _DAT_ff400020; _DAT_ff400018 = _DAT_ff400018 & 0xffffffef; uVar4 = _DAT_ff400020 & 0xf; if (uVar4 < 4) { puVar3 = &DAT_fffb20f8; if (uVar4 != 0) { puVar3 = &DAT_fffb20f8 + (long)(int)uVar4 * 0x28; } uVar4 = _DAT_ff400020 >> 0x11 & 0xf; if (uVar4 == 2) { uVar4 = _DAT_ff400020 >> 4 & 0x7ff; if ((uVar4 != 0) && (*(ulong *)(puVar3 + 0x10) != 0)) { if ((*(uint *)(puVar3 + 0x1c) & 0x7ffff) < (*(uint *)(puVar3 + 0x18) & 0x7ffff)) { uVar5 = (*(uint *)(puVar3 + 0x18) & 0x7ffff) - (*(uint *)(puVar3 + 0x1c) & 0x7ffff); if ((int)uVar5 < (int)uVar4) { uVar2 = uVar5 + 3 & 0xfffffffc; bVar1 = uVar4 <= uVar2; uVar4 = uVar4 - uVar2; if (bVar1) { uVar4 = 0; } } else { uVar5 = uVar4; uVar4 = 0; } FUN_fffa9d40(*(ulong *)(puVar3 + 0x10),(ushort)uVar5); *(uint *)(puVar3 + 0x1c) = *(uint *)(puVar3 + 0x1c) & 0xfff80000 | uVar5 + (*(uint *)(puVar3 + 0x1c) & 0x7ffff) & 0x7ffff; *(ulong *)(puVar3 + 0x10) = *(long *)(puVar3 + 0x10) + (ulong)uVar5; } for (; uVar4 != 0; uVar4 = uVar4 - uVar5) { uVar5 = uVar4; if (4 < uVar4) { uVar5 = 4; } FUN_fffa9d40((ulong)auStack_10,(ushort)uVar5); } } } else if (uVar4 == 6) { FUN_fffa9e78((undefined4 *)&DAT_fffb20b8); DAT_fffb20f3 = DAT_fffb20f3 | 2; *(uint *)(puVar3 + 0x1c) = *(uint *)(puVar3 + 0x1c) & 0xfff80000 | (*(uint *)(puVar3 + 0x1c) & 0x7ffff) + (uVar5 >> 4 & 0x7ff) & 0x7ffff; } } _DAT_ff400018 = _DAT_ff400018 | 0x10; _DAT_ff400014 = 0x10; return 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffaa028(void) { uint uVar1; uint uVar2; long lVar3; int iVar4; lVar3 = 0; do { if (((((int)lVar3 == 0) || (((&DAT_fffb20f9)[lVar3 * 0x28] & 1) != 0)) && (*(int *)((lVar3 + 0x7fa0048) * 0x20) < 0)) && (((*(byte *)(&DAT_fffb20fa + lVar3 * 0x14) & 3) != 3 || (((&DAT_fffb2110)[lVar3 * 10] & 0x7ffff) != 0)))) { uVar1 = ((&DAT_fffb2110)[lVar3 * 10] & 0x7ffff) - ((&DAT_fffb2114)[lVar3 * 10] & 0x7ffff); uVar2 = (ushort)(&DAT_fffb20fa)[lVar3 * 0x14] >> 4 & 0x7ff; if (uVar2 < uVar1) { uVar1 = uVar2; } while (((&DAT_fffb2114)[lVar3 * 10] & 0x7ffff) < ((&DAT_fffb2110)[lVar3 * 10] & 0x7ffff)) { iVar4 = 1000; while( true ) { iVar4 = iVar4 + -1; if (iVar4 == -1) goto LAB_fffaa05c; if (((_DAT_ff40002c >> 0x10 & 0xff) != 0) && (uVar1 + 3 >> 2 < (_DAT_ff40002c & 0xffff))) break; loop_forever1(); } if (iVar4 == 0) break; FUN_fffa9da4(&DAT_fffb20f8 + lVar3 * 0x28); uVar1 = ((&DAT_fffb2110)[lVar3 * 10] & 0x7ffff) - ((&DAT_fffb2114)[lVar3 * 10] & 0x7ffff); uVar2 = (ushort)(&DAT_fffb20fa)[lVar3 * 0x14] >> 4 & 0x7ff; if (uVar2 < uVar1) { uVar1 = uVar2; } } } LAB_fffaa05c: lVar3 = lVar3 + 1; if (lVar3 == 4) { _DAT_ff400014 = 0x20; return 1; } } while( true ); } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffaa184(void) { _DAT_ff400900 = _DAT_ff400900 & 0xfffff800; _DAT_ff400b00 = _DAT_ff400b00 | 0x80000000; _DAT_ff400804 = _DAT_ff400804 | 0x100; DAT_fffb20c0 = 1; _DAT_ff40000c = _DAT_ff40000c & 0xffffc000 | _DAT_ff40000c & 0x3ff | 0x2400; _DAT_ff400014 = 0x2000; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffaa218(void) { int *piVar1; _DAT_ff400804 = _DAT_ff400804 & 0xfffffffe; piVar1 = (int *)&DAT_ff400900; do { if (*piVar1 < 0) { *piVar1 = 0x48000000; } piVar1 = piVar1 + 8; } while (piVar1 != (int *)0xff400980); _DAT_ff400b00 = 0x8000000; _DAT_ff400b20 = 0x8000000; _DAT_ff400b40 = 0x8000000; _DAT_ff400b60 = 0x8000000; FUN_fffa962c(0); _DAT_ff400010 = 8; _DAT_ff40081c = 0x10001; _DAT_ff400814 = 0xf; _DAT_ff400810 = 0xf; _DAT_ff400800 = _DAT_ff400800 & 0xfffff80f; FUN_fffa9960(); _DAT_ff400014 = 0x1000; return 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffaa31c(void) { _DAT_ff400014 = 0x800; return 1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined4 FUN_fffaa334(void) { undefined4 uVar1; uVar1 = 0; if ((_DAT_ff400004 != 0) && (uVar1 = 0xb, (_DAT_ff400004 >> 2 & 1) == 0)) { uVar1 = 0; } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffaa368(void) { uint uVar1; uint uVar2; long lVar3; uint uVar4; int iVar5; ulong uVar6; uint uVar7; uint uVar8; uVar8 = _DAT_ff400014 & _DAT_ff400018; uVar4 = _DAT_ff400014; if (uVar8 != 0) { if ((uVar8 >> 4 & 1) != 0) { FUN_fffa9e9c(); } if ((uVar8 >> 5 & 1) != 0) { FUN_fffaa028(); } if ((uVar8 >> 0xc & 1) != 0) { FUN_fffaa218(); } if ((uVar8 >> 0xb & 1) != 0) { FUN_fffaa31c(); } if ((uVar8 >> 0xd & 1) != 0) { FUN_fffaa184(); } if ((uVar8 >> 0x12 & 1) != 0) { uVar7 = _DAT_ff400818 & _DAT_ff40081c; _DAT_ff400014 = 0x40000; _DAT_ff400818 = 0xffff; uVar4 = 0; for (uVar7 = uVar7 & 0xffff; uVar7 != 0; uVar7 = uVar7 >> 1) { if ((uVar7 & 1) != 0) { uVar6 = (ulong)(uVar4 * 0x20 + 0x908); uVar1 = *(uint *)(uVar6 + 0xff400000) & _DAT_ff400810; if ((uVar1 & 1) != 0) { _DAT_ff400018 = _DAT_ff400018 & 0xffffffdf; *(undefined4 *)(uVar6 + 0xff400000) = 1; if (uVar4 == 0) { FUN_fffa9ad8(); } else { lVar3 = (long)(int)uVar4; uVar2 = (&DAT_fffb2110)[lVar3 * 10]; DAT_fffb20ec = uVar2 & 0x7ffff; if (((*(uint *)((long)(int)(uVar4 * 0x20 + 0x910) + 0xff400000) & 0x1fffffff) == 0) && (((&DAT_fffb2114)[lVar3 * 10] & 0x7ffff) == DAT_fffb20ec)) { (&DAT_fffb2100)[lVar3 * 5] = 0; (&DAT_fffb2108)[lVar3 * 5] = 0; (&DAT_fffb2110)[lVar3 * 10] = uVar2 & 0xfff80000; } if (DAT_fffb20f2 == '\0') { FUN_fffa929c((long)&DAT_fffb20b8); } else { FUN_fffa9568((long)&DAT_fffb20b8); } } } if ((uVar1 >> 1 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 2; } if ((uVar1 >> 2 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 4; } if ((uVar1 >> 3 & 1) != 0) { _DAT_ff400018 = _DAT_ff400018 & 0xffffffdf; if (uVar4 != 0) { _DAT_ff400018 = _DAT_ff400018 | 0x60; _DAT_ff400804 = _DAT_ff400804 | 0x80; (&DAT_fffb20f9)[(ulong)uVar4 * 0x28] = (&DAT_fffb20f9)[(ulong)uVar4 * 0x28] | 4; } *(undefined4 *)(uVar6 + 0xff400000) = 8; } if ((uVar1 >> 4 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 0x10; } if ((uVar1 >> 5 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 0x20; } if ((uVar1 >> 6 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 0x40; } } uVar4 = uVar4 + 1; } } uVar4 = uVar8; if ((uVar8 >> 0x13 & 1) != 0) { uVar8 = _DAT_ff40081c & _DAT_ff400818; _DAT_ff400014 = 0x80000; _DAT_ff400818 = 0xffff0000; iVar5 = 0; for (uVar8 = uVar8 >> 0x10; uVar8 != 0; uVar8 = uVar8 >> 1) { if ((uVar8 & 1) != 0) { uVar6 = (ulong)(iVar5 * 0x20 + 0xb08); uVar7 = *(uint *)(uVar6 + 0xff400000) & _DAT_ff400814; if ((uVar7 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 1; if (iVar5 == 0) { FUN_fffa9ad8(); if ((uVar7 >> 3 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 8; uVar7 = uVar7 & 0xfffffff7; } } else { lVar3 = (long)iVar5; uVar1 = (&DAT_fffb2114)[lVar3 * 10]; (&DAT_fffb2100)[lVar3 * 5] = 0; DAT_fffb20ec = uVar1 & 0x7ffff; uVar1 = (&DAT_fffb2110)[lVar3 * 10]; (&DAT_fffb2108)[lVar3 * 5] = 0; (&DAT_fffb2110)[lVar3 * 10] = uVar1 & 0xfff80000; if (DAT_fffb20f2 == '\0') { FUN_fffa929c((long)&DAT_fffb20b8); } else { FUN_fffa9568((long)&DAT_fffb20b8); } } } if ((uVar7 >> 1 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 2; } if ((uVar7 >> 2 & 1) != 0) { *(undefined4 *)(uVar6 + 0xff400000) = 4; } if ((uVar7 >> 3 & 1) != 0) { FUN_fffa9ad8(); *(undefined4 *)(uVar6 + 0xff400000) = 8; } } iVar5 = iVar5 + 1; } } } _DAT_ff400014 = uVar4; return 0; } long FUN_fffaa71c(long param_1,int param_2,char *param_3) { long lVar1; uint uVar2; long lVar3; long lVar4; lVar3 = FUN_fffac630(param_3); lVar1 = param_1; do { lVar4 = lVar1; if (param_2 - (int)lVar3 <= (int)lVar4 - (int)param_1) { return param_1; } uVar2 = FUN_fffac64c((long)param_3,lVar4,(long)(int)lVar3); lVar1 = lVar4 + 1; } while (uVar2 != 0); return lVar4; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 FUN_fffaa794(long param_1) { ulong uVar1; undefined8 uVar2; void *dst; uVar1 = FUN_fffaa71c(*(long *)(param_1 + 8),*(int *)(param_1 + 0x10),s__MEMDUMP_fffad8c0); puts(s_bl2z_ptr__fffad8c9); put_hex(uVar1,0x20); puts(s__fffadb47 + 1); puts(s_img_info__image_base__fffad8d4); put_hex(*(ulong *)(param_1 + 8),0x20); puts(s__fffadb47 + 1); if (uVar1 == *(ulong *)(param_1 + 8)) { puts(s_NO_BL2z__fffad900); uVar2 = 0; } else { dst = (void *)(uVar1 - 4); uVar2 = 0; uVar1 = (ulong)((*(int *)(param_1 + 0x10) + (int)*(ulong *)(param_1 + 8)) - (int)dst); if ((_AO_UNK_ff80000c & 0xf) - 0xc < 2) { memcpy(0x5200000,(long)dst,uVar1); uVar2 = 0x5200000; } memset(dst,0,uVar1); puts(s_bl2z__ptr__fffad8eb); put_hex((ulong)dst,0x20); puts(s___size__fffad8f7); put_hex(uVar1,0x20); puts(s__fffadb47 + 1); } return uVar2; } void FUN_fffaa8cc(undefined *param_1) { int iVar1; iVar1 = DAT_fffaf008; if (DAT_fffaf008 != 0) { puts(s_jump_to_BL2z__fffad90a); put_hex((ulong)param_1,0x20); puts(s__fffadb47 + 1); (*(code *)param_1)(iVar1,0,0,0); puts(s_return_to_BL2_fffad918); return; } return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void handle_smc_call__ns(void) { ulong uVar1; char *s; if ((_DAT_ff80025c >> 0x18 & 1) == 0) { s = s_Handler_is_not_supported_fffad92f; } else { uVar1 = FUN_fffac9c4(); puts(s_smccc__fffad927); put_hex(uVar1 & 0xffffffff,0x20); s = s__fffadb47 + 1; } puts(s); return; } void FUN_fffaa9c4(void) { uint uVar1; uVar1 = is_verified_boot_enabled(); if ((uVar1 == 0) && (uVar1 = get_boot_device(), uVar1 == 5)) { puts(s_USB_mode__fffad949); FUN_fffa9020(); return; } /* "reset..." */ puts(s_fip_hdr_data_lost__reset____fffad1fd + 0x13); loop_forever2(); return; } uint fip_hdr_check__ns(undefined8 *ddrfw_fip,ulong param_2,int param_3) { byte bVar1; uint ret; undefined *puVar2; int i; long lVar3; /* ************************************************************************* * Usage: FUN_fffaaa08((ulong)&DAT_fffd0000,(ulong)&DAT_fffdc000,iVar8); * ************************************************************************* */ Empty_fffac950(); ret = FUN_fffab878((ulong)ddrfw_fip,param_2); lVar3 = param_2 + 0x20; i = 0; while ((i < 4 && (ret == 0))) { if (i == 0) { puVar2 = &DAT_fffadb78; } else if (i == 1) { puVar2 = &DAT_fffadb98; } else { puVar2 = &DAT_fffadb88; if (i != 2) { puVar2 = &DAT_fffadba8; } } bVar1 = FUN_fffac694((long)puVar2,lVar3); ret = (uint)bVar1; lVar3 = lVar3 + 0x28; if (bVar1 != 0) goto fip_hdr_check_error; i = i + 1; } if (ret != 0) { fip_hdr_check_error: serial_print(s_FIP_HDR_CHK__0x_fffad954,ret,0,(char *)0x0); serial_print(s__ADDR_0x_fffad964,(uint)ddrfw_fip,0,s__fffadb47 + 1); if (param_3 != 0) { FUN_fffaa9c4(); } } FUN_fffac954(); return ret; } uint FUN_fffaab1c(long param_1,long param_2,long param_3,uint param_4,int param_5) { uint i; Empty_fffac950(); i = FUN_fffaba20(param_1,param_2,param_3,param_4); if (i != 0) { s_BL3x_CHK__0x_fffad96d[3] = (char)param_4 + 0x30U & 0x33; serial_print(s_BL3x_CHK__0x_fffad96d,i,0,(char *)0x0); serial_print(s__ADDR_fffad97a,(uint)param_2,0,s__fffadb47 + 1); if (param_5 != 0) { FUN_fffaa9c4(); } } FUN_fffac954(); return i; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffaabc4(long param_1,long param_2,int param_3) { long lVar1; uint uVar2; uint uVar3; undefined1 *puVar4; undefined *puVar5; ulong uVar6; long lVar7; uint uVar8; long lVar9; int iVar10; long lVar11; undefined *puVar12; undefined8 local_50; undefined8 local_48; uint local_40; undefined8 local_38; ulong local_30; int local_20; char *local_18; undefined8 local_10; if ((param_1 == 0) || (param_2 == 0)) { uVar8 = 0xfffffffe; } else { local_20 = param_3; puVar4 = FUN_fffa1078(); puVar5 = FUN_fffa1180(); if ((puVar5 == (undefined *)0x0) || (puVar4 == (undefined1 *)0x0)) { uVar8 = 0xfffffffd; } else { *(undefined1 **)(puVar5 + 0x18) = puVar4; uVar8 = 3; local_18 = s_bl30_fffad981; local_40 = 0; lVar9 = param_1; do { lVar1 = param_2 + *(long *)(lVar9 + 0xa8); uVar6 = *(ulong *)(lVar9 + 0xb0); if ((0x3fffff < lVar1 - 0x1700000U) || (0x3fffff < ((uVar6 & 0xffffffff) - 0x1700000) + lVar1)) { return 0xffffffff; } if (uVar8 == 2) { if (uVar6 != 0) { puVar12 = *(undefined **)(puVar4 + 0x10); lVar11 = *(long *)(puVar4 + 0x18); if ((puVar12 == (undefined *)0x0) || (lVar11 == 0)) { return 0x191; } *(undefined8 *)(lVar11 + 8) = 0x5300000; local_10 = 0x5300000; FUN_fffa1310(lVar11,(long)puVar12); local_48 = 0x1400000; local_50 = local_10; local_38 = local_10; local_30 = 0x2000000; local_40 = uVar8; goto LAB_fffaad94; } } else { if (uVar8 == 3) { puVar12 = *(undefined **)(puVar4 + 0x20); lVar11 = *(long *)(puVar4 + 0x28); if ((puVar12 == (undefined *)0x0) || (lVar11 == 0)) { return 0x19f; } *(undefined8 *)(lVar11 + 8) = 0x1000000; FUN_fffa1324(lVar11,(long)puVar12); } else { if (uVar8 != 1) { uVar2 = FUN_fffa13e4(lVar1,(uint)uVar6,0x1000); if (uVar2 != 0) { return uVar2; } iVar10 = 600; do { iVar10 = iVar10 + -1; if (iVar10 == 0) { puts(s__BL30_init_fail__fffad986); return 0x173; } loop_forever1(); } while ((_DAT_ff80023c >> 0x14 & 3) != 3); goto LAB_fffaae4c; } lVar11 = *(long *)(puVar4 + 8); if (lVar11 == 0) { return 0x17f; } *(undefined8 *)(lVar11 + 8) = 0x5100000; FUN_fffa12f8(lVar11,(long)puVar5); local_48 = 0x200000; local_38 = 0x5000000; local_50 = 0x5100000; local_30 = 0x300000; puVar12 = puVar5; local_40 = uVar8; } LAB_fffaad94: if (local_40 != 0) { FUN_fffa60f8(&local_50,(ulong)(local_40 - 1 & 1)); if ((local_40 >> 1 & 1) == 0) { uVar6 = 0x254; } else { uVar6 = 0x250; } *(int *)(uVar6 | 0xff800000) = (int)local_38; uVar2 = 0xffff; if ((local_40 & 2) != 0) { uVar2 = 0xffff0000; } uVar3 = (uint)(local_30 >> 10); if ((local_40 & 1) != 0) { uVar3 = uVar3 << 0x10; } _DAT_ff80024c = uVar3 | uVar2 & _DAT_ff80024c; local_40 = 0; } lVar7 = *(long *)(lVar11 + 8); *(long *)(puVar12 + 8) = lVar7; *(int *)(lVar11 + 0x10) = (int)*(undefined8 *)(lVar9 + 0xb0) + -0x290; uVar2 = FUN_fffaab1c(param_1,lVar1,lVar7,uVar8,local_20); if (uVar2 != 0) { return uVar2; } FUN_fffa6124(); } LAB_fffaae4c: uVar8 = uVar8 - 1; lVar9 = lVar9 + -0x28; } while (uVar8 != 0xffffffff); uVar8 = 0; } } return uVar8; } undefined8 FUN_fffaaeac(void) { uint uVar1; undefined *puVar2; char *s; thunk_FUN_fffa5fc8(); uVar1 = FUN_fffaabc4(0x1400000,0x1700000,0); if ((uVar1 & 0xff) == 0) { puVar2 = FUN_fffa1180(); FUN_fffa1260(); Empty_fffac950(); FUN_fffa15ec(); s = s_USB_BOOT___SHOULD_NEVER_BE_HERE_fffad9bc; if (puVar2 != (undefined *)0x0) { puts(s_run_into_bl31_fffad9ad); s = (char *)FUN_fffac9c0(); } } else { s = s_BL3x_process_error__fffad998; } puts(s); return 0xff; } uint FUN_fffaaf44(long param_1,long param_2,int param_3) { byte bVar1; uint uVar3; undefined1 *puVar4; undefined *puVar5; long lVar6; uint uVar2; if (((param_1 != 0) && (param_2 != 0)) && (puVar4 = FUN_fffa1078(), puVar4 != (undefined1 *)0x0)) { bVar1 = FUN_fffac694((long)&DAT_fffadb98,param_1 + 0x48); uVar2 = (uint)bVar1; if (bVar1 != 0) { return uVar2; } lVar6 = *(long *)(puVar4 + 8); if (lVar6 != 0) { *(int *)(lVar6 + 0x10) = (int)*(undefined8 *)(param_1 + 0x60) + -0x290; *(undefined8 *)(lVar6 + 8) = 0x5100000; uVar3 = FUN_fffaab1c(param_1,param_2,0x5100000,1,param_3); if (uVar3 != 0) { return uVar3; } puVar5 = (undefined *)FUN_fffaa794(lVar6); if (puVar5 == (undefined *)0x0) { return uVar2; } FUN_fffaa8cc(puVar5); return uVar2; } } return 0xffffffff; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffab000(void) { int iVar1; byte bVar2; byte bVar3; uint uVar4; uint uVar5; ulong src; uint uVar6; int iVar7; uint uVar8; long lVar9; bVar3 = DAT_fffb1c42; bVar2 = DAT_fffb1c40; uVar6 = 0; iVar7 = 0; uVar8 = (uint)DAT_fffb1c40; do { uVar5 = (uint)bVar2; if (uVar8 < (uVar6 & 0xff) || uVar5 == (uVar6 & 0xff)) { return; } iVar1 = 0; if (uVar5 != 0) { iVar1 = (int)(uVar6 + bVar3) / (int)uVar5; } uVar5 = (uVar6 + bVar3) - iVar1 * uVar5; if (uVar6 == uVar8 - 1) { iVar7 = 1; } storage_load(0x10000,0x5100000,0x4000,s_FIP_TMP_HDR_fffad9dd,uVar5); uVar4 = fip_hdr_check__ns((undefined8 *)0x5100000,0x5100000,iVar7); if ((uVar4 & 0xff) == 0) { src = (ulong)(((int)_DAT_05100058 - 0xfffU & 0xfffff000) + 0x10000); lVar9 = _DAT_05100058 - src; storage_load(src,0x5104000,(ulong)(uint)((int)lVar9 + 0x10000 + (int)_DAT_05100060), s_BL31_fffad9e9,uVar5); uVar5 = FUN_fffaaf44(0x5100000,lVar9 + 0x5114000,iVar7); if ((uVar5 & 0xff) == 0) { return; } } uVar6 = uVar6 + 1; } while( true ); } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ ulong bl2_load_images(void) { int iVar1; byte bVar2; byte bVar3; uint uVar4; uint uVar5; uint uVar6; ulong tmp; undefined *puVar7; int iVar8; uint partition; thunk_FUN_fffa5fc8(); FUN_fffa2a68(); uVar5 = _DAT_ff6345e0; if ((((_AO_UNK_ff80000c & 0xf) == 0xc) || ((_AO_UNK_ff80000c & 0xf) == 0xd)) && ((_DAT_ff6345e0 >> 0xf & 1) != 0)) { /* not ran (librecomputer-alta) */ puts(s_CFG__fffad9ee); put_hex((ulong)uVar5,0x20); puts(s__fffadb47 + 1); FUN_fffab000(); } bVar3 = DAT_fffb1c42; bVar2 = DAT_fffb1c40; uVar5 = 0; iVar8 = 0; uVar6 = (uint)DAT_fffb1c40; do { partition = (uint)bVar2; if (uVar6 < (uVar5 & 0xff) || partition == (uVar5 & 0xff)) { puts(s_Never_should_be_here__fffad9fb); tmp = FUN_fffaa9c4(); return tmp; } iVar1 = 0; if (partition != 0) { iVar1 = (int)(uVar5 + bVar3) / (int)partition; } partition = (uVar5 + bVar3) - iVar1 * partition; if (uVar5 == uVar6 - 1) { iVar8 = 1; } /* Read FIP header As a reminder: -------------- offset dest size string (useless) part?? v~~~~~~ v~~~~~~~~ v~~~~~ v~~~~~~~~~~~~~~~~~ v~~~~~~~~ */ tmp = storage_load(0x10000,0x1700000,0x4000,s_FIP_HDR_fffad9f3,partition); if ((tmp & 0xff) == 0) { LAB_fffab208: uVar4 = fip_hdr_check__ns((undefined8 *)0x1700000,0x1400000,iVar8); if ((uVar4 & 0xff) == 0) { tmp = (ulong)(((int)_DAT_014000b0 + (int)_DAT_014000a8 + 0x1ff) - (int)_DAT_01400030 & 0xfffffe00); if ((_DAT_01400030 < 0x400000) && (tmp + _DAT_01400030 < 0x400000)) { /* `tmp` used for storage_load size. Good job, Amlogic... */ tmp = storage_load((ulong)((int)_DAT_01400030 + 0x10000),_DAT_01400030 + 0x1700000,tmp, s_BL3X_fffada12,partition); if ((tmp & 0xff) != 0) { if (iVar8 == 0) goto LAB_fffab298; FUN_fffaa9c4(); } uVar4 = FUN_fffaabc4(0x1400000,0x1700000,iVar8); if ((uVar4 & 0xff) == 0) { FUN_fffa2a6c(partition); puVar7 = FUN_fffa1180(); FUN_fffa1260(); Empty_fffac950(); FUN_fffa15ec(); if (puVar7 != (undefined *)0x0) { puts(s_run_into_bl31_fffad9ad); uVar5 = FUN_fffac9c0(); uVar5 = uVar5 & 0xff; tmp = 0x4e21; if (DAT_fffb1bd8 != '\0') { uVar6 = FUN_fffa1724(); tmp = (ulong)uVar6; if (uVar6 != 0) { uVar6 = (uint)DAT_fffb1bd0._3_1_; if (uVar5 < uVar6) { serial_print(s_FIP_ARB_check_fail__FIP_CVN__fffada17,uVar5,1,&DAT_fffada34); serial_print(s_FIP_MVN__fffada37,uVar6,1,s__fffadb47 + 1); tmp = 0x4e21; } else { _DAT_ff800260 = _DAT_ff800260 & 0xffffff | uVar5 << 0x18; tmp = 0; } } } return tmp; } } } } } else if (iVar8 != 0) { FUN_fffaa9c4(); goto LAB_fffab208; } LAB_fffab298: uVar5 = uVar5 + 1; } while( true ); } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffab314(byte param_1) { uint uVar1; uVar1 = 0x4e21; if ((DAT_fffb1bd8 != '\0') && (uVar1 = FUN_fffa1724(), uVar1 != 0)) { uVar1 = (uint)DAT_fffb1bd0._3_1_; if (param_1 < uVar1) { serial_print(s_FIP_ARB_check_fail__FIP_CVN__fffada17,(uint)param_1,1,&DAT_fffada34); serial_print(s_FIP_MVN__fffada37,uVar1,1,s__fffadb47 + 1); uVar1 = 0x4e21; } else { _DAT_ff800260 = _DAT_ff800260 & 0xffffff | (uint)param_1 << 0x18; uVar1 = 0; } } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffab3bc(byte param_1) { uint uVar1; uVar1 = 0x4e22; if ((DAT_fffb1bd8 != '\0') && (uVar1 = FUN_fffa1724(), uVar1 != 0)) { uVar1 = _DAT_ff800234 >> 0x10; if ((uint)param_1 < (uVar1 & 0xff)) { serial_print(s_BL30_ARB_check_fail__BL30_CVN__fffada40,(uint)param_1,1,&DAT_fffada34); serial_print(s_BL30_MVN__fffada5f,uVar1 & 0xff,1,s__fffadb47 + 1); uVar1 = 0x4e22; } else { _DAT_ff800264 = _DAT_ff800264 & 0xff00ffff | (uint)param_1 << 0x10; uVar1 = 0; } } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffab46c(byte param_1) { uint uVar1; uVar1 = 0x4e23; if ((DAT_fffb1bd8 != '\0') && (uVar1 = FUN_fffa1724(), uVar1 != 0)) { uVar1 = _DAT_ff80022c >> 0x10; if ((uint)param_1 < (uVar1 & 0xff)) { serial_print(s_BL31_ARB_check_fail__BL31_CVN__fffada69,(uint)param_1,1,&DAT_fffada34); serial_print(s_BL31_MVN__fffada88,uVar1 & 0xff,1,s__fffadb47 + 1); uVar1 = 0x4e23; } else { _DAT_ff800260 = _DAT_ff800260 & 0xff00ffff | (uint)param_1 << 0x10; uVar1 = 0; } } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffab51c(byte param_1) { uint uVar1; uVar1 = 0x4e24; if ((DAT_fffb1bd8 != '\0') && (uVar1 = FUN_fffa1724(), uVar1 != 0)) { uVar1 = _DAT_ff80022c >> 8; if ((uint)param_1 < (uVar1 & 0xff)) { serial_print(s_BL32_ARB_check_fail__BL32_CVN__fffada92,(uint)param_1,1,&DAT_fffada34); serial_print(s_BL32_MVN__fffadab1,uVar1 & 0xff,1,s__fffadb47 + 1); uVar1 = 0x4e24; } else { _DAT_ff800260 = _DAT_ff800260 & 0xffff00ff | (uint)param_1 << 8; uVar1 = 0; } } return uVar1; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffab5cc(byte param_1) { uint uVar1; uint uVar2; uVar2 = 0x4e25; if ((DAT_fffb1bd8 != '\0') && (uVar2 = FUN_fffa1724(), uVar1 = _DAT_ff80022c, uVar2 != 0)) { if ((uint)param_1 < (_DAT_ff80022c & 0xff)) { serial_print(s_BL33_ARB_check_fail__BL33_CVN__fffadabb,(uint)param_1,1,&DAT_fffada34); serial_print(s_BL33_MVN__fffadada,uVar1 & 0xff,1,s__fffadb47 + 1); uVar2 = 0x4e25; } else { _DAT_ff800260 = (uint)param_1 | _DAT_ff800260 & 0xffffff00; uVar2 = 0; } } return uVar2; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ undefined8 secureboot__ns(void) { int iVar1; byte bVar2; uint uVar3; uint uVar4; undefined8 uVar5; undefined8 local_10; undefined8 uStack_8; /* Looks like some secureboot stuff */ bVar2 = DAT_fffb1bd8; uVar4 = (uint)DAT_fffb1bd8; if (uVar4 == 0) { /* what's in that second `if` is not ran on alta it seems */ uVar3 = FUN_fffa1724(); if (uVar3 != 0) { /* "@AML" */ if (_DAT_fffa08d8 != 0x4c4d4140) goto LAB_fffab694; _DAT_ff800264 = (uint)bVar2 | (uint)DAT_fffa08e4 << 0x18; local_10 = 0; uStack_8 = 0; _DAT_ff800260 = uVar4; uVar4 = FUN_fffa1724(); serial_print(s_OTP_ARB__fffadae4,uVar4,(uint)bVar2,s__fffadb47 + 1); DAT_fffb1bd0 = _DAT_ff80022c; FUN_fffa1678(0xb0,0x10,(long)&local_10); uVar4 = (local_10._4_4_ & 0xff00ff00) >> 8 | (local_10._4_4_ & 0xff00ff) << 8; uVar3 = ~(uVar4 >> 0x10 | uVar4 << 0x10); uVar4 = uVar3 | uVar3 >> 1; uVar4 = uVar4 | uVar4 >> 2; uVar4 = uVar4 | uVar4 >> 4; uVar4 = uVar4 | uVar4 >> 8; uVar4 = uVar4 | uVar4 >> 0x10; uVar4 = ((uVar4 & 0xaaaaaaaa) >> 1) + (uVar4 & 0x55555555); uVar4 = ((uVar4 & 0xcccccccc) >> 2) + (uVar4 & 0x33333333); uVar4 = ((uVar4 & 0xf0f0f0f0) >> 4) + (uVar4 & 0xf0f0f0f); uVar4 = ((uVar4 & 0xff00ff00) >> 8) + (uVar4 & 0xff00ff); iVar1 = 0x20 - ((uVar4 >> 0x10) + (uVar4 & 0xffff)); if (uVar3 == 0) { iVar1 = 0x20; } DAT_fffb1bd0 = DAT_fffb1bd0 & 0xffffff | iVar1 << 0x18; } DAT_fffb1bd8 = 1; uVar5 = 0; } else { LAB_fffab694: uVar5 = 0xffffffff; } return uVar5; } undefined check_fw__ns(long param_1,long param_2,long param_3) { byte bVar1; uint uVar2; undefined auStack_30 [48]; if (((param_1 != 0) && (param_2 != 0)) && (param_3 != 0)) { uVar2 = FUN_fffa1710(); if (uVar2 != 0) { memset(auStack_30,0,0x30); memcpy((long)auStack_30,0xfffe7c20,0x20); FUN_fffa62bc(); memset(auStack_30,(uint)(param_2 == 0),0x30); } FUN_fffac334(param_1,*(uint *)(param_3 + 0xc),(long)auStack_30,0); bVar1 = FUN_fffac5b0((long)auStack_30,param_3 + 0x20,0x20); if (bVar1 == 0) { if (param_1 == param_2) { return 0; } FUN_fffa61ac(param_2,param_1,*(uint *)(param_3 + 0xc)); return 0; } } return 99; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ uint FUN_fffab878(ulong param_1,ulong param_2) { long lVar1; long lVar2; bool bVar3; byte bVar4; uint uVar5; uint *puVar6; undefined auStack_30 [48]; if ((param_1 == 0) || (param_2 == 0)) { return 0xffffffff; } puVar6 = (uint *)(param_1 + 0x4000); if (((uint)(param_1 >> 0x14) & 0xfff) != 0xfff) { puVar6 = (uint *)0x1404000; } memset(auStack_30,0,0x30); uVar5 = FUN_fffa1710(); if (uVar5 != 0) { memcpy((long)auStack_30,0xfffe7c20,0x20); FUN_fffa62bc(); } if (*(int *)(param_1 + 0x10) != -0x559bffff) { return 0xffffffff; } uVar5 = is_verified_boot_enabled(); lVar1 = param_1 + 0x10; if (uVar5 == 0) { FUN_fffac334(lVar1,(int)(param_1 + 0x3fe0) - (int)lVar1,(long)auStack_30,0); bVar4 = FUN_fffac5b0((long)auStack_30,param_1 + 0x3fe0,0x20); uVar5 = (uint)bVar4; } else { lVar2 = param_1 + (ulong)_DAT_fffa0f78 * -4 + 0x4000; FUN_fffac334(lVar1,(int)lVar2 - (int)lVar1,(long)auStack_30,0); bVar3 = FUN_fffabf88((uint *)0xfffa0b70,lVar2,(long)auStack_30,puVar6); uVar5 = 0xffffffff; if (!bVar3) goto LAB_fffab9e0; uVar5 = FUN_fffab314(*(byte *)(param_1 + 0x17)); } if (uVar5 == 0) { _DAT_fffa0000 = 0x50484432; _DAT_fffa0004 = 0x47584c46; _DAT_fffa0008 = 0x1400000; _DAT_fffa000c = 0; } LAB_fffab9e0: if ((uVar5 == 0) && (param_2 != param_1)) { FUN_fffa61ac(param_2,param_1,0x4000); } memset(auStack_30,0,0x30); return uVar5; } uint FUN_fffaba20(long param_1,long param_2,long param_3,uint param_4) { long lVar1; bool bVar2; byte bVar3; uint uVar4; undefined *puVar5; undefined *puVar6; long lVar7; int iVar8; undefined8 uVar9; long lVar10; undefined auStack_30 [32]; undefined auStack_10 [16]; if (3 < param_4) { return 0xffffffff; } memset(auStack_30,0,0x30); lVar10 = (long)(int)param_4; uVar9 = *(undefined8 *)(param_1 + lVar10 * 0x28 + 0x38); uVar4 = FUN_fffa1710(); if (uVar4 != 0) { memcpy((long)auStack_30,param_1 + lVar10 * 0x468 + 0x1b4,0x20); memcpy((long)auStack_10,param_1 + lVar10 * 0x468 + 0x1d4,0x10); FUN_fffa62bc(); } uVar4 = is_verified_boot_enabled(); lVar1 = param_2 + 0x10; iVar8 = (int)uVar9; if (uVar4 == 0) { FUN_fffac334(lVar1,(int)(param_2 + 0x270) - (int)lVar1,(long)auStack_30,0); bVar3 = FUN_fffac5b0((long)auStack_30,param_2 + 0x270,0x20); uVar4 = (uint)bVar3; if (bVar3 != 0) goto LAB_fffabc2c; FUN_fffac334(param_2 + 0x290,iVar8 - 0x290,(long)auStack_30,0); puVar5 = auStack_30; puVar6 = (undefined *)(param_2 + 0x30); lVar10 = 0x20; LAB_fffabc10: bVar3 = FUN_fffac5b0((long)puVar5,(long)puVar6,lVar10); uVar4 = (uint)bVar3; } else { lVar7 = param_1 + lVar10 * 0x468; lVar10 = param_2 + (ulong)*(uint *)(lVar7 + 0x5ec) * -4 + 0x290; FUN_fffac334(lVar1,(int)lVar10 - (int)lVar1,(long)auStack_30,0); bVar2 = FUN_fffabf88((uint *)(lVar7 + 0x1e4),lVar10,(long)auStack_30,(uint *)0x1404000); uVar4 = 0xffffffff; if (!bVar2) goto LAB_fffabc2c; FUN_fffac334(param_2 + 0x290,iVar8 - 0x290,(long)auStack_30,0); bVar3 = FUN_fffac5b0((long)auStack_30,param_2 + 0x30,0x20); if (bVar3 == 0) { bVar3 = *(byte *)(param_2 + 0x1c); if (param_4 == 0) { uVar4 = FUN_fffab3bc(bVar3); puVar6 = &DAT_fffadb78; } else if (param_4 == 1) { uVar4 = FUN_fffab46c(bVar3); puVar6 = &DAT_fffadb98; } else if (param_4 == 2) { uVar4 = FUN_fffab51c(bVar3); puVar6 = &DAT_fffadb88; } else { uVar4 = FUN_fffab5cc(bVar3); puVar6 = &DAT_fffadba8; } } else { puVar6 = (undefined *)0x0; uVar4 = 0x2712; } if ((puVar6 != (undefined *)0x0) && (uVar4 == 0)) { puVar5 = (undefined *)(param_2 + 0x50); lVar10 = 0x10; goto LAB_fffabc10; } } if (uVar4 == 0) { FUN_fffa61ac(param_3,param_2 + 0x290,iVar8 - 0x290); } LAB_fffabc2c: memset(auStack_30,0,0x30); return uVar4; } void FUN_fffabc60(long param_1,long param_2) { long lVar1; uint uVar2; long lVar3; lVar1 = 0; lVar3 = 0; for (uVar2 = 0; uVar2 < *(uint *)(param_1 + 0x408); uVar2 = uVar2 + 1) { lVar3 = ((ulong)*(uint *)(param_2 + lVar1) + lVar3) - (ulong)*(uint *)(param_1 + lVar1); *(int *)(param_2 + lVar1) = (int)lVar3; lVar3 = lVar3 >> 0x20; lVar1 = lVar1 + 4; } return; } void FUN_fffabca0(uint *param_1,uint *param_2,long param_3,uint *param_4) { long lVar1; uint uVar2; uint uVar3; uint uVar4; long lVar5; ulong uVar6; uint uVar7; ulong uVar8; for (uVar4 = 0; uVar4 < param_1[0x102]; uVar4 = uVar4 + 1) { param_2[uVar4] = 0; } for (uVar4 = 0; uVar4 < param_1[0x102]; uVar4 = uVar4 + 1) { uVar2 = *(uint *)(param_3 + (ulong)uVar4 * 4); uVar6 = (ulong)*param_2 + (ulong)uVar2 * (ulong)*param_4; uVar3 = param_1[0x101] * (int)uVar6; uVar8 = (uVar6 & 0xffffffff) + (ulong)uVar3 * (ulong)*param_1; uVar7 = 1; lVar5 = 0; while( true ) { lVar1 = lVar5 + 4; if (param_1[0x102] <= uVar7) break; uVar7 = uVar7 + 1; uVar6 = (ulong)*(uint *)((long)param_2 + lVar1) + (ulong)uVar2 * (ulong)*(uint *)((long)param_4 + lVar1) + (uVar6 >> 0x20); uVar8 = (uVar8 >> 0x20) + (ulong)uVar3 * (ulong)*(uint *)((long)param_1 + lVar1) + (uVar6 & 0xffffffff); *(int *)((long)param_2 + lVar5) = (int)uVar8; lVar5 = lVar1; } uVar8 = (uVar8 >> 0x20) + (uVar6 >> 0x20); param_2[uVar7 - 1] = (uint)uVar8; if (uVar8 >> 0x20 != 0) { FUN_fffabc60((long)param_1,(long)param_2); } } return; } void FUN_fffabd9c(uint *param_1,undefined *param_2,uint *param_3) { uint *dst; uint *puVar1; uint uVar2; undefined4 uVar3; uint uVar4; long lVar5; ulong uVar6; long lVar7; uint *puVar8; uint *puVar9; uint *puVar10; int iVar11; uVar2 = param_1[0x102]; dst = param_3 + (ulong)uVar2 * 2; lVar5 = 0; while( true ) { if (param_1[0x102] <= (uint)lVar5) break; uVar4 = ((param_1[0x102] + 0x3fffffff) - (uint)lVar5) * 4; param_3[lVar5] = (uint)(byte)param_2[uVar4 + 3] | (uint)(byte)param_2[uVar4] << 0x18 | (uint)(byte)param_2[uVar4 + 1] << 0x10 | (uint)(byte)param_2[uVar4 + 2] << 8; lVar5 = lVar5 + 1; } iVar11 = 0; for (uVar4 = param_1[0x80]; 0 < (int)uVar4; uVar4 = (int)uVar4 >> 1) { iVar11 = iVar11 + 1; } FUN_fffabca0(param_1,dst,(long)param_3,param_1 + 0x81); puVar8 = dst; puVar10 = param_3 + uVar2; for (uVar4 = iVar11 - 2; -1 < (int)uVar4; uVar4 = uVar4 - 1) { FUN_fffabca0(param_1,puVar10,(long)puVar8,puVar8); puVar1 = puVar8; if (puVar8 == dst) { puVar1 = param_3; } puVar9 = puVar1; puVar8 = puVar10; if ((1 << (ulong)(uVar4 & 0x1f) & param_1[0x80]) != 0) { FUN_fffabca0(param_1,puVar1,(long)puVar10,dst); puVar9 = puVar10; puVar8 = puVar1; } puVar10 = puVar9; } memset(dst,0,((ulong)param_1[0x102] & 0x3fffffff) << 2); *dst = 1; FUN_fffabca0(param_1,puVar10,(long)puVar8,dst); do { uVar6 = (ulong)param_1[0x102]; do { if ((int)uVar6 == 0) break; uVar6 = (ulong)((int)uVar6 - 1); if (puVar10[uVar6] < param_1[uVar6]) { iVar11 = param_1[0x102] - 1; lVar5 = (long)iVar11; lVar7 = 0; for (; -1 < iVar11; iVar11 = iVar11 + -1) { uVar3 = *(undefined4 *)((long)puVar10 + lVar7 + lVar5 * 4); *param_2 = (char)((uint)uVar3 >> 0x18); param_2[1] = (char)((uint)uVar3 >> 0x10); param_2[2] = (char)((uint)uVar3 >> 8); param_2[3] = (char)uVar3; lVar7 = lVar7 + -4; param_2 = param_2 + 4; } return; } } while (puVar10[uVar6] <= param_1[uVar6]); FUN_fffabc60((long)param_1,(long)puVar10); } while( true ); } bool FUN_fffabf88(uint *param_1,long param_2,long param_3,uint *param_4) { uint uVar1; byte bVar2; ulong uVar3; ulong uVar4; byte local_210 [512]; uint *local_10; if ((param_1 != (uint *)0x0) && (((uVar1 = param_1[0x102], uVar1 == 0x20 || (uVar1 == 0x40)) || (uVar1 == 0x80)))) { local_10 = param_4; memcpy((long)local_210,param_2,(ulong)(uVar1 * 4)); FUN_fffabd9c(param_1,local_210,local_10); local_210[0] = local_210[1] ^ 1 | local_210[0]; uVar4 = (ulong)(uVar1 * 4 - 0x20); for (uVar3 = 0; uVar3 < uVar4 - 0x16; uVar3 = uVar3 + 1) { local_210[0] = local_210[0] | ~local_210[uVar3 + 2]; } bVar2 = FUN_fffac5b0((long)(local_210 + (uVar4 - 0x14)),(long)&DAT_fffadaf0,0x14); if ((bVar2 | local_210[0]) == 0) { bVar2 = FUN_fffac5b0((long)(local_210 + uVar4),param_3,0x20); return bVar2 == 0; } } return false; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffac08c(undefined8 param_1,uint param_2,undefined8 param_3,char param_4) { undefined local_10 [16]; if ((param_4 == '\0') && ((param_2 & 0x3f) != 0)) { puts(s_Err_sha5_fffadb08); } else { _DAT_ff63e028 = 0xf; _DAT_ff63e008 = (uint)local_10 | 2; *(uint *)(DAT_fffb1708 + 0x20) = *(int *)(DAT_fffb1708 + 0x20) + param_2; do { } while (_DAT_ff63e028 == 0); } return; } void FUN_fffac160(long param_1,int param_2) { undefined4 uVar1; if (DAT_fffb1708 != 0) { puts(s_Err_sha4_fffadb12); return; } uVar1 = 0x100; if (param_2 == 0xe0) { uVar1 = 0xe0; } DAT_fffb1708 = param_1; *(undefined4 *)(param_1 + 0x28) = uVar1; *(undefined4 *)(param_1 + 0x20) = 0; *(undefined4 *)(param_1 + 0x24) = 0; return; } void FUN_fffac1a0(long param_1,long param_2,uint param_3) { uint uVar1; long lVar2; ulong uVar3; uint uVar4; lVar2 = DAT_fffb1708; if (DAT_fffb1708 != param_1) { puts(s_Err_sha3_fffadb1c); return; } uVar1 = *(uint *)(DAT_fffb1708 + 0x24); uVar4 = 0; if (uVar1 != 0) { uVar4 = 0x40 - uVar1; memcpy(DAT_fffb1708 + (ulong)uVar1 + 0x2c,param_2,(ulong)uVar4); param_3 = param_3 - uVar4; *(uint *)(lVar2 + 0x24) = *(int *)(lVar2 + 0x24) + uVar4; } uVar3 = (ulong)param_3; if (*(int *)(lVar2 + 0x24) == 0x40) { if (param_3 == 0) { return; } FUN_fffac08c(lVar2 + 0x2c,0x40,lVar2 + 0xac,'\0'); *(undefined4 *)(lVar2 + 0x24) = 0; if (param_3 < 0x41) goto LAB_fffac28c; } else if (param_3 < 0x41) { if (param_3 == 0) { return; } goto LAB_fffac28c; } uVar1 = param_3 & 0x3f; if ((param_3 & 0x3f) == 0) { uVar1 = 0x40; } uVar3 = (ulong)uVar4; uVar4 = uVar4 + (param_3 - uVar1); FUN_fffac08c(param_2 + uVar3,param_3 - uVar1,lVar2 + 0xac,'\0'); uVar3 = (ulong)uVar1; LAB_fffac28c: memcpy(lVar2 + 0x2c,param_2 + (ulong)uVar4,uVar3); *(int *)(lVar2 + 0x24) = (int)uVar3; return; } long FUN_fffac2b4(long param_1) { long lVar1; if (DAT_fffb1708 == param_1) { lVar1 = DAT_fffb1708 + 0xac; if (*(uint *)(DAT_fffb1708 + 0x24) - 1 < 0x40) { FUN_fffac08c(DAT_fffb1708 + 0x2c,*(uint *)(DAT_fffb1708 + 0x24),lVar1,'\x01'); DAT_fffb1708 = 0; } else { puts(s_Err_sha2_fffadb30); } } else { puts(s_Err_sha1_fffadb26); lVar1 = param_1 + 0xac; } return lVar1; } void FUN_fffac334(long param_1,uint param_2,long param_3,int param_4) { int iVar1; uint uVar2; uint uVar3; undefined auStack_e0 [172]; undefined auStack_34 [52]; uVar2 = param_2; if (0x1ffbf < param_2) { uVar2 = 0x1ffc0; } iVar1 = 0x100; if (param_4 != 0) { iVar1 = 0xe0; } FUN_fffac160((long)auStack_e0,iVar1); uVar3 = 0; while (uVar3 < param_2) { FUN_fffac1a0((long)auStack_e0,param_1 + (int)uVar3,uVar2); uVar3 = uVar3 + uVar2; if (param_2 - uVar3 < uVar2) { uVar2 = param_2 - uVar3; } } FUN_fffac2b4((long)auStack_e0); memcpy(param_3,(long)auStack_34,0x20); return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void print_version(void) { puts(s__TE__fffadb3a); put_dec((ulong)_DAT_ffd0f188); puts(s__BL2_fffadb40); puts(s_Built___05_09_43__Jul_8_2023__g1_fffaca08); puts(s__fffadb47); return; } void bl2_main(void) { Empty_fffac69c(); pinmux_init(); FUN_fffac528(); /* --- */ print_version(); bl2_arch_setup(); handle_smc_call__ns(); Empty_fffa5d7c(); boot_prep(); /* ******************************************* */ ddr_init(); FUN_fffa5778(); bl2_load_images(); /* "NEVER BE HERE" */ puts(s_USB_BOOT___SHOULD_NEVER_BE_HERE_fffad9bc + 0x12); do { /* WARNING: Do nothing block with infinite loop */ } while( true ); } undefined8 FUN_fffac46c(long param_1,long param_2,long param_3) { memcpy(param_2,param_1 + (ulong)(DAT_fffadea8 - 0x10000),param_3); return 0; } int FUN_fffac4a0(int *param_1,uint param_2) { uint uVar1; int iVar2; uint uVar3; ulong uVar4; ulong uVar5; int *piVar6; uVar4 = (ulong)(uint)((int)param_2 >> 2); uVar3 = param_2 & 3; iVar2 = 0; uVar5 = uVar4; piVar6 = param_1; while (uVar1 = (int)uVar5 - 1, uVar5 = (ulong)uVar1, uVar1 != 0xffffffff) { iVar2 = iVar2 + *piVar6; piVar6 = piVar6 + 1; } if (uVar3 == 1) { uVar3 = (uint)*(byte *)(param_1 + uVar4); } else if (uVar3 == 2) { uVar3 = (uint)*(ushort *)(param_1 + uVar4); } else { if (uVar3 != 3) { return iVar2; } uVar3 = param_1[uVar4] & 0xffffff; } return iVar2 + uVar3; } void bl2_arch_setup(void) { write_cpacr(0x300000); saradc_ch1_get(); pll_init(); return; } void FUN_fffac528(void) { DAT_fffb1710 = (char)((uint)DAT_fffb2198 >> 0x18); DAT_fffb1711 = (char)((uint)DAT_fffb2198 >> 0x10); return; } undefined FUN_fffac54c(uint param_1) { undefined uVar1; uVar1 = 0; if (param_1 < 4) { uVar1 = (&DAT_fffb1710)[(int)param_1]; } return uVar1; } undefined4 FUN_fffac56c(void) { undefined4 local_10 [4]; memcpy((long)local_10,(long)&DAT_fffb2198,4); return local_10[0]; } void * memset(void *dst,uint val,size_t len) { size_t i; for (i = 0; i != len; i = i + 1) { *(char *)((long)dst + i) = (char)val; } return dst; } byte FUN_fffac5b0(long param_1,long param_2,long param_3) { byte bVar1; long lVar2; bVar1 = 0; for (lVar2 = 0; lVar2 != param_3; lVar2 = lVar2 + 1) { bVar1 = bVar1 | *(byte *)(param_2 + lVar2) ^ *(byte *)(param_1 + lVar2); } return bVar1; } void memcpy(long param_1,long param_2,long param_3) { long lVar1; for (lVar1 = 0; lVar1 != param_3; lVar1 = lVar1 + 1) { *(undefined *)(param_1 + lVar1) = *(undefined *)(param_2 + lVar1); } return; } int FUN_fffac604(long param_1,long param_2) { byte bVar1; long lVar2; lVar2 = 0; do { bVar1 = *(byte *)(param_1 + lVar2); if ((uint)bVar1 != (uint)*(byte *)(param_2 + lVar2)) { return (uint)bVar1 - (uint)*(byte *)(param_2 + lVar2); } lVar2 = lVar2 + 1; } while (bVar1 != 0); return 0; } long FUN_fffac630(char *param_1) { char *pcVar1; for (pcVar1 = param_1; *pcVar1 != '\0'; pcVar1 = pcVar1 + 1) { } return (long)pcVar1 - (long)param_1; } uint FUN_fffac64c(long param_1,long param_2,long param_3) { byte bVar1; long lVar2; if (param_3 != 0) { lVar2 = 0; do { bVar1 = *(byte *)(param_1 + lVar2); if ((uint)bVar1 != (uint)*(byte *)(param_2 + lVar2)) { return (uint)bVar1 - (uint)*(byte *)(param_2 + lVar2); } if (bVar1 == 0) { return (uint)bVar1; } lVar2 = lVar2 + 1; } while (param_3 != lVar2); } return 0; } byte FUN_fffac694(long param_1,long param_2) { byte bVar1; bVar1 = FUN_fffac5b0(param_1,param_2,0x10); return bVar1; } void Empty_fffac69c(void) { return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ void FUN_fffac6a0(int param_1) { uint uVar1; _DAT_ff800054 = _DAT_ff800054 | 1; if (param_1 == 1) { uVar1 = 0x68; } else { uVar1 = 0xd; } _DAT_ff803014 = uVar1 | 0x9800000; _DAT_ff800014 = _DAT_ff800014 | 0x11; _DAT_ff803008 = 0xb000; return; } /* WARNING: Globals starting with '_' overlap smaller symbols at the same address */ int serial_putc(int c) { uint disable_uart; disable_uart = get_print_or_not_fffa1760(); if (disable_uart == 0) { if (c == L'\n') { do { } while ((_UART_STATUS_ff80300c >> 0x15 & 1) != 0); } do { _UART_WFIFO_ff803000 = c; } while ((_UART_STATUS_ff80300c >> 0x15 & 1) != 0); } return c; } undefined8 puts(char *s) { uint uVar1; uVar1 = get_print_or_not_fffa1760(); if (uVar1 == 0) { for (; (byte)*s != 0; s = (char *)((byte *)s + 1)) { serial_putc((uint)(byte)*s); } } return 0; } uint put_hex(ulong param_1,ulong param_2) { uint uVar1; uint uVar2; int c; ulong uVar3; uVar3 = param_2 & 0xffffffff; uVar2 = get_print_or_not_fffa1760(); if (uVar2 == 0) { while (uVar1 = (int)uVar3 - 4, uVar3 = (ulong)uVar1, -1 < (int)uVar1) { uVar2 = (uint)(param_1 >> (uVar3 & 0x3f)) & 0xf; if (uVar2 < 10) { c = uVar2 + 0x30; } else { c = uVar2 + 0x57; } uVar2 = serial_putc(c); } } return uVar2; } uint put_dec(ulong param_1) { uint uVar1; ulong uVar2; uint uVar3; int iVar4; ulong uVar5; ulong uVar6; byte abStack_20 [32]; uVar3 = get_print_or_not_fffa1760(); if (uVar3 == 0) { uVar5 = 0; do { uVar2 = param_1 / 10; abStack_20[uVar5] = (char)param_1 + (char)uVar2 * -10 + 0x30; iVar4 = (int)uVar5; uVar6 = uVar5 & 0xffffffff; uVar5 = uVar5 + 1; param_1 = uVar2; } while (iVar4 + 1U < 0x20 && uVar2 != 0); do { iVar4 = (int)uVar6; uVar1 = iVar4 - 1; uVar6 = (ulong)uVar1; uVar3 = serial_putc((uint)abStack_20[iVar4]); } while (uVar1 != 0xffffffff); } return uVar3; } ulong serial_print(char *s_start,uint i,int hex_or_dec,char *s_end) { uint ret; ulong ret_; ret = get_print_or_not_fffa1760(); if (ret == 0) { if (s_start != (char *)0x0) { puts(s_start); } if (hex_or_dec == 0) { ret = put_hex((ulong)i,0x20); } else { ret = put_dec((ulong)i); } if (s_end != (char *)0x0) { ret_ = puts(s_end); return ret_; } } return (ulong)ret; } undefined * platform_set_coherent_stack(void) { return PTR_DAT_fffac938; } bool platform_is_primary_cpu(short param_1) { return param_1 == 0; } void Empty_fffac950(void) { return; } void FUN_fffac954(void) { return; } void FUN_fffac958(ulong param_1,long param_2) { ulong uVar1; long lVar2; uVar1 = ctr_el0; lVar2 = 4L << (uVar1 >> 0x10 & 0xf); uVar1 = param_1 & (lVar2 - 1U ^ 0xffffffffffffffff); do { DC_CIVAC(uVar1); uVar1 = uVar1 + lVar2; } while (uVar1 < param_1 + param_2); UnkSytemRegWrite(0,3,3,0xf,4,0); return; } void FUN_fffac98c(ulong param_1,long param_2) { ulong uVar1; long lVar2; uVar1 = ctr_el0; lVar2 = 4L << (uVar1 >> 0x10 & 0xf); uVar1 = param_1 & (lVar2 - 1U ^ 0xffffffffffffffff); do { DC_IVAC(uVar1); uVar1 = uVar1 + lVar2; } while (uVar1 < param_1 + param_2); UnkSytemRegWrite(0,3,3,0xf,4,0); return; } void FUN_fffac9c0(void) { CallSecureMonitor(0); CallSecureMonitor(0); return; } void FUN_fffac9c4(void) { CallSecureMonitor(0); return; } void FUN_fffac9cc(undefined8 *param_1,long param_2) { undefined8 *puVar1; puVar1 = (undefined8 *)((long)param_1 + param_2); for (; 0xf < (long)puVar1 - (long)param_1; param_1 = param_1 + 2) { *param_1 = 0; param_1[1] = 0; } for (; param_1 != puVar1; param_1 = (undefined8 *)((long)param_1 + 1)) { *(undefined *)param_1 = 0; } return; } undefined8 FUN_fffac9f8(void) { undefined8 uVar1; uVar1 = id_aa64pfr0_el1; return uVar1; } void write_cpacr(undefined8 param_1) { cpacr_el1 = param_1; return; }