Push old Amlogic BL2 sourcesHEADmaster

10 files changed, 1186 insertions, 0 deletions

diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
new file mode 100644
index 0000000..01eb155
--- /dev/null
+++ b/include/lib/aarch64/arch.h
@@ -0,0 +1,425 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_H__
+#define __ARCH_H__
+
+
+/*******************************************************************************
+ * MIDR bit definitions
+ ******************************************************************************/
+#define MIDR_VAR_MASK		0xf
+#define MIDR_REV_MASK		0xf
+#define MIDR_PN_MASK		0xfff
+#define MIDR_VAR_SHIFT		20
+#define MIDR_REV_SHIFT		0
+#define MIDR_PN_SHIFT		4
+#define MIDR_PN_AEM		0xd0f
+#define MIDR_PN_A57		0xd07
+#define MIDR_PN_A53		0xd03
+
+/*******************************************************************************
+ * MPIDR macros
+ ******************************************************************************/
+#define MPIDR_CPU_MASK		MPIDR_AFFLVL_MASK
+#define MPIDR_CLUSTER_MASK	MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
+#define MPIDR_AFFINITY_BITS	8
+#define MPIDR_AFFLVL_MASK	0xff
+#define MPIDR_AFF0_SHIFT	0
+#define MPIDR_AFF1_SHIFT	8
+#define MPIDR_AFF2_SHIFT	16
+#define MPIDR_AFF3_SHIFT	32
+#define MPIDR_AFFINITY_MASK	0xff00ffffff
+#define MPIDR_AFFLVL_SHIFT	3
+#define MPIDR_AFFLVL0		0
+#define MPIDR_AFFLVL1		1
+#define MPIDR_AFFLVL2		2
+#define MPIDR_AFFLVL3		3
+/* TODO: Support only the first 3 affinity levels for now */
+#define MPIDR_MAX_AFFLVL	2
+
+/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
+#define FIRST_MPIDR		0
+
+/*******************************************************************************
+ * Implementation defined sysreg encodings
+ ******************************************************************************/
+#define CPUECTLR_EL1	S3_1_C15_C2_1
+#define CPUACTLR_EL1	S3_1_C15_C2_0
+
+/*******************************************************************************
+ * Generic timer memory mapped registers & offsets
+ ******************************************************************************/
+#define CNTCR_OFF			0x000
+#define CNTFID_OFF			0x020
+
+#define CNTCR_EN			(1 << 0)
+#define CNTCR_HDBG			(1 << 1)
+#define CNTCR_FCREQ(x)			((x) << 8)
+
+/*******************************************************************************
+ * System register bit definitions
+ ******************************************************************************/
+/* CLIDR definitions */
+#define LOUIS_SHIFT		21
+#define LOC_SHIFT		24
+#define CLIDR_FIELD_WIDTH	3
+
+/* CSSELR definitions */
+#define LEVEL_SHIFT		1
+
+/* D$ set/way op type defines */
+#define DCISW			0x0
+#define DCCISW			0x1
+#define DCCSW			0x2
+
+/* ID_AA64PFR0_EL1 definitions */
+#define ID_AA64PFR0_EL0_SHIFT	0
+#define ID_AA64PFR0_EL1_SHIFT	4
+#define ID_AA64PFR0_EL2_SHIFT	8
+#define ID_AA64PFR0_EL3_SHIFT	12
+#define ID_AA64PFR0_ELX_MASK	0xf
+
+/* ID_PFR1_EL1 definitions */
+#define ID_PFR1_VIRTEXT_SHIFT	12
+#define ID_PFR1_VIRTEXT_MASK	0xf
+#define GET_VIRT_EXT(id)	((id >> ID_PFR1_VIRTEXT_SHIFT) \
+				 & ID_PFR1_VIRTEXT_MASK)
+
+/* SCTLR definitions */
+#define SCTLR_EL2_RES1  ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
+			(1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) |  \
+			(1 << 4))
+
+#define SCTLR_EL1_RES1  ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
+			(1 << 11))
+#define SCTLR_M_BIT		(1 << 0)
+#define SCTLR_A_BIT		(1 << 1)
+#define SCTLR_C_BIT		(1 << 2)
+#define SCTLR_SA_BIT		(1 << 3)
+#define SCTLR_B_BIT		(1 << 7)
+#define SCTLR_Z_BIT		(1 << 11)
+#define SCTLR_I_BIT		(1 << 12)
+#define SCTLR_WXN_BIT		(1 << 19)
+#define SCTLR_EXCEPTION_BITS	(0x3 << 6)
+#define SCTLR_EE_BIT		(1 << 25)
+
+/* CPACR_El1 definitions */
+#define CPACR_EL1_FPEN(x)	(x << 20)
+#define CPACR_EL1_FP_TRAP_EL0	0x1
+#define CPACR_EL1_FP_TRAP_ALL	0x2
+#define CPACR_EL1_FP_TRAP_NONE	0x3
+
+/* SCR definitions */
+#define SCR_RES1_BITS		((1 << 4) | (1 << 5))
+#define SCR_TWE_BIT		(1 << 13)
+#define SCR_TWI_BIT		(1 << 12)
+#define SCR_ST_BIT		(1 << 11)
+#define SCR_RW_BIT		(1 << 10)
+#define SCR_SIF_BIT		(1 << 9)
+#define SCR_HCE_BIT		(1 << 8)
+#define SCR_SMD_BIT		(1 << 7)
+#define SCR_EA_BIT		(1 << 3)
+#define SCR_FIQ_BIT		(1 << 2)
+#define SCR_IRQ_BIT		(1 << 1)
+#define SCR_NS_BIT		(1 << 0)
+#define SCR_VALID_BIT_MASK	0x2f8f
+
+/* HCR definitions */
+#define HCR_RW_BIT		(1ull << 31)
+#define HCR_AMO_BIT		(1 << 5)
+#define HCR_IMO_BIT		(1 << 4)
+#define HCR_FMO_BIT		(1 << 3)
+
+/* CNTHCTL_EL2 definitions */
+#define EL1PCEN_BIT		(1 << 1)
+#define EL1PCTEN_BIT		(1 << 0)
+
+/* CNTKCTL_EL1 definitions */
+#define EL0PTEN_BIT		(1 << 9)
+#define EL0VTEN_BIT		(1 << 8)
+#define EL0PCTEN_BIT		(1 << 0)
+#define EL0VCTEN_BIT		(1 << 1)
+
+/* CPTR_EL3 definitions */
+#define TCPAC_BIT		(1 << 31)
+#define TTA_BIT			(1 << 20)
+#define TFP_BIT			(1 << 10)
+
+/* CPSR/SPSR definitions */
+#define DAIF_FIQ_BIT		(1 << 0)
+#define DAIF_IRQ_BIT		(1 << 1)
+#define DAIF_ABT_BIT		(1 << 2)
+#define DAIF_DBG_BIT		(1 << 3)
+#define SPSR_DAIF_SHIFT		6
+#define SPSR_DAIF_MASK		0xf
+
+#define SPSR_AIF_SHIFT		6
+#define SPSR_AIF_MASK		0x7
+
+#define SPSR_E_SHIFT		9
+#define SPSR_E_MASK			0x1
+#define SPSR_E_LITTLE		0x0
+#define SPSR_E_BIG			0x1
+
+#define SPSR_T_SHIFT		5
+#define SPSR_T_MASK			0x1
+#define SPSR_T_ARM			0x0
+#define SPSR_T_THUMB		0x1
+
+#define DISABLE_ALL_EXCEPTIONS \
+		(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
+
+
+/*
+ * TCR defintions
+ */
+#define TCR_EL3_RES1		((1UL << 31) | (1UL << 23))
+
+#define TCR_T0SZ_4GB		32
+
+#define TCR_RGN_INNER_NC	(0x0 << 8)
+#define TCR_RGN_INNER_WBA	(0x1 << 8)
+#define TCR_RGN_INNER_WT	(0x2 << 8)
+#define TCR_RGN_INNER_WBNA	(0x3 << 8)
+
+#define TCR_RGN_OUTER_NC	(0x0 << 10)
+#define TCR_RGN_OUTER_WBA	(0x1 << 10)
+#define TCR_RGN_OUTER_WT	(0x2 << 10)
+#define TCR_RGN_OUTER_WBNA	(0x3 << 10)
+
+#define TCR_SH_NON_SHAREABLE	(0x0 << 12)
+#define TCR_SH_OUTER_SHAREABLE	(0x2 << 12)
+#define TCR_SH_INNER_SHAREABLE	(0x3 << 12)
+
+#define MODE_SP_SHIFT		0x0
+#define MODE_SP_MASK		0x1
+#define MODE_SP_EL0		0x0
+#define MODE_SP_ELX		0x1
+
+#define MODE_RW_SHIFT		0x4
+#define MODE_RW_MASK		0x1
+#define MODE_RW_64			0x0
+#define MODE_RW_32			0x1
+
+#define MODE_EL_SHIFT		0x2
+#define MODE_EL_MASK		0x3
+#define MODE_EL3		0x3
+#define MODE_EL2		0x2
+#define MODE_EL1		0x1
+#define MODE_EL0		0x0
+
+#define MODE32_SHIFT		0
+#define MODE32_MASK		0xf
+#define MODE32_usr		0x0
+#define MODE32_fiq		0x1
+#define MODE32_irq		0x2
+#define MODE32_svc		0x3
+#define MODE32_mon		0x6
+#define MODE32_abt		0x7
+#define MODE32_hyp		0xa
+#define MODE32_und		0xb
+#define MODE32_sys		0xf
+
+#define GET_RW(mode)		(((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
+#define GET_EL(mode)		(((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
+#define GET_SP(mode)		(((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
+#define GET_M32(mode)		(((mode) >> MODE32_SHIFT) & MODE32_MASK)
+
+#define SPSR_64(el, sp, daif)				\
+	(MODE_RW_64 << MODE_RW_SHIFT |			\
+	((el) & MODE_EL_MASK) << MODE_EL_SHIFT |	\
+	((sp) & MODE_SP_MASK) << MODE_SP_SHIFT |	\
+	((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE32(mode, isa, endian, aif)		\
+	(MODE_RW_32 << MODE_RW_SHIFT |			\
+	((mode) & MODE32_MASK) << MODE32_SHIFT |	\
+	((isa) & SPSR_T_MASK) << SPSR_T_SHIFT |		\
+	((endian) & SPSR_E_MASK) << SPSR_E_SHIFT |	\
+	((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
+
+
+/* Physical timer control register bit fields shifts and masks */
+#define CNTP_CTL_ENABLE_SHIFT   0
+#define CNTP_CTL_IMASK_SHIFT    1
+#define CNTP_CTL_ISTATUS_SHIFT  2
+
+#define CNTP_CTL_ENABLE_MASK    1
+#define CNTP_CTL_IMASK_MASK     1
+#define CNTP_CTL_ISTATUS_MASK   1
+
+#define get_cntp_ctl_enable(x)  ((x >> CNTP_CTL_ENABLE_SHIFT) & \
+					CNTP_CTL_ENABLE_MASK)
+#define get_cntp_ctl_imask(x)   ((x >> CNTP_CTL_IMASK_SHIFT) & \
+					CNTP_CTL_IMASK_MASK)
+#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \
+					CNTP_CTL_ISTATUS_MASK)
+
+#define set_cntp_ctl_enable(x)  (x |= 1 << CNTP_CTL_ENABLE_SHIFT)
+#define set_cntp_ctl_imask(x)   (x |= 1 << CNTP_CTL_IMASK_SHIFT)
+
+#define clr_cntp_ctl_enable(x)  (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
+#define clr_cntp_ctl_imask(x)   (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
+
+/* Miscellaneous MMU related constants */
+#define NUM_2MB_IN_GB		(1 << 9)
+#define NUM_4K_IN_2MB		(1 << 9)
+#define NUM_GB_IN_4GB		(1 << 2)
+
+#define TWO_MB_SHIFT		21
+#define ONE_GB_SHIFT		30
+#define FOUR_KB_SHIFT		12
+
+#define ONE_GB_INDEX(x)		((x) >> ONE_GB_SHIFT)
+#define TWO_MB_INDEX(x)		((x) >> TWO_MB_SHIFT)
+#define FOUR_KB_INDEX(x)	((x) >> FOUR_KB_SHIFT)
+
+#define INVALID_DESC		0x0
+#define BLOCK_DESC		0x1
+#define TABLE_DESC		0x3
+
+#define FIRST_LEVEL_DESC_N	ONE_GB_SHIFT
+#define SECOND_LEVEL_DESC_N	TWO_MB_SHIFT
+#define THIRD_LEVEL_DESC_N	FOUR_KB_SHIFT
+
+#define LEVEL1			1
+#define LEVEL2			2
+#define LEVEL3			3
+
+#define XN			(1ull << 2)
+#define PXN			(1ull << 1)
+#define CONT_HINT		(1ull << 0)
+
+#define UPPER_ATTRS(x)		(x & 0x7) << 52
+#define NON_GLOBAL		(1 << 9)
+#define ACCESS_FLAG		(1 << 8)
+#define NSH			(0x0 << 6)
+#define OSH			(0x2 << 6)
+#define ISH			(0x3 << 6)
+
+#define PAGE_SIZE_SHIFT		FOUR_KB_SHIFT
+#define PAGE_SIZE		(1 << PAGE_SIZE_SHIFT)
+#define PAGE_SIZE_MASK		(PAGE_SIZE - 1)
+#define IS_PAGE_ALIGNED(addr)	(((addr) & PAGE_SIZE_MASK) == 0)
+
+#define XLAT_ENTRY_SIZE_SHIFT	3 /* Each MMU table entry is 8 bytes (1 << 3) */
+#define XLAT_ENTRY_SIZE		(1 << XLAT_ENTRY_SIZE_SHIFT)
+
+#define XLAT_TABLE_SIZE_SHIFT	PAGE_SIZE_SHIFT
+#define XLAT_TABLE_SIZE		(1 << XLAT_TABLE_SIZE_SHIFT)
+
+/* Values for number of entries in each MMU translation table */
+#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES	(1 << XLAT_TABLE_ENTRIES_SHIFT)
+#define XLAT_TABLE_ENTRIES_MASK	(XLAT_TABLE_ENTRIES - 1)
+
+/* Values to convert a memory address to an index into a translation table */
+#define L3_XLAT_ADDRESS_SHIFT	PAGE_SIZE_SHIFT
+#define L2_XLAT_ADDRESS_SHIFT	(L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_ADDRESS_SHIFT	(L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+/*
+ * AP[1] bit is ignored by hardware and is
+ * treated as if it is One in EL2/EL3
+ */
+#define AP_RO			(0x1 << 5)
+#define AP_RW			(0x0 << 5)
+
+#define NS				(0x1 << 3)
+#define ATTR_SO_INDEX			0x2
+#define ATTR_DEVICE_INDEX		0x1
+#define ATTR_IWBWA_OWBWA_NTR_INDEX	0x0
+#define LOWER_ATTRS(x)			(((x) & 0xfff) << 2)
+#define ATTR_SO				(0x0)
+#define ATTR_DEVICE			(0x4)
+#define ATTR_IWBWA_OWBWA_NTR		(0xff)
+#define MAIR_ATTR_SET(attr, index)	(attr << (index << 3))
+
+/* Exception Syndrome register bits and bobs */
+#define ESR_EC_SHIFT			26
+#define ESR_EC_MASK			0x3f
+#define ESR_EC_LENGTH			6
+#define EC_UNKNOWN			0x0
+#define EC_WFE_WFI			0x1
+#define EC_AARCH32_CP15_MRC_MCR		0x3
+#define EC_AARCH32_CP15_MRRC_MCRR	0x4
+#define EC_AARCH32_CP14_MRC_MCR		0x5
+#define EC_AARCH32_CP14_LDC_STC		0x6
+#define EC_FP_SIMD			0x7
+#define EC_AARCH32_CP10_MRC		0x8
+#define EC_AARCH32_CP14_MRRC_MCRR	0xc
+#define EC_ILLEGAL			0xe
+#define EC_AARCH32_SVC			0x11
+#define EC_AARCH32_HVC			0x12
+#define EC_AARCH32_SMC			0x13
+#define EC_AARCH64_SVC			0x15
+#define EC_AARCH64_HVC			0x16
+#define EC_AARCH64_SMC			0x17
+#define EC_AARCH64_SYS			0x18
+#define EC_IABORT_LOWER_EL		0x20
+#define EC_IABORT_CUR_EL		0x21
+#define EC_PC_ALIGN			0x22
+#define EC_DABORT_LOWER_EL		0x24
+#define EC_DABORT_CUR_EL		0x25
+#define EC_SP_ALIGN			0x26
+#define EC_AARCH32_FP			0x28
+#define EC_AARCH64_FP			0x2c
+#define EC_SERROR			0x2f
+
+#define EC_BITS(x)			(x >> ESR_EC_SHIFT) & ESR_EC_MASK
+
+/*******************************************************************************
+ * Imp. Def. register defines.
+ ******************************************************************************/
+/* CPUECTLR definitions */
+#define CPUECTLR_SMP_BIT	(1 << 6)
+
+/* A57 CPUACTLR definitions */
+#define CPUACTLR_NO_ALLOC_WBWA	(1 << 49)
+#define CPUACTLR_DIS_DMB_NULL	(1 << 58)
+#define CPUACTLR_DCC_AS_DCCI	(1 << 44)
+
+/*******************************************************************************
+ * Definitions of register offsets and fields in the CNTCTLBase Frame of the
+ * system level implementation of the Generic Timer.
+ ******************************************************************************/
+#define CNTNSAR			0x4
+#define CNTNSAR_NS_SHIFT(x)	x
+
+#define CNTACR_BASE(x)		(0x40 + (x << 2))
+#define CNTACR_RPCT_SHIFT	0x0
+#define CNTACR_RVCT_SHIFT	0x1
+#define CNTACR_RFRQ_SHIFT	0x2
+#define CNTACR_RVOFF_SHIFT	0x3
+#define CNTACR_RWVT_SHIFT	0x4
+#define CNTACR_RWPT_SHIFT	0x5
+
+#endif /* __ARCH_H__ */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
new file mode 100644
index 0000000..b3d2c53
--- /dev/null
+++ b/include/lib/aarch64/arch_helpers.h
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_HELPERS_H__
+#define __ARCH_HELPERS_H__
+
+#include <cdefs.h> /* For __dead2 */
+
+
+/*******************************************************************************
+ * Aarch64 translation tables manipulation helper prototypes
+ ******************************************************************************/
+unsigned long create_table_desc(unsigned long *next_table_ptr);
+unsigned long create_block_desc(unsigned long desc,
+				unsigned long addr,
+				unsigned int level);
+unsigned long create_device_block(unsigned long output_addr,
+				unsigned int level,
+				unsigned int ns);
+unsigned long create_romem_block(unsigned long output_addr,
+				unsigned int level,
+				unsigned int ns);
+unsigned long create_rwmem_block(unsigned long output_addr,
+				unsigned int level,
+				unsigned int ns);
+
+/*******************************************************************************
+ * TLB maintenance accessor prototypes
+ ******************************************************************************/
+void tlbialle1(void);
+void tlbialle1is(void);
+void tlbialle2(void);
+void tlbialle2is(void);
+void tlbialle3(void);
+void tlbialle3is(void);
+void tlbivmalle1(void);
+
+/*******************************************************************************
+ * Cache maintenance accessor prototypes
+ ******************************************************************************/
+void dcisw(unsigned long);
+void dccisw(unsigned long);
+void dccsw(unsigned long);
+void dccvac(unsigned long);
+void dcivac(unsigned long);
+void dccivac(unsigned long);
+void dccvau(unsigned long);
+void dczva(unsigned long);
+void flush_dcache_range(unsigned long, unsigned long);
+void inv_dcache_range(unsigned long, unsigned long);
+void dcsw_op_louis(unsigned int);
+void dcsw_op_all(unsigned int);
+
+void disable_mmu_el3(void);
+void disable_mmu_icache_el3(void);
+
+
+void _clean_dcache_addr(unsigned long);
+void _clean_invd_dcache_addr(unsigned long);
+
+
+/*******************************************************************************
+ * Misc. accessor prototypes
+ ******************************************************************************/
+void enable_irq(void);
+void enable_fiq(void);
+void enable_serror(void);
+void enable_debug_exceptions(void);
+
+void disable_irq(void);
+void disable_fiq(void);
+void disable_serror(void);
+void disable_debug_exceptions(void);
+
+unsigned long read_id_pfr1_el1(void);
+unsigned long read_id_aa64pfr0_el1(void);
+unsigned long read_current_el(void);
+unsigned long read_daif(void);
+unsigned long read_spsr_el1(void);
+unsigned long read_spsr_el2(void);
+unsigned long read_spsr_el3(void);
+unsigned long read_elr_el1(void);
+unsigned long read_elr_el2(void);
+unsigned long read_elr_el3(void);
+
+void write_daif(unsigned long);
+void write_spsr_el1(unsigned long);
+void write_spsr_el2(unsigned long);
+void write_spsr_el3(unsigned long);
+void write_elr_el1(unsigned long);
+void write_elr_el2(unsigned long);
+void write_elr_el3(unsigned long);
+
+void wfi(void);
+void wfe(void);
+void rfe(void);
+void sev(void);
+void dsb(void);
+void isb(void);
+
+unsigned int get_afflvl_shift(unsigned int);
+unsigned int mpidr_mask_lower_afflvls(unsigned long, unsigned int);
+
+void __dead2 eret(unsigned long, unsigned long,
+		unsigned long, unsigned long,
+		unsigned long, unsigned long,
+		unsigned long, unsigned long);
+
+void __dead2 smc(unsigned long, unsigned long,
+		unsigned long, unsigned long,
+		unsigned long, unsigned long,
+		unsigned long, unsigned long);
+
+/*******************************************************************************
+ * System register accessor prototypes
+ ******************************************************************************/
+unsigned long read_midr(void);
+unsigned long read_mpidr(void);
+
+unsigned long read_scr(void);
+unsigned long read_hcr(void);
+
+unsigned long read_vbar_el1(void);
+unsigned long read_vbar_el2(void);
+unsigned long read_vbar_el3(void);
+
+unsigned long read_sctlr_el1(void);
+unsigned long read_sctlr_el2(void);
+unsigned long read_sctlr_el3(void);
+
+unsigned long read_actlr_el1(void);
+unsigned long read_actlr_el2(void);
+unsigned long read_actlr_el3(void);
+
+unsigned long read_esr_el1(void);
+unsigned long read_esr_el2(void);
+unsigned long read_esr_el3(void);
+
+unsigned long read_afsr0_el1(void);
+unsigned long read_afsr0_el2(void);
+unsigned long read_afsr0_el3(void);
+
+unsigned long read_afsr1_el1(void);
+unsigned long read_afsr1_el2(void);
+unsigned long read_afsr1_el3(void);
+
+unsigned long read_far_el1(void);
+unsigned long read_far_el2(void);
+unsigned long read_far_el3(void);
+
+unsigned long read_mair_el1(void);
+unsigned long read_mair_el2(void);
+unsigned long read_mair_el3(void);
+
+unsigned long read_amair_el1(void);
+unsigned long read_amair_el2(void);
+unsigned long read_amair_el3(void);
+
+unsigned long read_rvbar_el1(void);
+unsigned long read_rvbar_el2(void);
+unsigned long read_rvbar_el3(void);
+
+unsigned long read_rmr_el1(void);
+unsigned long read_rmr_el2(void);
+unsigned long read_rmr_el3(void);
+
+unsigned long read_tcr_el1(void);
+unsigned long read_tcr_el2(void);
+unsigned long read_tcr_el3(void);
+
+unsigned long read_ttbr0_el1(void);
+unsigned long read_ttbr0_el2(void);
+unsigned long read_ttbr0_el3(void);
+
+unsigned long read_ttbr1_el1(void);
+
+unsigned long read_cptr_el2(void);
+unsigned long read_cptr_el3(void);
+
+unsigned long read_cpacr(void);
+unsigned long read_cpuectlr(void);
+unsigned int read_cntfrq_el0(void);
+unsigned int read_cntps_ctl_el1(void);
+unsigned int read_cntps_tval_el1(void);
+unsigned long read_cntps_cval_el1(void);
+unsigned long read_cntpct_el0(void);
+unsigned long read_cnthctl_el2(void);
+
+unsigned long read_tpidr_el3(void);
+
+void write_scr(unsigned long);
+void write_hcr(unsigned long);
+void write_cpacr(unsigned long);
+void write_cntfrq_el0(unsigned int);
+void write_cntps_ctl_el1(unsigned int);
+void write_cntps_tval_el1(unsigned int);
+void write_cntps_cval_el1(unsigned long);
+void write_cnthctl_el2(unsigned long);
+
+void write_vbar_el1(unsigned long);
+void write_vbar_el2(unsigned long);
+void write_vbar_el3(unsigned long);
+
+void write_sctlr_el1(unsigned long);
+void write_sctlr_el2(unsigned long);
+void write_sctlr_el3(unsigned long);
+
+void write_actlr_el1(unsigned long);
+void write_actlr_el2(unsigned long);
+void write_actlr_el3(unsigned long);
+
+void write_esr_el1(unsigned long);
+void write_esr_el2(unsigned long);
+void write_esr_el3(unsigned long);
+
+void write_afsr0_el1(unsigned long);
+void write_afsr0_el2(unsigned long);
+void write_afsr0_el3(unsigned long);
+
+void write_afsr1_el1(unsigned long);
+void write_afsr1_el2(unsigned long);
+void write_afsr1_el3(unsigned long);
+
+void write_far_el1(unsigned long);
+void write_far_el2(unsigned long);
+void write_far_el3(unsigned long);
+
+void write_mair_el1(unsigned long);
+void write_mair_el2(unsigned long);
+void write_mair_el3(unsigned long);
+
+void write_amair_el1(unsigned long);
+void write_amair_el2(unsigned long);
+void write_amair_el3(unsigned long);
+
+void write_rmr_el1(unsigned long);
+void write_rmr_el2(unsigned long);
+void write_rmr_el3(unsigned long);
+
+void write_tcr_el1(unsigned long);
+void write_tcr_el2(unsigned long);
+void write_tcr_el3(unsigned long);
+
+void write_ttbr0_el1(unsigned long);
+void write_ttbr0_el2(unsigned long);
+void write_ttbr0_el3(unsigned long);
+
+void write_ttbr1_el1(unsigned long);
+
+void write_cpuectlr(unsigned long);
+void write_cptr_el2(unsigned long);
+void write_cptr_el3(unsigned long);
+
+void write_tpidr_el3(unsigned long);
+
+void remap_zero_address(void);
+
+#define IS_IN_EL(x) \
+	(GET_EL(read_current_el()) == MODE_EL##x)
+
+#define IS_IN_EL1() IS_IN_EL(1)
+#define IS_IN_EL3() IS_IN_EL(3)
+
+
+#endif /* __ARCH_HELPERS_H__ */
diff --git a/include/lib/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h
new file mode 100644
index 0000000..5df655b
--- /dev/null
+++ b/include/lib/aarch64/xlat_tables.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __XLAT_TABLES_H__
+#define __XLAT_TABLES_H__
+
+#include <stdint.h>
+
+/*
+ * Flags for building up memory mapping attributes.
+ * These are organised so that a clear bit gives a more restrictive  mapping
+ * that a set bit, that way a bitwise-and two sets of attributes will never give
+ * an attribute which has greater access rights that any of the original
+ * attributes.
+ */
+typedef enum  {
+	MT_DEVICE	= 0 << 0,
+	MT_MEMORY	= 1 << 0,
+
+	MT_RO		= 0 << 1,
+	MT_RW		= 1 << 1,
+
+	MT_SECURE	= 0 << 2,
+	MT_NS		= 1 << 2
+} mmap_attr_t;
+
+/*
+ * Structure for specifying a single region of memory.
+ */
+typedef struct mmap_region {
+	unsigned long	base;
+	unsigned long	size;
+	mmap_attr_t	attr;
+} mmap_region_t;
+
+void mmap_add_region(unsigned long base, unsigned long size,
+			unsigned attr);
+void mmap_add(const mmap_region_t *mm);
+
+void init_xlat_tables(void);
+
+void enable_mmu_el1(void);
+void enable_mmu_el3(void);
+
+#endif /* __XLAT_TABLES_H__ */
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
new file mode 100644
index 0000000..037fa7d
--- /dev/null
+++ b/include/lib/bakery_lock.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BAKERY_LOCK_H__
+#define __BAKERY_LOCK_H__
+
+#include <platform_def.h>
+
+#define BAKERY_LOCK_MAX_CPUS		PLATFORM_CORE_COUNT
+
+typedef struct bakery_lock {
+	int owner;
+	volatile char entering[BAKERY_LOCK_MAX_CPUS];
+	volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
+} bakery_lock_t;
+
+#define NO_OWNER (-1)
+
+void bakery_lock_init(bakery_lock_t *bakery);
+void bakery_lock_get(unsigned long mpidr, bakery_lock_t *bakery);
+void bakery_lock_release(unsigned long mpidr, bakery_lock_t *bakery);
+int bakery_lock_try(unsigned long mpidr, bakery_lock_t *bakery);
+
+#endif /* __BAKERY_LOCK_H__ */
diff --git a/include/lib/cassert.h b/include/lib/cassert.h
new file mode 100644
index 0000000..0e5529d
--- /dev/null
+++ b/include/lib/cassert.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CASSERT_H__
+#define __CASSERT_H__
+
+/*******************************************************************************
+ * Macro to flag a compile time assertion. It uses the preprocessor to generate
+ * an invalid C construct if 'cond' evaluates to false.
+ * The following  compilation error is triggered if the assertion fails:
+ * "error: size of array 'msg' is negative"
+ ******************************************************************************/
+#define CASSERT(cond, msg)	typedef char msg[(cond) ? 1 : -1]
+
+#endif /* __CASSERT_H__ */
diff --git a/include/lib/io.h b/include/lib/io.h
new file mode 100644
index 0000000..43b7eda
--- /dev/null
+++ b/include/lib/io.h
@@ -0,0 +1,12 @@
+/*aml basic io module*/
+
+#ifndef __BL2_IO_H_
+#define __BL2_IO_H_
+
+#define writel(val,reg) (*((volatile unsigned *)(reg)))=(val)
+#define readl(reg)		(*((volatile unsigned *)(reg)))
+#define setbits_le32(reg,val)	(*((volatile unsigned *)(reg)))|=(val)
+#define clrbits_le32(reg,val)	(*((volatile unsigned *)(reg)))&=(~(val))
+#define clrsetbits_le32(reg,clr,set)	{unsigned __v=readl(reg);__v&=(~(clr));__v|=(set);writel(__v,reg);}
+
+#endif /*__BL2_IO_H_*/
\ No newline at end of file
diff --git a/include/lib/io_storage.h b/include/lib/io_storage.h
new file mode 100644
index 0000000..ae1158c
--- /dev/null
+++ b/include/lib/io_storage.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IO_H__
+#define __IO_H__
+
+#include <stdint.h>
+#include <stdio.h> /* For ssize_t */
+
+
+/* Device type which can be used to enable policy decisions about which device
+ * to access */
+typedef enum {
+	IO_TYPE_INVALID,
+	IO_TYPE_SEMIHOSTING,
+	IO_TYPE_MEMMAP,
+	IO_TYPE_FIRMWARE_IMAGE_PACKAGE,
+	IO_TYPE_MAX
+} io_type_t;
+
+
+/* Modes used when seeking data on a supported device */
+typedef enum {
+	IO_SEEK_INVALID,
+	IO_SEEK_SET,
+	IO_SEEK_END,
+	IO_SEEK_CUR,
+	IO_SEEK_MAX
+} io_seek_mode_t;
+
+
+/* Connector type, providing a means of identifying a device to open */
+struct io_dev_connector;
+
+
+/* File specification - used to refer to data on a device supporting file-like
+ * entities */
+typedef struct io_file_spec {
+	const char *path;
+	unsigned int mode;
+} io_file_spec_t;
+
+
+/* Block specification - used to refer to data on a device supporting
+ * block-like entities */
+typedef struct io_block_spec {
+	size_t offset;
+	size_t length;
+} io_block_spec_t;
+
+
+/* Access modes used when accessing data on a device */
+#define IO_MODE_INVALID (0)
+#define IO_MODE_RO	(1 << 0)
+#define IO_MODE_RW	(1 << 1)
+
+
+/* Return codes reported by 'io_*' APIs */
+#define IO_SUCCESS		(0)
+#define IO_FAIL			(-1)
+#define IO_NOT_SUPPORTED	(-2)
+#define IO_RESOURCES_EXHAUSTED	(-3)
+
+
+/* Open a connection to a device */
+int io_dev_open(const struct io_dev_connector *dev_con,
+		const uintptr_t dev_spec,
+		uintptr_t *dev_handle);
+
+
+/* Initialise a device explicitly - to permit lazy initialisation or
+ * re-initialisation */
+int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params);
+
+/* TODO: Consider whether an explicit "shutdown" API should be included */
+
+/* Close a connection to a device */
+int io_dev_close(uintptr_t dev_handle);
+
+
+/* Synchronous operations */
+int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle);
+
+int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset);
+
+int io_size(uintptr_t handle, size_t *length);
+
+int io_read(uintptr_t handle, uintptr_t buffer, size_t length,
+		size_t *length_read);
+
+int io_write(uintptr_t handle, const uintptr_t buffer, size_t length,
+		size_t *length_written);
+
+int io_close(uintptr_t handle);
+
+
+#endif /* __IO_H__ */
diff --git a/include/lib/mmio.h b/include/lib/mmio.h
new file mode 100644
index 0000000..5d33c59
--- /dev/null
+++ b/include/lib/mmio.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MMIO_H__
+#define __MMIO_H__
+
+#include <stdint.h>
+
+void mmio_write_8(uintptr_t addr, uint8_t value);
+uint8_t mmio_read_8(uintptr_t addr);
+
+void mmio_write_32(uintptr_t addr, uint32_t value);
+uint32_t mmio_read_32(uintptr_t addr);
+
+void mmio_write_64(uintptr_t addr, uint64_t value);
+uint64_t mmio_read_64(uintptr_t addr);
+
+#endif /* __MMIO_H__ */
diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h
new file mode 100644
index 0000000..b4eecc5
--- /dev/null
+++ b/include/lib/semihosting.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SEMIHOSTING_H__
+#define __SEMIHOSTING_H__
+
+#include <stdint.h>
+#include <stdio.h> /* For ssize_t */
+
+
+#define SEMIHOSTING_SYS_OPEN            0x01
+#define SEMIHOSTING_SYS_CLOSE           0x02
+#define SEMIHOSTING_SYS_WRITE0          0x04
+#define SEMIHOSTING_SYS_WRITEC          0x03
+#define SEMIHOSTING_SYS_WRITE           0x05
+#define SEMIHOSTING_SYS_READ            0x06
+#define SEMIHOSTING_SYS_READC           0x07
+#define SEMIHOSTING_SYS_SEEK            0x0A
+#define SEMIHOSTING_SYS_FLEN            0x0C
+#define SEMIHOSTING_SYS_REMOVE          0x0E
+#define SEMIHOSTING_SYS_SYSTEM          0x12
+#define SEMIHOSTING_SYS_ERRNO           0x13
+
+#define FOPEN_MODE_R			0x0
+#define FOPEN_MODE_RB			0x1
+#define FOPEN_MODE_RPLUS		0x2
+#define FOPEN_MODE_RPLUSB		0x3
+#define FOPEN_MODE_W			0x4
+#define FOPEN_MODE_WB			0x5
+#define FOPEN_MODE_WPLUS		0x6
+#define FOPEN_MODE_WPLUSB		0x7
+#define FOPEN_MODE_A			0x8
+#define FOPEN_MODE_AB			0x9
+#define FOPEN_MODE_APLUS		0xa
+#define FOPEN_MODE_APLUSB		0xb
+
+long semihosting_connection_supported(void);
+long semihosting_file_open(const char *file_name, size_t mode);
+long semihosting_file_seek(long file_handle, ssize_t offset);
+long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer);
+long semihosting_file_write(long file_handle,
+			    size_t *length,
+			    const uintptr_t buffer);
+long semihosting_file_close(long file_handle);
+long semihosting_file_length(long file_handle);
+long semihosting_system(char *command_line);
+long semihosting_get_flen(const char *file_name);
+long semihosting_download_file(const char *file_name,
+			       size_t buf_size,
+			       uintptr_t buf);
+void semihosting_write_char(char character);
+void semihosting_write_string(char *string);
+char semihosting_read_char(void);
+
+#endif /* __SEMIHOSTING_H__ */
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
new file mode 100644
index 0000000..cb0bc3e
--- /dev/null
+++ b/include/lib/spinlock.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SPINLOCK_H__
+#define __SPINLOCK_H__
+
+typedef struct spinlock {
+	volatile unsigned int lock;
+} spinlock_t;
+
+void spin_lock(spinlock_t *lock);
+void spin_unlock(spinlock_t *lock);
+
+#endif /* __SPINLOCK_H__ */