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authorFerass El Hafidi <vitali64pmemail@protonmail.com>2023-05-08 19:03:10 +0200
committerFerass El Hafidi <vitali64pmemail@protonmail.com>2023-05-08 19:03:10 +0200
commitf9ed707f171c8069e99e24e24c3da73d8b6f5716 (patch)
tree4da9838d387c8bc260e83f3f51f5dfa83e0b48ae /lib/aarch64/xlat_tables.c
downloadamlogic-bl2-master.tar.gz
Push old Amlogic BL2 sourcesHEADmaster
Diffstat (limited to 'lib/aarch64/xlat_tables.c')
-rw-r--r--lib/aarch64/xlat_tables.c298
1 files changed, 298 insertions, 0 deletions
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c
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+++ b/lib/aarch64/xlat_tables.c
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+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <platform_def.h>
+#include <string.h>
+#include <xlat_tables.h>
+#include <stdio.h>
+#include <fip.h>
+
+#ifndef DEBUG_XLAT_TABLE
+#define DEBUG_XLAT_TABLE 0
+#endif
+
+#if DEBUG_XLAT_TABLE
+#define debug_print(...) printf(__VA_ARGS__)
+#else
+#define debug_print(...) ((void)0)
+#endif
+
+
+#define UNSET_DESC ~0ul
+
+#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
+
+static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
+__aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
+
+static uint64_t **xlat_tables;
+//__aligned(XLAT_TABLE_SIZE) __attribute__((section("xlat_table")));
+
+static unsigned next_xlat;
+
+/*
+ * Array of all memory regions stored in order of ascending base address.
+ * The list is terminated by the first entry with size == 0.
+ */
+static mmap_region_t mmap[MAX_MMAP_REGIONS + 1];
+
+static void print_mmap(void)
+{
+#if DEBUG_XLAT_TABLE
+ debug_print("mmap:\n");
+ mmap_region_t *mm = mmap;
+ while (mm->size) {
+ debug_print(" %010lx %10lx %x\n", mm->base, mm->size, mm->attr);
+ ++mm;
+ };
+ debug_print("\n");
+#endif
+}
+
+void mmap_add_region(unsigned long base, unsigned long size, unsigned attr)
+{
+ mmap_region_t *mm = mmap;
+ mmap_region_t *mm_last = mm + sizeof(mmap) / sizeof(mmap[0]) - 1;
+
+ assert(IS_PAGE_ALIGNED(base));
+ assert(IS_PAGE_ALIGNED(size));
+
+ if (!size)
+ return;
+
+ /* Find correct place in mmap to insert new region */
+ while (mm->base < base && mm->size)
+ ++mm;
+
+ /* Make room for new region by moving other regions up by one place */
+ memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
+
+ /* Check we haven't lost the empty sentinal from the end of the array */
+ assert(mm_last->size == 0);
+
+ mm->base = base;
+ mm->size = size;
+ mm->attr = attr;
+}
+
+void mmap_add(const mmap_region_t *mm)
+{
+ while (mm->size) {
+ mmap_add_region(mm->base, mm->size, mm->attr);
+ ++mm;
+ }
+}
+
+static unsigned long mmap_desc(unsigned attr, unsigned long addr,
+ unsigned level)
+{
+ unsigned long desc = addr;
+
+ desc |= level == 3 ? TABLE_DESC : BLOCK_DESC;
+
+ desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0;
+
+ desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
+
+ desc |= LOWER_ATTRS(ACCESS_FLAG);
+
+ if (attr & MT_MEMORY) {
+ desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH);
+ if (attr & MT_RW)
+ desc |= UPPER_ATTRS(XN);
+ } else {
+ desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH);
+ desc |= UPPER_ATTRS(XN);
+ }
+
+ debug_print(attr & MT_MEMORY ? "MEM" : "DEV");
+ debug_print(attr & MT_RW ? "-RW" : "-RO");
+ debug_print(attr & MT_NS ? "-NS" : "-S");
+
+ return desc;
+}
+
+static int mmap_region_attr(mmap_region_t *mm, unsigned long base,
+ unsigned long size)
+{
+ int attr = mm->attr;
+
+ for (;;) {
+ ++mm;
+
+ if (!mm->size)
+ return attr; /* Reached end of list */
+
+ if (mm->base >= base + size)
+ return attr; /* Next region is after area so end */
+
+ if (mm->base + mm->size <= base)
+ continue; /* Next region has already been overtaken */
+
+ if ((mm->attr & attr) == attr)
+ continue; /* Region doesn't override attribs so skip */
+
+ attr &= mm->attr;
+
+ if (mm->base > base || mm->base + mm->size < base + size)
+ return -1; /* Region doesn't fully cover our area */
+ }
+}
+
+static mmap_region_t *init_xlation_table(mmap_region_t *mm, unsigned long base,
+ unsigned long *table, unsigned level)
+{
+ unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) *
+ XLAT_TABLE_ENTRIES_SHIFT;
+ unsigned level_size = 1 << level_size_shift;
+ unsigned long level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift;
+
+ assert(level <= 3);
+
+ debug_print("New xlat table:\n");
+
+ do {
+ unsigned long desc = UNSET_DESC;
+
+ if (mm->base + mm->size <= base) {
+ /* Area now after the region so skip it */
+ ++mm;
+ continue;
+ }
+
+ debug_print(" %010lx %8lx " + 6 - 2 * level, base, level_size);
+
+ if (mm->base >= base + level_size) {
+ /* Next region is after area so nothing to map yet */
+ desc = INVALID_DESC;
+ } else if (mm->base <= base &&
+ mm->base + mm->size >= base + level_size) {
+ /* Next region covers all of area */
+ int attr = mmap_region_attr(mm, base, level_size);
+ if (attr >= 0)
+ desc = mmap_desc(attr, base, level);
+ }
+ /* else Next region only partially covers area, so need */
+
+ if (desc == UNSET_DESC) {
+ /* Area not covered by a region so need finer table */
+ unsigned long *new_table = xlat_tables[next_xlat++];
+ assert(next_xlat <= MAX_XLAT_TABLES);
+ desc = TABLE_DESC | (unsigned long)new_table;
+
+ /* Recurse to fill in new table */
+ mm = init_xlation_table(mm, base, new_table, level+1);
+ }
+
+ debug_print("\n");
+
+ *table++ = desc;
+ base += level_size;
+ } while (mm->size && (base & level_index_mask));
+
+ return mm;
+}
+
+void init_xlat_tables(void)
+{
+ /* move mmu table to ddr*/
+ memset((void *)MMU_TABLE_BASE, 0, MMU_TABLE_SIZE);
+ uint64_t * xlat_tables_x[MAX_XLAT_TABLES] = {0};
+ uint32_t loop = 0;
+ for (loop=0; loop<MAX_XLAT_TABLES; loop++) {
+ xlat_tables_x[loop] = (uint64_t *)(uint64_t)(MMU_TABLE_BASE + loop * MMU_TABLE_SIZE);
+ }
+ xlat_tables = xlat_tables_x;
+
+ print_mmap();
+ init_xlation_table(mmap, 0, l1_xlation_table, 1);
+}
+
+/*******************************************************************************
+ * Macro generating the code for the function enabling the MMU in the given
+ * exception level, assuming that the pagetables have already been created.
+ *
+ * _el: Exception level at which the function will run
+ * _tcr_extra: Extra bits to set in the TCR register. This mask will
+ * be OR'ed with the default TCR value.
+ * _tlbi_fct: Function to invalidate the TLBs at the current
+ * exception level
+ ******************************************************************************/
+#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
+ void enable_mmu_el##_el(void) \
+ { \
+ uint64_t mair, tcr, ttbr; \
+ uint32_t sctlr; \
+ \
+ assert(IS_IN_EL(_el)); \
+ assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
+ \
+ /* Set attributes in the right indices of the MAIR */ \
+ mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
+ mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
+ ATTR_IWBWA_OWBWA_NTR_INDEX); \
+ write_mair_el##_el(mair); \
+ \
+ /* Invalidate TLBs at the current exception level */ \
+ _tlbi_fct(); \
+ \
+ /* Set TCR bits as well. */ \
+ /* Inner & outer WBWA & shareable + T0SZ = 32 */ \
+ tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
+ TCR_RGN_INNER_WBA | TCR_T0SZ_4GB; \
+ tcr |= _tcr_extra; \
+ write_tcr_el##_el(tcr); \
+ \
+ /* Set TTBR bits as well */ \
+ ttbr = (uint64_t) l1_xlation_table; \
+ write_ttbr0_el##_el(ttbr); \
+ \
+ /* Ensure all translation table writes have drained */ \
+ /* into memory, the TLB invalidation is complete, */ \
+ /* and translation register writes are committed */ \
+ /* before enabling the MMU */ \
+ dsb(); \
+ isb(); \
+ \
+ sctlr = read_sctlr_el##_el(); \
+ sctlr |= SCTLR_WXN_BIT | SCTLR_I_BIT; \
+ sctlr |= SCTLR_A_BIT | SCTLR_C_BIT; \
+ write_sctlr_el##_el(sctlr); \
+ \
+ /* Ensure the MMU enable takes effect immediately */ \
+ isb(); \
+ }
+
+/* Define EL1 and EL3 variants of the function enabling the MMU */
+DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1)
+DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3)