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authorFerass El Hafidi <vitali64pmemail@protonmail.com>2023-05-08 19:03:10 +0200
committerFerass El Hafidi <vitali64pmemail@protonmail.com>2023-05-08 19:03:10 +0200
commitf9ed707f171c8069e99e24e24c3da73d8b6f5716 (patch)
tree4da9838d387c8bc260e83f3f51f5dfa83e0b48ae /plat/gxb/aarch64/cache.S
downloadamlogic-bl2-master.tar.gz
Push old Amlogic BL2 sourcesHEADmaster
Diffstat (limited to 'plat/gxb/aarch64/cache.S')
-rw-r--r--plat/gxb/aarch64/cache.S38
1 files changed, 38 insertions, 0 deletions
diff --git a/plat/gxb/aarch64/cache.S b/plat/gxb/aarch64/cache.S
new file mode 100644
index 0000000..d80c716
--- /dev/null
+++ b/plat/gxb/aarch64/cache.S
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * This file is based on sample code from ARMv8 ARM.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+ .global disable_mmu_el1
+ .global disable_mmu_icache_el1
+
+/*
+ * void disable_mmu_el1(void)
+ *
+ * disable mmu and dcache.
+ */
+func disable_mmu_el1
+ mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
+do_disable_mmu:
+ mrs x0, sctlr_el1
+ bic x0, x0, x1
+ msr sctlr_el1, x0
+ isb // ensure MMU is off
+ mov x0, #DCCISW // DCache clean and invalidate
+ b dcsw_op_all
+
+/*
+ * void disable_mmu_icache_el1(void)
+ *
+ * disable mmu and dcache.
+ */
+func disable_mmu_icache_el1
+ mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
+ b do_disable_mmu \ No newline at end of file