diff options
Diffstat (limited to 'log')
| -rw-r--r-- | log | 5316 |
1 files changed, 5316 insertions, 0 deletions
@@ -0,0 +1,5316 @@ + REALCLEAN + DEPS build/juno/debug/bl31/bl31.ld.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc -ffreestanding -Wa,--fatal-warnings -mgeneral-regs-only -D__ASSEMBLY__ -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -M -MT ./build/juno/debug/bl31/bl31.ld -MF build/juno/debug/bl31/bl31.ld.d bl31/bl31.ld.S + DEPS build/juno/debug/bl31/sysreg_helpers.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc -ffreestanding -Wa,--fatal-warnings -mgeneral-regs-only -D__ASSEMBLY__ -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -M -MT ./build/juno/debug/bl31/sysreg_helpers.o -MF build/juno/debug/bl31/sysreg_helpers.d lib/aarch64/sysreg_helpers.S + DEPS build/juno/debug/bl31/platform_helpers.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc -ffreestanding -Wa,--fatal-warnings -mgeneral-regs-only -D__ASSEMBLY__ -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -M -MT ./build/juno/debug/bl31/platform_helpers.o -MF build/juno/debug/bl31/platform_helpers.d plat/common/aarch64/platform_helpers.S + DEPS build/juno/debug/bl31/tlb_helpers.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc -ffreestanding -Wa,--fatal-warnings -mgeneral-regs-only -D__ASSEMBLY__ -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -M -MT ./build/juno/debug/bl31/tlb_helpers.o -MF build/juno/debug/bl31/tlb_helpers.d lib/aarch64/tlb_helpers.S + DEPS build/juno/debug/bl31/misc_helpers.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc -ffreestanding -Wa,--fatal-warnings -mgeneral-regs-only -D__ASSEMBLY__ -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -M -MT ./build/juno/debug/bl31/misc_helpers.o -MF build/juno/debug/bl31/misc_helpers.d lib/aarch64/misc_helpers.S + DEPS build/juno/debug/bl31/cache_helpers.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc 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build/juno/debug/bl1/plat_helpers.d plat/juno/aarch64/plat_helpers.S + DEPS build/juno/debug/bl1/bl1_plat_helpers.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc -ffreestanding -Wa,--fatal-warnings -mgeneral-regs-only -D__ASSEMBLY__ -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -M -MT ./build/juno/debug/bl1/bl1_plat_helpers.o -MF build/juno/debug/bl1/bl1_plat_helpers.d plat/juno/aarch64/bl1_plat_helpers.S + DEPS build/juno/debug/bl1/platform_up_stack.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -Wa,--gdwarf-2 -nostdinc -ffreestanding -Wa,--fatal-warnings -mgeneral-regs-only -D__ASSEMBLY__ -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -M -MT ./build/juno/debug/bl1/platform_up_stack.o -MF build/juno/debug/bl1/platform_up_stack.d plat/common/aarch64/platform_up_stack.S + DEPS build/juno/debug/bl1/plat_io_storage.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/plat_io_storage.o -MF build/juno/debug/bl1/plat_io_storage.d plat/juno/plat_io_storage.c + DEPS build/juno/debug/bl1/plat_common.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/plat_common.o -MF build/juno/debug/bl1/plat_common.d plat/common/aarch64/plat_common.c + DEPS build/juno/debug/bl1/xlat_tables.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/xlat_tables.o -MF build/juno/debug/bl1/xlat_tables.d lib/aarch64/xlat_tables.c + DEPS build/juno/debug/bl1/mmio.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/mmio.o -MF build/juno/debug/bl1/mmio.d lib/mmio.c + DEPS build/juno/debug/bl1/io_memmap.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/io_memmap.o -MF build/juno/debug/bl1/io_memmap.d drivers/io/io_memmap.c + DEPS build/juno/debug/bl1/io_fip.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/io_fip.o -MF build/juno/debug/bl1/io_fip.d drivers/io/io_fip.c + DEPS build/juno/debug/bl1/serial.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/serial.o -MF build/juno/debug/bl1/serial.d drivers/arm/serial/serial.c + DEPS build/juno/debug/bl1/io_storage.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/io_storage.o -MF build/juno/debug/bl1/io_storage.d lib/io_storage.c + DEPS build/juno/debug/bl1/std.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/std.o -MF build/juno/debug/bl1/std.d lib/stdlib/std.c + DEPS build/juno/debug/bl1/xlat_helpers.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/xlat_helpers.o -MF build/juno/debug/bl1/xlat_helpers.d lib/aarch64/xlat_helpers.c + DEPS build/juno/debug/bl1/debug.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/debug.o -MF build/juno/debug/bl1/debug.d common/debug.c + DEPS build/juno/debug/bl1/bl_common.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/bl_common.o -MF build/juno/debug/bl1/bl_common.d common/bl_common.c + DEPS build/juno/debug/bl1/bl1_arch_setup.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/bl1_arch_setup.o -MF build/juno/debug/bl1/bl1_arch_setup.d bl1/aarch64/bl1_arch_setup.c + DEPS build/juno/debug/bl1/bl1_main.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/bl1_main.o -MF build/juno/debug/bl1/bl1_main.d bl1/bl1_main.c + DEPS build/juno/debug/bl1/juno_common.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/juno_common.o -MF build/juno/debug/bl1/juno_common.d plat/juno/aarch64/juno_common.c + DEPS build/juno/debug/bl1/bl1_plat_setup.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/bl1_plat_setup.o -MF build/juno/debug/bl1/bl1_plat_setup.d plat/juno/bl1_plat_setup.c + DEPS build/juno/debug/bl1/cci400.d +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -M -MT ./build/juno/debug/bl1/cci400.o -MF build/juno/debug/bl1/cci400.d drivers/arm/cci400/cci400.c + CC lib/locks/bakery/bakery_lock.c +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -c lib/locks/bakery/bakery_lock.c -o build/juno/debug/bl2/bakery_lock.o + CC plat/juno/bl2_plat_setup.c +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -c plat/juno/bl2_plat_setup.c -o build/juno/debug/bl2/bl2_plat_setup.o + CC plat/juno/mhu.c +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -c plat/juno/mhu.c -o build/juno/debug/bl2/mhu.o + CC plat/juno/aarch64/juno_common.c +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -c plat/juno/aarch64/juno_common.c -o build/juno/debug/bl2/juno_common.o + CC plat/juno/scp_bootloader.c +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -c plat/juno/scp_bootloader.c -o build/juno/debug/bl2/scp_bootloader.o + CC plat/juno/scpi.c +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -c plat/juno/scpi.c -o build/juno/debug/bl2/scpi.o + CC bl2/bl2_main.c +/mnt/fileroot/xiaobo.gu/work/toolchain/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-gcc -g -nostdinc -pedantic -ffreestanding -Wall -mgeneral-regs-only -std=c99 -c -Os -DIMF_READ_INTERRUPT_ID=0 -DDEBUG=1 -DNS_TIMER_SWITCH=0 -DRESET_TO_BL31=0 -Iinclude/bl1 -Iinclude/bl2 -Iinclude/bl31 -Iinclude/bl31/services -Iinclude/bl32 -Iinclude/bl32/payloads -Iinclude/common -Iinclude/drivers -Iinclude/drivers/arm -Iinclude/drivers/serial -Iinclude/lib -Iinclude/lib/aarch64 -Iinclude/plat/common -Iinclude/stdlib -Iinclude/stdlib/sys -Iplat/juno/include/ -ffunction-sections -fdata-sections -c bl2/bl2_main.c -o build/juno/debug/bl2/bl2_main.o +In file included from bl2/firmware/spl.c:4:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_eth_pinmux.h:29:0: warning: "ETH_BANK0_GPIOY1_Y9" redefined [enabled by default] + #define ETH_BANK0_GPIOY1_Y9 (0) + ^ +In file included from bl2/firmware/spl.c:3:0, + from bl2/bl2_main.c:43: +bl2/firmware/am_eth_pinmux.h:17:0: note: this is the location of the previous definition + #define ETH_BANK0_GPIOY1_Y9 0 + ^ +In file included from bl2/firmware/spl.c:4:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_eth_pinmux.h:30:0: warning: "ETH_BANK0_REG1" redefined [enabled by default] + #define ETH_BANK0_REG1 (6) + ^ +In file included from bl2/firmware/spl.c:3:0, + from bl2/bl2_main.c:43: +bl2/firmware/am_eth_pinmux.h:18:0: note: this is the location of the previous definition + #define ETH_BANK0_REG1 6 + ^ +In file included from bl2/firmware/spl.c:4:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_eth_pinmux.h:33:0: warning: "ETH_CLK_IN_GPIOY0_REG6_18" redefined [enabled by default] + #define ETH_CLK_IN_GPIOY0_REG6_18 (0) + ^ +In file included from bl2/firmware/spl.c:3:0, + from bl2/bl2_main.c:43: +bl2/firmware/am_eth_pinmux.h:21:0: note: this is the location of the previous definition + #define ETH_CLK_IN_GPIOY0_REG6_18 0 + ^ +In file included from bl2/firmware/spl.c:4:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_eth_pinmux.h:34:0: warning: "ETH_CLK_OUT_GPIOY0_REG6_17" redefined [enabled by default] + #define ETH_CLK_OUT_GPIOY0_REG6_17 (1) + ^ +In file included from bl2/firmware/spl.c:3:0, + from bl2/bl2_main.c:43: +bl2/firmware/am_eth_pinmux.h:22:0: note: this is the location of the previous definition + #define ETH_CLK_OUT_GPIOY0_REG6_17 1 + ^ +In file included from bl2/firmware/mtd.h:11:0, + from bl2/firmware/aml_nand.h:4, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/div64.h: In function ‘lldiv’: +bl2/firmware/div64.h:45:2: warning: implicit declaration of function ‘typeof’ [-Wimplicit-function-declaration] + do_div(__res, divisor); + ^ +bl2/firmware/div64.h:30:22: error: expected expression before ‘)’ token + (void)(((typeof(n) *)0) == ((uint64_t *)0)); \ + ^ +bl2/firmware/div64.h:45:2: note: in expansion of macro ‘do_div’ + do_div(__res, divisor); + ^ +bl2/firmware/div64.h:27:25: warning: ISO C forbids braced-groups within expressions [-Wpedantic] + # define do_div(n,base) ({ \ + ^ +bl2/firmware/div64.h:45:2: note: in expansion of macro ‘do_div’ + do_div(__res, divisor); + ^ +In file included from bl2/firmware/mtd-abi.h:11:0, + from bl2/firmware/mtd.h:12, + from bl2/firmware/aml_nand.h:4, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/compat.h: At top level: +bl2/firmware/compat.h:51:0: warning: "PAGE_SIZE" redefined [enabled by default] + #define PAGE_SIZE 4096 + ^ +In file included from bl2/bl2_main.c:31:0: +include/lib/aarch64/arch.h:329:0: note: this is the location of the previous definition + #define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) + ^ +In file included from bl2/firmware/aml_nand.h:4:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/mtd.h:50:2: error: unknown type name ‘u_long’ + u_long time; + ^ +bl2/firmware/mtd.h:51:2: error: unknown type name ‘u_long’ + u_long retries; + ^ +bl2/firmware/mtd.h:52:2: error: unknown type name ‘u_int’ + u_int dev; + ^ +bl2/firmware/mtd.h:53:2: error: unknown type name ‘u_int’ + u_int cell; + ^ +bl2/firmware/mtd.h:55:2: error: unknown type name ‘u_long’ + u_long priv; + ^ +bl2/firmware/mtd.h:56:2: error: unknown type name ‘u_char’ + u_char state; + ^ +bl2/firmware/mtd.h:62:2: error: unknown type name ‘u_int32_t’ + u_int32_t erasesize; /* For this region */ + ^ +bl2/firmware/mtd.h:63:2: error: unknown type name ‘u_int32_t’ + u_int32_t numblocks; /* Number of blocks of erasesize in this region */ + ^ +bl2/firmware/mtd.h:114:2: error: unknown type name ‘u_char’ + u_char type; + ^ +bl2/firmware/mtd.h:115:2: error: unknown type name ‘u_int32_t’ + u_int32_t flags; + ^ +bl2/firmware/mtd.h:122:2: error: unknown type name ‘u_int32_t’ + u_int32_t erasesize; + ^ +bl2/firmware/mtd.h:130:2: error: unknown type name ‘u_int32_t’ + u_int32_t writesize; + ^ +bl2/firmware/mtd.h:132:2: error: unknown type name ‘u_int32_t’ + u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + ^ +bl2/firmware/mtd.h:133:2: error: unknown type name ‘u_int32_t’ + u_int32_t oobavail; /* Available OOB bytes per block */ + ^ +bl2/firmware/mtd.h:162:38: error: unknown type name ‘loff_t’ + int (*point) (struct mtd_info *mtd, loff_t from, size_t len, + ^ +bl2/firmware/mtd.h:163:33: error: unknown type name ‘phys_addr_t’ + size_t *retlen, void **virt, phys_addr_t *phys); + ^ +bl2/firmware/mtd.h:166:41: error: unknown type name ‘loff_t’ + void (*unpoint) (struct mtd_info *mtd, loff_t from, size_t len); + ^ +bl2/firmware/mtd.h:169:37: error: unknown type name ‘loff_t’ + int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:169:78: error: unknown type name ‘u_char’ + int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:170:38: error: unknown type name ‘loff_t’ + int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + ^ +bl2/firmware/mtd.h:170:38: error: unknown type name ‘u_char’ +bl2/firmware/mtd.h:179:44: error: unknown type name ‘loff_t’ + int (*panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + ^ +bl2/firmware/mtd.h:179:44: error: unknown type name ‘u_char’ +bl2/firmware/mtd.h:181:41: error: unknown type name ‘loff_t’ + int (*read_oob) (struct mtd_info *mtd, loff_t from, + ^ +bl2/firmware/mtd.h:183:42: error: unknown type name ‘loff_t’ + int (*write_oob) (struct mtd_info *mtd, loff_t to, + ^ +bl2/firmware/mtd.h:192:51: error: unknown type name ‘loff_t’ + int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:192:92: error: unknown type name ‘u_char’ + int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:194:51: error: unknown type name ‘loff_t’ + int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:194:92: error: unknown type name ‘u_char’ + int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:195:52: error: unknown type name ‘loff_t’ + int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:195:93: error: unknown type name ‘u_char’ + int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + ^ +bl2/firmware/mtd.h:196:51: error: unknown type name ‘loff_t’ + int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len); + ^ +bl2/firmware/mtd.h:211:37: error: unknown type name ‘loff_t’ + int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); + ^ +bl2/firmware/mtd.h:212:39: error: unknown type name ‘loff_t’ + int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); + ^ +bl2/firmware/mtd.h:215:44: error: unknown type name ‘loff_t’ + int (*block_isbad) (struct mtd_info *mtd, loff_t ofs); + ^ +bl2/firmware/mtd.h:216:46: error: unknown type name ‘loff_t’ + int (*block_markbad) (struct mtd_info *mtd, loff_t ofs); + ^ +In file included from bl2/firmware/mtd.h:11:0, + from bl2/firmware/aml_nand.h:4, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/mtd.h: In function ‘mtd_div_by_eb’: +bl2/firmware/div64.h:30:22: error: expected expression before ‘)’ token + (void)(((typeof(n) *)0) == ((uint64_t *)0)); \ + ^ +bl2/firmware/mtd.h:243:2: note: in expansion of macro ‘do_div’ + do_div(sz, mtd->erasesize); + ^ +bl2/firmware/div64.h:27:25: warning: ISO C forbids braced-groups within expressions [-Wpedantic] + # define do_div(n,base) ({ \ + ^ +bl2/firmware/mtd.h:243:2: note: in expansion of macro ‘do_div’ + do_div(sz, mtd->erasesize); + ^ +bl2/firmware/mtd.h: In function ‘mtd_mod_by_eb’: +bl2/firmware/div64.h:30:22: error: expected expression before ‘)’ token + (void)(((typeof(n) *)0) == ((uint64_t *)0)); \ + ^ +bl2/firmware/mtd.h:249:9: note: in expansion of macro ‘do_div’ + return do_div(sz, mtd->erasesize); + ^ +bl2/firmware/div64.h:27:25: warning: ISO C forbids braced-groups within expressions [-Wpedantic] + # define do_div(n,base) ({ \ + ^ +bl2/firmware/mtd.h:249:9: note: in expansion of macro ‘do_div’ + return do_div(sz, mtd->erasesize); + ^ +In file included from bl2/firmware/aml_nand.h:4:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/mtd.h: At top level: +bl2/firmware/mtd.h:307:25: warning: ISO C does not permit named variadic macros [-Wvariadic-macros] + #define MTDDEBUG(n, args...) \ + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:450:2: error: unknown type name ‘u8’ + u8 id[MAX_ID_LEN]; + ^ +bl2/firmware/nand.h:458:2: error: unknown type name ‘u8’ + u8 onfi_mode; + ^ +bl2/firmware/nand.h:467:2: error: unknown type name ‘u_int32_t’ + u_int32_t mask_flags; + ^ +bl2/firmware/nand.h:480:10: error: unknown type name ‘u_char’ + u_char env_valid; + ^ +bl2/firmware/nand.h:481:10: error: unknown type name ‘u_char’ + u_char env_init; + ^ +bl2/firmware/nand.h:482:10: error: unknown type name ‘u_char’ + u_char part_num_before_sys; + ^ +bl2/firmware/nand.h:530:2: error: unknown type name ‘u_char’ + u_char env_valid; + ^ +bl2/firmware/nand.h:531:2: error: unknown type name ‘u_char’ + u_char env_init; + ^ +bl2/firmware/nand.h:532:2: error: unknown type name ‘u_char’ + u_char part_num_before_sys; + ^ +bl2/firmware/nand.h:639:2: error: unknown type name ‘u8’ + u8 flag; + ^ +bl2/firmware/nand.h:640:2: error: unknown type name ‘u8’ + u8 reg_cnt; + ^ +bl2/firmware/nand.h:641:2: error: unknown type name ‘u8’ + u8 retry_cnt; + ^ +bl2/firmware/nand.h:642:2: error: unknown type name ‘u8’ + u8 default_flag; + ^ +bl2/firmware/nand.h:643:2: error: unknown type name ‘u8’ + u8 cur_cnt[MAX_CHIP_NUM]; + ^ +bl2/firmware/nand.h:644:2: error: unknown type name ‘u8’ + u8 reg_addr[READ_RETRY_REG_NUM]; + ^ +bl2/firmware/nand.h:645:2: error: unknown type name ‘u8’ + u8 reg_default_value[MAX_CHIP_NUM][READ_RETRY_REG_NUM]; + ^ +bl2/firmware/nand.h:655:2: error: unknown type name ‘u8’ + u8 flag; + ^ +bl2/firmware/nand.h:656:2: error: unknown type name ‘u8’ + u8 reg_cnt; + ^ +bl2/firmware/nand.h:657:2: error: unknown type name ‘u8’ + u8 reg_addr[ENHANCE_SLC_REG_NUM]; + ^ +bl2/firmware/nand.h:658:2: error: unknown type name ‘u8’ + u8 reg_default_value[MAX_CHIP_NUM][ENHANCE_SLC_REG_NUM]; + ^ +bl2/firmware/nand.h:667:2: error: unknown type name ‘u8’ + u8 slc_flag; + ^ +bl2/firmware/nand.h:668:2: error: unknown type name ‘u8’ + u8 dynamic_read_flag; + ^ +bl2/firmware/nand.h:669:2: error: unknown type name ‘u8’ + u8 read_case_num_max_lower_page;//Nmax _lower_page + ^ +bl2/firmware/nand.h:670:2: error: unknown type name ‘u8’ + u8 read_case_num_max_upper_page;//Nmax_upper_page + ^ +bl2/firmware/nand.h:671:2: error: unknown type name ‘u8’ + u8 cur_case_num_lower_page[MAX_CHIP_NUM];//N_lower_page + ^ +bl2/firmware/nand.h:672:2: error: unknown type name ‘u8’ + u8 cur_case_num_upper_page[MAX_CHIP_NUM];//N_upper_page + ^ +bl2/firmware/nand.h:673:2: error: unknown type name ‘u8’ + u8 reg_addr_init[DYNAMIC_REG_INIT_NUM]; + ^ +bl2/firmware/nand.h:674:2: error: unknown type name ‘u8’ + u8 reg_addr_lower_page[DYNAMIC_REG_NUM]; + ^ +bl2/firmware/nand.h:675:2: error: unknown type name ‘u8’ + u8 reg_addr_upper_page[DYNAMIC_REG_NUM]; + ^ +bl2/firmware/nand.h:686:5: error: unknown type name ‘u8’ + u8 type; + ^ +bl2/firmware/nand.h:702:2: error: unknown type name ‘u8’ + u8 mfr_type; + ^ +bl2/firmware/nand.h:712:2: error: unknown type name ‘u8’ + u8 plane_num; + ^ +bl2/firmware/nand.h:713:2: error: unknown type name ‘u8’ + u8 chip_num; + ^ +bl2/firmware/nand.h:714:2: error: unknown type name ‘u8’ + u8 internal_chipnr; + ^ +bl2/firmware/nand.h:724:2: error: unknown type name ‘u8’ + u8 user_byte_mode; + ^ +bl2/firmware/nand.h:725:2: error: unknown type name ‘u8’ + u8 ops_mode; + ^ +bl2/firmware/nand.h:726:2: error: unknown type name ‘u8’ + u8 cached_prog_status; + ^ +bl2/firmware/nand.h:727:2: error: unknown type name ‘u8’ + u8 max_bch_mode; + ^ +bl2/firmware/nand.h:738:2: error: unknown type name ‘u8’ + u8 ecc_cnt_limit; + ^ +bl2/firmware/nand.h:739:2: error: unknown type name ‘u8’ + u8 ecc_cnt_cur; + ^ +bl2/firmware/nand.h:740:2: error: unknown type name ‘u8’ + u8 ecc_max; + ^ +bl2/firmware/nand.h:749:20: error: field ‘chip’ has incomplete type + struct nand_chip chip; + ^ +bl2/firmware/nand.h:750:2: error: unknown type name ‘u8’ + u8 key_protect; + ^ +bl2/firmware/nand.h:803:36: error: field ‘platform_nand_data’ has incomplete type + struct platform_nand_data platform_nand_data; + ^ +bl2/firmware/nand.h:808:2: error: unknown type name ‘u8’ + u8 dev_num; + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h: In function ‘mtd_to_nand_chip’: +bl2/firmware/nand.h:79:16: error: expected declaration specifiers or ‘...’ before ‘(’ token + const typeof( ((type *)0)->member ) *__mptr = (const typeof( ((type *)0)->member ) *)(ptr); \ + ^ +bl2/firmware/nand.h:813:9: note: in expansion of macro ‘container_of’ + return container_of(mtd, struct aml_nand_chip, mtd); + ^ +bl2/firmware/nand.h:80:20: error: ‘__mptr’ undeclared (first use in this function) + (type *)( (char *)__mptr - offsetof(type,member) );}) + ^ +bl2/firmware/nand.h:813:9: note: in expansion of macro ‘container_of’ + return container_of(mtd, struct aml_nand_chip, mtd); + ^ +bl2/firmware/nand.h:80:20: note: each undeclared identifier is reported only once for each function it appears in + (type *)( (char *)__mptr - offsetof(type,member) );}) + ^ +bl2/firmware/nand.h:813:9: note: in expansion of macro ‘container_of’ + return container_of(mtd, struct aml_nand_chip, mtd); + ^ +bl2/firmware/nand.h:813:34: warning: implicit declaration of function ‘offsetof’ [-Wimplicit-function-declaration] + return container_of(mtd, struct aml_nand_chip, mtd); + ^ +bl2/firmware/nand.h:80:3: note: in definition of macro ‘container_of’ + (type *)( (char *)__mptr - offsetof(type,member) );}) + ^ +bl2/firmware/nand.h:813:27: error: expected expression before ‘struct’ + return container_of(mtd, struct aml_nand_chip, mtd); + ^ +bl2/firmware/nand.h:80:38: note: in definition of macro ‘container_of’ + (type *)( (char *)__mptr - offsetof(type,member) );}) + ^ +bl2/firmware/nand.h:78:41: warning: ISO C forbids braced-groups within expressions [-Wpedantic] + #define container_of(ptr, type, member) ({ \ + ^ +bl2/firmware/nand.h:813:9: note: in expansion of macro ‘container_of’ + return container_of(mtd, struct aml_nand_chip, mtd); + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h: In function ‘nand_get_chip’: +bl2/firmware/nand.h:819:2: warning: implicit declaration of function ‘SET_CBUS_REG_MASK’ [-Wimplicit-function-declaration] + SET_CBUS_REG_MASK(P_PAD_PULL_UP_EN_REG2, 0x84ff); + ^ +bl2/firmware/nand.h:819:20: error: ‘P_PAD_PULL_UP_EN_REG2’ undeclared (first use in this function) + SET_CBUS_REG_MASK(P_PAD_PULL_UP_EN_REG2, 0x84ff); + ^ +bl2/firmware/nand.h:822:20: error: ‘P_PAD_PULL_UP_REG2’ undeclared (first use in this function) + SET_CBUS_REG_MASK(P_PAD_PULL_UP_REG2, 0x0400); + ^ +bl2/firmware/nand.h:824:20: error: ‘P_PERIPHS_PIN_MUX_2’ undeclared (first use in this function) + SET_CBUS_REG_MASK(P_PERIPHS_PIN_MUX_2, ((0x3ff<<18) | (1<<17))); + ^ +bl2/firmware/nand.h: In function ‘nand_release_chip’: +bl2/firmware/nand.h:829:2: warning: implicit declaration of function ‘CLEAR_CBUS_REG_MASK’ [-Wimplicit-function-declaration] + CLEAR_CBUS_REG_MASK(P_PAD_PULL_UP_REG2, 0x0400); + ^ +bl2/firmware/nand.h:829:22: error: ‘P_PAD_PULL_UP_REG2’ undeclared (first use in this function) + CLEAR_CBUS_REG_MASK(P_PAD_PULL_UP_REG2, 0x0400); + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h: At top level: +bl2/firmware/aml_nand.h:8:0: warning: "NAND_CMD" redefined [enabled by default] + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:84:0: note: this is the location of the previous definition + #define NAND_CMD P_NAND_BASE+0x0 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:9:0: warning: "NAND_CFG" redefined [enabled by default] + #define NAND_CFG ((0xc1108604-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:85:0: note: this is the location of the previous definition + #define NAND_CFG P_NAND_BASE+0x1 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:10:0: warning: "NAND_DADR" redefined [enabled by default] + #define NAND_DADR ((0xc1108608-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:86:0: note: this is the location of the previous definition + #define NAND_DADR P_NAND_BASE+0x2 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:11:0: warning: "NAND_IADR" redefined [enabled by default] + #define NAND_IADR ((0xc110860c-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:87:0: note: this is the location of the previous definition + #define NAND_IADR P_NAND_BASE+0x3 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:12:0: warning: "NAND_BUF" redefined [enabled by default] + #define NAND_BUF ((0xc1108610-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:88:0: note: this is the location of the previous definition + #define NAND_BUF P_NAND_BASE+0x4 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:13:0: warning: "NAND_INFO" redefined [enabled by default] + #define NAND_INFO ((0xc1108614-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:89:0: note: this is the location of the previous definition + #define NAND_INFO P_NAND_BASE+0x5 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:14:0: warning: "NAND_DC" redefined [enabled by default] + #define NAND_DC ((0xc1108618-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:90:0: note: this is the location of the previous definition + #define NAND_DC P_NAND_BASE+0x6 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:15:0: warning: "NAND_ADR" redefined [enabled by default] + #define NAND_ADR ((0xc110861c-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:91:0: note: this is the location of the previous definition + #define NAND_ADR P_NAND_BASE+0x7 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:16:0: warning: "NAND_DL" redefined [enabled by default] + #define NAND_DL ((0xc1108620-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:92:0: note: this is the location of the previous definition + #define NAND_DL P_NAND_BASE+0x8 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:17:0: warning: "NAND_DH" redefined [enabled by default] + #define NAND_DH ((0xc1108624-IO_CBUS_BASE)>>2) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:93:0: note: this is the location of the previous definition + #define NAND_DH P_NAND_BASE+0x9 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:22:0: warning: "NAND_CYCLE_DELAY" redefined [enabled by default] + #define NAND_CYCLE_DELAY 90 + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:97:0: note: this is the location of the previous definition + #define NAND_CYCLE_DELAY 100 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:23:0: warning: "NAND_BOOT_NAME" redefined [enabled by default] + #define NAND_BOOT_NAME "nand0" + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:98:0: note: this is the location of the previous definition + #define NAND_BOOT_NAME "nandboot" + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:24:0: warning: "NAND_NORMAL_NAME" redefined [enabled by default] + #define NAND_NORMAL_NAME "nand1" + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:99:0: note: this is the location of the previous definition + #define NAND_NORMAL_NAME "nandnormal" + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:25:0: warning: "NAND_MULTI_NAME" redefined [enabled by default] + #define NAND_MULTI_NAME "nand2" + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:100:0: note: this is the location of the previous definition + #define NAND_MULTI_NAME "nandmulti" + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:79:0: warning: "DWR_SYNC" redefined [enabled by default] + #define DWR_SYNC DWR + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:163:0: note: this is the location of the previous definition + #define DWR_SYNC (0x7<<14) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:80:0: warning: "DRD_SYNC" redefined [enabled by default] + #define DRD_SYNC DRD + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:164:0: note: this is the location of the previous definition + #define DRD_SYNC (0x3<<14) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:138:0: warning: "NFC_CMD_SEED" redefined [enabled by default] + #define NFC_CMD_SEED(seed) (SEED|(seed&0x7fff)) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:224:0: note: this is the location of the previous definition + #define NFC_CMD_SEED(seed) (SEED|(0xc2 + seed&0x7fff)) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:160:0: warning: "NAND_ECC_NONE" redefined [enabled by default] + #define NAND_ECC_NONE (0x0) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:249:0: note: this is the location of the previous definition + #define NAND_ECC_NONE (0x0<<14) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:163:0: warning: "NAND_ECC_BCH16" redefined [enabled by default] + #define NAND_ECC_BCH16 (0x3) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:255:0: note: this is the location of the previous definition + #define NAND_ECC_BCH16 (0x7<<14) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:198:0: warning: "NFC_SEND_CMD_IDLE" redefined [enabled by default] + #define NFC_SEND_CMD_IDLE(ce,time) NFC_SEND_CMD(NFC_CMD_IDLE(ce,time)) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:306:0: note: this is the location of the previous definition + #define NFC_SEND_CMD_IDLE(ce,time) {while(NFC_CMDFIFO_SIZE()>0);NFC_SEND_CMD(NFC_CMD_IDLE(ce,time));} + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:238:0: warning: "NAND_DEFAULT_OPTIONS" redefined [enabled by default] + #define NAND_DEFAULT_OPTIONS (NAND_TIMING_MODE5 | NAND_ECC_BCH8_512_MODE) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:404:0: note: this is the location of the previous definition + #define NAND_DEFAULT_OPTIONS (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:244:0: warning: "AML_INTERLEAVING_MODE" redefined [enabled by default] + #define AML_INTERLEAVING_MODE 4 + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:351:0: note: this is the location of the previous definition + #define AML_INTERLEAVING_MODE 8 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:259:0: warning: "NAND_BCH16_ECC_SIZE" redefined [enabled by default] + #define NAND_BCH16_ECC_SIZE 28 + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:366:0: note: this is the location of the previous definition + #define NAND_BCH16_ECC_SIZE 26 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:274:0: warning: "NAND_ECC_BCH8_1K_MODE" redefined [enabled by default] + #define NAND_ECC_BCH8_1K_MODE 0x00000002 + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:386:0: note: this is the location of the previous definition + #define NAND_ECC_BCH8_1K_MODE 0x00000006 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:275:0: warning: "NAND_ECC_BCH16_MODE" redefined [enabled by default] + #define NAND_ECC_BCH16_MODE 0x00000003 + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:385:0: note: this is the location of the previous definition + #define NAND_ECC_BCH16_MODE 0x00000005 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:280:0: warning: "NAND_ECC_SHORT_MODE" redefined [enabled by default] + #define NAND_ECC_SHORT_MODE 0x00000008 + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:381:0: note: this is the location of the previous definition + #define NAND_ECC_SHORT_MODE 0x00000001 + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:320:8: error: redefinition of ‘struct aml_nand_flash_dev’ + struct aml_nand_flash_dev { + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:448:8: note: originally defined here + struct aml_nand_flash_dev { + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:322:2: error: unknown type name ‘u8’ + u8 id[MAX_ID_LEN]; + ^ +bl2/firmware/aml_nand.h:339:8: error: redefinition of ‘struct aml_nand_chip’ + struct aml_nand_chip { + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:700:8: note: originally defined here + struct aml_nand_chip { + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:341:2: error: unknown type name ‘u8’ + u8 mfr_type; + ^ +bl2/firmware/aml_nand.h:348:2: error: unknown type name ‘u8’ + u8 plane_num; + ^ +bl2/firmware/aml_nand.h:349:2: error: unknown type name ‘u8’ + u8 chip_num; + ^ +bl2/firmware/aml_nand.h:350:2: error: unknown type name ‘u8’ + u8 internal_chipnr; + ^ +bl2/firmware/aml_nand.h:359:2: error: unknown type name ‘u8’ + u8 user_byte_mode; + ^ +bl2/firmware/aml_nand.h:360:2: error: unknown type name ‘u8’ + u8 ops_mode; + ^ +bl2/firmware/aml_nand.h:361:2: error: unknown type name ‘u8’ + u8 cached_prog_status; + ^ +bl2/firmware/aml_nand.h:372:20: error: field ‘chip’ has incomplete type + struct nand_chip chip; + ^ +bl2/firmware/aml_nand.h:400:8: error: redefinition of ‘struct aml_nand_platform’ + struct aml_nand_platform { + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:758:9: note: originally defined here + struct aml_nand_platform *platform; + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:414:36: error: field ‘platform_nand_data’ has incomplete type + struct platform_nand_data platform_nand_data; + ^ +bl2/firmware/aml_nand.h:417:8: error: redefinition of ‘struct aml_nand_device’ + struct aml_nand_device { + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:806:8: note: originally defined here + struct aml_nand_device { + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h:419:2: error: unknown type name ‘u8’ + u8 dev_num; + ^ +bl2/firmware/aml_nand.h:424:21: error: redefinition of ‘nand_get_chip’ + static void inline nand_get_chip(void ) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:816:21: note: previous definition of ‘nand_get_chip’ was here + static void inline nand_get_chip(void ) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/aml_nand.h: In function ‘nand_get_chip’: +bl2/firmware/aml_nand.h:426:15: error: ‘P_PREG_PAD_GPIO3_EN_N’ undeclared (first use in this function) + setbits_le32(P_PREG_PAD_GPIO3_EN_N,0x3ffff); //disable gpio output + ^ +include/drivers/serial/serial.h:59:55: note: in definition of macro ‘setbits_le32’ + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/aml_nand.h:428:15: error: ‘P_PERIPHS_PIN_MUX_5’ undeclared (first use in this function) + setbits_le32(P_PERIPHS_PIN_MUX_5,0x7<<7); + ^ +include/drivers/serial/serial.h:59:55: note: in definition of macro ‘setbits_le32’ + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/aml_nand.h:433:15: error: ‘P_PERIPHS_PIN_MUX_2’ undeclared (first use in this function) + setbits_le32(P_PERIPHS_PIN_MUX_2, (1<<27) | (1<<26) | (1<<25) | (0xf<<18)); + ^ +include/drivers/serial/serial.h:59:55: note: in definition of macro ‘setbits_le32’ + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h: At top level: +bl2/firmware/aml_nand.h:437:20: error: redefinition of ‘nand_release_chip’ + static void inline nand_release_chip(void) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:827:20: note: previous definition of ‘nand_release_chip’ was here + static void inline nand_release_chip(void) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/aml_nand.h: In function ‘nand_release_chip’: +bl2/firmware/aml_nand.h:439:16: error: ‘P_PREG_PAD_GPIO3_O’ undeclared (first use in this function) + setbits_le32 (P_PREG_PAD_GPIO3_O,0x3ffff); + ^ +include/drivers/serial/serial.h:59:55: note: in definition of macro ‘setbits_le32’ + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/aml_nand.h:440:15: error: ‘P_PREG_PAD_GPIO3_EN_N’ undeclared (first use in this function) + clrbits_le32(P_PREG_PAD_GPIO3_EN_N,0x3ffff); //enable gpio output + ^ +include/drivers/serial/serial.h:60:55: note: in definition of macro ‘clrbits_le32’ + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/aml_nand.h:444:15: error: ‘P_PERIPHS_PIN_MUX_2’ undeclared (first use in this function) + clrbits_le32(P_PERIPHS_PIN_MUX_2, (1<<27) | (1<<26) | (1<<25) | (0xf<<18)); + ^ +include/drivers/serial/serial.h:60:55: note: in definition of macro ‘clrbits_le32’ + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h: At top level: +bl2/firmware/aml_nand.h:461:37: error: conflicting types for ‘mtd_to_nand_chip’ + static inline struct aml_nand_chip *mtd_to_nand_chip(struct mtd_info *mtd) + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:811:37: note: previous definition of ‘mtd_to_nand_chip’ was here + static inline struct aml_nand_chip *mtd_to_nand_chip(struct mtd_info *mtd) + ^ +In file included from bl2/firmware/spl.c:7:0, + from bl2/bl2_main.c:43: +bl2/firmware/aml_nand.h: In function ‘mtd_to_nand_chip’: +bl2/firmware/aml_nand.h:464:13: error: dereferencing pointer to incomplete type + return chip->priv; + ^ +bl2/firmware/aml_nand.h: At top level: +bl2/firmware/aml_nand.h:467:12: error: conflicting types for ‘aml_nand_init’ + extern int aml_nand_init(struct aml_nand_chip *aml_chip); + ^ +In file included from bl2/firmware/aml_nand.h:5:0, + from bl2/firmware/spl.c:7, + from bl2/bl2_main.c:43: +bl2/firmware/nand.h:833:12: note: previous declaration of ‘aml_nand_init’ was here + extern int aml_nand_init(struct aml_nand_chip *aml_chip); + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:35:0: warning: "P_AO_RTI_PIN_MUX_REG" redefined [enabled by default] + #define P_AO_RTI_PIN_MUX_REG AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:5:0: note: this is the location of the previous definition + #define P_AO_RTI_PIN_MUX_REG (0xc8100014) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:125:0: warning: "P_AO_UART_WFIFO" redefined [enabled by default] + #define P_AO_UART_WFIFO AOBUS_REG_ADDR(AO_UART_WFIFO) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:4:0: note: this is the location of the previous definition + #define P_AO_UART_WFIFO (0xc81004c0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:6:4: warning: #warning is a GCC extension [enabled by default] + #warning(Please check the IO_AOBUS_BASE!) + ^ +bl2/firmware/c_always_on_pointer.h:6:4: warning: #warning (Please check the IO_AOBUS_BASE!) [-Wcpp] +bl2/firmware/c_always_on_pointer.h:17:0: warning: "P_AO_RTI_STATUS_REG0" redefined [enabled by default] + #define P_AO_RTI_STATUS_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x00 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:25:0: note: this is the location of the previous definition + #define P_AO_RTI_STATUS_REG0 AOBUS_REG_ADDR(AO_RTI_STATUS_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:18:0: warning: "P_AO_RTI_STATUS_REG1" redefined [enabled by default] + #define P_AO_RTI_STATUS_REG1 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x01 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:27:0: note: this is the location of the previous definition + #define P_AO_RTI_STATUS_REG1 AOBUS_REG_ADDR(AO_RTI_STATUS_REG1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:19:0: warning: "P_AO_RTI_STATUS_REG2" redefined [enabled by default] + #define P_AO_RTI_STATUS_REG2 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x02 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:29:0: note: this is the location of the previous definition + #define P_AO_RTI_STATUS_REG2 AOBUS_REG_ADDR(AO_RTI_STATUS_REG2) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:21:0: warning: "P_AO_RTI_PWR_CNTL_REG0" redefined [enabled by default] + #define P_AO_RTI_PWR_CNTL_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x04 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:33:0: note: this is the location of the previous definition + #define P_AO_RTI_PWR_CNTL_REG0 AOBUS_REG_ADDR(AO_RTI_PWR_CNTL_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:22:0: warning: "P_AO_RTI_PIN_MUX_REG" redefined [enabled by default] + #define P_AO_RTI_PIN_MUX_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x05 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:35:0: note: this is the location of the previous definition + #define P_AO_RTI_PIN_MUX_REG AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:24:0: warning: "P_AO_WD_GPIO_REG" redefined [enabled by default] + #define P_AO_WD_GPIO_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x06 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:37:0: note: this is the location of the previous definition + #define P_AO_WD_GPIO_REG AOBUS_REG_ADDR(AO_WD_GPIO_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:26:0: warning: "P_AO_REMAP_REG0" redefined [enabled by default] + #define P_AO_REMAP_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x07 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:39:0: note: this is the location of the previous definition + #define P_AO_REMAP_REG0 AOBUS_REG_ADDR(AO_REMAP_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:27:0: warning: "P_AO_REMAP_REG1" redefined [enabled by default] + #define P_AO_REMAP_REG1 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x08 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:41:0: note: this is the location of the previous definition + #define P_AO_REMAP_REG1 AOBUS_REG_ADDR(AO_REMAP_REG1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:28:0: warning: "P_AO_GPIO_O_EN_N" redefined [enabled by default] + #define P_AO_GPIO_O_EN_N (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x09 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:43:0: note: this is the location of the previous definition + #define P_AO_GPIO_O_EN_N AOBUS_REG_ADDR(AO_GPIO_O_EN_N) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:29:0: warning: "P_AO_GPIO_I" redefined [enabled by default] + #define P_AO_GPIO_I (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x0A << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:45:0: note: this is the location of the previous definition + #define P_AO_GPIO_I AOBUS_REG_ADDR(AO_GPIO_I) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:31:0: warning: "P_AO_RTI_PULL_UP_REG" redefined [enabled by default] + #define P_AO_RTI_PULL_UP_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x0B << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:47:0: note: this is the location of the previous definition + #define P_AO_RTI_PULL_UP_REG AOBUS_REG_ADDR(AO_RTI_PULL_UP_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:34:0: warning: "P_AO_RTI_WD_MARK" redefined [enabled by default] + #define P_AO_RTI_WD_MARK (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x0D << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:49:0: note: this is the location of the previous definition + #define P_AO_RTI_WD_MARK AOBUS_REG_ADDR(AO_RTI_WD_MARK) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:36:0: warning: "P_AO_RTI_GEN_CNTL_REG0" redefined [enabled by default] + #define P_AO_RTI_GEN_CNTL_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x10 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:55:0: note: this is the location of the previous definition + #define P_AO_RTI_GEN_CNTL_REG0 AOBUS_REG_ADDR(AO_RTI_GEN_CNTL_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:37:0: warning: "P_AO_WATCHDOG_REG" redefined [enabled by default] + #define P_AO_WATCHDOG_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x11 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:57:0: note: this is the location of the previous definition + #define P_AO_WATCHDOG_REG AOBUS_REG_ADDR(AO_WATCHDOG_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:38:0: warning: "P_AO_WATCHDOG_RESET" redefined [enabled by default] + #define P_AO_WATCHDOG_RESET (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x12 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:59:0: note: this is the location of the previous definition + #define P_AO_WATCHDOG_RESET AOBUS_REG_ADDR(AO_WATCHDOG_RESET) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:40:0: warning: "P_AO_TIMER_REG" redefined [enabled by default] + #define P_AO_TIMER_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x13 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:61:0: note: this is the location of the previous definition + #define P_AO_TIMER_REG AOBUS_REG_ADDR(AO_TIMER_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:41:0: warning: "P_AO_TIMERA_REG" redefined [enabled by default] + #define P_AO_TIMERA_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x14 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:63:0: note: this is the location of the previous definition + #define P_AO_TIMERA_REG AOBUS_REG_ADDR(AO_TIMERA_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:42:0: warning: "P_AO_TIMERE_REG" redefined [enabled by default] + #define P_AO_TIMERE_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x15 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:65:0: note: this is the location of the previous definition + #define P_AO_TIMERE_REG AOBUS_REG_ADDR(AO_TIMERE_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:44:0: warning: "P_AO_AHB2DDR_CNTL" redefined [enabled by default] + #define P_AO_AHB2DDR_CNTL (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x18 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:67:0: note: this is the location of the previous definition + #define P_AO_AHB2DDR_CNTL AOBUS_REG_ADDR(AO_AHB2DDR_CNTL) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:46:0: warning: "P_AO_IRQ_MASK_FIQ_SEL" redefined [enabled by default] + #define P_AO_IRQ_MASK_FIQ_SEL (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x20 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:69:0: note: this is the location of the previous definition + #define P_AO_IRQ_MASK_FIQ_SEL AOBUS_REG_ADDR(AO_IRQ_MASK_FIQ_SEL) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:47:0: warning: "P_AO_IRQ_GPIO_REG" redefined [enabled by default] + #define P_AO_IRQ_GPIO_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x21 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:71:0: note: this is the location of the previous definition + #define P_AO_IRQ_GPIO_REG AOBUS_REG_ADDR(AO_IRQ_GPIO_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:48:0: warning: "P_AO_IRQ_STAT" redefined [enabled by default] + #define P_AO_IRQ_STAT (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x22 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:73:0: note: this is the location of the previous definition + #define P_AO_IRQ_STAT AOBUS_REG_ADDR(AO_IRQ_STAT) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:49:0: warning: "P_AO_IRQ_STAT_CLR" redefined [enabled by default] + #define P_AO_IRQ_STAT_CLR (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x23 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:75:0: note: this is the location of the previous definition + #define P_AO_IRQ_STAT_CLR AOBUS_REG_ADDR(AO_IRQ_STAT_CLR) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:51:0: warning: "P_AO_DEBUG_REG0" redefined [enabled by default] + #define P_AO_DEBUG_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x28 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:77:0: note: this is the location of the previous definition + #define P_AO_DEBUG_REG0 AOBUS_REG_ADDR(AO_DEBUG_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:52:0: warning: "P_AO_DEBUG_REG1" redefined [enabled by default] + #define P_AO_DEBUG_REG1 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x29 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:79:0: note: this is the location of the previous definition + #define P_AO_DEBUG_REG1 AOBUS_REG_ADDR(AO_DEBUG_REG1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:53:0: warning: "P_AO_DEBUG_REG2" redefined [enabled by default] + #define P_AO_DEBUG_REG2 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x2a << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:81:0: note: this is the location of the previous definition + #define P_AO_DEBUG_REG2 AOBUS_REG_ADDR(AO_DEBUG_REG2) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:54:0: warning: "P_AO_DEBUG_REG3" redefined [enabled by default] + #define P_AO_DEBUG_REG3 (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x2b << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:83:0: note: this is the location of the previous definition + #define P_AO_DEBUG_REG3 AOBUS_REG_ADDR(AO_DEBUG_REG3) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:56:0: warning: "AO_IR_BLASTER_ADDR0" redefined [enabled by default] + #define AO_IR_BLASTER_ADDR0 0x30 + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:84:0: note: this is the location of the previous definition + #define AO_IR_BLASTER_ADDR0 ((0x00 << 10) | (0x30 << 2)) ///../ucode/c_always_on_pointer.h:58 + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:57:0: warning: "AO_IR_BLASTER_ADDR1" redefined [enabled by default] + #define AO_IR_BLASTER_ADDR1 0x31 + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:86:0: note: this is the location of the previous definition + #define AO_IR_BLASTER_ADDR1 ((0x00 << 10) | (0x31 << 2)) ///../ucode/c_always_on_pointer.h:59 + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:58:0: warning: "AO_IR_BLASTER_ADDR2" redefined [enabled by default] + #define AO_IR_BLASTER_ADDR2 0x32 + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:88:0: note: this is the location of the previous definition + #define AO_IR_BLASTER_ADDR2 ((0x00 << 10) | (0x32 << 2)) ///../ucode/c_always_on_pointer.h:60 + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:60:0: warning: "P_AO_CEC_GEN_CNTL" redefined [enabled by default] + #define P_AO_CEC_GEN_CNTL (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x40 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:99:0: note: this is the location of the previous definition + #define P_AO_CEC_GEN_CNTL AOBUS_REG_ADDR(AO_CEC_GEN_CNTL) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:61:0: warning: "P_AO_CEC_RW_REG" redefined [enabled by default] + #define P_AO_CEC_RW_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x41 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:101:0: note: this is the location of the previous definition + #define P_AO_CEC_RW_REG AOBUS_REG_ADDR(AO_CEC_RW_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:62:0: warning: "P_AO_CEC_INTR_MASKN" redefined [enabled by default] + #define P_AO_CEC_INTR_MASKN (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x42 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:103:0: note: this is the location of the previous definition + #define P_AO_CEC_INTR_MASKN AOBUS_REG_ADDR(AO_CEC_INTR_MASKN) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:63:0: warning: "P_AO_CEC_INTR_CLR" redefined [enabled by default] + #define P_AO_CEC_INTR_CLR (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x43 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:105:0: note: this is the location of the previous definition + #define P_AO_CEC_INTR_CLR AOBUS_REG_ADDR(AO_CEC_INTR_CLR) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:64:0: warning: "P_AO_CEC_INTR_STAT" redefined [enabled by default] + #define P_AO_CEC_INTR_STAT (volatile unsigned long *)(IO_AOBUS_BASE | (0x00 << 10) | (0x44 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:107:0: note: this is the location of the previous definition + #define P_AO_CEC_INTR_STAT AOBUS_REG_ADDR(AO_CEC_INTR_STAT) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:69:0: warning: "P_AO_IR_DEC_LDR_ACTIVE" redefined [enabled by default] + #define P_AO_IR_DEC_LDR_ACTIVE (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x20 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:109:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_LDR_ACTIVE AOBUS_REG_ADDR(AO_IR_DEC_LDR_ACTIVE) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:70:0: warning: "P_AO_IR_DEC_LDR_IDLE" redefined [enabled by default] + #define P_AO_IR_DEC_LDR_IDLE (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x21 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:111:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_LDR_IDLE AOBUS_REG_ADDR(AO_IR_DEC_LDR_IDLE) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:71:0: warning: "P_AO_IR_DEC_LDR_REPEAT" redefined [enabled by default] + #define P_AO_IR_DEC_LDR_REPEAT (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x22 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:113:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_LDR_REPEAT AOBUS_REG_ADDR(AO_IR_DEC_LDR_REPEAT) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:72:0: warning: "P_AO_IR_DEC_BIT_0" redefined [enabled by default] + #define P_AO_IR_DEC_BIT_0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x23 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:115:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_BIT_0 AOBUS_REG_ADDR(AO_IR_DEC_BIT_0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:73:0: warning: "P_AO_IR_DEC_REG0" redefined [enabled by default] + #define P_AO_IR_DEC_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x24 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:117:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_REG0 AOBUS_REG_ADDR(AO_IR_DEC_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:74:0: warning: "P_AO_IR_DEC_FRAME" redefined [enabled by default] + #define P_AO_IR_DEC_FRAME (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x25 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:119:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_FRAME AOBUS_REG_ADDR(AO_IR_DEC_FRAME) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:75:0: warning: "P_AO_IR_DEC_STATUS" redefined [enabled by default] + #define P_AO_IR_DEC_STATUS (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x26 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:121:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_STATUS AOBUS_REG_ADDR(AO_IR_DEC_STATUS) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:76:0: warning: "P_AO_IR_DEC_REG1" redefined [enabled by default] + #define P_AO_IR_DEC_REG1 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x27 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:123:0: note: this is the location of the previous definition + #define P_AO_IR_DEC_REG1 AOBUS_REG_ADDR(AO_IR_DEC_REG1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:81:0: warning: "P_AO_UART_WFIFO" redefined [enabled by default] + #define P_AO_UART_WFIFO (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x30 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:125:0: note: this is the location of the previous definition + #define P_AO_UART_WFIFO AOBUS_REG_ADDR(AO_UART_WFIFO) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:82:0: warning: "P_AO_UART_RFIFO" redefined [enabled by default] + #define P_AO_UART_RFIFO (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x31 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:127:0: note: this is the location of the previous definition + #define P_AO_UART_RFIFO AOBUS_REG_ADDR(AO_UART_RFIFO) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:83:0: warning: "P_AO_UART_CONTROL" redefined [enabled by default] + #define P_AO_UART_CONTROL (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x32 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:129:0: note: this is the location of the previous definition + #define P_AO_UART_CONTROL AOBUS_REG_ADDR(AO_UART_CONTROL) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:84:0: warning: "P_AO_UART_STATUS" redefined [enabled by default] + #define P_AO_UART_STATUS (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x33 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:131:0: note: this is the location of the previous definition + #define P_AO_UART_STATUS AOBUS_REG_ADDR(AO_UART_STATUS) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:85:0: warning: "P_AO_UART_MISC" redefined [enabled by default] + #define P_AO_UART_MISC (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x34 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:133:0: note: this is the location of the previous definition + #define P_AO_UART_MISC AOBUS_REG_ADDR(AO_UART_MISC) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:86:0: warning: "P_AO_UART_REG5" redefined [enabled by default] + #define P_AO_UART_REG5 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x35 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:135:0: note: this is the location of the previous definition + #define P_AO_UART_REG5 AOBUS_REG_ADDR(AO_UART_REG5) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:91:0: warning: "P_AO_UART2_WFIFO" redefined [enabled by default] + #define P_AO_UART2_WFIFO (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x38 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:137:0: note: this is the location of the previous definition + #define P_AO_UART2_WFIFO AOBUS_REG_ADDR(AO_UART2_WFIFO) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:92:0: warning: "P_AO_UART2_RFIFO" redefined [enabled by default] + #define P_AO_UART2_RFIFO (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x39 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:139:0: note: this is the location of the previous definition + #define P_AO_UART2_RFIFO AOBUS_REG_ADDR(AO_UART2_RFIFO) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:93:0: warning: "P_AO_UART2_CONTROL" redefined [enabled by default] + #define P_AO_UART2_CONTROL (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x3a << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:141:0: note: this is the location of the previous definition + #define P_AO_UART2_CONTROL AOBUS_REG_ADDR(AO_UART2_CONTROL) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:94:0: warning: "P_AO_UART2_STATUS" redefined [enabled by default] + #define P_AO_UART2_STATUS (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x3b << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:143:0: note: this is the location of the previous definition + #define P_AO_UART2_STATUS AOBUS_REG_ADDR(AO_UART2_STATUS) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:95:0: warning: "P_AO_UART2_MISC" redefined [enabled by default] + #define P_AO_UART2_MISC (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x3c << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:145:0: note: this is the location of the previous definition + #define P_AO_UART2_MISC AOBUS_REG_ADDR(AO_UART2_MISC) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:96:0: warning: "P_AO_UART2_REG5" redefined [enabled by default] + #define P_AO_UART2_REG5 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x3d << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:147:0: note: this is the location of the previous definition + #define P_AO_UART2_REG5 AOBUS_REG_ADDR(AO_UART2_REG5) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:101:0: warning: "P_AO_I2C_M_0_CONTROL_REG" redefined [enabled by default] + #define P_AO_I2C_M_0_CONTROL_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x40 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:149:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_CONTROL_REG AOBUS_REG_ADDR(AO_I2C_M_0_CONTROL_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:102:0: warning: "P_AO_I2C_M_0_SLAVE_ADDR" redefined [enabled by default] + #define P_AO_I2C_M_0_SLAVE_ADDR (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x41 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:151:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_SLAVE_ADDR AOBUS_REG_ADDR(AO_I2C_M_0_SLAVE_ADDR) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:103:0: warning: "P_AO_I2C_M_0_TOKEN_LIST0" redefined [enabled by default] + #define P_AO_I2C_M_0_TOKEN_LIST0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x42 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:153:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_TOKEN_LIST0 AOBUS_REG_ADDR(AO_I2C_M_0_TOKEN_LIST0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:104:0: warning: "P_AO_I2C_M_0_TOKEN_LIST1" redefined [enabled by default] + #define P_AO_I2C_M_0_TOKEN_LIST1 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x43 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:155:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_TOKEN_LIST1 AOBUS_REG_ADDR(AO_I2C_M_0_TOKEN_LIST1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:105:0: warning: "P_AO_I2C_M_0_WDATA_REG0" redefined [enabled by default] + #define P_AO_I2C_M_0_WDATA_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x44 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:157:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_WDATA_REG0 AOBUS_REG_ADDR(AO_I2C_M_0_WDATA_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:106:0: warning: "P_AO_I2C_M_0_WDATA_REG1" redefined [enabled by default] + #define P_AO_I2C_M_0_WDATA_REG1 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x45 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:159:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_WDATA_REG1 AOBUS_REG_ADDR(AO_I2C_M_0_WDATA_REG1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:107:0: warning: "P_AO_I2C_M_0_RDATA_REG0" redefined [enabled by default] + #define P_AO_I2C_M_0_RDATA_REG0 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x46 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:161:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_RDATA_REG0 AOBUS_REG_ADDR(AO_I2C_M_0_RDATA_REG0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:108:0: warning: "P_AO_I2C_M_0_RDATA_REG1" redefined [enabled by default] + #define P_AO_I2C_M_0_RDATA_REG1 (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x47 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:163:0: note: this is the location of the previous definition + #define P_AO_I2C_M_0_RDATA_REG1 AOBUS_REG_ADDR(AO_I2C_M_0_RDATA_REG1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:112:0: warning: "P_AO_I2C_S_CONTROL_REG" redefined [enabled by default] + #define P_AO_I2C_S_CONTROL_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x50 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:165:0: note: this is the location of the previous definition + #define P_AO_I2C_S_CONTROL_REG AOBUS_REG_ADDR(AO_I2C_S_CONTROL_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:113:0: warning: "P_AO_I2C_S_SEND_REG" redefined [enabled by default] + #define P_AO_I2C_S_SEND_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x51 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:167:0: note: this is the location of the previous definition + #define P_AO_I2C_S_SEND_REG AOBUS_REG_ADDR(AO_I2C_S_SEND_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:114:0: warning: "P_AO_I2C_S_RECV_REG" redefined [enabled by default] + #define P_AO_I2C_S_RECV_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x52 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:169:0: note: this is the location of the previous definition + #define P_AO_I2C_S_RECV_REG AOBUS_REG_ADDR(AO_I2C_S_RECV_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:115:0: warning: "P_AO_I2C_S_CNTL1_REG" redefined [enabled by default] + #define P_AO_I2C_S_CNTL1_REG (volatile unsigned long *)(IO_AOBUS_BASE | (0x01 << 10) | (0x53 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:171:0: note: this is the location of the previous definition + #define P_AO_I2C_S_CNTL1_REG AOBUS_REG_ADDR(AO_I2C_S_CNTL1_REG) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:122:0: warning: "P_AO_RTC_ADDR0" redefined [enabled by default] + #define P_AO_RTC_ADDR0 (volatile unsigned long *)(0xDA004000 | (0xd0 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:173:0: note: this is the location of the previous definition + #define P_AO_RTC_ADDR0 AOBUS_REG_ADDR(AO_RTC_ADDR0) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:123:0: warning: "P_AO_RTC_ADDR1" redefined [enabled by default] + #define P_AO_RTC_ADDR1 (volatile unsigned long *)(0xDA004000 | (0xd1 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:175:0: note: this is the location of the previous definition + #define P_AO_RTC_ADDR1 AOBUS_REG_ADDR(AO_RTC_ADDR1) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:124:0: warning: "P_AO_RTC_ADDR2" redefined [enabled by default] + #define P_AO_RTC_ADDR2 (volatile unsigned long *)(0xDA004000 | (0xd2 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:177:0: note: this is the location of the previous definition + #define P_AO_RTC_ADDR2 AOBUS_REG_ADDR(AO_RTC_ADDR2) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:125:0: warning: "P_AO_RTC_ADDR3" redefined [enabled by default] + #define P_AO_RTC_ADDR3 (volatile unsigned long *)(0xDA004000 | (0xd3 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:179:0: note: this is the location of the previous definition + #define P_AO_RTC_ADDR3 AOBUS_REG_ADDR(AO_RTC_ADDR3) + ^ +In file included from bl2/firmware/spl.c:9:0, + from bl2/bl2_main.c:43: +bl2/firmware/c_always_on_pointer.h:126:0: warning: "P_AO_RTC_ADDR4" redefined [enabled by default] + #define P_AO_RTC_ADDR4 (volatile unsigned long *)(0xDA004000 | (0xd4 << 2)) + ^ +In file included from bl2/firmware/spl.c:8:0, + from bl2/bl2_main.c:43: +bl2/firmware/ao_reg.h:181:0: note: this is the location of the previous definition + #define P_AO_RTC_ADDR4 AOBUS_REG_ADDR(AO_RTC_ADDR4) + ^ +In file included from bl2/firmware/spl.c:10:0, + from bl2/bl2_main.c:43: +bl2/firmware/cache.h: In function ‘invalidate_l2_cache’: +bl2/firmware/cache.h:37:2: error: ‘asm’ undeclared (first use in this function) + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + ^ +bl2/firmware/cache.h:37:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + ^ +bl2/firmware/cache.h:35:15: warning: unused variable ‘val’ [-Wunused-variable] + unsigned int val=0; + ^ +In file included from bl2/firmware/spl.c:12:0, + from bl2/bl2_main.c:43: +bl2/firmware/canvas.h: At top level: +bl2/firmware/canvas.h:26:2: error: unknown type name ‘ulong’ + ulong addr; + ^ +bl2/firmware/canvas.h:27:2: error: unknown type name ‘u32’ + u32 width; + ^ +bl2/firmware/canvas.h:28:2: error: unknown type name ‘u32’ + u32 height; + ^ +bl2/firmware/canvas.h:29:2: error: unknown type name ‘u32’ + u32 wrap; + ^ +bl2/firmware/canvas.h:30:2: error: unknown type name ‘u32’ + u32 blkmode; + ^ +bl2/firmware/canvas.h:51:27: error: unknown type name ‘u32’ + extern void canvas_config(u32 index, ulong addr, u32 width, + ^ +bl2/firmware/canvas.h:51:38: error: unknown type name ‘ulong’ + extern void canvas_config(u32 index, ulong addr, u32 width, + ^ +bl2/firmware/canvas.h:51:50: error: unknown type name ‘u32’ + extern void canvas_config(u32 index, ulong addr, u32 width, + ^ +bl2/firmware/canvas.h:52:27: error: unknown type name ‘u32’ + u32 height, u32 wrap, u32 blkmode); + ^ +bl2/firmware/canvas.h:52:39: error: unknown type name ‘u32’ + u32 height, u32 wrap, u32 blkmode); + ^ +bl2/firmware/canvas.h:52:49: error: unknown type name ‘u32’ + u32 height, u32 wrap, u32 blkmode); + ^ +bl2/firmware/canvas.h:54:25: error: unknown type name ‘u32’ + extern void canvas_read(u32 index, canvas_t *p); + ^ +bl2/firmware/canvas.h:58:32: error: unknown type name ‘u32’ + extern void canvas_update_addr(u32 index, u32 addr); + ^ +bl2/firmware/canvas.h:58:43: error: unknown type name ‘u32’ + extern void canvas_update_addr(u32 index, u32 addr); + ^ +bl2/firmware/canvas.h:60:37: error: unknown type name ‘u32’ + extern unsigned int canvas_get_addr(u32 index); + ^ +In file included from bl2/firmware/spl.c:15:0, + from bl2/bl2_main.c:43: +bl2/firmware/reg_addr.h:102:0: warning: "P_AM_ANALOG_TOP_REG1" redefined [enabled by default] + #define P_AM_ANALOG_TOP_REG1 CBUS_REG_ADDR(AM_ANALOG_TOP_REG1) + ^ +In file included from bl2/bl2_main.c:42:0: +bl2/ddr/ddr.c:30:0: note: this is the location of the previous definition + #define P_AM_ANALOG_TOP_REG1 0xC11081BC + ^ +In file included from bl2/firmware/spl.c:15:0, + from bl2/bl2_main.c:43: +bl2/firmware/reg_addr.h:595:0: warning: "P_HHI_MPLL_CNTL5" redefined [enabled by default] + #define P_HHI_MPLL_CNTL5 CBUS_REG_ADDR(HHI_MPLL_CNTL5) + ^ +In file included from bl2/bl2_main.c:42:0: +bl2/ddr/ddr.c:31:0: note: this is the location of the previous definition + #define P_HHI_MPLL_CNTL5 0xC883C290 + ^ +In file included from bl2/firmware/spl.c:15:0, + from bl2/bl2_main.c:43: +bl2/firmware/reg_addr.h:614:0: warning: "P_HHI_SYS_PLL_CNTL" redefined [enabled by default] + #define P_HHI_SYS_PLL_CNTL CBUS_REG_ADDR(HHI_SYS_PLL_CNTL) + ^ +In file included from bl2/bl2_main.c:42:0: +bl2/ddr/ddr.c:32:0: note: this is the location of the previous definition + #define P_HHI_SYS_PLL_CNTL 0xC883C300 + ^ +In file included from bl2/firmware/spl.c:19:0, + from bl2/bl2_main.c:43: +bl2/firmware/string.h:20:44: error: unknown type name ‘__kernel_size_t’ + extern void * memcpy(void *, const void *, __kernel_size_t); + ^ +bl2/firmware/string.h:27:45: error: unknown type name ‘__kernel_size_t’ + extern void * memmove(void *, const void *, __kernel_size_t); + ^ +bl2/firmware/string.h:30:41: error: unknown type name ‘__kernel_size_t’ + extern void * memchr(const void *, int, __kernel_size_t); + ^ +bl2/firmware/string.h:39:35: error: unknown type name ‘__kernel_size_t’ + extern void * memset(void *, int, __kernel_size_t); + ^ +bl2/firmware/string.h:57:32: error: unknown type name ‘__kernel_size_t’ + extern void memzero(void *ptr, __kernel_size_t n); + ^ +In file included from bl2/firmware/spl.c:22:0, + from bl2/bl2_main.c:43: +bl2/firmware/timer.c:4:0: warning: "PREG_CTLREG0_ADDR" redefined [enabled by default] + #define PREG_CTLREG0_ADDR 0x1233333 + ^ +In file included from bl2/firmware/aml_eth_reg.h:474:0, + from bl2/firmware/spl.c:5, + from bl2/bl2_main.c:43: +bl2/firmware/register.h:372:0: note: this is the location of the previous definition + #define PREG_CTLREG0_ADDR 0x2000 + ^ +In file included from bl2/firmware/spl.c:22:0, + from bl2/bl2_main.c:43: +bl2/firmware/timer.c:5:0: warning: "P_ISA_TIMER_MUX" redefined [enabled by default] + #define P_ISA_TIMER_MUX 0x1233333 + ^ +In file included from bl2/firmware/spl.c:15:0, + from bl2/bl2_main.c:43: +bl2/firmware/reg_addr.h:446:0: note: this is the location of the previous definition + #define P_ISA_TIMER_MUX CBUS_REG_ADDR(ISA_TIMER_MUX) + ^ +In file included from bl2/firmware/spl.c:22:0, + from bl2/bl2_main.c:43: +bl2/firmware/timer.c: In function ‘timer_init’: +bl2/firmware/timer.c:8:5: warning: implicit declaration of function ‘WRITE_CBUS_REG_BITS’ [-Wimplicit-function-declaration] + WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5); + ^ +bl2/firmware/timer.c: In function ‘get_utimer’: +bl2/firmware/timer.c:15:5: warning: implicit declaration of function ‘READ_CBUS_REG’ [-Wimplicit-function-declaration] + return TIMERE_SUB(TIMERE_GET(),base); + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h: At top level: +bl2/firmware/uart.h:27:0: warning: "UART_PORT_CONS" redefined [enabled by default] + #define UART_PORT_CONS UART_PORT_AO + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:11:0: note: this is the location of the previous definition + #define UART_PORT_CONS P_AO_UART_WFIFO + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:51:0: warning: "UART_WFIFO" redefined [enabled by default] + #define UART_WFIFO 0 + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:6:0: note: this is the location of the previous definition + #define UART_WFIFO (0<<2) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:52:0: warning: "UART_RFIFO" redefined [enabled by default] + #define UART_RFIFO 1 + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:7:0: note: this is the location of the previous definition + #define UART_RFIFO (1<<2) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:53:0: warning: "UART_CONTROL" redefined [enabled by default] + #define UART_CONTROL 2 + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:8:0: note: this is the location of the previous definition + #define UART_CONTROL (2<<2) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:54:0: warning: "UART_STATUS" redefined [enabled by default] + #define UART_STATUS 3 + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:9:0: note: this is the location of the previous definition + #define UART_STATUS (3<<2) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:55:0: warning: "UART_MISC" redefined [enabled by default] + #define UART_MISC 4 + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:10:0: note: this is the location of the previous definition + #define UART_MISC (4<<2) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:58:0: warning: "P_UART" redefined [enabled by default] + #define P_UART(uart_base,reg) (uart_base + (reg<<2)) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:14:0: note: this is the location of the previous definition + #define P_UART(uart_base,reg) (uart_base+reg) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:93:0: warning: "UART_STAT_MASK_RFIFO_CNT" redefined [enabled by default] + #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:46:0: note: this is the location of the previous definition + #define UART_STAT_MASK_RFIFO_CNT (0x3f<<0) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:94:0: warning: "UART_STAT_MASK_TFIFO_CNT" redefined [enabled by default] + #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:47:0: note: this is the location of the previous definition + #define UART_STAT_MASK_TFIFO_CNT (0x3f<<8) + ^ +In file included from bl2/firmware/timming.c:5:0, + from bl2/firmware/spl.c:23, + from bl2/bl2_main.c:43: +bl2/firmware/uart.h:104:0: warning: "P_UART_MISC" redefined [enabled by default] + #define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC ) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:55:0: note: this is the location of the previous definition + #define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC) + ^ +In file included from bl2/firmware/spl.c:25:0, + from bl2/bl2_main.c:43: +bl2/firmware/serial.c: In function ‘serial_init’: +bl2/firmware/serial.c:39:5: warning: passing argument 1 of ‘serial_set_pin_port’ makes integer from pointer without a cast [enabled by default] + serial_set_pin_port(UART_PORT_CONS); + ^ +In file included from bl2/firmware/spl.c:24:0, + from bl2/bl2_main.c:43: +bl2/firmware/uartpin.c:5:21: note: expected ‘unsigned int’ but argument is of type ‘volatile long unsigned int *’ + SPL_STATIC_FUNC int serial_set_pin_port(unsigned port_base) + ^ +In file included from bl2/firmware/spl.c:27:0, + from bl2/bl2_main.c:43: +bl2/firmware/sdpinmux.c: In function ‘disable_sdio’: +bl2/firmware/sdpinmux.c:21:5: warning: implicit declaration of function ‘CBUS_REG_ADDR’ [-Wimplicit-function-declaration] + setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdpinmux.c:21:5: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/sdpinmux.c:22:5: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/sdpinmux.c:27:13: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PERIPHS_PIN_MUX_8,0x3f); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/sdpinmux.c:30:13: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PERIPHS_PIN_MUX_2,0x3f<<10); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/sdpinmux.c:33:13: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PERIPHS_PIN_MUX_6,(0x3f<<24)); + ^ +bl2/firmware/sdpinmux.c: In function ‘enable_sdio’: +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/sdpinmux.c:43:5: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/sdpinmux.c:44:5: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdpinmux.c:49:13: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PERIPHS_PIN_MUX_8,0x3f); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdpinmux.c:53:13: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PERIPHS_PIN_MUX_2,0x3f<<10); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/sdpinmux.c:57:13: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PERIPHS_PIN_MUX_2,(0x1f<<22)); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdpinmux.c:58:13: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PERIPHS_PIN_MUX_6,(0x3f<<24)); + ^ +bl2/firmware/pll.c: In function ‘clk_util_clk_msr’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/pll.c:19:2: note: in expansion of macro ‘writel’ + writel((uS_gate_time-1),P_MSR_CLK_REG0); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/pll.c:22:2: note: in expansion of macro ‘writel’ + writel(readl(P_MSR_CLK_REG0)|(clk_mux<<20) |(1<<19)|(1<<16), + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +include/drivers/serial/serial.h:57:56: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/pll.c:22:9: note: in expansion of macro ‘readl’ + writel(readl(P_MSR_CLK_REG0)|(clk_mux<<20) |(1<<19)|(1<<16), + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/pll.c:26:15: note: in expansion of macro ‘readl’ + { dummy_rd = readl(P_MSR_CLK_REG0); } + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/pll.c:29:10: note: in expansion of macro ‘readl’ + while( (readl(P_MSR_CLK_REG0) & (1 << 31)) ) {} + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/pll.c:32:2: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_MSR_CLK_REG0, 1<<16 ); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/pll.c:34:17: note: in expansion of macro ‘readl’ + measured_val = readl(P_MSR_CLK_REG2)&0xFFFFF; //20bit length + ^ +In file included from bl2/firmware/spl.c:29:0, + from bl2/bl2_main.c:43: +bl2/firmware/pll.c:16:18: warning: variable ‘dummy_rd’ set but not used [-Wunused-but-set-variable] + unsigned long dummy_rd; + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/pll.c: In function ‘pll_init’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:121:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,1); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:121:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,1); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:149:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,5); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:149:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,5); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:184:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,2); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:184:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,2); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:203:4: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,6); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/pll.c:203:4: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,6); + ^ +In file included from bl2/firmware/spl.c:32:0, + from bl2/bl2_main.c:43: +bl2/firmware/power.c: At top level: +bl2/firmware/power.c:46:30: warning: ISO C forbids empty initializer braces [-Wpedantic] + static char format_buf[12] = {}; + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/power.c: In function ‘vcck_set_default_voltage’: +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/power.c:121:5: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PERIPHS_PIN_MUX_2, (1 << 2)); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/power.c:122:5: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PERIPHS_PIN_MUX_1, (1 << 29)); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/power.c:123:15: note: in expansion of macro ‘readl’ + misc_cd = readl(P_PWM_MISC_REG_CD); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/power.c:139:20: note: in expansion of macro ‘readl’ + serial_put_hex(readl(P_PWM_PWM_C), 32); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/power.c:143:5: note: in expansion of macro ‘writel’ + writel(vcck_pwm_table[i].pwm_value, P_PWM_PWM_C); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/power.c:144:5: note: in expansion of macro ‘writel’ + writel(((misc_cd & ~(0x7f << 8)) | ((1 << 15) | (PWM_PRE_DIV << 8) | (1 << 0))), P_PWM_MISC_REG_CD); + ^ +bl2/firmware/ddr_init_hw.c: In function ‘init_dmc_m8m2’: +bl2/firmware/ddr_init_hw.c:7:37: error: ‘P_DMC_DDR_CTRL’ undeclared (first use in this function) + writel(timing_set->t_mmc_ddr_ctrl, P_DMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:14:21: error: ‘DMC_SEC_AM_PORT_CTRL’ undeclared (first use in this function) + writel(0xffffffff, DMC_SEC_AM_PORT_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:15:21: error: ‘DMC_DEV_RANGE_CTRL’ undeclared (first use in this function) + writel(0xffffffff, DMC_DEV_RANGE_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:16:21: error: ‘DMC_DEV_RANGE_CTRL1’ undeclared (first use in this function) + writel(0xffffffff, DMC_DEV_RANGE_CTRL1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:17:21: error: ‘M8M2_DMC_SEC_CTRL’ undeclared (first use in this function) + writel(0x80000000, M8M2_DMC_SEC_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:20:30: error: ‘P_DMC_2ARB_CTRL’ undeclared (first use in this function) + writel((0x1f | (0xf << 6)), P_DMC_2ARB_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:23:21: error: ‘P_DMC_REFR_CTRL2’ undeclared (first use in this function) + writel(0x20109a27, P_DMC_REFR_CTRL2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:24:19: error: ‘P_DMC_REFR_CTRL1’ undeclared (first use in this function) + writel(0x80389f, P_DMC_REFR_CTRL1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:27:17: error: ‘P_DMC_REQ_CTRL’ undeclared (first use in this function) + writel(0xffff, P_DMC_REQ_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +In file included from bl2/firmware/ddr.c:16:0, + from bl2/firmware/spl.c:34, + from bl2/bl2_main.c:43: +bl2/firmware/ddr_init_hw.c:30:2: warning: implicit declaration of function ‘asm’ [-Wimplicit-function-declaration] + asm("NOP"); + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/ddr_init_hw.c: In function ‘init_dmc_m8’: +bl2/firmware/ddr_init_hw.c:51:37: error: ‘P_MMC_DDR_CTRL’ undeclared (first use in this function) + writel(timing_set->t_mmc_ddr_ctrl, P_MMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:53:21: error: ‘DMC_SEC_RANGE0_ST’ undeclared (first use in this function) + writel(0x00000000, DMC_SEC_RANGE0_ST); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:54:21: error: ‘DMC_SEC_RANGE0_END’ undeclared (first use in this function) + writel(0xffffffff, DMC_SEC_RANGE0_END); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:55:17: error: ‘DMC_SEC_PORT0_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT0_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:56:17: error: ‘DMC_SEC_PORT1_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT1_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:57:17: error: ‘DMC_SEC_PORT2_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT2_RANGE0); + ^ +bl2/firmware/ddr_init_hw.c:57:2: note: in expansion of macro ‘writel’ + writel(0xffff, DMC_SEC_PORT2_RANGE0); + ^ +bl2/firmware/ddr_init_hw.c:58:17: error: ‘DMC_SEC_PORT3_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT3_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:59:17: error: ‘DMC_SEC_PORT4_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT4_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:60:17: error: ‘DMC_SEC_PORT5_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT5_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:61:17: error: ‘DMC_SEC_PORT6_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT6_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:62:17: error: ‘DMC_SEC_PORT7_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT7_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:63:17: error: ‘DMC_SEC_PORT8_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT8_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:64:17: error: ‘DMC_SEC_PORT9_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT9_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:65:17: error: ‘DMC_SEC_PORT10_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT10_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:66:17: error: ‘DMC_SEC_PORT11_RANGE0’ undeclared (first use in this function) + writel(0xffff, DMC_SEC_PORT11_RANGE0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:67:21: error: ‘M8_DMC_SEC_CTRL’ undeclared (first use in this function) + writel(0x80000000, M8_DMC_SEC_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:75:16: error: ‘P_MMC_REQ_CTRL’ undeclared (first use in this function) + writel(0xfff, P_MMC_REQ_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:79:41: error: ‘P_MMC_DDR_TIMING0’ undeclared (first use in this function) + writel(timing_set->t_mmc_ddr_timming0, P_MMC_DDR_TIMING0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:80:41: error: ‘P_MMC_DDR_TIMING1’ undeclared (first use in this function) + writel(timing_set->t_mmc_ddr_timming1, P_MMC_DDR_TIMING1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:81:41: error: ‘P_MMC_DDR_TIMING2’ undeclared (first use in this function) + writel(timing_set->t_mmc_ddr_timming2, P_MMC_DDR_TIMING2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:82:39: error: ‘P_MMC_AREFR_CTRL’ undeclared (first use in this function) + writel(timing_set->t_mmc_arefr_ctrl, P_MMC_AREFR_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c:85:12: error: ‘P_MMC_PARB_CTRL’ undeclared (first use in this function) + writel(0, P_MMC_PARB_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_hw.c: In function ‘ddr_init_hw’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/ddr_init_hw.c:123:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/ddr_init_hw.c:123:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +bl2/firmware/ddr_init_hw.c: In function ‘ddr_info_dump’: +bl2/firmware/ddr_init_hw.c:160:30: error: ‘M8M2_DMC_SEC_CTRL’ undeclared (first use in this function) + dmc_sec_ctrl_value = readl(M8M2_DMC_SEC_CTRL); + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_hw.c:166:30: error: ‘M8_DMC_SEC_CTRL’ undeclared (first use in this function) + dmc_sec_ctrl_value = readl(M8_DMC_SEC_CTRL); + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c: In function ‘init_pctl_ddr3’: +bl2/firmware/ddr_init_pctl.c:176:13: error: ‘P_DMC_SOFT_RST’ undeclared (first use in this function) + writel(0, P_DMC_SOFT_RST); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:177:13: error: ‘P_DMC_SOFT_RST1’ undeclared (first use in this function) + writel(0, P_DMC_SOFT_RST1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:186:13: error: ‘P_MMC_SOFT_RST’ undeclared (first use in this function) + writel(0, P_MMC_SOFT_RST); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:187:13: error: ‘P_MMC_SOFT_RST1’ undeclared (first use in this function) + writel(0, P_MMC_SOFT_RST1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:210:15: error: ‘P_DDR0_SOFT_RESET’ undeclared (first use in this function) + writel(0x0, P_DDR0_SOFT_RESET); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:214:15: error: ‘P_DDR1_SOFT_RESET’ undeclared (first use in this function) + writel(0x0, P_DDR1_SOFT_RESET); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:221:38: error: ‘P_DDR0_APD_CTRL’ undeclared (first use in this function) + writel(timing_set->t_ddr_apd_ctrl, P_DDR0_APD_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:226:38: error: ‘P_DDR0_CLK_CTRL’ undeclared (first use in this function) + writel(timing_set->t_ddr_clk_ctrl, P_DDR0_CLK_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:233:38: error: ‘P_DDR1_APD_CTRL’ undeclared (first use in this function) + writel(timing_set->t_ddr_apd_ctrl, P_DDR1_APD_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:238:38: error: ‘P_DDR1_CLK_CTRL’ undeclared (first use in this function) + writel(timing_set->t_ddr_clk_ctrl, P_DDR1_CLK_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:243:21: error: ‘P_DDR0_PUB_IOVCR0’ undeclared (first use in this function) + writel(0x49494949,P_DDR0_PUB_IOVCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:244:21: error: ‘P_DDR0_PUB_IOVCR1’ undeclared (first use in this function) + writel(0x49494949,P_DDR0_PUB_IOVCR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:247:21: error: ‘P_DDR1_PUB_IOVCR0’ undeclared (first use in this function) + writel(0x49494949,P_DDR1_PUB_IOVCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:248:21: error: ‘P_DDR1_PUB_IOVCR1’ undeclared (first use in this function) + writel(0x49494949,P_DDR1_PUB_IOVCR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:253:40: error: ‘P_DDR0_PCTL_TOGCNT1U’ undeclared (first use in this function) + writel(timing_set->t_pctl_1us_pck, P_DDR0_PCTL_TOGCNT1U); //1us = nn cycles. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:254:40: error: ‘P_DDR0_PCTL_TOGCNT100N’ undeclared (first use in this function) + writel(timing_set->t_pctl_100ns_pck, P_DDR0_PCTL_TOGCNT100N); //100ns = nn cycles. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:255:40: error: ‘P_DDR0_PCTL_TINIT’ undeclared (first use in this function) + writel(timing_set->t_pctl_init_us, P_DDR0_PCTL_TINIT); //200us. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:256:40: error: ‘P_DDR0_PCTL_TRSTH’ undeclared (first use in this function) + writel(timing_set->t_pctl_rsth_us, P_DDR0_PCTL_TRSTH); // 0 for ddr2; 2 for simulation; 500 for ddr3. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:257:40: error: ‘P_DDR0_PCTL_TRSTL’ undeclared (first use in this function) + writel(timing_set->t_pctl_rstl_us, P_DDR0_PCTL_TRSTL); // 0 for ddr2; 2 for simulation; 500 for ddr3. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:263:36: error: ‘P_DDR0_PCTL_MCFG’ undeclared (first use in this function) + writel(timing_set->t_pctl_mcfg, P_DDR0_PCTL_MCFG ); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:265:36: error: ‘P_DDR0_PCTL_MCFG1’ undeclared (first use in this function) + writel(timing_set->t_pctl_mcfg1, P_DDR0_PCTL_MCFG1); //enable hardware c_active_in; + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:267:33: error: ‘P_DDR0_PUB_DCR’ undeclared (first use in this function) + writel(timing_set->t_pub_dcr, P_DDR0_PUB_DCR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:269:35: error: ‘P_DDR0_PUB_MR0’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[0], P_DDR0_PUB_MR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:270:35: error: ‘P_DDR0_PUB_MR1’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[1], P_DDR0_PUB_MR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:271:35: error: ‘P_DDR0_PUB_MR2’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[2], P_DDR0_PUB_MR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:272:35: error: ‘P_DDR0_PUB_MR3’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[3], P_DDR0_PUB_MR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:275:38: error: ‘P_DDR0_PUB_DTPR0’ undeclared (first use in this function) + writel( timing_set->t_pub_dtpr[0], P_DDR0_PUB_DTPR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:276:38: error: ‘P_DDR0_PUB_DTPR1’ undeclared (first use in this function) + writel( timing_set->t_pub_dtpr[1], P_DDR0_PUB_DTPR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:277:38: error: ‘P_DDR0_PUB_DTPR2’ undeclared (first use in this function) + writel( timing_set->t_pub_dtpr[2], P_DDR0_PUB_DTPR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:280:60: error: ‘P_DDR0_PUB_PGCR2’ undeclared (first use in this function) + writel( (readl(P_DDR0_PUB_PGCR2) & 0xfffc0000) | 0xc00 , P_DDR0_PUB_PGCR2 ); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:284:98: error: ‘P_DDR0_PUB_DTCR’ undeclared (first use in this function) + writel( ((readl(P_DDR1_PUB_DTCR) & 0x00ffffbf) | (1 << 28 ) | (1 << 24) | (1 << 6) |(1<<23) ), P_DDR0_PUB_DTCR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:284:19: error: ‘P_DDR1_PUB_DTCR’ undeclared (first use in this function) + writel( ((readl(P_DDR1_PUB_DTCR) & 0x00ffffbf) | (1 << 28 ) | (1 << 24) | (1 << 6) |(1<<23) ), P_DDR0_PUB_DTCR); + ^ +include/drivers/serial/serial.h:57:56: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:284:13: note: in expansion of macro ‘readl’ + writel( ((readl(P_DDR1_PUB_DTCR) & 0x00ffffbf) | (1 << 28 ) | (1 << 24) | (1 << 6) |(1<<23) ), P_DDR0_PUB_DTCR); + ^ +bl2/firmware/ddr_init_pctl.c:287:15: error: ‘P_DDR0_PUB_DX0GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR0_PUB_DX0GCR3); //for pdr mode bug //for pdr mode bug this will cause some chip bit deskew jiaxing add + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:288:15: error: ‘P_DDR0_PUB_DX1GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR0_PUB_DX1GCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:289:15: error: ‘P_DDR0_PUB_DX2GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR0_PUB_DX2GCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:290:15: error: ‘P_DDR0_PUB_DX3GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR0_PUB_DX3GCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:296:47: error: ‘P_DDR0_PUB_DSGCR’ undeclared (first use in this function) + writel((readl(P_DDR0_PUB_DSGCR))|(0x1<<06), P_DDR0_PUB_DSGCR); //eanble gate extension dqs gate can help to bit deskew also + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:299:49: error: ‘P_DDR0_PUB_ZQCR’ undeclared (first use in this function) + writel(((readl(P_DDR0_PUB_ZQCR))&0xff01fffc), P_DDR0_PUB_ZQCR); //for vt bug disable IODLMT + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:306:76: error: ‘P_DDR0_PUB_ZQ0PR’ undeclared (first use in this function) + writel((timing_set->t_pub_zq0pr)|((readl(P_DDR0_PUB_ZQ0PR))&0xffffff00), P_DDR0_PUB_ZQ0PR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:309:35: error: ‘P_DDR0_PUB_DXCCR’ undeclared (first use in this function) + writel(timing_set->t_pub_dxccr, P_DDR0_PUB_DXCCR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:310:67: error: ‘P_DDR0_PUB_ACBDLR0’ undeclared (first use in this function) + writel(readl(P_DDR0_PUB_ACBDLR0) | (timing_set->t_pub_acbdlr0), P_DDR0_PUB_ACBDLR0); //place before write level + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:313:37: error: ‘P_DDR0_PUB_PTR0’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[0] , P_DDR0_PUB_PTR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:314:37: error: ‘P_DDR0_PUB_PTR1’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[1] , P_DDR0_PUB_PTR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:317:50: error: ‘P_DDR0_PUB_ACIOCR0’ undeclared (first use in this function) + writel(readl(P_DDR0_PUB_ACIOCR0) & 0xdfffffff, P_DDR0_PUB_ACIOCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:322:37: error: ‘P_DDR0_PUB_PTR3’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[3] , P_DDR0_PUB_PTR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:323:37: error: ‘P_DDR0_PUB_PTR4’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[4] , P_DDR0_PUB_PTR4); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:328:40: error: ‘P_DDR1_PCTL_TOGCNT1U’ undeclared (first use in this function) + writel(timing_set->t_pctl_1us_pck, P_DDR1_PCTL_TOGCNT1U); //1us = nn cycles. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:329:40: error: ‘P_DDR1_PCTL_TOGCNT100N’ undeclared (first use in this function) + writel(timing_set->t_pctl_100ns_pck, P_DDR1_PCTL_TOGCNT100N); //100ns = nn cycles. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:330:40: error: ‘P_DDR1_PCTL_TINIT’ undeclared (first use in this function) + writel(timing_set->t_pctl_init_us, P_DDR1_PCTL_TINIT); //200us. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:331:40: error: ‘P_DDR1_PCTL_TRSTH’ undeclared (first use in this function) + writel(timing_set->t_pctl_rsth_us, P_DDR1_PCTL_TRSTH); // 0 for ddr2; 2 for simulation; 500 for ddr3. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:332:40: error: ‘P_DDR1_PCTL_TRSTL’ undeclared (first use in this function) + writel(timing_set->t_pctl_rstl_us, P_DDR1_PCTL_TRSTL); // 0 for ddr2; 2 for simulation; 500 for ddr3. + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:338:36: error: ‘P_DDR1_PCTL_MCFG’ undeclared (first use in this function) + writel(timing_set->t_pctl_mcfg, P_DDR1_PCTL_MCFG ); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:340:36: error: ‘P_DDR1_PCTL_MCFG1’ undeclared (first use in this function) + writel(timing_set->t_pctl_mcfg1, P_DDR1_PCTL_MCFG1); //enable hardware c_active_in; + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:342:33: error: ‘P_DDR1_PUB_DCR’ undeclared (first use in this function) + writel(timing_set->t_pub_dcr, P_DDR1_PUB_DCR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:344:35: error: ‘P_DDR1_PUB_MR0’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[0], P_DDR1_PUB_MR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:345:35: error: ‘P_DDR1_PUB_MR1’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[1], P_DDR1_PUB_MR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:346:35: error: ‘P_DDR1_PUB_MR2’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[2], P_DDR1_PUB_MR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:347:35: error: ‘P_DDR1_PUB_MR3’ undeclared (first use in this function) + writel(timing_set->t_pub_mr[3], P_DDR1_PUB_MR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:353:47: error: ‘P_DDR1_PUB_DSGCR’ undeclared (first use in this function) + writel((readl(P_DDR1_PUB_DSGCR))|(0x1<<06), P_DDR1_PUB_DSGCR); //eanble gate extension dqs gate can help to bit deskew also + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:356:49: error: ‘P_DDR1_PUB_ZQCR’ undeclared (first use in this function) + writel(((readl(P_DDR1_PUB_ZQCR))&0xff01fffc), P_DDR1_PUB_ZQCR); //for vt bug disable IODLMT + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:358:38: error: ‘P_DDR1_PUB_DTPR0’ undeclared (first use in this function) + writel( timing_set->t_pub_dtpr[0], P_DDR1_PUB_DTPR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:359:38: error: ‘P_DDR1_PUB_DTPR1’ undeclared (first use in this function) + writel( timing_set->t_pub_dtpr[1], P_DDR1_PUB_DTPR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:360:38: error: ‘P_DDR1_PUB_DTPR2’ undeclared (first use in this function) + writel( timing_set->t_pub_dtpr[2], P_DDR1_PUB_DTPR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:363:60: error: ‘P_DDR1_PUB_PGCR2’ undeclared (first use in this function) + writel( (readl(P_DDR1_PUB_PGCR2) & 0xfffc0000) | 0xc00 , P_DDR1_PUB_PGCR2 ); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:370:15: error: ‘P_DDR1_PUB_DX0GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR1_PUB_DX0GCR3); //for pdr mode bug //for pdr mode bug this will cause some chip bit deskew jiaxing add + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:371:15: error: ‘P_DDR1_PUB_DX1GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR1_PUB_DX1GCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:372:15: error: ‘P_DDR1_PUB_DX2GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR1_PUB_DX2GCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:373:15: error: ‘P_DDR1_PUB_DX3GCR3’ undeclared (first use in this function) + writel(0x8, P_DDR1_PUB_DX3GCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:389:76: error: ‘P_DDR1_PUB_ZQ0PR’ undeclared (first use in this function) + writel((timing_set->t_pub_zq0pr)|((readl(P_DDR1_PUB_ZQ0PR))&0xffffff00), P_DDR1_PUB_ZQ0PR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:392:35: error: ‘P_DDR1_PUB_DXCCR’ undeclared (first use in this function) + writel(timing_set->t_pub_dxccr, P_DDR1_PUB_DXCCR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:393:67: error: ‘P_DDR1_PUB_ACBDLR0’ undeclared (first use in this function) + writel(readl(P_DDR1_PUB_ACBDLR0) | (timing_set->t_pub_acbdlr0), P_DDR1_PUB_ACBDLR0); //place before write level + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:396:37: error: ‘P_DDR1_PUB_PTR0’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[0] , P_DDR1_PUB_PTR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:397:37: error: ‘P_DDR1_PUB_PTR1’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[1] , P_DDR1_PUB_PTR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:400:50: error: ‘P_DDR1_PUB_ACIOCR0’ undeclared (first use in this function) + writel(readl(P_DDR1_PUB_ACIOCR0) & 0xdfffffff, P_DDR1_PUB_ACIOCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:405:37: error: ‘P_DDR1_PUB_PTR3’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[3] , P_DDR1_PUB_PTR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:406:37: error: ‘P_DDR1_PUB_PTR4’ undeclared (first use in this function) + writel(timing_set->t_pub_ptr[4] , P_DDR1_PUB_PTR4); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:410:17: error: ‘P_DDR0_PCTL_DFISTSTAT0’ undeclared (first use in this function) + while(!(readl(P_DDR0_PCTL_DFISTSTAT0) & 1)) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:414:13: error: ‘P_DDR0_PCTL_POWCTL’ undeclared (first use in this function) + writel(1, P_DDR0_PCTL_POWCTL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:415:17: error: ‘P_DDR0_PCTL_POWSTAT’ undeclared (first use in this function) + while(!(readl(P_DDR0_PCTL_POWSTAT) & 1) ) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:420:17: error: ‘P_DDR1_PCTL_DFISTSTAT0’ undeclared (first use in this function) + while(!(readl(P_DDR1_PCTL_DFISTSTAT0) & 1)) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:424:13: error: ‘P_DDR1_PCTL_POWCTL’ undeclared (first use in this function) + writel(1, P_DDR1_PCTL_POWCTL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:425:17: error: ‘P_DDR1_PCTL_POWSTAT’ undeclared (first use in this function) + while(!(readl(P_DDR1_PCTL_POWSTAT) & 1) ) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:432:36: error: ‘P_DDR0_PCTL_TRFC’ undeclared (first use in this function) + writel(timing_set->t_pctl_trfc, P_DDR0_PCTL_TRFC); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:433:36: error: ‘P_DDR0_PCTL_TREFI’ undeclared (first use in this function) + writel(timing_set->t_pctl_trefi, P_DDR0_PCTL_TREFI); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:435:45: error: ‘P_DDR0_PCTL_TREFI_MEM_DDR3’ undeclared (first use in this function) + writel(timing_set->t_pctl_trefi_mem_ddr3, P_DDR0_PCTL_TREFI_MEM_DDR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:436:35: error: ‘P_DDR0_PCTL_TMRD’ undeclared (first use in this function) + writel(timing_set->t_pctl_tmrd, P_DDR0_PCTL_TMRD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:437:34: error: ‘P_DDR0_PCTL_TRP’ undeclared (first use in this function) + writel(timing_set->t_pctl_trp, P_DDR0_PCTL_TRP); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:438:34: error: ‘P_DDR0_PCTL_TAL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tal, P_DDR0_PCTL_TAL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:439:35: error: ‘P_DDR0_PCTL_TCWL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcwl, P_DDR0_PCTL_TCWL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:440:34: error: ‘P_DDR0_PCTL_TCL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcl, P_DDR0_PCTL_TCL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:441:35: error: ‘P_DDR0_PCTL_TRAS’ undeclared (first use in this function) + writel(timing_set->t_pctl_tras, P_DDR0_PCTL_TRAS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:442:34: error: ‘P_DDR0_PCTL_TRC’ undeclared (first use in this function) + writel(timing_set->t_pctl_trc, P_DDR0_PCTL_TRC); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:443:35: error: ‘P_DDR0_PCTL_TRCD’ undeclared (first use in this function) + writel(timing_set->t_pctl_trcd, P_DDR0_PCTL_TRCD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:444:35: error: ‘P_DDR0_PCTL_TRRD’ undeclared (first use in this function) + writel(timing_set->t_pctl_trrd, P_DDR0_PCTL_TRRD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:445:35: error: ‘P_DDR0_PCTL_TRTP’ undeclared (first use in this function) + writel(timing_set->t_pctl_trtp, P_DDR0_PCTL_TRTP); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:446:34: error: ‘P_DDR0_PCTL_TWR’ undeclared (first use in this function) + writel(timing_set->t_pctl_twr, P_DDR0_PCTL_TWR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:447:35: error: ‘P_DDR0_PCTL_TWTR’ undeclared (first use in this function) + writel(timing_set->t_pctl_twtr, P_DDR0_PCTL_TWTR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:448:36: error: ‘P_DDR0_PCTL_TEXSR’ undeclared (first use in this function) + writel(timing_set->t_pctl_texsr, P_DDR0_PCTL_TEXSR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:449:34: error: ‘P_DDR0_PCTL_TXP’ undeclared (first use in this function) + writel(timing_set->t_pctl_txp, P_DDR0_PCTL_TXP); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:450:35: error: ‘P_DDR0_PCTL_TDQS’ undeclared (first use in this function) + writel(timing_set->t_pctl_tdqs, P_DDR0_PCTL_TDQS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:451:35: error: ‘P_DDR0_PCTL_TRTW’ undeclared (first use in this function) + writel(timing_set->t_pctl_trtw, P_DDR0_PCTL_TRTW); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:452:37: error: ‘P_DDR0_PCTL_TCKSRE’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcksre, P_DDR0_PCTL_TCKSRE); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:453:37: error: ‘P_DDR0_PCTL_TCKSRX’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcksrx, P_DDR0_PCTL_TCKSRX); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:454:35: error: ‘P_DDR0_PCTL_TMOD’ undeclared (first use in this function) + writel(timing_set->t_pctl_tmod, P_DDR0_PCTL_TMOD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:455:35: error: ‘P_DDR0_PCTL_TCKE’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcke, P_DDR0_PCTL_TCKE); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:456:36: error: ‘P_DDR0_PCTL_TZQCS’ undeclared (first use in this function) + writel(timing_set->t_pctl_tzqcs, P_DDR0_PCTL_TZQCS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:457:36: error: ‘P_DDR0_PCTL_TZQCL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tzqcl, P_DDR0_PCTL_TZQCL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:458:37: error: ‘P_DDR0_PCTL_TXPDLL’ undeclared (first use in this function) + writel(timing_set->t_pctl_txpdll, P_DDR0_PCTL_TXPDLL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:459:37: error: ‘P_DDR0_PCTL_TZQCSI’ undeclared (first use in this function) + writel(timing_set->t_pctl_tzqcsi, P_DDR0_PCTL_TZQCSI); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:460:36: error: ‘P_DDR0_PCTL_SCFG’ undeclared (first use in this function) + writel(timing_set->t_pctl_scfg, P_DDR0_PCTL_SCFG); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:469:36: error: ‘P_DDR1_PCTL_TRFC’ undeclared (first use in this function) + writel(timing_set->t_pctl_trfc, P_DDR1_PCTL_TRFC); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:470:36: error: ‘P_DDR1_PCTL_TREFI’ undeclared (first use in this function) + writel(timing_set->t_pctl_trefi, P_DDR1_PCTL_TREFI); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:472:45: error: ‘P_DDR1_PCTL_TREFI_MEM_DDR3’ undeclared (first use in this function) + writel(timing_set->t_pctl_trefi_mem_ddr3, P_DDR1_PCTL_TREFI_MEM_DDR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:473:35: error: ‘P_DDR1_PCTL_TMRD’ undeclared (first use in this function) + writel(timing_set->t_pctl_tmrd, P_DDR1_PCTL_TMRD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:474:34: error: ‘P_DDR1_PCTL_TRP’ undeclared (first use in this function) + writel(timing_set->t_pctl_trp, P_DDR1_PCTL_TRP); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:475:34: error: ‘P_DDR1_PCTL_TAL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tal, P_DDR1_PCTL_TAL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:476:35: error: ‘P_DDR1_PCTL_TCWL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcwl, P_DDR1_PCTL_TCWL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:477:34: error: ‘P_DDR1_PCTL_TCL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcl, P_DDR1_PCTL_TCL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:478:35: error: ‘P_DDR1_PCTL_TRAS’ undeclared (first use in this function) + writel(timing_set->t_pctl_tras, P_DDR1_PCTL_TRAS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:479:34: error: ‘P_DDR1_PCTL_TRC’ undeclared (first use in this function) + writel(timing_set->t_pctl_trc, P_DDR1_PCTL_TRC); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:480:35: error: ‘P_DDR1_PCTL_TRCD’ undeclared (first use in this function) + writel(timing_set->t_pctl_trcd, P_DDR1_PCTL_TRCD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:481:35: error: ‘P_DDR1_PCTL_TRRD’ undeclared (first use in this function) + writel(timing_set->t_pctl_trrd, P_DDR1_PCTL_TRRD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:482:35: error: ‘P_DDR1_PCTL_TRTP’ undeclared (first use in this function) + writel(timing_set->t_pctl_trtp, P_DDR1_PCTL_TRTP); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:483:34: error: ‘P_DDR1_PCTL_TWR’ undeclared (first use in this function) + writel(timing_set->t_pctl_twr, P_DDR1_PCTL_TWR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:484:35: error: ‘P_DDR1_PCTL_TWTR’ undeclared (first use in this function) + writel(timing_set->t_pctl_twtr, P_DDR1_PCTL_TWTR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:485:36: error: ‘P_DDR1_PCTL_TEXSR’ undeclared (first use in this function) + writel(timing_set->t_pctl_texsr, P_DDR1_PCTL_TEXSR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:486:34: error: ‘P_DDR1_PCTL_TXP’ undeclared (first use in this function) + writel(timing_set->t_pctl_txp, P_DDR1_PCTL_TXP); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:487:35: error: ‘P_DDR1_PCTL_TDQS’ undeclared (first use in this function) + writel(timing_set->t_pctl_tdqs, P_DDR1_PCTL_TDQS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:488:35: error: ‘P_DDR1_PCTL_TRTW’ undeclared (first use in this function) + writel(timing_set->t_pctl_trtw, P_DDR1_PCTL_TRTW); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:489:37: error: ‘P_DDR1_PCTL_TCKSRE’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcksre, P_DDR1_PCTL_TCKSRE); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:490:37: error: ‘P_DDR1_PCTL_TCKSRX’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcksrx, P_DDR1_PCTL_TCKSRX); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:491:35: error: ‘P_DDR1_PCTL_TMOD’ undeclared (first use in this function) + writel(timing_set->t_pctl_tmod, P_DDR1_PCTL_TMOD); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:492:35: error: ‘P_DDR1_PCTL_TCKE’ undeclared (first use in this function) + writel(timing_set->t_pctl_tcke, P_DDR1_PCTL_TCKE); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:493:36: error: ‘P_DDR1_PCTL_TZQCS’ undeclared (first use in this function) + writel(timing_set->t_pctl_tzqcs, P_DDR1_PCTL_TZQCS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:494:36: error: ‘P_DDR1_PCTL_TZQCL’ undeclared (first use in this function) + writel(timing_set->t_pctl_tzqcl, P_DDR1_PCTL_TZQCL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:495:37: error: ‘P_DDR1_PCTL_TXPDLL’ undeclared (first use in this function) + writel(timing_set->t_pctl_txpdll, P_DDR1_PCTL_TXPDLL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:496:37: error: ‘P_DDR1_PCTL_TZQCSI’ undeclared (first use in this function) + writel(timing_set->t_pctl_tzqcsi, P_DDR1_PCTL_TZQCSI); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:497:36: error: ‘P_DDR1_PCTL_SCFG’ undeclared (first use in this function) + writel(timing_set->t_pctl_scfg, P_DDR1_PCTL_SCFG); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:505:28: error: ‘P_DDR0_PCTL_SCTL’ undeclared (first use in this function) + writel(UPCTL_CMD_CONFIG, P_DDR0_PCTL_SCTL); //DDR 0 + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:506:17: error: ‘P_DDR0_PCTL_STAT’ undeclared (first use in this function) + while(!(readl(P_DDR0_PCTL_STAT) & 1)) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:511:28: error: ‘P_DDR1_PCTL_SCTL’ undeclared (first use in this function) + writel(UPCTL_CMD_CONFIG, P_DDR1_PCTL_SCTL); //DDR 1 + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:512:17: error: ‘P_DDR1_PCTL_STAT’ undeclared (first use in this function) + while(!(readl(P_DDR1_PCTL_STAT) & 1)) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:519:23: error: ‘P_DDR0_PCTL_PPCFG’ undeclared (first use in this function) + writel((0xf0 << 1),P_DDR0_PCTL_PPCFG); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:524:14: error: ‘P_DDR0_PUB_DX2GCR0’ undeclared (first use in this function) + writel(0, P_DDR0_PUB_DX2GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:525:14: error: ‘P_DDR0_PUB_DX3GCR0’ undeclared (first use in this function) + writel(0, P_DDR0_PUB_DX3GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:526:14: error: ‘P_DDR0_PUB_DX4GCR0’ undeclared (first use in this function) + writel(0, P_DDR0_PUB_DX4GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:527:14: error: ‘P_DDR0_PUB_DX5GCR0’ undeclared (first use in this function) + writel(0, P_DDR0_PUB_DX5GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:533:23: error: ‘P_DDR1_PCTL_PPCFG’ undeclared (first use in this function) + writel((0xf0 << 1),P_DDR1_PCTL_PPCFG); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:538:14: error: ‘P_DDR1_PUB_DX2GCR0’ undeclared (first use in this function) + writel(0, P_DDR1_PUB_DX2GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:539:14: error: ‘P_DDR1_PUB_DX3GCR0’ undeclared (first use in this function) + writel(0, P_DDR1_PUB_DX3GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:540:14: error: ‘P_DDR1_PUB_DX4GCR0’ undeclared (first use in this function) + writel(0, P_DDR1_PUB_DX4GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:541:14: error: ‘P_DDR1_PUB_DX5GCR0’ undeclared (first use in this function) + writel(0, P_DDR1_PUB_DX5GCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:547:12: error: ‘P_DDR0_PCTL_DFISTCFG0’ undeclared (first use in this function) + writel(4,P_DDR0_PCTL_DFISTCFG0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:548:12: error: ‘P_DDR0_PCTL_DFISTCFG1’ undeclared (first use in this function) + writel(1,P_DDR0_PCTL_DFISTCFG1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:549:12: error: ‘P_DDR0_PCTL_DFITCTRLDELAY’ undeclared (first use in this function) + writel(2,P_DDR0_PCTL_DFITCTRLDELAY); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:550:12: error: ‘P_DDR0_PCTL_DFITPHYWRDATA’ undeclared (first use in this function) + writel(1,P_DDR0_PCTL_DFITPHYWRDATA); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:559:19: error: ‘P_DDR0_PCTL_DFITPHYWRLAT’ undeclared (first use in this function) + writel(nTempVal,P_DDR0_PCTL_DFITPHYWRLAT); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:562:19: error: ‘P_DDR0_PCTL_DFITRDDATAEN’ undeclared (first use in this function) + writel(nTempVal,P_DDR0_PCTL_DFITRDDATAEN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:565:13: error: ‘P_DDR0_PCTL_DFITPHYRDLAT’ undeclared (first use in this function) + writel(13,P_DDR0_PCTL_DFITPHYRDLAT); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:566:12: error: ‘P_DDR0_PCTL_DFITDRAMCLKDIS’ undeclared (first use in this function) + writel(1,P_DDR0_PCTL_DFITDRAMCLKDIS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:567:12: error: ‘P_DDR0_PCTL_DFITDRAMCLKEN’ undeclared (first use in this function) + writel(1,P_DDR0_PCTL_DFITDRAMCLKEN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:568:17: error: ‘P_DDR0_PCTL_DFITCTRLUPDMIN’ undeclared (first use in this function) + writel(0x4000,P_DDR0_PCTL_DFITCTRLUPDMIN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:570:4: error: ‘P_DDR0_PCTL_DFILPCFG0’ undeclared (first use in this function) + P_DDR0_PCTL_DFILPCFG0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:571:16: error: ‘P_DDR0_PCTL_DFITPHYUPDTYPE1’ undeclared (first use in this function) + writel(0x200,P_DDR0_PCTL_DFITPHYUPDTYPE1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:575:12: error: ‘P_DDR0_PCTL_DFIODTCFG’ undeclared (first use in this function) + writel(8,P_DDR0_PCTL_DFIODTCFG); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:577:31: error: ‘P_DDR0_PCTL_DFIODTCFG1’ undeclared (first use in this function) + writel(( 0x0 | (0x6 << 16)),P_DDR0_PCTL_DFIODTCFG1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:580:44: error: ‘P_DDR0_PUB_DTAR0’ undeclared (first use in this function) + writel((0x0 + timing_set->t_pub0_dtar), P_DDR0_PUB_DTAR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:581:44: error: ‘P_DDR0_PUB_DTAR1’ undeclared (first use in this function) + writel((0x08 + timing_set->t_pub0_dtar), P_DDR0_PUB_DTAR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:582:44: error: ‘P_DDR0_PUB_DTAR2’ undeclared (first use in this function) + writel((0x10 + timing_set->t_pub0_dtar), P_DDR0_PUB_DTAR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:583:44: error: ‘P_DDR0_PUB_DTAR3’ undeclared (first use in this function) + writel((0x18 + timing_set->t_pub0_dtar), P_DDR0_PUB_DTAR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:588:12: error: ‘P_DDR1_PCTL_DFISTCFG0’ undeclared (first use in this function) + writel(4,P_DDR1_PCTL_DFISTCFG0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:589:12: error: ‘P_DDR1_PCTL_DFISTCFG1’ undeclared (first use in this function) + writel(1,P_DDR1_PCTL_DFISTCFG1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:590:12: error: ‘P_DDR1_PCTL_DFITCTRLDELAY’ undeclared (first use in this function) + writel(2,P_DDR1_PCTL_DFITCTRLDELAY); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:591:12: error: ‘P_DDR1_PCTL_DFITPHYWRDATA’ undeclared (first use in this function) + writel(1,P_DDR1_PCTL_DFITPHYWRDATA); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:600:19: error: ‘P_DDR1_PCTL_DFITPHYWRLAT’ undeclared (first use in this function) + writel(nTempVal,P_DDR1_PCTL_DFITPHYWRLAT); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:603:19: error: ‘P_DDR1_PCTL_DFITRDDATAEN’ undeclared (first use in this function) + writel(nTempVal,P_DDR1_PCTL_DFITRDDATAEN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:606:13: error: ‘P_DDR1_PCTL_DFITPHYRDLAT’ undeclared (first use in this function) + writel(13,P_DDR1_PCTL_DFITPHYRDLAT); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:607:12: error: ‘P_DDR1_PCTL_DFITDRAMCLKDIS’ undeclared (first use in this function) + writel(1,P_DDR1_PCTL_DFITDRAMCLKDIS); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:608:12: error: ‘P_DDR1_PCTL_DFITDRAMCLKEN’ undeclared (first use in this function) + writel(1,P_DDR1_PCTL_DFITDRAMCLKEN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:609:17: error: ‘P_DDR1_PCTL_DFITCTRLUPDMIN’ undeclared (first use in this function) + writel(0x4000,P_DDR1_PCTL_DFITCTRLUPDMIN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:611:4: error: ‘P_DDR1_PCTL_DFILPCFG0’ undeclared (first use in this function) + P_DDR1_PCTL_DFILPCFG0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:612:16: error: ‘P_DDR1_PCTL_DFITPHYUPDTYPE1’ undeclared (first use in this function) + writel(0x200,P_DDR1_PCTL_DFITPHYUPDTYPE1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:616:12: error: ‘P_DDR1_PCTL_DFIODTCFG’ undeclared (first use in this function) + writel(8,P_DDR1_PCTL_DFIODTCFG); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:618:31: error: ‘P_DDR1_PCTL_DFIODTCFG1’ undeclared (first use in this function) + writel(( 0x0 | (0x6 << 16)),P_DDR1_PCTL_DFIODTCFG1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:621:44: error: ‘P_DDR1_PUB_DTAR0’ undeclared (first use in this function) + writel((0x0 + timing_set->t_pub1_dtar), P_DDR1_PUB_DTAR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:622:44: error: ‘P_DDR1_PUB_DTAR1’ undeclared (first use in this function) + writel((0x08 + timing_set->t_pub1_dtar), P_DDR1_PUB_DTAR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:623:44: error: ‘P_DDR1_PUB_DTAR2’ undeclared (first use in this function) + writel((0x10 + timing_set->t_pub1_dtar), P_DDR1_PUB_DTAR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:624:44: error: ‘P_DDR1_PUB_DTAR3’ undeclared (first use in this function) + writel((0x18 + timing_set->t_pub1_dtar), P_DDR1_PUB_DTAR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:628:12: error: ‘P_DDR0_PCTL_CMDTSTATEN’ undeclared (first use in this function) + writel(1,P_DDR0_PCTL_CMDTSTATEN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:629:17: error: ‘P_DDR0_PCTL_CMDTSTAT’ undeclared (first use in this function) + while(!(readl(P_DDR0_PCTL_CMDTSTAT) & 0x1)) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:634:12: error: ‘P_DDR1_PCTL_CMDTSTATEN’ undeclared (first use in this function) + writel(1,P_DDR1_PCTL_CMDTSTATEN); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:635:17: error: ‘P_DDR1_PCTL_CMDTSTAT’ undeclared (first use in this function) + while(!(readl(P_DDR1_PCTL_CMDTSTAT) & 0x1)) { + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:648:20: error: ‘P_DDR0_PUB_PIR’ undeclared (first use in this function) + writel(nTempVal, P_DDR0_PUB_PIR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:653:16: error: ‘P_DDR0_PUB_PGSR0’ undeclared (first use in this function) + while((readl(P_DDR0_PUB_PGSR0) != 0x8000000f) && + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:671:20: error: ‘P_DDR1_PUB_PIR’ undeclared (first use in this function) + writel(nTempVal, P_DDR1_PUB_PIR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:676:16: error: ‘P_DDR1_PUB_PGSR0’ undeclared (first use in this function) + while((readl(P_DDR1_PUB_PGSR0) != 0x8000000f) && + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_init_pctl.c:1000:46: error: ‘P_DDR0_PUB_PGCR0’ undeclared (first use in this function) + writel((readl(P_DDR0_PUB_PGCR0) & (~0x3F)),P_DDR0_PUB_PGCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:1036:46: error: ‘P_DDR1_PUB_PGCR0’ undeclared (first use in this function) + writel((readl(P_DDR1_PUB_PGCR0) & (~0x3F)),P_DDR1_PUB_PGCR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:1044:47: error: ‘P_DDR0_PUB_PGCR3’ undeclared (first use in this function) + writel((0x7d<<9)|(readl(P_DDR0_PUB_PGCR3)), P_DDR0_PUB_PGCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:1055:47: error: ‘P_DDR1_PUB_PGCR3’ undeclared (first use in this function) + writel((0x7d<<9)|(readl(P_DDR1_PUB_PGCR3)), P_DDR1_PUB_PGCR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:1068:17: error: ‘P_DDR0_PUB_PLLCR’ undeclared (first use in this function) + writel(1<<29, P_DDR0_PUB_PLLCR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_init_pctl.c:1080:17: error: ‘P_DDR1_PUB_PLLCR’ undeclared (first use in this function) + writel(1<<29, P_DDR1_PUB_PLLCR); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c: In function ‘print_ddr_channel’: +bl2/firmware/ddr_auto_detect.c:32:23: error: ‘P_DMC_DDR_CTRL’ undeclared (first use in this function) + channel_set = readl(P_DMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/ddr_auto_detect.c:43:23: error: ‘P_MMC_DDR_CTRL’ undeclared (first use in this function) + channel_set = readl(P_MMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +In file included from bl2/firmware/ddr.c:18:0, + from bl2/firmware/spl.c:34, + from bl2/bl2_main.c:43: +bl2/firmware/ddr_auto_detect.c: In function ‘print_ddr_size’: +bl2/firmware/ddr_auto_detect.c:62:64: warning: ISO C forbids conditional expr with only one void side [-Wpedantic] + (((mem_size>>9)&0x1)&&((mem_size)>=1024)) ? serial_puts(".5") : 0; + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/ddr_auto_detect.c: In function ‘dtar_reset’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/ddr_auto_detect.c:183:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/ddr_auto_detect.c:183:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +bl2/firmware/ddr_auto_detect.c:232:38: error: ‘P_DMC_DDR_CTRL’ undeclared (first use in this function) + writel(timing_reg->t_mmc_ddr_ctrl, P_DMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:241:38: error: ‘P_MMC_DDR_CTRL’ undeclared (first use in this function) + writel(timing_reg->t_mmc_ddr_ctrl, P_MMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:251:39: error: ‘P_DDR0_CLK_CTRL’ undeclared (first use in this function) + writel(readl(P_DDR0_CLK_CTRL) | 0x1, P_DDR0_CLK_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:252:39: error: ‘P_DDR1_CLK_CTRL’ undeclared (first use in this function) + writel(readl(P_DDR1_CLK_CTRL) | 0x1, P_DDR1_CLK_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:255:43: error: ‘P_DDR0_PUB_DTAR0’ undeclared (first use in this function) + writel((0x0 + timing_reg->t_pub0_dtar), P_DDR0_PUB_DTAR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:256:43: error: ‘P_DDR0_PUB_DTAR1’ undeclared (first use in this function) + writel((0x08 + timing_reg->t_pub0_dtar), P_DDR0_PUB_DTAR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:257:43: error: ‘P_DDR0_PUB_DTAR2’ undeclared (first use in this function) + writel((0x10 + timing_reg->t_pub0_dtar), P_DDR0_PUB_DTAR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:258:43: error: ‘P_DDR0_PUB_DTAR3’ undeclared (first use in this function) + writel((0x18 + timing_reg->t_pub0_dtar), P_DDR0_PUB_DTAR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:260:43: error: ‘P_DDR1_PUB_DTAR0’ undeclared (first use in this function) + writel((0x0 + timing_reg->t_pub1_dtar), P_DDR1_PUB_DTAR0); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:261:43: error: ‘P_DDR1_PUB_DTAR1’ undeclared (first use in this function) + writel((0x08 + timing_reg->t_pub1_dtar), P_DDR1_PUB_DTAR1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:262:43: error: ‘P_DDR1_PUB_DTAR2’ undeclared (first use in this function) + writel((0x10 + timing_reg->t_pub1_dtar), P_DDR1_PUB_DTAR2); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:263:43: error: ‘P_DDR1_PUB_DTAR3’ undeclared (first use in this function) + writel((0x18 + timing_reg->t_pub1_dtar), P_DDR1_PUB_DTAR3); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c: In function ‘ddr_size_auto_detect’: +bl2/firmware/ddr_auto_detect.c:312:27: error: ‘P_DMC_DDR_CTRL’ undeclared (first use in this function) + writel(dmc_reg_setting, P_DMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:314:27: error: ‘P_MMC_DDR_CTRL’ undeclared (first use in this function) + writel(dmc_reg_setting, P_MMC_DDR_CTRL); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr_auto_detect.c:323:3: note: in expansion of macro ‘writel’ + writel(DDR_SIZE_AUTO_DETECT_PATTERN, cur_mask_addr); + ^ +In file included from bl2/firmware/ddr.c:18:0, + from bl2/firmware/spl.c:34, + from bl2/bl2_main.c:43: +bl2/firmware/ddr_auto_detect.c:331:3: error: ‘asm’ undeclared (first use in this function) + asm volatile("DSB"); /*sync ddr data*/ + ^ +bl2/firmware/ddr_auto_detect.c:331:7: error: expected ‘;’ before ‘volatile’ + asm volatile("DSB"); /*sync ddr data*/ + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/ddr_auto_detect.c:343:4: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/ddr_auto_detect.c:343:4: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +bl2/firmware/ddr.c: In function ‘set_ddr_clock’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/ddr.c:69:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,3); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/timing.h:138:5: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); \ + ^ +bl2/firmware/ddr.c:69:3: note: in expansion of macro ‘PLL_LOCK_CHECK’ + PLL_LOCK_CHECK(n_pll_try_times,3); + ^ +bl2/firmware/ddr.c:74:12: error: ‘P_DDR0_SOFT_RESET’ undeclared (first use in this function) + writel(0, P_DDR0_SOFT_RESET); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr.c:75:12: error: ‘P_DDR1_SOFT_RESET’ undeclared (first use in this function) + writel(0, P_DDR1_SOFT_RESET); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +In file included from bl2/firmware/spl.c:34:0, + from bl2/bl2_main.c:43: +bl2/firmware/ddr.c:76:2: warning: implicit declaration of function ‘MMC_Wr’ [-Wimplicit-function-declaration] + MMC_Wr(AM_DDR_CLK_CNTL, 0x80004040); // enable DDR PLL CLOCK. + ^ +bl2/firmware/ddr.c:76:9: error: ‘AM_DDR_CLK_CNTL’ undeclared (first use in this function) + MMC_Wr(AM_DDR_CLK_CNTL, 0x80004040); // enable DDR PLL CLOCK. + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/ddr.c:83:22: error: ‘P_DMC_SOFT_RST’ undeclared (first use in this function) + writel(0xffffffff, P_DMC_SOFT_RST); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr.c:84:22: error: ‘P_DMC_SOFT_RST1’ undeclared (first use in this function) + writel(0xffffffff, P_DMC_SOFT_RST1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr.c:87:22: error: ‘P_MMC_SOFT_RST’ undeclared (first use in this function) + writel(0xffffffff, P_MMC_SOFT_RST); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/ddr.c:88:22: error: ‘P_MMC_SOFT_RST1’ undeclared (first use in this function) + writel(0xffffffff, P_MMC_SOFT_RST1); + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +In file included from bl2/firmware/spl.c:34:0, + from bl2/bl2_main.c:43: +bl2/firmware/ddr.c: In function ‘lowlevel_mem_test_device’: +bl2/firmware/ddr.c:157:38: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + return tag&&(unsigned)memTestDevice((volatile datum *)(timing_reg->phy_memory_start),timing_reg->phy_memory_size); + ^ +bl2/firmware/ddr.c:157:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + return tag&&(unsigned)memTestDevice((volatile datum *)(timing_reg->phy_memory_start),timing_reg->phy_memory_size); + ^ +bl2/firmware/ddr.c: In function ‘lowlevel_mem_test_data’: +bl2/firmware/ddr.c:166:39: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + return tag&&(unsigned)memTestDataBus((volatile datum *) (timing_reg->phy_memory_start)); + ^ +bl2/firmware/ddr.c: In function ‘lowlevel_mem_test_addr’: +bl2/firmware/ddr.c:180:42: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + return tag&&(unsigned)memTestAddressBus((volatile datum *)(timing_reg->phy_memory_start), timing_reg->phy_memory_size); + ^ +bl2/firmware/ddr.c:180:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + return tag&&(unsigned)memTestAddressBus((volatile datum *)(timing_reg->phy_memory_start), timing_reg->phy_memory_size); + ^ +bl2/firmware/ddr.c: At top level: +bl2/firmware/ddr.c:196:10: error: conflicting types for ‘ddr_test’ + unsigned ddr_test(int arg) + ^ +In file included from bl2/bl2_main.c:42:0: +bl2/ddr/ddr.c:325:14: note: previous definition of ‘ddr_test’ was here + unsigned int ddr_test(void){ + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/ddr.c: In function ‘ddr_init_test’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/ddr.c:298:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/ddr.c:298:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/ddr.c:326:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/ddr.c:326:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +In file included from bl2/firmware/nfio.c:10:0, + from bl2/firmware/sdio.c:6, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/aml_a9_cache.c: At top level: +bl2/firmware/aml_a9_cache.c:38:1: error: unknown type name ‘s32’ + static inline s32 log_2_n_round_up(u32 n) + ^ +bl2/firmware/aml_a9_cache.c:38:36: error: unknown type name ‘u32’ + static inline s32 log_2_n_round_up(u32 n) + ^ +bl2/firmware/aml_a9_cache.c:54:24: error: unknown type name ‘u32’ + static void set_csselr(u32 level, u32 type) + ^ +bl2/firmware/aml_a9_cache.c:54:35: error: unknown type name ‘u32’ + static void set_csselr(u32 level, u32 type) + ^ +bl2/firmware/aml_a9_cache.c:61:1: error: unknown type name ‘u32’ + static u32 get_ccsidr(void) + ^ +bl2/firmware/aml_a9_cache.c: In function ‘get_ccsidr’: +bl2/firmware/aml_a9_cache.c:63:2: error: unknown type name ‘u32’ + u32 ccsidr; + ^ +bl2/firmware/aml_a9_cache.c:66:2: error: ‘asm’ undeclared (first use in this function) + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); + ^ +bl2/firmware/aml_a9_cache.c:66:6: error: expected ‘;’ before ‘volatile’ + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); + ^ +bl2/firmware/aml_a9_cache.c: At top level: +bl2/firmware/aml_a9_cache.c:70:1: error: unknown type name ‘u32’ + static u32 get_clidr(void) + ^ +bl2/firmware/aml_a9_cache.c: In function ‘get_clidr’: +bl2/firmware/aml_a9_cache.c:72:2: error: unknown type name ‘u32’ + u32 clidr; + ^ +bl2/firmware/aml_a9_cache.c:75:2: error: ‘asm’ undeclared (first use in this function) + asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr)); + ^ +bl2/firmware/aml_a9_cache.c:75:6: error: expected ‘;’ before ‘volatile’ + asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr)); + ^ +bl2/firmware/aml_a9_cache.c: At top level: +bl2/firmware/aml_a9_cache.c:79:42: error: unknown type name ‘u32’ + static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, + ^ +bl2/firmware/aml_a9_cache.c:79:53: error: unknown type name ‘u32’ + static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, + ^ +bl2/firmware/aml_a9_cache.c:80:7: error: unknown type name ‘u32’ + u32 num_ways, u32 way_shift, + ^ +bl2/firmware/aml_a9_cache.c:80:21: error: unknown type name ‘u32’ + u32 num_ways, u32 way_shift, + ^ +bl2/firmware/aml_a9_cache.c:81:7: error: unknown type name ‘u32’ + u32 log2_line_len) + ^ +bl2/firmware/aml_a9_cache.c:103:48: error: unknown type name ‘u32’ + static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, + ^ +bl2/firmware/aml_a9_cache.c:103:59: error: unknown type name ‘u32’ + static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, + ^ +bl2/firmware/aml_a9_cache.c:104:13: error: unknown type name ‘u32’ + u32 num_ways, u32 way_shift, + ^ +bl2/firmware/aml_a9_cache.c:104:27: error: unknown type name ‘u32’ + u32 num_ways, u32 way_shift, + ^ +bl2/firmware/aml_a9_cache.c:105:13: error: unknown type name ‘u32’ + u32 log2_line_len) + ^ +bl2/firmware/aml_a9_cache.c:130:42: error: unknown type name ‘u32’ + static void v7_maint_dcache_level_setway(u32 level, u32 operation) + ^ +bl2/firmware/aml_a9_cache.c:130:53: error: unknown type name ‘u32’ + static void v7_maint_dcache_level_setway(u32 level, u32 operation) + ^ +bl2/firmware/aml_a9_cache.c:165:33: error: unknown type name ‘u32’ + static void v7_maint_dcache_all(u32 operation) + ^ +bl2/firmware/aml_a9_cache.c:181:41: error: unknown type name ‘u32’ + static void v7_dcache_clean_inval_range(u32 start, + ^ +bl2/firmware/aml_a9_cache.c:182:6: error: unknown type name ‘u32’ + u32 stop, u32 line_len) + ^ +bl2/firmware/aml_a9_cache.c:182:16: error: unknown type name ‘u32’ + u32 stop, u32 line_len) + ^ +bl2/firmware/aml_a9_cache.c:194:35: error: unknown type name ‘u32’ + static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) + ^ +bl2/firmware/aml_a9_cache.c:194:46: error: unknown type name ‘u32’ + static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) + ^ +bl2/firmware/aml_a9_cache.c:194:56: error: unknown type name ‘u32’ + static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) + ^ +bl2/firmware/aml_a9_cache.c:224:35: error: unknown type name ‘u32’ + static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) + ^ +bl2/firmware/aml_a9_cache.c:224:46: error: unknown type name ‘u32’ + static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) + ^ +bl2/firmware/aml_a9_cache.c:224:56: error: unknown type name ‘u32’ + static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) + ^ +bl2/firmware/aml_a9_cache.c: In function ‘v7_inval_tlb’: +bl2/firmware/aml_a9_cache.c:253:2: error: ‘asm’ undeclared (first use in this function) + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); + ^ +bl2/firmware/aml_a9_cache.c:253:6: error: expected ‘;’ before ‘volatile’ + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); + ^ +bl2/firmware/aml_a9_cache.c:255:6: error: expected ‘;’ before ‘volatile’ + asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); + ^ +bl2/firmware/aml_a9_cache.c:257:6: error: expected ‘;’ before ‘volatile’ + asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); + ^ +bl2/firmware/aml_a9_cache.c:8:25: error: expected ‘;’ before ‘volatile’ + #define CP15DSB asm volatile("dsb": : : "memory"); + ^ +bl2/firmware/aml_a9_cache.c:259:2: note: in expansion of macro ‘CP15DSB’ + CP15DSB; + ^ +bl2/firmware/aml_a9_cache.c:9:25: error: expected ‘;’ before ‘volatile’ + #define CP15ISB asm volatile("isb": : : "memory"); + ^ +bl2/firmware/aml_a9_cache.c:261:2: note: in expansion of macro ‘CP15ISB’ + CP15ISB; + ^ +bl2/firmware/aml_a9_cache.c: In function ‘invalidate_dcache_all’: +bl2/firmware/aml_a9_cache.c:266:2: warning: implicit declaration of function ‘v7_maint_dcache_all’ [-Wimplicit-function-declaration] + v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); + ^ +bl2/firmware/aml_a9_cache.c: In function ‘invalidate_dcache_range’: +bl2/firmware/aml_a9_cache.c:287:2: warning: implicit declaration of function ‘v7_dcache_maint_range’ [-Wimplicit-function-declaration] + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); + ^ +bl2/firmware/aml_a9_cache.c: In function ‘cp_delay’: +bl2/firmware/aml_a9_cache.c:323:3: warning: implicit declaration of function ‘nop’ [-Wimplicit-function-declaration] + nop(); + ^ +bl2/firmware/aml_a9_cache.c:324:2: error: ‘asm’ undeclared (first use in this function) + asm volatile("" : : : "memory"); + ^ +bl2/firmware/aml_a9_cache.c:324:6: error: expected ‘;’ before ‘volatile’ + asm volatile("" : : : "memory"); + ^ +bl2/firmware/aml_a9_cache.c: In function ‘mmu_setup’: +bl2/firmware/aml_a9_cache.c:334:2: error: ‘asm’ undeclared (first use in this function) + asm volatile("mov r0, #0");// @ set up for MCR + ^ +bl2/firmware/aml_a9_cache.c:334:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mov r0, #0");// @ set up for MCR + ^ +bl2/firmware/aml_a9_cache.c:335:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, r0, c8, c7, 0");// @ invalidate TLBs + ^ +bl2/firmware/aml_a9_cache.c:336:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, r0, c7, c5, 0");// @ invalidate icache + ^ +bl2/firmware/aml_a9_cache.c:341:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mrc p15, 0, r0, c1, c0, 0");// + ^ +bl2/firmware/aml_a9_cache.c:342:6: error: expected ‘;’ before ‘volatile’ + asm volatile("bic r0, r0, #0x00002000");// @ clear bits 13(--V--) + ^ +bl2/firmware/aml_a9_cache.c:344:6: error: expected ‘;’ before ‘volatile’ + asm volatile("bic r0, r0, #0x00000007");// @ clear bits 2:0 (-CAM) + ^ +bl2/firmware/aml_a9_cache.c:346:6: error: expected ‘;’ before ‘volatile’ + asm volatile("orr r0, r0, #0x00000002");// @ set bit 1 (--A-) Align + ^ +bl2/firmware/aml_a9_cache.c:348:6: error: expected ‘;’ before ‘volatile’ + asm volatile("orr r0, r0, #0x00000800");// @ set bit 12 (Z---) BTB + ^ +bl2/firmware/aml_a9_cache.c:349:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, r0, c1, c0, 0");// + ^ +bl2/firmware/aml_a9_cache.c:354:2: error: unknown type name ‘uint’ + uint nVal = 0; + ^ +bl2/firmware/aml_a9_cache.c:360:20: error: ‘SEC_PROT_RW_RW’ undeclared (first use in this function) + nVal = (i<<20)|(SEC_PROT_RW_RW | SEC_WB); + ^ +bl2/firmware/aml_a9_cache.c:360:37: error: ‘SEC_WB’ undeclared (first use in this function) + nVal = (i<<20)|(SEC_PROT_RW_RW | SEC_WB); + ^ +bl2/firmware/aml_a9_cache.c:362:20: error: ‘SEC_PROT_RW_NA’ undeclared (first use in this function) + nVal = (i<<20)|(SEC_PROT_RW_NA | SEC_XN | SEC_SO_MEM); + ^ +bl2/firmware/aml_a9_cache.c:362:37: error: ‘SEC_XN’ undeclared (first use in this function) + nVal = (i<<20)|(SEC_PROT_RW_NA | SEC_XN | SEC_SO_MEM); + ^ +bl2/firmware/aml_a9_cache.c:362:46: error: ‘SEC_SO_MEM’ undeclared (first use in this function) + nVal = (i<<20)|(SEC_PROT_RW_NA | SEC_XN | SEC_SO_MEM); + ^ +bl2/firmware/aml_a9_cache.c:364:47: error: ‘SEC_DEVICE’ undeclared (first use in this function) + nVal = (i<<20)|(SEC_PROT_RW_NA | SEC_XN | SEC_DEVICE); + ^ +bl2/firmware/aml_a9_cache.c:366:46: error: ‘SECTION’ undeclared (first use in this function) + nVal = (i<<20)|(SEC_PROT_RW_NA | SEC_XN | SECTION); + ^ +bl2/firmware/aml_a9_cache.c:407:2: error: unknown type name ‘u32’ + u32 *page_table = (u32 *)(pVMMUTable); + ^ +bl2/firmware/aml_a9_cache.c:407:21: error: ‘u32’ undeclared (first use in this function) + u32 *page_table = (u32 *)(pVMMUTable); + ^ +bl2/firmware/aml_a9_cache.c:407:26: error: expected expression before ‘)’ token + u32 *page_table = (u32 *)(pVMMUTable); + ^ +bl2/firmware/aml_a9_cache.c:409:6: error: expected ‘;’ before ‘reg’ + u32 reg; + ^ +bl2/firmware/aml_a9_cache.c:412:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, %0, c2, c0, 0" + ^ +bl2/firmware/aml_a9_cache.c:415:6: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, %0, c3, c0, 0" + ^ +bl2/firmware/aml_a9_cache.c:418:7: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); // invalidate BTAC + ^ +bl2/firmware/aml_a9_cache.c:419:7: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); // invalidate ICache + ^ +bl2/firmware/aml_a9_cache.c:420:9: error: expected ‘;’ before ‘volatile’ + asm volatile("dsb"); + ^ +bl2/firmware/aml_a9_cache.c:421:9: error: expected ‘;’ before ‘volatile’ + asm volatile("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); // invalidate TLBs + ^ +bl2/firmware/aml_a9_cache.c:422:6: error: expected ‘;’ before ‘volatile’ + asm volatile("dsb"); + ^ +bl2/firmware/aml_a9_cache.c:423:7: error: expected ‘;’ before ‘volatile’ + asm volatile("isb"); + ^ +bl2/firmware/aml_a9_cache.c:426:2: error: ‘reg’ undeclared (first use in this function) + reg = get_cr(); /* get control reg. */ + ^ +bl2/firmware/aml_a9_cache.c:426:2: warning: implicit declaration of function ‘get_cr’ [-Wimplicit-function-declaration] +bl2/firmware/aml_a9_cache.c:428:2: warning: implicit declaration of function ‘set_cr’ [-Wimplicit-function-declaration] + set_cr(reg | CR_M); + ^ +bl2/firmware/aml_a9_cache.c:428:15: error: ‘CR_M’ undeclared (first use in this function) + set_cr(reg | CR_M); + ^ +bl2/firmware/aml_a9_cache.c:407:7: warning: unused variable ‘page_table’ [-Wunused-variable] + u32 *page_table = (u32 *)(pVMMUTable); + ^ +bl2/firmware/aml_a9_cache.c: In function ‘cache_enable’: +bl2/firmware/aml_a9_cache.c:437:19: error: ‘CR_C’ undeclared (first use in this function) + if (cache_bit == CR_C) + ^ +bl2/firmware/aml_a9_cache.c: In function ‘cache_disable’: +bl2/firmware/aml_a9_cache.c:450:19: error: ‘CR_C’ undeclared (first use in this function) + if (cache_bit == CR_C) { + ^ +bl2/firmware/aml_a9_cache.c:456:16: error: ‘CR_M’ undeclared (first use in this function) + cache_bit |= CR_M; + ^ +bl2/firmware/aml_a9_cache.c: In function ‘aml_cache_disable’: +bl2/firmware/aml_a9_cache.c:468:16: error: ‘CR_I’ undeclared (first use in this function) + cache_disable(CR_I); + ^ +bl2/firmware/aml_a9_cache.c:469:16: error: ‘CR_C’ undeclared (first use in this function) + cache_disable(CR_C); + ^ +bl2/firmware/aml_a9_cache.c: In function ‘aml_cache_enable’: +bl2/firmware/aml_a9_cache.c:478:15: error: ‘CR_I’ undeclared (first use in this function) + cache_enable(CR_I); + ^ +bl2/firmware/aml_a9_cache.c:479:15: error: ‘CR_C’ undeclared (first use in this function) + cache_enable(CR_C); + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/nfio.c: In function ‘nfio_reset’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:106:16: note: in expansion of macro ‘P_NAND_CMD’ + while ((readl(P_NAND_CMD)>>22&0x1f) > 0); + ^ +bl2/firmware/nfio.c: In function ‘nfio_read_id’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:137:27: note: in expansion of macro ‘P_NAND_CMD’ + writel((CE0 | IDLE | 0), P_NAND_CMD); + ^ +In file included from bl2/firmware/sdio.c:6:0, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/nfio.c:151:2: warning: implicit declaration of function ‘readb’ [-Wimplicit-function-declaration] + nand_retry.id = readb(P_NAND_BUF)&0xff; + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/nfio.c: In function ‘nfio_page_read_hwctrl’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:510:16: note: in expansion of macro ‘P_NAND_CMD’ + while ((readl(P_NAND_CMD)>>22&0x1f) > 0); + ^ +bl2/firmware/nfio.c: In function ‘nf_init’: +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/nfio.c:716:2: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PAD_PULL_UP_EN_REG2, 0x85ff); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/nfio.c:719:2: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PAD_PULL_UP_REG2, 0x0500); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/nfio.c:722:2: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PERIPHS_PIN_MUX_2, ((0x3ff<<18) | (1<<17))); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/nfio.c:742:2: note: in expansion of macro ‘writel’ + writel((((0<<9) | (1<<8) | 3)), P_HHI_NAND_CLK_CNTL); + ^ +bl2/firmware/aml_nand.h:9:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CFG ((0xc1108604-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:45:65: note: in expansion of macro ‘NAND_CFG’ + #define P_NAND_CFG CBUS_REG_ADDR(NAND_CFG) + ^ +bl2/firmware/nfio.c:755:9: note: in expansion of macro ‘P_NAND_CFG’ + , P_NAND_CFG); + ^ +In file included from bl2/firmware/sdio.c:6:0, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/nfio.c:825:25: error: ‘NAND_MFR_SANDISK’ undeclared (first use in this function) + if (nand_retry.id == NAND_MFR_SANDISK) { + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/nfio.c: In function ‘nf_set_pux’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:884:27: note: in expansion of macro ‘P_NAND_CMD’ + writel((ce | IDLE | 40), P_NAND_CMD); + ^ +bl2/firmware/nfio.c: In function ‘send_plane0_cmd’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:985:21: note: in expansion of macro ‘P_NAND_CMD’ + writel(ce | IDLE, P_NAND_CMD); + ^ +In file included from bl2/firmware/sdio.c:6:0, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/nfio.c:944:35: warning: variable ‘ran_mode’ set but not used [-Wunused-but-set-variable] + unsigned int /*nand_read_info,*/ ran_mode; + ^ +bl2/firmware/nfio.c:943:21: warning: variable ‘plane_mode’ set but not used [-Wunused-but-set-variable] + int /*chip_num,*/ plane_mode; + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/nfio.c: In function ‘send_plane1_cmd’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:1108:21: note: in expansion of macro ‘P_NAND_CMD’ + writel(ce | IDLE, P_NAND_CMD); + ^ +In file included from bl2/firmware/sdio.c:6:0, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/nfio.c:1092:53: warning: variable ‘plane0’ set but not used [-Wunused-but-set-variable] + unsigned page_in_blk, blk_num, /*pages_in_block,*/ plane0, plane1; + ^ +bl2/firmware/nfio.c:1089:21: warning: variable ‘plane_mode’ set but not used [-Wunused-but-set-variable] + int /*chip_num,*/ plane_mode; + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/nfio.c: In function ‘send_read_cmd’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:1168:28: note: in expansion of macro ‘P_NAND_CMD’ + writel(ce | CLE | 0xa2, P_NAND_CMD); + ^ +In file included from bl2/firmware/sdio.c:6:0, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/nfio.c:1159:21: warning: variable ‘plane_mode’ set but not used [-Wunused-but-set-variable] + int /*chip_num,*/ plane_mode; + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/nfio.c: In function ‘send_reset_cmd’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:1232:29: note: in expansion of macro ‘P_NAND_CMD’ + writel((ce | CLE | 0xff), P_NAND_CMD); //reset + ^ +bl2/firmware/nfio.c: In function ‘nf_read_check’: +bl2/firmware/aml_nand.h:8:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_CMD ((0xc1108600-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:58:45: note: in definition of macro ‘readl’ + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/aml_nand.h:44:65: note: in expansion of macro ‘NAND_CMD’ + #define P_NAND_CMD CBUS_REG_ADDR(NAND_CMD) + ^ +bl2/firmware/nfio.c:1271:16: note: in expansion of macro ‘P_NAND_CMD’ + while ((readl(P_NAND_CMD)>>22&0x1f) > 0); + ^ +bl2/firmware/nfio.c: In function ‘nf_normal_read_page_hwctrl’: +bl2/firmware/aml_nand.h:11:62: error: ‘IO_CBUS_BASE’ undeclared (first use in this function) + #define NAND_IADR ((0xc110860c-IO_CBUS_BASE)>>2) + ^ +include/drivers/serial/serial.h:57:49: note: in definition of macro ‘writel’ + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/aml_nand.h:47:65: note: in expansion of macro ‘NAND_IADR’ + #define P_NAND_IADR CBUS_REG_ADDR(NAND_IADR) + ^ +bl2/firmware/nfio.c:1374:19: note: in expansion of macro ‘P_NAND_IADR’ + writel(info_adr, P_NAND_IADR); + ^ +In file included from bl2/firmware/sdio.c:6:0, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/nfio.c:1342:46: warning: variable ‘newoobtype’ set but not used [-Wunused-but-set-variable] + int i, k, chip_num, plane_mode=0, ecc_mode, newoobtype = 0,extra_len=0; + ^ +In file included from bl2/firmware/spl.c:36:0, + from bl2/bl2_main.c:43: +bl2/firmware/sdio.c: In function ‘wait_busy’: +bl2/firmware/sdio.c:132:5: warning: implicit declaration of function ‘WRITE_CBUS_REG’ [-Wimplicit-function-declaration] + WRITE_CBUS_REG(SDIO_STATUS_IRQ,0x1fff<<sdio_timing_out_count_bit); + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/sdio.c: In function ‘sdio_send_cmd’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:147:5: note: in expansion of macro ‘writel’ + writel(arg,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:148:5: note: in expansion of macro ‘writel’ + writel(cmd,P_CMD_SEND); + ^ +In file included from bl2/firmware/spl.c:36:0, + from bl2/bl2_main.c:43: +bl2/firmware/sdio.c: In function ‘sdio_read’: +bl2/firmware/sdio.c:247:37: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + WRITE_CBUS_REG(SDIO_M_ADDR, (unsigned)((unsigned char *)&switch_status)); + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:286:7: note: in expansion of macro ‘writel’ + writel(1<<8,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdio.c:346:5: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_SDIO_IRQ_CONFIG,1<<soft_reset_bit); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:347:2: note: in expansion of macro ‘writel’ + writel(((1<<8) | (1<<9)),P_SDIO_STATUS_IRQ); + ^ +bl2/firmware/sdio.c: In function ‘sdio_init’: +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdio.c:425:5: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_SDIO_IRQ_CONFIG,1<<soft_reset_bit); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:427:5: note: in expansion of macro ‘writel’ + writel( (2 << sdio_write_CRC_ok_status_bit) | + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:437:5: note: in expansion of macro ‘writel’ + writel(SD_boot_type,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdio.c:446:5: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_SDIO_IRQ_CONFIG,1<<soft_reset_bit); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:447:5: note: in expansion of macro ‘writel’ + writel(((1<<8) | (1<<9)),P_SDIO_STATUS_IRQ); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:452:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT);// delay some time for sdio_card ready + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:453:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:454:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:455:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:456:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:457:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:458:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:459:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:460:5: note: in expansion of macro ‘writel’ + writel(0,P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:468:9: note: in expansion of macro ‘writel’ + writel(1<<8,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/sdio.c:469:13: note: in expansion of macro ‘readl’ + if((readl(P_CMD_ARGUMENT)&0x1ff) == 0x1aa) + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdio.c:478:9: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_SDIO_IRQ_CONFIG,1<<soft_reset_bit); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:479:9: note: in expansion of macro ‘writel’ + writel(((1<<8) | (1<<9)),P_SDIO_STATUS_IRQ); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdio.c:506:9: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_SDIO_IRQ_CONFIG,1<<soft_reset_bit); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:507:9: note: in expansion of macro ‘writel’ + writel(((1<<8) | (1<<9)),P_SDIO_STATUS_IRQ); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/sdio.c:519:13: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_SDIO_IRQ_CONFIG,1<<soft_reset_bit); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:520:13: note: in expansion of macro ‘writel’ + writel(((1<<8) | (1<<9)),P_SDIO_STATUS_IRQ); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:528:13: note: in expansion of macro ‘writel’ + writel(1<<8,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/sdio.c:530:20: note: in expansion of macro ‘readl’ + temp = readl(P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:545:9: note: in expansion of macro ‘writel’ + writel(0x8300,P_SDIO_EXTENSION); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:560:9: note: in expansion of macro ‘writel’ + writel(1<<8,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/sdio.c:561:16: note: in expansion of macro ‘readl’ + temp = readl(P_CMD_ARGUMENT); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:602:5: note: in expansion of macro ‘writel’ + writel(1<<8,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/sdio.c:606:15: note: in expansion of macro ‘readl’ + cid = readl(P_CMD_ARGUMENT) ; + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:610:5: note: in expansion of macro ‘writel’ + writel(1<<8,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:619:5: note: in expansion of macro ‘writel’ + writel(1<<8,P_SDIO_MULT_CONFIG); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:646:9: note: in expansion of macro ‘writel’ + writel(0x80000000,P_SDIO_M_ADDR); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/sdio.c:647:9: note: in expansion of macro ‘writel’ + writel(79<<16,P_SDIO_EXTENSION); + ^ +In file included from bl2/bl2_main.c:43:0: +bl2/firmware/spl.c: At top level: +bl2/firmware/spl.c:39:45: error: unknown type name ‘__kernel_size_t’ + extern void ipl_memcpy(void*, const void *, __kernel_size_t); + ^ +In file included from bl2/firmware/romboot.c:6:0, + from bl2/firmware/loaduboot.c:13, + from bl2/firmware/spl.c:42, + from bl2/bl2_main.c:43: +bl2/firmware/secure.c: In function ‘aml_m8_sec_boot_check’: +bl2/firmware/secure.c:137:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v3 fp_01 = (t_func_v3)g_action[g_nStep][1]; //void rsa_init(1,2,3) + ^ +bl2/firmware/secure.c:138:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_r3 fp_02 = (t_func_r3)g_action[g_nStep][2]; //int mpi_read_string(1,2,3) + ^ +bl2/firmware/secure.c:139:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v3 fp_03 = (t_func_v3)g_action[g_nStep][3]; //void efuse_read(1,2,3) + ^ +bl2/firmware/secure.c:140:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_r2 fp_04 = (t_func_r2)g_action[g_nStep][4]; //int boot_rsa_read_puk(a,b) + ^ +bl2/firmware/secure.c:141:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_r3 fp_05 = (t_func_r3)g_action[g_nStep][5]; //int rsa_public(1,2,3) + ^ +bl2/firmware/secure.c:142:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v2 fp_06 = (t_func_v2)g_action[g_nStep][6]; //void boot_aes_setkey_dec(1,2) + ^ +bl2/firmware/secure.c:143:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v1 fp_07 = (t_func_v1)g_action[g_nStep][7]; //void boot_aes_setiv_init(1) + ^ +bl2/firmware/secure.c:144:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v4 fp_08 = (t_func_v4)g_action[g_nStep][8]; //void boot_aes_crypt_cbc(1,2,3,4) + ^ +bl2/firmware/secure.c:145:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v4 fp_09 = (t_func_v4)g_action[g_nStep][9]; //void sha2(1,2,3,4) + ^ +bl2/firmware/secure.c:146:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_r3 fp_10 = (t_func_r3)g_action[g_nStep][10]; //int memcpy(1,2,3) + ^ +bl2/firmware/secure.c:147:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_r3 fp_11 = (t_func_r3)g_action[g_nStep][11];//int memcmp(1,2,3) + ^ +bl2/firmware/secure.c:148:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_r1 fp_12 = (t_func_r1)g_action[g_nStep][12];//int mpi_msb(1) + ^ +bl2/firmware/secure.c:149:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v3 fp_13 = (t_func_v3)g_action[g_nStep][13];//void memset(1,2,3) + ^ +bl2/firmware/secure.c:153:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_01((int)&cb1_ctx,0,0); + ^ +bl2/firmware/secure.c:157:12: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_02((int)cb1_ctx.szBuf1,(int)pkey1,nkey1Len) || fp_02((int)cb1_ctx.szBuf2,(int)pkey2,nkey2Len)) + ^ +bl2/firmware/secure.c:157:32: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_02((int)cb1_ctx.szBuf1,(int)pkey1,nkey1Len) || fp_02((int)cb1_ctx.szBuf2,(int)pkey2,nkey2Len)) + ^ +bl2/firmware/secure.c:157:62: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_02((int)cb1_ctx.szBuf1,(int)pkey1,nkey1Len) || fp_02((int)cb1_ctx.szBuf2,(int)pkey2,nkey2Len)) + ^ +bl2/firmware/secure.c:157:82: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_02((int)cb1_ctx.szBuf1,(int)pkey1,nkey1Len) || fp_02((int)cb1_ctx.szBuf2,(int)pkey2,nkey2Len)) + ^ +bl2/firmware/secure.c:159:25: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + cb1_ctx.len = ( fp_12((int)cb1_ctx.szBuf1 ) + 7 ) >> 3; + ^ +bl2/firmware/secure.c:164:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_03((int)&nState,0,4); + ^ +bl2/firmware/secure.c:172:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_04((int)&cb1_ctx,(nState & (1<<23)) ? 1 : 0); + ^ +bl2/firmware/secure.c:176:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_10((int)(unsigned char*)&chk_blk,(int)(unsigned char*)pSRC,sizeof(chk_blk)); + ^ +bl2/firmware/secure.c:176:38: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_10((int)(unsigned char*)&chk_blk,(int)(unsigned char*)pSRC,sizeof(chk_blk)); + ^ +bl2/firmware/secure.c:179:12: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_05((int)&cb1_ctx, (int)pBuf+i,(int)pBuf+i )) + ^ +bl2/firmware/secure.c:179:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_05((int)&cb1_ctx, (int)pBuf+i,(int)pBuf+i )) + ^ +bl2/firmware/secure.c:179:39: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_05((int)&cb1_ctx, (int)pBuf+i,(int)pBuf+i )) + ^ +bl2/firmware/secure.c:195:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_10((int)(void*)pSRC,(int)(void*)(pSRC+chk_blk.nLength1), + ^ +bl2/firmware/secure.c:195:26: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_10((int)(void*)pSRC,(int)(void*)(pSRC+chk_blk.nLength1), + ^ +bl2/firmware/secure.c:198:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_10((int)(void*)szkey,(int)(void*)chk_blk.szkey2,sizeof(szkey)); + ^ +bl2/firmware/secure.c:198:26: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_10((int)(void*)szkey,(int)(void*)chk_blk.szkey2,sizeof(szkey)); + ^ +bl2/firmware/secure.c:200:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_06((int) &cb2_ctx,(int)szkey ); + ^ +bl2/firmware/secure.c:200:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_06((int) &cb2_ctx,(int)szkey ); + ^ +bl2/firmware/secure.c:202:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_07((int)&szkey[32]); + ^ +bl2/firmware/secure.c:205:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_08 ((int) &cb2_ctx, (int)&szkey[32],(int) &ct32[i*4],(int) &ct32[i*4] ); + ^ +bl2/firmware/secure.c:205:26: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_08 ((int) &cb2_ctx, (int)&szkey[32],(int) &ct32[i*4],(int) &ct32[i*4] ); + ^ +bl2/firmware/secure.c:205:42: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_08 ((int) &cb2_ctx, (int)&szkey[32],(int) &ct32[i*4],(int) &ct32[i*4] ); + ^ +bl2/firmware/secure.c:205:59: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_08 ((int) &cb2_ctx, (int)&szkey[32],(int) &ct32[i*4],(int) &ct32[i*4] ); + ^ +bl2/firmware/secure.c:207:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_09((int) pSRC,chk_blk.nLength3,(int)szkey, 0 ); + ^ +bl2/firmware/secure.c:207:36: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_09((int) pSRC,chk_blk.nLength3,(int)szkey, 0 ); + ^ +bl2/firmware/secure.c:209:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_11((int)szkey,(int)chk_blk.szkey1,32)) + ^ +bl2/firmware/secure.c:209:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if(fp_11((int)szkey,(int)chk_blk.szkey1,32)) + ^ +bl2/firmware/secure.c: In function ‘aml_sec_boot_check’: +bl2/firmware/secure.c:255:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + unsigned int nBLKStart = ((unsigned int )aml_sec_boot_check) & (0xFFFF8000); + ^ +bl2/firmware/secure.c:282:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + aml_spl_blk *pblk = (aml_spl_blk *)(nBLKStart + nSPLLen - 1152 ); + ^ +bl2/firmware/secure.c:284:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v3 fp_3 = (t_func_v3)g_action[g_nStep][3]; + ^ +bl2/firmware/secure.c:285:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v4 fp_9 = (t_func_v4)g_action[g_nStep][9]; + ^ +bl2/firmware/secure.c:286:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_r3 fp_11 = (t_func_r3)g_action[g_nStep][11]; + ^ +bl2/firmware/secure.c:288:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_3((int)szCheck,452,36); + ^ +bl2/firmware/secure.c:290:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_9((int)pblk->sz2,260,(int)szHash, 0 ); + ^ +bl2/firmware/secure.c:290:26: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_9((int)pblk->sz2,260,(int)szHash, 0 ); + ^ +bl2/firmware/secure.c:292:15: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + nRet = fp_11((int)szCheck+2,(int)szHash,32); + ^ +bl2/firmware/secure.c:292:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + nRet = fp_11((int)szCheck+2,(int)szHash,32); + ^ +bl2/firmware/secure.c:314:62: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_9((int)(nBLKStart+pblk->nSPLStartOffset),pblk->splLenght,(int)szHash, 0 ); + ^ +bl2/firmware/secure.c:316:15: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + nRet = fp_11((int)pblk->sz4,(int)szHash,32); + ^ +bl2/firmware/secure.c:316:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + nRet = fp_11((int)pblk->sz4,(int)szHash,32); + ^ +bl2/firmware/secure.c: In function ‘aml_is_secure_set’: +bl2/firmware/secure.c:482:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v3 fp_03 = (t_func_v3)g_action[g_nStep][3]; + ^ +bl2/firmware/secure.c:483:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + t_func_v3 fp_13 = (t_func_v3)g_action[g_nStep][13]; + ^ +bl2/firmware/secure.c:486:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + fp_03((int)&nState,0,4); + ^ +In file included from bl2/firmware/loaduboot.c:13:0, + from bl2/firmware/spl.c:42, + from bl2/bl2_main.c:43: +bl2/firmware/romboot.c: In function ‘fw_print_info’: +bl2/firmware/romboot.c:53:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if((((unsigned int)fw_print_info >> 24) & 0xFF) != 0xD9) + ^ +bl2/firmware/romboot.c: In function ‘fw_load_intl’: +bl2/firmware/romboot.c:153:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if((((unsigned int)fw_load_intl >> 24) & 0xFF) != ((AHB_SRAM_BASE>>24)&0xFF)) + ^ +bl2/firmware/romboot.c:155:3: warning: implicit declaration of function ‘ipl_memcpy’ [-Wimplicit-function-declaration] + memcpy((void*)temp_addr,(void*)target,size); //here need fine tune!! + ^ +bl2/firmware/romboot.c:155:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + memcpy((void*)temp_addr,(void*)target,size); //here need fine tune!! + ^ +bl2/firmware/romboot.c:155:27: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + memcpy((void*)temp_addr,(void*)target,size); //here need fine tune!! + ^ +bl2/firmware/romboot.c:213:13: warning: implicit declaration of function ‘spi_init’ [-Wimplicit-function-declaration] + spi_init(); + ^ +bl2/firmware/romboot.c:222:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + ipl_memcpy((unsigned char*)temp_addr,(unsigned char*)mem,size); + ^ +bl2/firmware/romboot.c:247:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + if(aml_sec_boot_check((unsigned char *)temp_addr)) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/romboot.c:249:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/romboot.c:249:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +In file included from bl2/firmware/loaduboot.c:13:0, + from bl2/firmware/spl.c:42, + from bl2/bl2_main.c:43: +bl2/firmware/romboot.c:272:26: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=uclDecompress((char*)target,&len,(char*)temp_addr); + ^ +bl2/firmware/romboot.c:272:45: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=uclDecompress((char*)target,&len,(char*)temp_addr); + ^ +bl2/firmware/romboot.c:281:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=check_sum((unsigned*)target,magic_info->crc[1],size); + ^ +bl2/firmware/romboot.c: In function ‘fw_load_extl’: +bl2/firmware/romboot.c:313:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + if((((unsigned int)fw_load_extl >> 24) & 0xFF) != ((AHB_SRAM_BASE>>24)&0xFF)) + ^ +bl2/firmware/romboot.c:315:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + memcpy((void*)temp_addr,(void*)target,size); //here need fine tune!! + ^ +bl2/firmware/romboot.c:315:27: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + memcpy((void*)temp_addr,(void*)target,size); //here need fine tune!! + ^ +bl2/firmware/romboot.c:330:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + if(aml_sec_boot_check((unsigned char *)temp_addr)) + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:33:3: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/romboot.c:332:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:34:3: note: in expansion of macro ‘writel’ + writel((10|((1<<AML_WATCHDOG_ENABLE_OFFSET)| \ + ^ +bl2/firmware/romboot.c:332:3: note: in expansion of macro ‘AML_WATCH_DOG_START’ + AML_WATCH_DOG_START(); + ^ +In file included from bl2/firmware/loaduboot.c:13:0, + from bl2/firmware/spl.c:42, + from bl2/bl2_main.c:43: +bl2/firmware/romboot.c:357:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=uclDecompress((char*)target,&len,(char*)temp_addr); + ^ +bl2/firmware/romboot.c:357:42: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=uclDecompress((char*)target,&len,(char*)temp_addr); + ^ +bl2/firmware/romboot.c:367:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=check_sum((unsigned*)target,magic_info->crc[1],size); + ^ +bl2/firmware/romboot.c: In function ‘load_ext’: +bl2/firmware/romboot.c:406:30: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=uclDecompress((char*)(__load_table[i].dest),&len,(char*)(temp_addr+__load_table[i].src)); + ^ +bl2/firmware/romboot.c:406:65: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + rc=uclDecompress((char*)(__load_table[i].dest),&len,(char*)(temp_addr+__load_table[i].src)); + ^ +bl2/firmware/romboot.c:415:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + memcpy((void*)(__load_table[i].dest),(const void*)(__load_table[i].src+temp_addr),__load_table[i].size&0x3fffff); + ^ +bl2/firmware/romboot.c:415:46: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + memcpy((void*)(__load_table[i].dest),(const void*)(__load_table[i].src+temp_addr),__load_table[i].size&0x3fffff); + ^ +In file included from bl2/firmware/spl.c:42:0, + from bl2/bl2_main.c:43: +bl2/firmware/loaduboot.c: In function ‘load_uboot’: +bl2/firmware/loaduboot.c:86:43: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] + unsigned int *pAUINF = (unsigned int *)(((unsigned int)load_uboot & 0xFFFF8000)+(AML_UBOOT_SINFO_OFFSET)); + ^ +In file included from bl2/ddr/ddr.c:22:0, + from bl2/bl2_main.c:42: +bl2/firmware/spl.c: In function ‘main’: +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:20:2: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); \ + ^ +bl2/firmware/spl.c:62:2: note: in expansion of macro ‘AML_WATCH_DOG_SET’ + AML_WATCH_DOG_SET(5000); //5s + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:21:2: note: in expansion of macro ‘writel’ + writel((((int)(time * 1000 / AML_WATCHDOG_TIME_SLICE)) | \ + ^ +bl2/firmware/spl.c:62:2: note: in expansion of macro ‘AML_WATCH_DOG_SET’ + AML_WATCH_DOG_SET(5000); //5s + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/spl.c:111:22: note: in expansion of macro ‘readl’ + unsigned pinmux_2 = readl(P_PERIPHS_PIN_MUX_2); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/spl.c:135:2: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PREG_PAD_GPIO0_O,0x3f<<22); + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/spl.c:136:2: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PREG_PAD_GPIO0_EN_N,0x3f<<22); + ^ +include/drivers/serial/serial.h:60:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define clrbits_le32(reg,val) (*((volatile unsigned *)reg))&=(~val) + ^ +bl2/firmware/spl.c:137:2: note: in expansion of macro ‘clrbits_le32’ + clrbits_le32(P_PERIPHS_PIN_MUX_2,7<<12); //clear sd d1~d3 pinmux + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/spl.c:139:7: note: in expansion of macro ‘readl’ + if(!(readl(P_PREG_PAD_GPIO0_I)&(1<<26))){ //sd_d3 low, debug board in + ^ +include/drivers/serial/serial.h:59:34: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define setbits_le32(reg,val) (*((volatile unsigned *)reg))|=val + ^ +bl2/firmware/spl.c:142:3: note: in expansion of macro ‘setbits_le32’ + setbits_le32(P_PERIPHS_PIN_MUX_8,3<<9); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/spl.c:144:7: note: in expansion of macro ‘readl’ + if((readl(P_PREG_PAD_GPIO0_I)&(1<<22))) + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/spl.c:149:3: note: in expansion of macro ‘writel’ + writel(pinmux_2,P_PERIPHS_PIN_MUX_2); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/spl.c:211:22: note: in expansion of macro ‘readl’ + unsigned int nPLL = readl(P_HHI_A9_CLK_CNTL); + ^ +include/drivers/serial/serial.h:58:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define readl(reg) (*((volatile unsigned *)reg)) + ^ +bl2/firmware/spl.c:215:10: note: in expansion of macro ‘readl’ + nPLL = readl(P_HHI_SYS_PLL_CNTL); + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:27:2: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_TC); \ + ^ +bl2/firmware/spl.c:279:2: note: in expansion of macro ‘AML_WATCH_DOG_DISABLE’ + AML_WATCH_DOG_DISABLE(); //disable watchdog + ^ +include/drivers/serial/serial.h:57:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] + #define writel(val,reg) (*((volatile unsigned *)reg))=(val) + ^ +bl2/firmware/plat-cpu.h:28:2: note: in expansion of macro ‘writel’ + writel(0, P_WATCHDOG_RESET); + ^ +bl2/firmware/spl.c:279:2: note: in expansion of macro ‘AML_WATCH_DOG_DISABLE’ + AML_WATCH_DOG_DISABLE(); //disable watchdog + ^ +In file included from bl2/firmware/spl.c:29:0, + from bl2/bl2_main.c:43: +bl2/bl2_main.c: At top level: +bl2/firmware/pll.c:41:13: warning: ‘wait_clock’ defined but not used [-Wunused-function] + static void wait_clock(unsigned clk,unsigned dest) + ^ +In file included from bl2/firmware/spl.c:32:0, + from bl2/bl2_main.c:43: +bl2/firmware/power.c:115:12: warning: ‘vcck_set_default_voltage’ defined but not used [-Wunused-function] + static int vcck_set_default_voltage(int voltage) + ^ +In file included from bl2/firmware/spl.c:34:0, + from bl2/bl2_main.c:43: +bl2/firmware/ddr.c:13:13: warning: ‘wait_pll’ declared ‘static’ but never defined [-Wunused-function] + static void wait_pll(unsigned clk,unsigned dest); + ^ +In file included from bl2/firmware/ddr.c:17:0, + from bl2/firmware/spl.c:34, + from bl2/bl2_main.c:43: +bl2/firmware/ddr_init_pctl.c:28:13: warning: ‘serial_put_dec_nothing’ defined but not used [-Wunused-function] + static void serial_put_dec_nothing(unsigned int data){ + ^ +In file included from bl2/firmware/nfio.c:10:0, + from bl2/firmware/sdio.c:6, + from bl2/firmware/spl.c:36, + from bl2/bl2_main.c:43: +bl2/firmware/aml_a9_cache.c:61:12: warning: ‘get_ccsidr’ defined but not used [-Wunused-function] + static u32 get_ccsidr(void) + ^ +bl2/firmware/aml_a9_cache.c:70:12: warning: ‘get_clidr’ defined but not used [-Wunused-function] + static u32 get_clidr(void) + ^ +make: *** [build/juno/debug/bl2/bl2_main.o] Error 1 |