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path: root/drivers/clk/sifive
Commit message (Expand)AuthorAge
* clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCIBen Dooks2023-07-06
* dt-bindings: clock: sifive: sync FU740 PRCI clock binding headerIcenowy Zheng2022-09-06
* clk: sifive: Fix -Wint-to-pointer-cast warningBin Meng2021-10-20
* drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan2021-07-06
* drivers: clk: add fu740 supportGreen Wan2021-05-31
* dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-05
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-13
* clk: sifive: Include device_compat.hSean Anderson2020-10-15
* sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam2020-08-04
* fu540: prci: use common reset indexes defined in binding headerSagar Shrikant Kadam2020-08-04
* clk: sifive: fu540-prci: Release ethernet clock resetPragnesh Patel2020-06-04
* clk: sifive: fu540-prci: Add ddr clock initializationPragnesh Patel2020-06-04
* clk: sifive: fu540-prci: Add clock enable and disable opsPragnesh Patel2020-06-04
* common: Drop linux/delay.h from common headerSimon Glass2020-05-18
* dm: core: Require users of devres to include the headerSimon Glass2020-02-05
* clk: sifive: Drop GEMGXL clock driverAnup Patel2019-07-19
* clk: sifive: Sync-up main driver with upstream LinuxAnup Patel2019-07-19
* clk: sifive: Sync-up DT bindings header with upstream LinuxAnup Patel2019-07-19
* clk: sifive: Sync-up WRPLL library with upstream LinuxAnup Patel2019-07-19
* clk: sifive: Factor-out PLL library as separate moduleAnup Patel2019-07-19
* clk: sifive: Add clock driver for GEMGXL MGMTBin Meng2019-06-01
* clk: sifive: fu540-prci: Change include orderJagan Teki2019-05-09
* clk: Add SiFive FU540 PRCI clock driverAnup Patel2019-02-27