path: root/arch/arm/dts/imx8mp-venice-gw74xx.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 Gateworks Corporation
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mp.dtsi"

/ {
	model = "Gateworks Venice GW74xx i.MX8MP board";
	compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";

	aliases {
		ethernet0 = &eqos;
		ethernet1 = &fec;
		ethernet2 = &lan1;
		ethernet3 = &lan2;
		ethernet4 = &lan3;
		ethernet5 = &lan4;
		ethernet6 = &lan5;
	};

	chosen {
		stdout-path = &uart2;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-0 {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-1 {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-2 {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-3 {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		key-4 {
			label = "tamper";
			linux,code = <BTN_4>;
			interrupt-parent = <&gsc>;
			interrupts = <5>;
		};

		key-5 {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_HEARTBEAT;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	};

	reg_usb2_vbus: regulator-usb2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb2>;
		compatible = "regulator-fixed";
		regulator-name = "usb_usb2_vbus";
		gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_can>;
		regulator-name = "can2_stby";
		gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_wifi_en: regulator-wifi-en {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_wifi>;
		compatible = "regulator-fixed";
		regulator-name = "wl";
		gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <70000>;
		enable-active-high;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&A53_0 {
	cpu-supply = <&reg_arm>;
};

&A53_1 {
	cpu-supply = <&reg_arm>;
};

&A53_2 {
	cpu-supply = <&reg_arm>;
};

&A53_3 {
	cpu-supply = <&reg_arm>;
};

/* off-board header */
&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x0>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	local-mac-address = [00 00 00 00 00 00];
	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can2_stby>;
	status = "okay";
};

&gpio1 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "dio0", "", "dio1", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio2 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "pcie3_wdis#", "",
		"", "", "pcie2_wdis#", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio3 {
	gpio-line-names =
		"m2_gdis#", "", "", "", "", "", "", "m2_rst#",
		"", "", "", "", "", "", "", "",
		"m2_off#", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "m2_wdis#", "", "", "",
		"", "", "", "", "", "", "", "uart_rs485";
};

&gpio5 {
	gpio-line-names =
		"uart_half", "uart_term", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio4>;
		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@8 {
				gw,mode = <1>;
				reg = <0x08>;
				label = "vdd_bat";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vdd_adc1";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vdd_adc2";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_vin";
				gw,voltage-divider-ohms = <22100 1000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_2p5";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_soc";
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_arm";
			};

			channel@98 {
				gw,mode = <2>;
				reg = <0x98>;
				label = "vdd_1p8";
			};

			channel@9a {
				gw,mode = <2>;
				reg = <0x9a>;
				label = "vdd_1p2";
			};

			channel@9c {
				gw,mode = <2>;
				reg = <0x9c>;
				label = "vdd_dram";
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	pmic@25 {
		compatible = "nxp,pca9450c";
		reg = <0x25>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio3>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <720000>;
				regulator-max-microvolt = <1000000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			reg_arm: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <720000>;
				regulator-max-microvolt = <1025000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
			};

			BUCK4 {
				regulator-name = "BUCK4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3600000>;
				regulator-boot-on;
				regulator-always-on;
			};

			BUCK5 {
				regulator-name = "BUCK5";
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <1950000>;
				regulator-boot-on;
				regulator-always-on;
			};

			BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <1045000>;
				regulator-max-microvolt = <1155000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <1950000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <1710000>;
				regulator-max-microvolt = <1890000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	accelerometer@19 {
		compatible = "st,lis2de12";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};

	switch: switch@5f {
		compatible = "microchip,ksz9897";
		reg = <0x5f>;
		pinctrl-0 = <&pinctrl_ksz>;
		interrupt-parent = <&gpio4>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			lan1: port@0 {
				reg = <0>;
				label = "lan1";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			lan2: port@1 {
				reg = <1>;
				label = "lan2";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			lan3: port@2 {
				reg = <2>;
				label = "lan3";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			lan4: port@3 {
				reg = <3>;
				label = "lan4";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			lan5: port@4 {
				reg = <4>;
				label = "lan5";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&fec>;
				phy-mode = "rgmii-id";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

/* off-board header */
&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
		 <&clk IMX8MP_CLK_PCIE_ROOT>,
		 <&clk IMX8MP_CLK_HSIO_AXI>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
	assigned-clock-rates = <10000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
	status = "okay";
};

/* GPS / off-board header */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* RS232 console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* bluetooth HCI */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
	cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
	rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm4330-bt";
		shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
	};
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

/* USB1 - Type C front panel */
&usb3_0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1>;
	fsl,over-current-active-low;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb_dwc3_0 {
	/* dual role is implemented but not a full featured OTG */
	adp-disable;
	hnp-disable;
	srp-disable;
	dr_mode = "otg";
	usb-role-switch;
	role-switch-default-mode = "peripheral";
	status = "okay";

	connector {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbcon1>;
		compatible = "gpio-usb-b-connector", "usb-b-connector";
		type = "micro";
		label = "Type-C";
		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
	};
};

/* USB2 - USB3.0 Hub */
&usb3_phy1 {
	vbus-supply = <&reg_usb2_vbus>;
	status = "okay";
};

&usb3_1 {
	fsl,permanently-attached;
	fsl,disable-port-power-control;
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

/* SDIO WiFi */
&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	non-removable;
	vmmc-supply = <&reg_wifi_en>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	wifi@0 {
		compatible = "cypress,cyw4373-fmac";
		reg = <0>;
	};
};

/* eMMC */
&usdhc3 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000040 /* DIO0 */
			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000040 /* DIO1 */
			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000040 /* M2SKT_OFF# */
			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */
			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */
			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */
			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000150 /* M2SKT_WDIS# */
			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x40000150 /* M2SKT_GDIS# */
			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */
			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */
			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x150
		>;
	};

	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x140 /* RST# */
			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x150 /* IRQ# */
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x140
			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x140
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x150
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2
			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c3
			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c3
			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2
			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x400001c3
			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x400001c3
		>;
	};

	pinctrl_ksz: kszgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x150 /* IRQ# */
			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x140 /* RST# */
		>;
	};

	pinctrl_gpio_leds: ledgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x10
			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x10
		>;
	};

	pinctrl_pcie0: pciegrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x110
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x140
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140
		>;
	};

	pinctrl_reg_can: regcangrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x154
		>;
	};

	pinctrl_reg_usb2: regusb2grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x140
		>;
	};

	pinctrl_reg_wifi: regwifigrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x110
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6
			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6
			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6
			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK	0xd6
		>;
	};

	pinctrl_spi2: spi2grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x82
			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x82
			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x82
			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140
			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22	0x140
		>;
	};

	pinctrl_uart3_gpio: uart3gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x110
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140
			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140
		>;
	};

	pinctrl_usb1: usb1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140
		>;
	};

	pinctrl_usbcon1: usb1congrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
		>;
	};
};