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// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2017-2018 NXP
 * Copyright 2019-2023 Kococonnector GmbH
 */

/dts-v1/;

/* First 128KB is for PSCI ATF. */
/memreserve/ 0x80000000 0x00020000;

#include "fsl-imx8qm.dtsi"
#include "imx8qm-u-boot.dtsi"

/ {
	model = "Advantech iMX8QM DMSSE20";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	aliases {
		mmc0 = &usdhc1;
		mmc2 = &usdhc3;
	};

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon";
		stdout-path = &lpuart0;
	};

	reg_usb_otg1_vbus: usb_otg1_vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: usdhc2_vmmc {
		compatible = "regulator-fixed";
		regulator-name = "sw-3p3-sd1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx8qm-mek {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000048
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
			>;
		};

		pinctrl_fec2: fec2grp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
				SC_P_ENET1_MDC_CONN_ENET1_MDC			0x06000020
				SC_P_ENET1_MDIO_CONN_ENET1_MDIO			0x06000020
				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
			>;
		};

		pinctrl_lpi2c1: lpi2c1grp {
			fsl,pins = <
				SC_P_GPT0_CLK_DMA_I2C1_SCL		0xc600004c
				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0xc600004c
			>;
		};

		pinctrl_lpi2c2: lpi2c2grp {
			fsl,pins = <
				SC_P_GPT1_CLK_DMA_I2C2_SCL		0xc600004c
				SC_P_GPT1_CAPTURE_DMA_I2C2_SDA		0xc600004c
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
			>;
		};

		pinctrl_rtc_mc_8803: rtc-mc-8803-grp{
			fsl,pins = <
				SC_P_SIM0_POWER_EN_DMA_I2C3_SDA		0xc600004c
				SC_P_SIM0_PD_DMA_I2C3_SCL		0xc600004c
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000020
				SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08	0x00000020
			>;
		};

		pinctrl_usdhc3_gpio: usdhc3grpgpio {
			fsl,pins = <
				SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000021
				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000021
				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000021
				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
			>;
		};
	};
};

&gpio2 {
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&gpio5 {
	status = "okay";
};

&usdhc1 {
	bus-width = <8>;
	non-removable;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	status = "okay";
};

&usdhc2 {
	bus-width = <4>;
	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	bus-width = <4>;
	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	pinctrl-names = "default","state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&fec1 {
	fsl,ar8031-phy-fixup;
	fsl,magic-packet;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@4 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <4>;
		};
	};
};

&fec2 {
	fsl,ar8031-phy-fixup;
	fsl,magic-packet;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@4 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <4>;
		};
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";
};

&i2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	status = "okay";
};

&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rtc_mc_8803>;
	status = "okay";

	rv8803@32 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "microcrystal,rv8803";
		reg = <0x32>;
	};

	24c02@50 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "atmel,24c04";
		reg = <0x50>;
	};
};

&lpuart0 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};