blob: 7496029705f61ea4a76831a090af9a6e68e1b946 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 MediaTek Inc.
* Copyright (C) 2021 BayLibre, SAS
* Author: Fabien Parent <fparent@baylibre.com>
*/
#include <clk.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <ram.h>
#include <asm/arch/misc.h>
#include <asm/armv8/mmu.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8516-clk.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
int ret;
ret = fdtdec_setup_memory_banksize();
if (ret)
return ret;
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
int mtk_pll_early_init(void)
{
return 0;
}
int mtk_soc_early_init(void)
{
return 0;
}
void reset_cpu(void)
{
psci_system_reset();
}
int print_cpuinfo(void)
{
printf("CPU: MediaTek MT8183\n");
return 0;
}
static struct mm_region mt8183_mem_map[] = {
{
/* DDR */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
}, {
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
0,
}
};
struct mm_region *mem_map = mt8183_mem_map;
|