1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
|
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
#define PMUGRF_BASE 0xfdc20000
#define GRF_BASE 0xfdc60000
#define GRF_GPIO1B_DS_2 0x218
#define GRF_GPIO1B_DS_3 0x21c
#define GRF_GPIO1C_DS_0 0x220
#define GRF_GPIO1C_DS_1 0x224
#define GRF_GPIO1C_DS_2 0x228
#define GRF_GPIO1C_DS_3 0x22c
#define SGRF_BASE 0xFDD18000
#define SGRF_SOC_CON4 0x10
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
#define PMU_BASE_ADDR 0xfdd90000
#define PMU_NOC_AUTO_CON0 (0x70)
#define PMU_NOC_AUTO_CON1 (0x74)
#define EDP_PHY_GRF_BASE 0xfdcb0000
#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
#define CPU_GRF_BASE 0xfdc30000
#define GRF_CORE_PVTPLL_CON0 (0x10)
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
GPIO0D1_MASK = GENMASK(6, 4),
GPIO0D1_GPIO = 0,
GPIO0D1_UART2_TXM0,
GPIO0D0_SHIFT = 0,
GPIO0D0_MASK = GENMASK(2, 0),
GPIO0D0_GPIO = 0,
GPIO0D0_UART2_RXM0,
};
/* GRF_IOFUNC_SEL3 */
enum {
UART2_IO_SEL_SHIFT = 10,
UART2_IO_SEL_MASK = GENMASK(11, 10),
UART2_IO_SEL_M0 = 0,
};
static struct mm_region rk3568_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xf0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xf0000000UL,
.phys = 0xf0000000UL,
.size = 0x10000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x300000000,
.phys = 0x300000000,
.size = 0x0c0c00000,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000",
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
};
struct mm_region *mem_map = rk3568_mem_map;
void board_debug_uart_init(void)
{
static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
static struct rk3568_grf * const grf = (void *)GRF_BASE;
/* UART2 M0 */
rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
/* Switch iomux */
rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
GPIO0D1_MASK | GPIO0D0_MASK,
GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
}
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
/*
* When perform idle operation, corresponding clock can
* be opened or gated automatically.
*/
writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
/* Disable eDP phy by default */
writel(0x00070007, EDP_PHY_GRF_CON10);
writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
/* Set core pvtpll ring length */
writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
/* Set the emmc sdmmc0 to secure */
rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
| SDMMC0_HPROT_SECURE_CTRL << 4));
/* set the emmc driver strength to level 2 */
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
#endif
return 0;
}
|