blob: 079d5238d5f7ae4cd95f65d7561a46730e76b7f6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Heungjun Kim <riverful.kim@samsung.com>
*/
#ifndef __ASM_ARM_ARCH_CLOCK_H_
#define __ASM_ARM_ARCH_CLOCK_H_
#ifndef __ASSEMBLY__
struct s5pc100_clock {
unsigned int apll_lock;
unsigned int mpll_lock;
unsigned int epll_lock;
unsigned int hpll_lock;
unsigned char res1[0xf0];
unsigned int apll_con;
unsigned int mpll_con;
unsigned int epll_con;
unsigned int hpll_con;
unsigned char res2[0xf0];
unsigned int src0;
unsigned int src1;
unsigned int src2;
unsigned int src3;
unsigned char res3[0xf0];
unsigned int div0;
unsigned int div1;
unsigned int div2;
unsigned int div3;
unsigned int div4;
unsigned char res4[0x1ec];
unsigned int gate_d00;
unsigned int gate_d01;
unsigned int gate_d02;
unsigned char res5[0x54];
unsigned int gate_sclk0;
unsigned int gate_sclk1;
};
struct s5pc110_clock {
unsigned int apll_lock;
unsigned char res1[0x4];
unsigned int mpll_lock;
unsigned char res2[0x4];
unsigned int epll_lock;
unsigned char res3[0xc];
unsigned int vpll_lock;
unsigned char res4[0xdc];
unsigned int apll_con;
unsigned char res5[0x4];
unsigned int mpll_con;
unsigned char res6[0x4];
unsigned int epll_con;
unsigned char res7[0xc];
unsigned int vpll_con;
unsigned char res8[0xdc];
unsigned int src0;
unsigned int src1;
unsigned int src2;
unsigned int src3;
unsigned char res9[0xf0];
unsigned int div0;
unsigned int div1;
unsigned int div2;
unsigned int div3;
unsigned int div4;
unsigned char res10[0x1ec];
unsigned int gate_d00;
unsigned int gate_d01;
unsigned int gate_d02;
unsigned char res11[0x54];
unsigned int gate_sclk0;
unsigned int gate_sclk1;
};
#endif
#endif
|