blob: 3ccaf02242c667657b7cec8e21dd9d8cb666f6e4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
#undef DPLL_SSC_RATE_1PER
int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
{
unsigned int dram_freq = bd->dram_freq;
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT (DPLLCTRL.bit[29:20])
*/
tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~0x000f0000;
switch (dram_freq) {
case 1333:
tmp |= 0x000d0000;
break;
case 1600:
tmp |= 0x000c0000;
break;
default:
pr_err("Unsupported frequency");
return -EINVAL;
}
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~SC_DPLLCTRL_SSC_RATE;
#else
tmp |= SC_DPLLCTRL_SSC_RATE;
#endif
writel(tmp, sc_base + SC_DPLLCTRL);
tmp = readl(sc_base + SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
return 0;
}
|