arch/mips/mach-octeon/cache.c


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2020 Marvell International Ltd.
 */

#include <cpu_func.h>

/* Octeon memory write barrier */
#define CVMX_SYNCW	asm volatile ("syncw\nsyncw\n" : : : "memory")

void flush_dcache_range(ulong start_addr, ulong stop)
{
	/* Flush all pending writes */
	CVMX_SYNCW;
}

void flush_cache(ulong start_addr, ulong size)
{
}

void invalidate_dcache_range(ulong start_addr, ulong stop)
{
	/* Don't need to do anything for OCTEON */
}