blob: 8f668cc67ed07e57988323650f6d43dd228c20a3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
menu "Xtensa architecture"
depends on XTENSA
config SYS_ARCH
string
default "xtensa"
config SYS_CPU
string "Xtensa Core Variant"
choice
prompt "Target select"
config TARGET_XTFPGA
bool "Support XTFPGA"
select BOARD_POSTCLK_INIT
endchoice
config SYS_ICACHE_OFF
bool "Do not enable icache"
help
Do not enable instruction cache in U-Boot.
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
help
Do not enable data cache in U-Boot.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
source "board/cadence/xtfpga/Kconfig"
endmenu
|