blob: e9b80cad506af2d2c8b4563d6364d199e19d8bec (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
Overview
--------
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
SoC overview.
LS1012AQDS board Overview
-----------------------
- SERDES Connections, 4 lanes supporting:
- PCI Express - 3.0
- SGMII, SGMII 2.5
- SATA 3.0
- DDR Controller
- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
- QSPI Controller
- A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
emulator
- USB 3.0
- One USB 3.0 controller with integrated PHY
- One high-speed USB 3.0 port
- USB 2.0
- One USB 2.0 controller with ULPI interface
- Two enhanced secure digital host controllers:
- SDHC1 controller can be connected to onboard SDHC connector
- SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
- 2 I2C controllers
- One SATA onboard connectors
- UART
- 5 SAI
- One SAI port with audio codec SGTL5000:
• Provides MIC bias
• Provides headphone and line output
- One SAI port terminated at 2x6 header
- Three SAI Tx/Rx ports terminated at 2x3 headers
- ARM JTAG support
Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2
QSPI flash map
--------------
Images | Size |QSPI Flash Address
------------------------------------------
RCW + PBI | 1MB | 0x4000_0000
U-Boot | 1MB | 0x4010_0000
U-Boot Env | 1MB | 0x4020_0000
PPA FIT image | 2MB | 0x4050_0000
Linux ITB | ~53MB | 0x40A0_0000
|