1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC Memory Controller device-tree bindings
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
- Asynchronous SRAM-like memories and ASICs
- Asynchronous, synchronous, and page mode burst NOR flash
- NAND flash
- Pseudo-SRAM devices
properties:
compatible:
items:
- enum:
- ti,am3352-gpmc
- ti,am64-gpmc
- ti,omap2420-gpmc
- ti,omap2430-gpmc
- ti,omap3430-gpmc
- ti,omap4430-gpmc
reg:
minItems: 1
maxItems: 2
reg-names:
items:
- const: cfg
- const: data
interrupts:
maxItems: 1
clocks:
maxItems: 1
description: |
Functional clock. Used for bus timing calculations and
GPMC configuration.
clock-names:
items:
- const: fck
power-domains:
maxItems: 1
dmas:
items:
- description: DMA channel for GPMC NAND prefetch
dma-names:
items:
- const: rxtx
"#address-cells": true
"#size-cells": true
gpmc,num-cs:
description: maximum number of supported chip-select lines.
$ref: /schemas/types.yaml#/definitions/uint32
gpmc,num-waitpins:
description: maximum number of supported wait pins.
$ref: /schemas/types.yaml#/definitions/uint32
ranges:
minItems: 1
description: |
Must be set up to reflect the memory layout with four
integer values for each chip-select line in use,
<cs-number> 0 <physical address of mapping> <size>
items:
- description: NAND bank 0
- description: NOR/SRAM bank 0
- description: NOR/SRAM bank 1
'#interrupt-cells':
const: 2
interrupt-controller:
description: |
The GPMC driver implements and interrupt controller for
the NAND events "fifoevent" and "termcount" plus the
rising/falling edges on the GPMC_WAIT pins.
The interrupt number mapping is as follows
0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 pin edge
3 - GPMC_WAIT1 pin edge, and so on.
'#gpio-cells':
const: 2
gpio-controller:
description: |
The GPMC driver implements a GPIO controller for the
GPMC WAIT pins that can be used as general purpose inputs.
0 maps to GPMC_WAIT0 pin.
ti,hwmods:
description:
Name of the HWMOD associated with GPMC. This is for legacy
omap2/3 platforms only.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
ti,no-idle-on-init:
description:
Prevent idling the module at init. This is for legacy omap2/3
platforms only.
type: boolean
deprecated: true
patternProperties:
"@[0-7],[a-f0-9]+$":
type: object
description: |
The child device node represents the device connected to the GPMC
bus. The device can be a NAND chip, SRAM device, NOR device
or an ASIC.
$ref: "ti,gpmc-child.yaml"
required:
- compatible
- reg
- gpmc,num-cs
- gpmc,num-waitpins
- "#address-cells"
- "#size-cells"
allOf:
- if:
properties:
compatible:
contains:
const: ti,am64-gpmc
then:
required:
- reg-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
clocks = <&l3s_clkctrl>;
clock-names = "fck";
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>;
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
};
};
|