~funderscore blog cgit wiki get in touch
aboutsummaryrefslogtreecommitdiff
blob: 580c0b1b0cf3019e35dd277d6f39d3df0175ffed (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 * Author: Finley Xiao <finley.xiao@rock-chips.com>
 */

#include <common.h>
#include <bitfield.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rv1126.h>
#include <asm/arch-rockchip/grf_rv1126.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rockchip,rv1126-cru.h>

DECLARE_GLOBAL_DATA_PTR;

#define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div)		\
{								\
	.rate	= _rate##U,					\
	.aclk_div = _aclk_div,					\
	.pclk_div = _pclk_div,					\
}

#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))

static struct rockchip_cpu_rate_table rv1126_cpu_rates[] = {
	RV1126_CPUCLK_RATE(1200000000, 1, 5),
	RV1126_CPUCLK_RATE(1008000000, 1, 5),
	RV1126_CPUCLK_RATE(816000000, 1, 3),
	RV1126_CPUCLK_RATE(600000000, 1, 3),
	RV1126_CPUCLK_RATE(408000000, 1, 1),
};

static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
	RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
	RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
	RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
	RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
	RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0),
	RK3036_PLL_RATE(100000000, 1, 100, 6, 4, 1, 0),
	{ /* sentinel */ },
};

static struct rockchip_pll_clock rv1126_pll_clks[] = {
	[APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0),
		     RV1126_MODE_CON, 0, 10, 0, rv1126_pll_rates),
	[DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8),
		     RV1126_MODE_CON, 2, 10, 0, NULL),
	[CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16),
		     RV1126_MODE_CON, 4, 10, 0, rv1126_pll_rates),
	[HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24),
		     RV1126_MODE_CON, 6, 10, 0, rv1126_pll_rates),
	[GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0),
		     RV1126_PMU_MODE, 0, 10, 0, rv1126_pll_rates),
};

static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,
				  struct rv1126_pmuclk_priv *pmu_priv,
				  ulong rate);
/*
 *
 * rational_best_approximation(31415, 10000,
 *		(1 << 8) - 1, (1 << 5) - 1, &n, &d);
 *
 * you may look at given_numerator as a fixed point number,
 * with the fractional part size described in given_denominator.
 *
 * for theoretical background, see:
 * http://en.wikipedia.org/wiki/Continued_fraction
 */
static void rational_best_approximation(unsigned long given_numerator,
					unsigned long given_denominator,
					unsigned long max_numerator,
					unsigned long max_denominator,
					unsigned long *best_numerator,
					unsigned long *best_denominator)
{
	unsigned long n, d, n0, d0, n1, d1;

	n = given_numerator;
	d = given_denominator;
	n0 = 0;
	d1 = 0;
	n1 = 1;
	d0 = 1;
	for (;;) {
		unsigned long t, a;

		if (n1 > max_numerator || d1 > max_denominator) {
			n1 = n0;
			d1 = d0;
			break;
		}
		if (d == 0)
			break;
		t = d;
		a = n / d;
		d = n % d;
		n = t;
		t = n0 + a * n1;
		n0 = n1;
		n1 = t;
		t = d0 + a * d1;
		d0 = d1;
		d1 = t;
	}
	*best_numerator = n1;
	*best_denominator = d1;
}

static ulong rv1126_gpll_get_pmuclk(struct rv1126_pmuclk_priv *priv)
{
	return rockchip_pll_get_rate(&rv1126_pll_clks[GPLL],
				     priv->pmucru, GPLL);
}

static ulong rv1126_gpll_set_pmuclk(struct rv1126_pmuclk_priv *pmu_priv, ulong rate)
{
	struct udevice *cru_dev;
	struct rv1126_clk_priv *priv;
	int ret;

	ret = uclass_get_device_by_driver(UCLASS_CLK,
					  DM_DRIVER_GET(rockchip_rv1126_cru),
					  &cru_dev);
	if (ret) {
		printf("%s: could not find cru device\n", __func__);
		return ret;
	}
	priv = dev_get_priv(cru_dev);

	if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) {
		printf("%s: failed to set gpll rate %lu\n", __func__, rate);
		return -EINVAL;
	}
	return 0;
}

static ulong rv1126_rtc32k_get_pmuclk(struct rv1126_pmuclk_priv *priv)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	unsigned long m, n;
	u32 fracdiv;

	fracdiv = readl(&pmucru->pmu_clksel_con[13]);
	m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK;
	m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT;
	n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK;
	n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT;

	return OSC_HZ * m / n;
}

static ulong rv1126_rtc32k_set_pmuclk(struct rv1126_pmuclk_priv *priv,
				      ulong rate)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	unsigned long m, n, val;

	rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
		     RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT);

	rational_best_approximation(rate, OSC_HZ,
				    GENMASK(16 - 1, 0),
				    GENMASK(16 - 1, 0),
				    &m, &n);
	val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n;
	writel(val, &pmucru->pmu_clksel_con[13]);

	return rv1126_rtc32k_get_pmuclk(priv);
}

static ulong rv1126_i2c_get_pmuclk(struct rv1126_pmuclk_priv *priv,
				   ulong clk_id)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	u32 div, con;

	switch (clk_id) {
	case CLK_I2C0:
		con = readl(&pmucru->pmu_clksel_con[2]);
		div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT;
		break;
	case CLK_I2C2:
		con = readl(&pmucru->pmu_clksel_con[3]);
		div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT;
		break;
	default:
		return -ENOENT;
	}

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_i2c_set_pmuclk(struct rv1126_pmuclk_priv *priv,
				   ulong clk_id, ulong rate)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 127);

	switch (clk_id) {
	case CLK_I2C0:
		rk_clrsetreg(&pmucru->pmu_clksel_con[2], CLK_I2C0_DIV_MASK,
			     (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT);
		break;
	case CLK_I2C2:
		rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C2_DIV_MASK,
			     (src_clk_div - 1) << CLK_I2C2_DIV_SHIFT);
		break;
	default:
		return -ENOENT;
	}

	return rv1126_i2c_get_pmuclk(priv, clk_id);
}

static ulong rv1126_pwm_get_pmuclk(struct rv1126_pmuclk_priv *priv,
				   ulong clk_id)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	u32 div, sel, con;

	switch (clk_id) {
	case CLK_PWM0:
		con = readl(&pmucru->pmu_clksel_con[6]);
		sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;
		div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT;
		if (sel == CLK_PWM0_SEL_XIN24M)
			return OSC_HZ;
		break;
	case CLK_PWM1:
		con = readl(&pmucru->pmu_clksel_con[6]);
		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
		div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT;
		if (sel == CLK_PWM1_SEL_XIN24M)
			return OSC_HZ;
		break;
	default:
		return -ENOENT;
	}

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_pwm_set_pmuclk(struct rv1126_pmuclk_priv *priv,
				   ulong clk_id, ulong rate)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	int src_clk_div;

	switch (clk_id) {
	case CLK_PWM0:
		if (rate == OSC_HZ) {
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM0_SEL_MASK,
				     CLK_PWM0_SEL_XIN24M << CLK_PWM0_SEL_SHIFT);
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM0_DIV_MASK, 0);
		} else {
			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
			assert(src_clk_div - 1 <= 127);
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM0_DIV_MASK,
				     (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT);
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM0_SEL_MASK,
				     CLK_PWM0_SEL_GPLL << CLK_PWM0_SEL_SHIFT);
		}
		break;
	case CLK_PWM1:
		if (rate == OSC_HZ) {
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM1_SEL_MASK,
				     CLK_PWM1_SEL_XIN24M << CLK_PWM1_SEL_SHIFT);
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM1_DIV_MASK, 0);
		} else {
			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
			assert(src_clk_div - 1 <= 127);
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM1_DIV_MASK,
				     (src_clk_div - 1) << CLK_PWM1_DIV_SHIFT);
			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
				     CLK_PWM1_SEL_MASK,
				     CLK_PWM1_SEL_GPLL << CLK_PWM1_SEL_SHIFT);
		}
		break;
	default:
		return -ENOENT;
	}

	return rv1126_pwm_get_pmuclk(priv, clk_id);
}

static ulong rv1126_spi_get_pmuclk(struct rv1126_pmuclk_priv *priv)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	u32 div, con;

	con = readl(&pmucru->pmu_clksel_con[9]);
	div = (con & CLK_SPI0_DIV_MASK) >> CLK_SPI0_DIV_SHIFT;

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_spi_set_pmuclk(struct rv1126_pmuclk_priv *priv,
				   ulong rate)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 127);

	rk_clrsetreg(&pmucru->pmu_clksel_con[9],
		     CLK_SPI0_SEL_MASK | CLK_SPI0_DIV_MASK,
		     CLK_SPI0_SEL_GPLL << CLK_SPI0_SEL_SHIFT |
		     (src_clk_div - 1) << CLK_SPI0_DIV_SHIFT);

	return rv1126_spi_get_pmuclk(priv);
}

static ulong rv1126_pdpmu_get_pmuclk(struct rv1126_pmuclk_priv *priv)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	u32 div, con;

	con = readl(&pmucru->pmu_clksel_con[1]);
	div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT;

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_pdpmu_set_pmuclk(struct rv1126_pmuclk_priv *priv,
				     ulong rate)
{
	struct rv1126_pmucru *pmucru = priv->pmucru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 31);

	rk_clrsetreg(&pmucru->pmu_clksel_con[1],
		     PCLK_PDPMU_DIV_MASK,
		     (src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT);

	return rv1126_pdpmu_get_pmuclk(priv);
}

static ulong rv1126_pmuclk_get_rate(struct clk *clk)
{
	struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev);
	ulong rate = 0;

	if (!priv->gpll_hz) {
		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
		return -ENOENT;
	}

	debug("%s %ld\n", __func__, clk->id);
	switch (clk->id) {
	case PLL_GPLL:
		rate = rv1126_gpll_get_pmuclk(priv);
		break;
	case CLK_RTC32K:
		rate = rv1126_rtc32k_get_pmuclk(priv);
		break;
	case CLK_I2C0:
	case CLK_I2C2:
		rate = rv1126_i2c_get_pmuclk(priv, clk->id);
		break;
	case CLK_PWM0:
	case CLK_PWM1:
		rate = rv1126_pwm_get_pmuclk(priv, clk->id);
		break;
	case CLK_SPI0:
		rate = rv1126_spi_get_pmuclk(priv);
		break;
	case PCLK_PDPMU:
		rate = rv1126_pdpmu_get_pmuclk(priv);
		break;
	default:
		debug("%s: Unsupported CLK#%ld\n", __func__, clk->id);
		return -ENOENT;
	}

	return rate;
}

static ulong rv1126_pmuclk_set_rate(struct clk *clk, ulong rate)
{
	struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev);
	ulong ret = 0;

	if (!priv->gpll_hz) {
		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
		return -ENOENT;
	}

	debug("%s %ld %ld\n", __func__, clk->id, rate);
	switch (clk->id) {
	case PLL_GPLL:
		ret = rv1126_gpll_set_pmuclk(priv, rate);
		break;
	case CLK_RTC32K:
		ret = rv1126_rtc32k_set_pmuclk(priv, rate);
		break;
	case CLK_I2C0:
	case CLK_I2C2:
		ret = rv1126_i2c_set_pmuclk(priv, clk->id, rate);
		break;
	case CLK_PWM0:
	case CLK_PWM1:
		ret = rv1126_pwm_set_pmuclk(priv, clk->id, rate);
		break;
	case CLK_SPI0:
		ret = rv1126_spi_set_pmuclk(priv, rate);
		break;
	case PCLK_PDPMU:
		ret = rv1126_pdpmu_set_pmuclk(priv, rate);
		break;
	default:
		debug("%s: Unsupported CLK#%ld\n", __func__, clk->id);
		return -ENOENT;
	}

	return ret;
}

static int rv1126_rtc32k_set_parent(struct clk *clk, struct clk *parent)
{
	struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev);
	struct rv1126_pmucru *pmucru = priv->pmucru;

	if (parent->id == CLK_OSC0_DIV32K)
		rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
			     RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT);
	else
		rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
			     RTC32K_SEL_OSC1_32K << RTC32K_SEL_SHIFT);

	return 0;
}

static int rv1126_pmuclk_set_parent(struct clk *clk, struct clk *parent)
{
	switch (clk->id) {
	case CLK_RTC32K:
		return rv1126_rtc32k_set_parent(clk, parent);
	default:
		debug("%s: Unsupported CLK#%ld\n", __func__, clk->id);
		return -ENOENT;
	}
}

static struct clk_ops rv1126_pmuclk_ops = {
	.get_rate = rv1126_pmuclk_get_rate,
	.set_rate = rv1126_pmuclk_set_rate,
	.set_parent = rv1126_pmuclk_set_parent,
};

static int rv1126_pmuclk_probe(struct udevice *dev)
{
	struct rv1126_pmuclk_priv *priv = dev_get_priv(dev);

	priv->gpll_hz =	rv1126_gpll_get_pmuclk(priv);

	return 0;
}

static int rv1126_pmuclk_of_to_plat(struct udevice *dev)
{
	struct rv1126_pmuclk_priv *priv = dev_get_priv(dev);

	priv->pmucru = dev_read_addr_ptr(dev);

	return 0;
}

static int rv1126_pmuclk_bind(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
	int ret;

	ret = offsetof(struct rv1126_pmucru, pmu_softrst_con[0]);
	ret = rockchip_reset_bind(dev, ret, 2);
	if (ret)
		debug("Warning: software reset driver bind failed\n");
#endif
	return 0;
}

static const struct udevice_id rv1126_pmuclk_ids[] = {
	{ .compatible = "rockchip,rv1126-pmucru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rv1126_pmucru) = {
	.name		= "rockchip_rv1126_pmucru",
	.id		= UCLASS_CLK,
	.of_match	= rv1126_pmuclk_ids,
	.priv_auto	= sizeof(struct rv1126_pmuclk_priv),
	.of_to_plat	= rv1126_pmuclk_of_to_plat,
	.ops		= &rv1126_pmuclk_ops,
	.bind		= rv1126_pmuclk_bind,
	.probe		= rv1126_pmuclk_probe,
};

static int rv1126_armclk_set_clk(struct rv1126_clk_priv *priv, ulong hz)
{
	struct rv1126_cru *cru = priv->cru;
	const struct rockchip_cpu_rate_table *rate;
	ulong old_rate;

	rate = rockchip_get_cpu_settings(rv1126_cpu_rates, hz);
	if (!rate) {
		printf("%s unsupported rate\n", __func__);
		return -EINVAL;
	}

	/*
	 * set up dependent divisors for DBG and ACLK clocks.
	 */
	old_rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL],
					 priv->cru, APLL);
	if (old_rate > hz) {
		if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL],
					  priv->cru, APLL, hz))
			return -EINVAL;
		rk_clrsetreg(&cru->clksel_con[1],
			     CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK,
			     rate->pclk_div << CORE_DBG_DIV_SHIFT |
			     rate->aclk_div << CORE_ACLK_DIV_SHIFT);
	} else if (old_rate < hz) {
		rk_clrsetreg(&cru->clksel_con[1],
			     CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK,
			     rate->pclk_div << CORE_DBG_DIV_SHIFT |
			     rate->aclk_div << CORE_ACLK_DIV_SHIFT);
		if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL],
					  priv->cru, APLL, hz))
			return -EINVAL;
	}

	return 0;
}

static ulong rv1126_pdcore_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 con, div;

	con = readl(&cru->clksel_con[0]);
	div = (con & CORE_HCLK_DIV_MASK) >> CORE_HCLK_DIV_SHIFT;

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_pdcore_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 31);

	rk_clrsetreg(&cru->clksel_con[0], CORE_HCLK_DIV_MASK,
		     (src_clk_div - 1) << CORE_HCLK_DIV_SHIFT);

	return rv1126_pdcore_get_clk(priv);
}

static ulong rv1126_pdbus_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
{
	struct rv1126_cru *cru = priv->cru;
	u32 con, div, sel, parent;

	switch (clk_id) {
	case ACLK_PDBUS:
		con = readl(&cru->clksel_con[2]);
		div = (con & ACLK_PDBUS_DIV_MASK) >> ACLK_PDBUS_DIV_SHIFT;
		sel = (con & ACLK_PDBUS_SEL_MASK) >> ACLK_PDBUS_SEL_SHIFT;
		if (sel == ACLK_PDBUS_SEL_GPLL)
			parent = priv->gpll_hz;
		else if (sel == ACLK_PDBUS_SEL_CPLL)
			parent = priv->cpll_hz;
		else
			return -ENOENT;
		break;
	case HCLK_PDBUS:
		con = readl(&cru->clksel_con[2]);
		div = (con & HCLK_PDBUS_DIV_MASK) >> HCLK_PDBUS_DIV_SHIFT;
		sel = (con & HCLK_PDBUS_SEL_MASK) >> HCLK_PDBUS_SEL_SHIFT;
		if (sel == HCLK_PDBUS_SEL_GPLL)
			parent = priv->gpll_hz;
		else if (sel == HCLK_PDBUS_SEL_CPLL)
			parent = priv->cpll_hz;
		else
			return -ENOENT;
		break;
	case PCLK_PDBUS:
	case PCLK_WDT:
		con = readl(&cru->clksel_con[3]);
		div = (con & PCLK_PDBUS_DIV_MASK) >> PCLK_PDBUS_DIV_SHIFT;
		sel = (con & PCLK_PDBUS_SEL_MASK) >> PCLK_PDBUS_SEL_SHIFT;
		if (sel == PCLK_PDBUS_SEL_GPLL)
			parent = priv->gpll_hz;
		else if (sel == PCLK_PDBUS_SEL_CPLL)
			parent = priv->cpll_hz;
		else
			return -ENOENT;
		break;
	default:
		return -ENOENT;
	}

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_pdbus_set_clk(struct rv1126_clk_priv *priv, ulong clk_id,
				  ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div, clk_sel;

	switch (clk_id) {
	case ACLK_PDBUS:
		if (CPLL_HZ % rate) {
			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
			clk_sel = ACLK_PDBUS_SEL_GPLL;
		} else {
			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
			clk_sel = ACLK_PDBUS_SEL_CPLL;
		}
		assert(src_clk_div - 1 <= 31);
		rk_clrsetreg(&cru->clksel_con[2],
			     ACLK_PDBUS_SEL_MASK | ACLK_PDBUS_DIV_MASK,
			     clk_sel << ACLK_PDBUS_SEL_SHIFT |
			     (src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT);
		break;
	case HCLK_PDBUS:
		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
		assert(src_clk_div - 1 <= 31);
		rk_clrsetreg(&cru->clksel_con[2],
			     HCLK_PDBUS_SEL_MASK | HCLK_PDBUS_DIV_MASK,
			     HCLK_PDBUS_SEL_GPLL << HCLK_PDBUS_SEL_SHIFT |
			     (src_clk_div - 1) << HCLK_PDBUS_DIV_SHIFT);
		break;
	case PCLK_PDBUS:
	case PCLK_WDT:
		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
		assert(src_clk_div - 1 <= 31);
		rk_clrsetreg(&cru->clksel_con[3],
			     PCLK_PDBUS_SEL_MASK | PCLK_PDBUS_DIV_MASK,
			     PCLK_PDBUS_SEL_GPLL << PCLK_PDBUS_SEL_SHIFT |
			     (src_clk_div - 1) << PCLK_PDBUS_DIV_SHIFT);
		break;

	default:
		printf("do not support this pdbus freq\n");
		return -EINVAL;
	}

	return rv1126_pdbus_get_clk(priv, clk_id);
}

static ulong rv1126_pdphp_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
{
	struct rv1126_cru *cru = priv->cru;
	u32 con, div, parent;

	switch (clk_id) {
	case ACLK_PDPHP:
		con = readl(&cru->clksel_con[53]);
		div = (con & ACLK_PDPHP_DIV_MASK) >> ACLK_PDPHP_DIV_SHIFT;
		parent = priv->gpll_hz;
		break;
	case HCLK_PDPHP:
		con = readl(&cru->clksel_con[53]);
		div = (con & HCLK_PDPHP_DIV_MASK) >> HCLK_PDPHP_DIV_SHIFT;
		parent = priv->gpll_hz;
		break;
	default:
		return -ENOENT;
	}

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_pdphp_set_clk(struct rv1126_clk_priv *priv, ulong clk_id,
				  ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 31);

	switch (clk_id) {
	case ACLK_PDPHP:
		rk_clrsetreg(&cru->clksel_con[53],
			     ACLK_PDPHP_SEL_MASK | ACLK_PDPHP_DIV_MASK,
			     ACLK_PDPHP_SEL_GPLL << ACLK_PDPHP_SEL_SHIFT |
			     (src_clk_div - 1) << ACLK_PDPHP_DIV_SHIFT);
		break;
	case HCLK_PDPHP:
		rk_clrsetreg(&cru->clksel_con[53],
			     HCLK_PDPHP_DIV_MASK,
			     (src_clk_div - 1) << HCLK_PDPHP_DIV_SHIFT);
		break;
	default:
		printf("do not support this pdphp freq\n");
		return -EINVAL;
	}

	return rv1126_pdphp_get_clk(priv, clk_id);
}

static ulong rv1126_pdaudio_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 con, div;

	con = readl(&cru->clksel_con[26]);
	div = (con & HCLK_PDAUDIO_DIV_MASK) >> HCLK_PDAUDIO_DIV_SHIFT;

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_pdaudio_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 31);

	rk_clrsetreg(&cru->clksel_con[26], HCLK_PDAUDIO_DIV_MASK,
		     (src_clk_div - 1) << HCLK_PDAUDIO_DIV_SHIFT);

	return rv1126_pdaudio_get_clk(priv);
}

static ulong rv1126_i2c_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, con;

	switch (clk_id) {
	case CLK_I2C1:
		con = readl(&cru->clksel_con[5]);
		div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT;
		break;
	case CLK_I2C3:
		con = readl(&cru->clksel_con[5]);
		div = (con & CLK_I2C3_DIV_MASK) >> CLK_I2C3_DIV_SHIFT;
		break;
	case CLK_I2C4:
		con = readl(&cru->clksel_con[6]);
		div = (con & CLK_I2C4_DIV_MASK) >> CLK_I2C4_DIV_SHIFT;
		break;
	case CLK_I2C5:
		con = readl(&cru->clksel_con[6]);
		div = (con & CLK_I2C5_DIV_MASK) >> CLK_I2C5_DIV_SHIFT;
		break;
	default:
		return -ENOENT;
	}

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_i2c_set_clk(struct rv1126_clk_priv *priv, ulong clk_id,
				ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 127);

	switch (clk_id) {
	case CLK_I2C1:
		rk_clrsetreg(&cru->clksel_con[5], CLK_I2C1_DIV_MASK,
			     (src_clk_div - 1) << CLK_I2C1_DIV_SHIFT);
		break;
	case CLK_I2C3:
		rk_clrsetreg(&cru->clksel_con[5], CLK_I2C3_DIV_MASK,
			     (src_clk_div - 1) << CLK_I2C3_DIV_SHIFT);
		break;
	case CLK_I2C4:
		rk_clrsetreg(&cru->clksel_con[6], CLK_I2C4_DIV_MASK,
			     (src_clk_div - 1) << CLK_I2C4_DIV_SHIFT);
		break;
	case CLK_I2C5:
		rk_clrsetreg(&cru->clksel_con[6], CLK_I2C5_DIV_MASK,
			     (src_clk_div - 1) << CLK_I2C5_DIV_SHIFT);
		break;
	default:
		return -ENOENT;
	}

	return rv1126_i2c_get_clk(priv, clk_id);
}

static ulong rv1126_spi_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, con;

	con = readl(&cru->clksel_con[8]);
	div = (con & CLK_SPI1_DIV_MASK) >> CLK_SPI1_DIV_SHIFT;

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_spi_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 127);

	rk_clrsetreg(&cru->clksel_con[8],
		     CLK_SPI1_SEL_MASK | CLK_SPI1_DIV_MASK,
		     CLK_SPI1_SEL_GPLL << CLK_SPI1_SEL_SHIFT |
		     (src_clk_div - 1) << CLK_SPI1_DIV_SHIFT);

	return rv1126_spi_get_clk(priv);
}

static ulong rv1126_pwm_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con;

	con = readl(&cru->clksel_con[9]);
	sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
	div = (con & CLK_PWM2_DIV_MASK) >> CLK_PWM2_DIV_SHIFT;
	if (sel == CLK_PWM2_SEL_XIN24M)
		return OSC_HZ;

	return DIV_TO_RATE(priv->gpll_hz, div);
}

static ulong rv1126_pwm_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	if (rate == OSC_HZ) {
		rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK,
			     CLK_PWM2_SEL_XIN24M << CLK_PWM2_SEL_SHIFT);
		rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, 0);
	} else {
		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
		assert(src_clk_div - 1 <= 127);
		rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK,
			     (src_clk_div - 1) << CLK_PWM2_DIV_SHIFT);
		rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK,
			     CLK_PWM2_SEL_GPLL << CLK_PWM2_SEL_SHIFT);
	}

	return rv1126_pwm_get_clk(priv);
}

static ulong rv1126_saradc_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, con;

	con = readl(&cru->clksel_con[20]);
	div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;

	return DIV_TO_RATE(OSC_HZ, div);
}

static ulong rv1126_saradc_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
	assert(src_clk_div - 1 <= 2047);
	rk_clrsetreg(&cru->clksel_con[20], CLK_SARADC_DIV_MASK,
		     (src_clk_div - 1) << CLK_SARADC_DIV_SHIFT);

	return rv1126_saradc_get_clk(priv);
}

static ulong rv1126_crypto_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	switch (clk_id) {
	case CLK_CRYPTO_CORE:
		con = readl(&cru->clksel_con[7]);
		div = (con & CLK_CRYPTO_CORE_DIV_MASK) >> CLK_CRYPTO_CORE_DIV_SHIFT;
		sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >> CLK_CRYPTO_CORE_SEL_SHIFT;
		if (sel == CLK_CRYPTO_CORE_SEL_GPLL)
			parent = priv->gpll_hz;
		else if (sel == CLK_CRYPTO_CORE_SEL_CPLL)
			parent = priv->cpll_hz;
		else
			return -ENOENT;
		break;
	case CLK_CRYPTO_PKA:
		con = readl(&cru->clksel_con[7]);
		div = (con & CLK_CRYPTO_PKA_DIV_MASK) >> CLK_CRYPTO_PKA_DIV_SHIFT;
		sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >> CLK_CRYPTO_PKA_SEL_SHIFT;
		if (sel == CLK_CRYPTO_PKA_SEL_GPLL)
			parent = priv->gpll_hz;
		else if (sel == CLK_CRYPTO_PKA_SEL_CPLL)
			parent = priv->cpll_hz;
		else
			return -ENOENT;
		break;
	case ACLK_CRYPTO:
		con = readl(&cru->clksel_con[4]);
		div = (con & ACLK_CRYPTO_DIV_MASK) >> ACLK_CRYPTO_DIV_SHIFT;
		sel = (con & ACLK_CRYPTO_SEL_MASK) >> ACLK_CRYPTO_SEL_SHIFT;
		if (sel == ACLK_CRYPTO_SEL_GPLL)
			parent = priv->gpll_hz;
		else if (sel == ACLK_CRYPTO_SEL_CPLL)
			parent = priv->cpll_hz;
		else
			return -ENOENT;
		break;
	default:
		return -ENOENT;
	}

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_crypto_set_clk(struct rv1126_clk_priv *priv, ulong clk_id,
				   ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 31);

	switch (clk_id) {
	case CLK_CRYPTO_CORE:
		rk_clrsetreg(&cru->clksel_con[7],
			     CLK_CRYPTO_CORE_SEL_MASK |
			     CLK_CRYPTO_CORE_DIV_MASK,
			     CLK_CRYPTO_CORE_SEL_GPLL <<
			     CLK_CRYPTO_CORE_SEL_SHIFT |
			     (src_clk_div - 1) << CLK_CRYPTO_CORE_DIV_SHIFT);
		break;
	case CLK_CRYPTO_PKA:
		rk_clrsetreg(&cru->clksel_con[7],
			     CLK_CRYPTO_PKA_SEL_MASK |
			     CLK_CRYPTO_PKA_DIV_MASK,
			     CLK_CRYPTO_PKA_SEL_GPLL <<
			     CLK_CRYPTO_PKA_SEL_SHIFT |
			     (src_clk_div - 1) << CLK_CRYPTO_PKA_DIV_SHIFT);
		break;
	case ACLK_CRYPTO:
		rk_clrsetreg(&cru->clksel_con[4],
			     ACLK_CRYPTO_SEL_MASK | ACLK_CRYPTO_DIV_MASK,
			     ACLK_CRYPTO_SEL_GPLL << ACLK_CRYPTO_SEL_SHIFT |
			     (src_clk_div - 1) << ACLK_CRYPTO_DIV_SHIFT);
		break;
	default:
		return -ENOENT;
	}

	return rv1126_crypto_get_clk(priv, clk_id);
}

static ulong rv1126_mmc_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, con_id;

	switch (clk_id) {
	case HCLK_SDMMC:
	case CLK_SDMMC:
		con_id = 55;
		break;
	case HCLK_SDIO:
	case CLK_SDIO:
		con_id = 56;
		break;
	case HCLK_EMMC:
	case CLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		con_id = 57;
		break;
	default:
		return -ENOENT;
	}

	con = readl(&cru->clksel_con[con_id]);
	div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
	sel = (con & EMMC_SEL_MASK) >> EMMC_SEL_SHIFT;
	if (sel == EMMC_SEL_GPLL)
		return DIV_TO_RATE(priv->gpll_hz, div) / 2;
	else if (sel == EMMC_SEL_CPLL)
		return DIV_TO_RATE(priv->cpll_hz, div) / 2;
	else if (sel == EMMC_SEL_XIN24M)
		return DIV_TO_RATE(OSC_HZ, div) / 2;

	return -ENOENT;
}

static ulong rv1126_mmc_set_clk(struct rv1126_clk_priv *priv, ulong clk_id,
				ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;
	u32 con_id;

	switch (clk_id) {
	case HCLK_SDMMC:
	case CLK_SDMMC:
		con_id = 55;
		break;
	case HCLK_SDIO:
	case CLK_SDIO:
		con_id = 56;
		break;
	case HCLK_EMMC:
	case CLK_EMMC:
		con_id = 57;
		break;
	default:
		return -ENOENT;
	}

	/* Select clk_sdmmc/emmc source from GPLL by default */
	/* mmc clock defaulg div 2 internal, need provide double in cru */
	src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, rate);

	if (src_clk_div > 127) {
		/* use 24MHz source for 400KHz clock */
		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, rate);
		rk_clrsetreg(&cru->clksel_con[con_id],
			     EMMC_SEL_MASK | EMMC_DIV_MASK,
			     EMMC_SEL_XIN24M << EMMC_SEL_SHIFT |
			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
	} else {
		rk_clrsetreg(&cru->clksel_con[con_id],
			     EMMC_SEL_MASK | EMMC_DIV_MASK,
			     EMMC_SEL_GPLL << EMMC_SEL_SHIFT |
			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
	}

	return rv1126_mmc_get_clk(priv, clk_id);
}

static ulong rv1126_sfc_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[58]);
	div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;
	sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;
	if (sel == SCLK_SFC_SEL_GPLL)
		parent = priv->gpll_hz;
	else if (sel == SCLK_SFC_SEL_CPLL)
		parent = priv->cpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_sfc_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	rk_clrsetreg(&cru->clksel_con[58],
		     SCLK_SFC_SEL_MASK | SCLK_SFC_DIV_MASK,
		     SCLK_SFC_SEL_GPLL << SCLK_SFC_SEL_SHIFT |
		     (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT);

	return rv1126_sfc_get_clk(priv);
}

static ulong rv1126_nand_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[59]);
	div = (con & CLK_NANDC_DIV_MASK) >> CLK_NANDC_DIV_SHIFT;
	sel = (con & CLK_NANDC_SEL_MASK) >> CLK_NANDC_SEL_SHIFT;
	if (sel == CLK_NANDC_SEL_GPLL)
		parent = priv->gpll_hz;
	else if (sel == CLK_NANDC_SEL_CPLL)
		parent = priv->cpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_nand_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	rk_clrsetreg(&cru->clksel_con[59],
		     CLK_NANDC_SEL_MASK | CLK_NANDC_DIV_MASK,
		     CLK_NANDC_SEL_GPLL << CLK_NANDC_SEL_SHIFT |
		     (src_clk_div - 1) << CLK_NANDC_DIV_SHIFT);

	return rv1126_nand_get_clk(priv);
}

static ulong rv1126_aclk_vop_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[45]);
	div = (con & ACLK_PDVO_DIV_MASK) >> ACLK_PDVO_DIV_SHIFT;
	sel = (con & ACLK_PDVO_SEL_MASK) >> ACLK_PDVO_SEL_SHIFT;
	if (sel == ACLK_PDVO_SEL_GPLL)
		parent = priv->gpll_hz;
	else if (sel == ACLK_PDVO_SEL_CPLL)
		parent = priv->cpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_aclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 31);
	rk_clrsetreg(&cru->clksel_con[45],
		     ACLK_PDVO_SEL_MASK | ACLK_PDVO_DIV_MASK,
		     ACLK_PDVO_SEL_GPLL << ACLK_PDVO_SEL_SHIFT |
		     (src_clk_div - 1) << ACLK_PDVO_DIV_SHIFT);

	return rv1126_aclk_vop_get_clk(priv);
}

static ulong rv1126_dclk_vop_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[47]);
	div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT;
	sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT;
	if (sel == DCLK_VOP_SEL_GPLL)
		parent = priv->gpll_hz;
	else if (sel == DCLK_VOP_SEL_CPLL)
		parent = priv->cpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_dclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	ulong pll_rate, now, best_rate = 0;
	u32 i, div, best_div = 0, best_sel = 0;

	for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
		switch (i) {
		case DCLK_VOP_SEL_GPLL:
			pll_rate = priv->gpll_hz;
			break;
		case DCLK_VOP_SEL_CPLL:
			pll_rate = priv->cpll_hz;
			break;
		default:
			printf("do not support this vop pll sel\n");
			return -EINVAL;
		}

		div = DIV_ROUND_UP(pll_rate, rate);
		if (div > 255)
			continue;
		now = pll_rate / div;
		if (abs(rate - now) < abs(rate - best_rate)) {
			best_rate = now;
			best_div = div;
			best_sel = i;
		}
		debug("pll_rate=%lu, best_rate=%lu, best_div=%u, best_sel=%u\n",
		      pll_rate, best_rate, best_div, best_sel);
	}

	if (best_rate) {
		rk_clrsetreg(&cru->clksel_con[47],
			     DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK,
			     best_sel << DCLK_VOP_SEL_SHIFT |
			     (best_div - 1) << DCLK_VOP_DIV_SHIFT);
	} else {
		printf("do not support this vop freq %lu\n", rate);
		return -EINVAL;
	}

	return rv1126_dclk_vop_get_clk(priv);
}

static ulong rv1126_scr1_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[3]);
	div = (con & CLK_SCR1_DIV_MASK) >> CLK_SCR1_DIV_SHIFT;
	sel = (con & CLK_SCR1_SEL_MASK) >> CLK_SCR1_SEL_SHIFT;
	if (sel == CLK_SCR1_SEL_GPLL)
		parent = priv->gpll_hz;
	else if (sel == CLK_SCR1_SEL_CPLL)
		parent = priv->cpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_scr1_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 31);
	rk_clrsetreg(&cru->clksel_con[3],
		     CLK_SCR1_SEL_MASK | CLK_SCR1_DIV_MASK,
		     CLK_SCR1_SEL_GPLL << CLK_SCR1_SEL_SHIFT |
		     (src_clk_div - 1) << CLK_SCR1_DIV_SHIFT);

	return rv1126_scr1_get_clk(priv);
}

static ulong rv1126_gmac_src_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[63]);
	div = (con & CLK_GMAC_SRC_DIV_MASK) >> CLK_GMAC_SRC_DIV_SHIFT;
	sel = (con & CLK_GMAC_SRC_SEL_MASK) >> CLK_GMAC_SRC_SEL_SHIFT;
	if (sel == CLK_GMAC_SRC_SEL_CPLL)
		parent = priv->cpll_hz;
	else if (sel == CLK_GMAC_SRC_SEL_GPLL)
		parent = priv->gpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_gmac_src_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
	assert(src_clk_div - 1 <= 31);
	rk_clrsetreg(&cru->clksel_con[63],
		     CLK_GMAC_SRC_SEL_MASK | CLK_GMAC_SRC_DIV_MASK,
		     CLK_GMAC_SRC_SEL_CPLL << CLK_GMAC_SRC_SEL_SHIFT |
		     (src_clk_div - 1) << CLK_GMAC_SRC_DIV_SHIFT);

	return rv1126_gmac_src_get_clk(priv);
}

static ulong rv1126_gmac_out_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[61]);
	div = (con & CLK_GMAC_OUT_DIV_MASK) >> CLK_GMAC_OUT_DIV_SHIFT;
	sel = (con & CLK_GMAC_OUT_SEL_MASK) >> CLK_GMAC_OUT_SEL_SHIFT;
	if (sel == CLK_GMAC_OUT_SEL_CPLL)
		parent = priv->cpll_hz;
	else if (sel == CLK_GMAC_OUT_SEL_GPLL)
		parent = priv->gpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_gmac_out_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	int src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
	assert(src_clk_div - 1 <= 31);
	rk_clrsetreg(&cru->clksel_con[61],
		     CLK_GMAC_OUT_SEL_MASK | CLK_GMAC_OUT_DIV_MASK,
		     CLK_GMAC_OUT_SEL_CPLL << CLK_GMAC_OUT_SEL_SHIFT |
		     (src_clk_div - 1) << CLK_GMAC_OUT_DIV_SHIFT);

	return rv1126_gmac_out_get_clk(priv);
}

static ulong rv1126_gmac_tx_rx_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	u32 con, sel, div_sel;

	con = readl(&cru->gmac_con);
	sel = (con & GMAC_MODE_SEL_MASK) >> GMAC_MODE_SEL_SHIFT;

	if (sel == GMAC_RGMII_MODE) {
		if (rate == 2500000)
			div_sel = RGMII_CLK_DIV50;
		else if (rate == 25000000)
			div_sel = RGMII_CLK_DIV5;
		else
			div_sel = RGMII_CLK_DIV0;
		rk_clrsetreg(&cru->gmac_con, RGMII_CLK_SEL_MASK,
			     div_sel << RGMII_CLK_SEL_SHIFT);
	} else if (sel == GMAC_RMII_MODE) {
		if (rate == 2500000)
			div_sel = RMII_CLK_DIV20;
		else
			div_sel = RMII_CLK_DIV2;
		rk_clrsetreg(&cru->gmac_con, RMII_CLK_SEL_MASK,
			     div_sel << RMII_CLK_SEL_SHIFT);
	}

	return 0;
}

static ulong rv1126_pclk_gmac_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, con, parent;

	parent = rv1126_pdphp_get_clk(priv, ACLK_PDPHP);

	con = readl(&cru->clksel_con[63]);
	div = (con & PCLK_GMAC_DIV_MASK) >> PCLK_GMAC_DIV_SHIFT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_dclk_decom_get_clk(struct rv1126_clk_priv *priv)
{
	struct rv1126_cru *cru = priv->cru;
	u32 div, sel, con, parent;

	con = readl(&cru->clksel_con[25]);
	div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;
	sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT;
	if (sel == DCLK_DECOM_SEL_GPLL)
		parent = priv->gpll_hz;
	else if (sel == DCLK_DECOM_SEL_CPLL)
		parent = priv->cpll_hz;
	else
		return -ENOENT;

	return DIV_TO_RATE(parent, div);
}

static ulong rv1126_dclk_decom_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct rv1126_cru *cru = priv->cru;
	u32 src_clk_div;

	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
	assert(src_clk_div - 1 <= 127);
	rk_clrsetreg(&cru->clksel_con[25],
		     DCLK_DECOM_SEL_MASK | DCLK_DECOM_DIV_MASK,
		     DCLK_DECOM_SEL_GPLL << DCLK_DECOM_SEL_SHIFT |
		     (src_clk_div - 1) << DCLK_DECOM_DIV_SHIFT);

	return rv1126_dclk_decom_get_clk(priv);
}

static ulong rv1126_clk_get_rate(struct clk *clk)
{
	struct rv1126_clk_priv *priv = dev_get_priv(clk->dev);
	ulong rate = 0;

	if (!priv->gpll_hz) {
		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
		return -ENOENT;
	}

	switch (clk->id) {
	case PLL_APLL:
	case ARMCLK:
		rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru,
					     APLL);
		break;
	case PLL_CPLL:
		rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru,
					     CPLL);
		break;
	case PLL_HPLL:
		rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru,
					     HPLL);
		break;
	case PLL_DPLL:
		rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru,
					     DPLL);
		break;
	case HCLK_PDCORE_NIU:
		rate = rv1126_pdcore_get_clk(priv);
		break;
	case ACLK_PDBUS:
	case HCLK_PDBUS:
	case PCLK_PDBUS:
	case PCLK_WDT:
		rate = rv1126_pdbus_get_clk(priv, clk->id);
		break;
	case ACLK_PDPHP:
	case HCLK_PDPHP:
		rate = rv1126_pdphp_get_clk(priv, clk->id);
		break;
	case HCLK_PDAUDIO:
		rate = rv1126_pdaudio_get_clk(priv);
		break;
	case CLK_I2C1:
	case CLK_I2C3:
	case CLK_I2C4:
	case CLK_I2C5:
		rate = rv1126_i2c_get_clk(priv, clk->id);
		break;
	case CLK_SPI1:
		rate = rv1126_spi_get_clk(priv);
		break;
	case CLK_PWM2:
		rate = rv1126_pwm_get_clk(priv);
		break;
	case CLK_SARADC:
		rate = rv1126_saradc_get_clk(priv);
		break;
	case CLK_CRYPTO_CORE:
	case CLK_CRYPTO_PKA:
	case ACLK_CRYPTO:
		rate = rv1126_crypto_get_clk(priv, clk->id);
		break;
	case CLK_SDMMC:
	case HCLK_SDMMC:
	case CLK_SDIO:
	case HCLK_SDIO:
	case CLK_EMMC:
	case HCLK_EMMC:
	case SCLK_EMMC_SAMPLE:
		rate = rv1126_mmc_get_clk(priv, clk->id);
		break;
	case SCLK_SFC:
		rate = rv1126_sfc_get_clk(priv);
		break;
	case CLK_NANDC:
		rate = rv1126_nand_get_clk(priv);
		break;
	case ACLK_PDVO:
	case ACLK_VOP:
		rate = rv1126_aclk_vop_get_clk(priv);
		break;
	case DCLK_VOP:
		rate = rv1126_dclk_vop_get_clk(priv);
		break;
	case CLK_SCR1_CORE:
		rate = rv1126_scr1_get_clk(priv);
		break;
	case CLK_GMAC_SRC:
		rate = rv1126_gmac_src_get_clk(priv);
		break;
	case CLK_GMAC_ETHERNET_OUT:
		rate = rv1126_gmac_out_get_clk(priv);
		break;
	case PCLK_GMAC:
		rate = rv1126_pclk_gmac_get_clk(priv);
		break;
	case DCLK_DECOM:
		rate = rv1126_dclk_decom_get_clk(priv);
		break;
	default:
		debug("%s: Unsupported CLK#%ld\n", __func__, clk->id);
		return -ENOENT;
	}

	return rate;
};

static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rv1126_clk_priv *priv = dev_get_priv(clk->dev);
	ulong ret = 0;

	if (!priv->gpll_hz) {
		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
		return -ENOENT;
	}

	switch (clk->id) {
	case PLL_APLL:
	case ARMCLK:
		if (priv->armclk_hz)
			rv1126_armclk_set_clk(priv, rate);
		priv->armclk_hz = rate;
		break;
	case PLL_CPLL:
		ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru,
					    CPLL, rate);
		break;
	case PLL_HPLL:
		ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru,
					    HPLL, rate);
		break;
	case ACLK_PDBUS:
	case HCLK_PDBUS:
	case PCLK_PDBUS:
	case PCLK_WDT:
		ret = rv1126_pdbus_set_clk(priv, clk->id, rate);
		break;
	case ACLK_PDPHP:
	case HCLK_PDPHP:
		ret = rv1126_pdphp_set_clk(priv, clk->id, rate);
		break;
	case HCLK_PDCORE_NIU:
		ret = rv1126_pdcore_set_clk(priv, rate);
		break;
	case HCLK_PDAUDIO:
		ret = rv1126_pdaudio_set_clk(priv, rate);
		break;
	case CLK_I2C1:
	case CLK_I2C3:
	case CLK_I2C4:
	case CLK_I2C5:
		ret = rv1126_i2c_set_clk(priv, clk->id, rate);
		break;
	case CLK_SPI1:
		ret = rv1126_spi_set_clk(priv, rate);
		break;
	case CLK_PWM2:
		ret = rv1126_pwm_set_clk(priv, rate);
		break;
	case CLK_SARADC:
		ret = rv1126_saradc_set_clk(priv, rate);
		break;
	case CLK_CRYPTO_CORE:
	case CLK_CRYPTO_PKA:
	case ACLK_CRYPTO:
		ret = rv1126_crypto_set_clk(priv, clk->id, rate);
		break;
	case CLK_SDMMC:
	case HCLK_SDMMC:
	case CLK_SDIO:
	case HCLK_SDIO:
	case CLK_EMMC:
	case HCLK_EMMC:
		ret = rv1126_mmc_set_clk(priv, clk->id, rate);
		break;
	case SCLK_SFC:
		ret = rv1126_sfc_set_clk(priv, rate);
		break;
	case CLK_NANDC:
		ret = rv1126_nand_set_clk(priv, rate);
		break;
	case ACLK_PDVO:
	case ACLK_VOP:
		ret = rv1126_aclk_vop_set_clk(priv, rate);
		break;
	case DCLK_VOP:
		ret = rv1126_dclk_vop_set_clk(priv, rate);
		break;
	case CLK_SCR1_CORE:
		ret = rv1126_scr1_set_clk(priv, rate);
		break;
	case CLK_GMAC_SRC:
		ret = rv1126_gmac_src_set_clk(priv, rate);
		break;
	case CLK_GMAC_ETHERNET_OUT:
		ret = rv1126_gmac_out_set_clk(priv, rate);
		break;
	case CLK_GMAC_TX_RX:
		ret = rv1126_gmac_tx_rx_set_clk(priv, rate);
		break;
	case DCLK_DECOM:
		ret = rv1126_dclk_decom_set_clk(priv, rate);
		break;
	default:
		debug("%s: Unsupported CLK#%ld\n", __func__, clk->id);
		return -ENOENT;
	}

	return ret;
};

#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int rv1126_gmac_src_set_parent(struct clk *clk, struct clk *parent)
{
	struct rv1126_clk_priv *priv = dev_get_priv(clk->dev);
	struct rv1126_grf *grf = priv->grf;

	if (parent->id == CLK_GMAC_SRC_M0)
		rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK,
			     GMAC_SRC_SEL_M0 << GMAC_SRC_SEL_SHIFT);
	else if (parent->id == CLK_GMAC_SRC_M1)
		rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK,
			     GMAC_SRC_SEL_M1 << GMAC_SRC_SEL_SHIFT);

	return 0;
}

static int rv1126_gmac_src_m0_set_parent(struct clk *clk, struct clk *parent)
{
	struct rv1126_clk_priv *priv = dev_get_priv(clk->dev);
	struct rv1126_cru *cru = priv->cru;

	if (parent->id == CLK_GMAC_DIV)
		rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK,
			     GMAC_SRC_M0_SEL_INT << GMAC_SRC_M0_SEL_SHIFT);
	else
		rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK,
			     GMAC_SRC_M0_SEL_EXT << GMAC_SRC_M0_SEL_SHIFT);

	return 0;
}

static int rv1126_gmac_src_m1_set_parent(struct clk *clk, struct clk *parent)
{
	struct rv1126_clk_priv *priv = dev_get_priv(clk->dev);
	struct rv1126_cru *cru = priv->cru;

	if (parent->id == CLK_GMAC_DIV)
		rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK,
			     GMAC_SRC_M1_SEL_INT << GMAC_SRC_M1_SEL_SHIFT);
	else
		rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK,
			     GMAC_SRC_M1_SEL_EXT << GMAC_SRC_M1_SEL_SHIFT);

	return 0;
}

static int rv1126_gmac_tx_rx_set_parent(struct clk *clk, struct clk *parent)
{
	struct rv1126_clk_priv *priv = dev_get_priv(clk->dev);
	struct rv1126_cru *cru = priv->cru;

	if (parent->id == RGMII_MODE_CLK)
		rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK,
			     GMAC_RGMII_MODE << GMAC_MODE_SEL_SHIFT);
	else
		rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK,
			     GMAC_RMII_MODE << GMAC_MODE_SEL_SHIFT);

	return 0;
}

static int rv1126_clk_set_parent(struct clk *clk, struct clk *parent)
{
	switch (clk->id) {
	case CLK_GMAC_SRC:
		return rv1126_gmac_src_set_parent(clk, parent);
	case CLK_GMAC_SRC_M0:
		return rv1126_gmac_src_m0_set_parent(clk, parent);
	case CLK_GMAC_SRC_M1:
		return rv1126_gmac_src_m1_set_parent(clk, parent);
	case CLK_GMAC_TX_RX:
		return rv1126_gmac_tx_rx_set_parent(clk, parent);
	default:
		return -ENOENT;
	}

	return 0;
}
#endif

static struct clk_ops rv1126_clk_ops = {
	.get_rate = rv1126_clk_get_rate,
	.set_rate = rv1126_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
	.set_parent = rv1126_clk_set_parent,
#endif
};

static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,
				  struct rv1126_pmuclk_priv *pmu_priv,
				  ulong rate)
{
	ulong emmc_rate, sfc_rate, nandc_rate;
	bool restore = false;

	if (priv->gpll_hz != OSC_HZ) {
		emmc_rate = rv1126_mmc_get_clk(priv, CLK_EMMC);
		sfc_rate = rv1126_sfc_get_clk(priv);
		nandc_rate = rv1126_nand_get_clk(priv);
		debug("%s emmc=%lu, sfc=%lu, nandc=%lu\n", __func__,
		      emmc_rate, sfc_rate, nandc_rate);
		restore = true;
	}

	/*
	 * the child div is big enough for gpll 1188MHz,
	 * even maskrom has change some clocks.
	 */
	if (rockchip_pll_set_rate(&rv1126_pll_clks[GPLL],
				  pmu_priv->pmucru, GPLL, rate))
		return -EINVAL;
	pmu_priv->gpll_hz = rate;
	priv->gpll_hz = rate;

	if (restore) {
		rv1126_mmc_set_clk(priv, CLK_EMMC, emmc_rate);
		rv1126_sfc_set_clk(priv,  sfc_rate);
		rv1126_nand_set_clk(priv, nandc_rate);
	}

	return 0;
}

static int rv1126_gpll_set_clk(struct rv1126_clk_priv *priv, ulong rate)
{
	struct udevice *pmucru_dev;
	struct rv1126_pmuclk_priv *pmu_priv;
	int ret;

	ret = uclass_get_device_by_driver(UCLASS_CLK,
					  DM_DRIVER_GET(rockchip_rv1126_pmucru),
					  &pmucru_dev);
	if (ret) {
		printf("%s: could not find pmucru device\n", __func__);
		return ret;
	}
	pmu_priv = dev_get_priv(pmucru_dev);
	priv->gpll_hz = pmu_priv->gpll_hz;

	if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) {
		printf("%s: failed to set gpll rate %lu\n", __func__, rate);
		return -EINVAL;
	}

	rv1126_pdpmu_set_pmuclk(pmu_priv, PCLK_PDPMU_HZ);
	rv1126_rtc32k_set_pmuclk(pmu_priv, CLK_OSC0_DIV_HZ);

	return 0;
}

static void rv1126_clk_init(struct rv1126_clk_priv *priv)
{
	int ret;

	priv->sync_kernel = false;
	if (!priv->armclk_enter_hz) {
		priv->armclk_enter_hz =
			rockchip_pll_get_rate(&rv1126_pll_clks[APLL],
					      priv->cru, APLL);
		priv->armclk_init_hz = priv->armclk_enter_hz;
	}

	if (priv->armclk_init_hz != APLL_HZ) {
		ret = rv1126_armclk_set_clk(priv, APLL_HZ);
		if (!ret)
			priv->armclk_init_hz = APLL_HZ;
	}
	if (priv->cpll_hz != CPLL_HZ) {
		ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru,
					    CPLL, CPLL_HZ);
		if (!ret)
			priv->cpll_hz = CPLL_HZ;
	}
	if (priv->hpll_hz != HPLL_HZ) {
		ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru,
					    HPLL, HPLL_HZ);
		if (!ret)
			priv->hpll_hz = HPLL_HZ;
	}
	if (priv->gpll_hz != GPLL_HZ)
		rv1126_gpll_set_clk(priv, GPLL_HZ);

	rv1126_pdbus_set_clk(priv, ACLK_PDBUS, ACLK_PDBUS_HZ);
	rv1126_pdbus_set_clk(priv, HCLK_PDBUS, HCLK_PDBUS_HZ);
	rv1126_pdbus_set_clk(priv, PCLK_PDBUS, PCLK_PDBUS_HZ);
	rv1126_pdphp_set_clk(priv, ACLK_PDPHP, ACLK_PDPHP_HZ);
	rv1126_pdphp_set_clk(priv, HCLK_PDPHP, HCLK_PDPHP_HZ);
	rv1126_pdcore_set_clk(priv, HCLK_PDCORE_HZ);
	rv1126_pdaudio_set_clk(priv, HCLK_PDAUDIO_HZ);
}

static int rv1126_clk_probe(struct udevice *dev)
{
	struct rv1126_clk_priv *priv = dev_get_priv(dev);
	int ret;

	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	if (IS_ERR(priv->grf))
		return PTR_ERR(priv->grf);

	rv1126_clk_init(priv);

	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
	ret = clk_set_defaults(dev, 1);
	if (ret)
		debug("%s clk_set_defaults failed %d\n", __func__, ret);
	else
		priv->sync_kernel = true;

	return 0;
}

static int rv1126_clk_of_to_plat(struct udevice *dev)
{
	struct rv1126_clk_priv *priv = dev_get_priv(dev);

	priv->cru = dev_read_addr_ptr(dev);

	return 0;
}

static int rv1126_clk_bind(struct udevice *dev)
{
	int ret;
	struct udevice *sys_child;
	struct sysreset_reg *priv;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
				 &sys_child);
	if (ret) {
		debug("Warning: No sysreset driver: ret=%d\n", ret);
	} else {
		priv = malloc(sizeof(struct sysreset_reg));
		priv->glb_srst_fst_value = offsetof(struct rv1126_cru,
						    glb_srst_fst);
		priv->glb_srst_snd_value = offsetof(struct rv1126_cru,
						    glb_srst_snd);
		dev_set_priv(sys_child, priv);
	}

#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
	ret = offsetof(struct rv1126_cru, softrst_con[0]);
	ret = rockchip_reset_bind(dev, ret, 15);
	if (ret)
		debug("Warning: software reset driver bind failed\n");
#endif
	return 0;
}

static const struct udevice_id rv1126_clk_ids[] = {
	{ .compatible = "rockchip,rv1126-cru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rv1126_cru) = {
	.name		= "rockchip_rv1126_cru",
	.id		= UCLASS_CLK,
	.of_match	= rv1126_clk_ids,
	.priv_auto	= sizeof(struct rv1126_clk_priv),
	.of_to_plat	= rv1126_clk_of_to_plat,
	.ops		= &rv1126_clk_ops,
	.bind		= rv1126_clk_bind,
	.probe		= rv1126_clk_probe,
};