1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
|
/*
* NXP GPMI NAND flash driver (DT initialization)
*
* Copyright (C) 2018 Toradex
* Copyright 2019 NXP
*
* Authors:
* Stefan Agner <stefan.agner@toradex.com>
*
* Based on denali_dt.c
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dm.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/printk.h>
#include <clk.h>
#include <mxs_nand.h>
struct mxs_nand_dt_data {
unsigned int max_ecc_strength_supported;
int max_chain_delay; /* See the async EDO mode */
};
static const struct mxs_nand_dt_data mxs_nand_imx6q_data = {
.max_ecc_strength_supported = 40,
.max_chain_delay = 12000,
};
static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = {
.max_ecc_strength_supported = 62,
.max_chain_delay = 12000,
};
static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
.max_ecc_strength_supported = 62,
.max_chain_delay = 12000,
};
static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = {
.max_ecc_strength_supported = 62,
.max_chain_delay = 12000,
};
static const struct udevice_id mxs_nand_dt_ids[] = {
{
.compatible = "fsl,imx6q-gpmi-nand",
.data = (unsigned long)&mxs_nand_imx6q_data,
},
{
.compatible = "fsl,imx6qp-gpmi-nand",
.data = (unsigned long)&mxs_nand_imx6q_data,
},
{
.compatible = "fsl,imx6sx-gpmi-nand",
.data = (unsigned long)&mxs_nand_imx6sx_data,
},
{
.compatible = "fsl,imx7d-gpmi-nand",
.data = (unsigned long)&mxs_nand_imx7d_data,
},
{
.compatible = "fsl,imx8qxp-gpmi-nand",
.data = (unsigned long)&mxs_nand_imx8qxp_data,
},
{ /* sentinel */ }
};
static int mxs_nand_dt_probe(struct udevice *dev)
{
struct mxs_nand_info *info = dev_get_priv(dev);
const struct mxs_nand_dt_data *data;
struct resource res;
int ret;
data = (void *)dev_get_driver_data(dev);
if (data) {
info->max_ecc_strength_supported = data->max_ecc_strength_supported;
info->max_chain_delay = data->max_chain_delay;
}
info->dev = dev;
ret = dev_read_resource_byname(dev, "gpmi-nand", &res);
if (ret)
return ret;
info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));
ret = dev_read_resource_byname(dev, "bch", &res);
if (ret)
return ret;
info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res));
info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
if (IS_ENABLED(CONFIG_CLK) &&
(IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) {
/* Assigned clock already set clock */
struct clk gpmi_clk;
info->gpmi_clk = devm_clk_get(dev, "gpmi_io");
if (IS_ERR(info->gpmi_clk)) {
ret = PTR_ERR(info->gpmi_clk);
debug("Can't get gpmi io clk: %d\n", ret);
return ret;
}
ret = clk_enable(info->gpmi_clk);
if (ret < 0) {
debug("Can't enable gpmi io clk: %d\n", ret);
return ret;
}
if (IS_ENABLED(CONFIG_IMX8)) {
ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk);
if (ret < 0) {
debug("Can't get gpmi_apb clk: %d\n", ret);
return ret;
}
ret = clk_enable(&gpmi_clk);
if (ret < 0) {
debug("Can't enable gpmi_apb clk: %d\n", ret);
return ret;
}
ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk);
if (ret < 0) {
debug("Can't get gpmi_bch clk: %d\n", ret);
return ret;
}
ret = clk_enable(&gpmi_clk);
if (ret < 0) {
debug("Can't enable gpmi_bch clk: %d\n", ret);
return ret;
}
}
ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk);
if (ret < 0) {
debug("Can't get gpmi_bch_apb clk: %d\n", ret);
return ret;
}
ret = clk_enable(&gpmi_clk);
if (ret < 0) {
debug("Can't enable gpmi_bch_apb clk: %d\n", ret);
return ret;
}
}
return mxs_nand_init_ctrl(info);
}
U_BOOT_DRIVER(mxs_nand_dt) = {
.name = "mxs-nand-dt",
.id = UCLASS_MTD,
.of_match = mxs_nand_dt_ids,
.probe = mxs_nand_dt_probe,
.priv_auto = sizeof(struct mxs_nand_info),
};
void board_nand_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MTD,
DM_DRIVER_GET(mxs_nand_dt),
&dev);
if (ret && ret != -ENODEV)
pr_err("Failed to initialize MXS NAND controller. (error %d)\n",
ret);
}
|