1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
|
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2016 Nexell Co., Ltd.
*
* Author: junghyun, kim <jhkim@nexell.co.kr>
*/
#ifndef _S5PXX18_SOC_DISPTOP_H_
#define _S5PXX18_SOC_DISPTOP_H_
#include "s5pxx18_soc_disptype.h"
#define NUMBER_OF_DISPTOP_MODULE 1
#define PHY_BASEADDR_DISPLAYTOP_MODULE 0xC0100000
#define PHY_BASEADDR_DISPTOP_LIST \
{ PHY_BASEADDR_DISPLAYTOP_MODULE }
#define HDMI_ADDR_OFFSET \
(((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x100000 \
: 0x000000)
#define OTHER_ADDR_OFFSET \
(((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x000000 \
: 0x100000)
#define PHY_BASEADDR_DISPLAYTOP_MODULE_OFFSET (OTHER_ADDR_OFFSET + 0x001000)
#define PHY_BASEADDR_DUALDISPLAY_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x002000)
#define PHY_BASEADDR_RESCONV_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x003000)
#define PHY_BASEADDR_LCDINTERFACE_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x004000)
#define PHY_BASEADDR_HDMI_MODULE (PHY_BASEADDR_DISPLAYTOP_MODULE + 0x000000)
#define PHY_BASEADDR_LVDS_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x00a000)
#define NUMBER_OF_DUALDISPLAY_MODULE 1
#define INTNUM_OF_DUALDISPLAY_MODULE_PRIMIRQ \
INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_PRIMIRQ
#define INTNUM_OF_DUALDISPLAY_MODULE_SECONDIRQ \
INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_SECONDIRQ
#define RESETINDEX_OF_DUALDISPLAY_MODULE_I_NRST \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_DUALDISPLAY_NRST
#define PADINDEX_OF_DUALDISPLAY_O_NCS \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
#define PADINDEX_OF_DUALDISPLAY_O_NRD \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
#define PADINDEX_OF_DUALDISPLAY_O_RS \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
#define PADINDEX_OF_DUALDISPLAY_O_NWR \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
#define PADINDEX_OF_DUALDISPLAY_PADPRIMVCLK \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_HSYNC \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_VSYNC \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADDE \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
#define PADINDEX_OF_DUALDISPLAY_PRIM_0_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_
#define PADINDEX_OF_DUALDISPLAY_PRIM_1_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_
#define PADINDEX_OF_DUALDISPLAY_PRIM_2_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_
#define PADINDEX_OF_DUALDISPLAY_PRIM_3_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_
#define PADINDEX_OF_DUALDISPLAY_PRIM_4_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_
#define PADINDEX_OF_DUALDISPLAY_PRIM_5_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_
#define PADINDEX_OF_DUALDISPLAY_PRIM_6_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_
#define PADINDEX_OF_DUALDISPLAY_PRIM_7_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_
#define PADINDEX_OF_DUALDISPLAY_PRIM_8_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_
#define PADINDEX_OF_DUALDISPLAY_PRIM_9_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_
#define PADINDEX_OF_DUALDISPLAY_PRIM_10_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_
#define PADINDEX_OF_DUALDISPLAY_PRIM_11_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_
#define PADINDEX_OF_DUALDISPLAY_PRIM_12_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_
#define PADINDEX_OF_DUALDISPLAY_PRIM_13_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_
#define PADINDEX_OF_DUALDISPLAY_PRIM_14_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_
#define PADINDEX_OF_DUALDISPLAY_PRIM_15_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_
#define PADINDEX_OF_DUALDISPLAY_PRIM_16_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_
#define PADINDEX_OF_DUALDISPLAY_PRIM_17_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_
#define PADINDEX_OF_DUALDISPLAY_PRIM_18_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_
#define PADINDEX_OF_DUALDISPLAY_PRIM_19_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_
#define PADINDEX_OF_DUALDISPLAY_PRIM_20_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_
#define PADINDEX_OF_DUALDISPLAY_PRIM_21_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_
#define PADINDEX_OF_DUALDISPLAY_PRIM_22_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_
#define PADINDEX_OF_DUALDISPLAY_PRIM_23_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_
#define PADINDEX_OF_DUALDISPLAY_PADSECONDVCLK \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_HSYNC \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_VSYNC \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADDE \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
#define PADINDEX_OF_DUALDISPLAY_SECOND_0_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_
#define PADINDEX_OF_DUALDISPLAY_SECOND_1_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_
#define PADINDEX_OF_DUALDISPLAY_SECOND_2_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_
#define PADINDEX_OF_DUALDISPLAY_SECOND_3_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_
#define PADINDEX_OF_DUALDISPLAY_SECOND_4_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_
#define PADINDEX_OF_DUALDISPLAY_SECOND_5_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_
#define PADINDEX_OF_DUALDISPLAY_SECOND_6_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_
#define PADINDEX_OF_DUALDISPLAY_SECOND_7_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_
#define PADINDEX_OF_DUALDISPLAY_SECOND_8_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_
#define PADINDEX_OF_DUALDISPLAY_SECOND_9_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_
#define PADINDEX_OF_DUALDISPLAY_SECOND_10_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_
#define PADINDEX_OF_DUALDISPLAY_SECOND_11_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_
#define PADINDEX_OF_DUALDISPLAY_SECOND_12_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_
#define PADINDEX_OF_DUALDISPLAY_SECOND_13_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_
#define PADINDEX_OF_DUALDISPLAY_SECOND_14_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_
#define PADINDEX_OF_DUALDISPLAY_SECOND_15_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_
#define PADINDEX_OF_DUALDISPLAY_SECOND_16_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_
#define PADINDEX_OF_DUALDISPLAY_SECOND_17_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_
#define PADINDEX_OF_DUALDISPLAY_SECOND_18_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_
#define PADINDEX_OF_DUALDISPLAY_SECOND_19_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_
#define PADINDEX_OF_DUALDISPLAY_SECOND_20_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_
#define PADINDEX_OF_DUALDISPLAY_SECOND_21_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_
#define PADINDEX_OF_DUALDISPLAY_SECOND_22_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_
#define PADINDEX_OF_DUALDISPLAY_SECOND_23_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_
#define NUMBER_OF_RESCONV_MODULE 1
#define INTNUM_OF_RESCONV_MODULE INTNUM_OF_DISPLAYTOP_MODULE_RESCONV_IRQ
#define RESETINDEX_OF_RESCONV_MODULE_I_NRST \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_RESCONV_NRST
#define RESETINDEX_OF_RESCONV_MODULE RESETINDEX_OF_RESCONV_MODULE_I_NRST
#define NUMBER_OF_LCDINTERFACE_MODULE 1
#define RESETINDEX_OF_LCDINTERFACE_MODULE_I_NRST \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_LCDIF_NRST
#define PADINDEX_OF_LCDINTERFACE_O_VCLK \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK
#define PADINDEX_OF_LCDINTERFACE_O_NHSYNC \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC
#define PADINDEX_OF_LCDINTERFACE_O_NVSYNC \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC
#define PADINDEX_OF_LCDINTERFACE_O_DE \
PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE
#define PADINDEX_OF_LCDINTERFACE_RGB24_0_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_
#define PADINDEX_OF_LCDINTERFACE_RGB24_1_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_
#define PADINDEX_OF_LCDINTERFACE_RGB24_2_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_
#define PADINDEX_OF_LCDINTERFACE_RGB24_3_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_
#define PADINDEX_OF_LCDINTERFACE_RGB24_4_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_
#define PADINDEX_OF_LCDINTERFACE_RGB24_5_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_
#define PADINDEX_OF_LCDINTERFACE_RGB24_6_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_
#define PADINDEX_OF_LCDINTERFACE_RGB24_7_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_
#define PADINDEX_OF_LCDINTERFACE_RGB24_8_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_
#define PADINDEX_OF_LCDINTERFACE_RGB24_9_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_
#define PADINDEX_OF_LCDINTERFACE_RGB24_10_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_
#define PADINDEX_OF_LCDINTERFACE_RGB24_11_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_
#define PADINDEX_OF_LCDINTERFACE_RGB24_12_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_
#define PADINDEX_OF_LCDINTERFACE_RGB24_13_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_
#define PADINDEX_OF_LCDINTERFACE_RGB24_14_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_
#define PADINDEX_OF_LCDINTERFACE_RGB24_15_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_
#define PADINDEX_OF_LCDINTERFACE_RGB24_16_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_
#define PADINDEX_OF_LCDINTERFACE_RGB24_17_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_
#define PADINDEX_OF_LCDINTERFACE_RGB24_18_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_
#define PADINDEX_OF_LCDINTERFACE_RGB24_19_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_
#define PADINDEX_OF_LCDINTERFACE_RGB24_20_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_
#define PADINDEX_OF_LCDINTERFACE_RGB24_21_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_
#define PADINDEX_OF_LCDINTERFACE_RGB24_22_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_
#define PADINDEX_OF_LCDINTERFACE_RGB24_23_ \
PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_
#define NUMBER_OF_HDMI_MODULE 1
#define INTNUM_OF_HDMI_MODULE INTNUM_OF_DISPLAYTOP_MODULE_HDMI_IRQ
#define RESETINDEX_OF_HDMI_MODULE_I_NRST \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_NRST
#define RESETINDEX_OF_HDMI_MODULE_I_NRST_VIDEO \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_VIDEO_NRST
#define RESETINDEX_OF_HDMI_MODULE_I_NRST_SPDIF \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_SPDIF_NRST
#define RESETINDEX_OF_HDMI_MODULE_I_NRST_TMDS \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_TMDS_NRST
#define RESETINDEX_OF_HDMI_MODULE_I_NRST_PHY \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_PHY_NRST
#define PADINDEX_OF_HDMI_I_PHY_CLKI PADINDEX_OF_DISPLAYTOP_I_HDMI_CLKI
#define PADINDEX_OF_HDMI_O_PHY_CLKO PADINDEX_OF_DISPLAYTOP_O_HDMI_CLKO
#define PADINDEX_OF_HDMI_IO_PHY_REXT PADINDEX_OF_DISPLAYTOP_IO_HDMI_REXT
#define PADINDEX_OF_HDMI_O_PHY_TX0P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0P
#define PADINDEX_OF_HDMI_O_PHY_TX0N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0N
#define PADINDEX_OF_HDMI_O_PHY_TX1P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1P
#define PADINDEX_OF_HDMI_O_PHY_TX1N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1N
#define PADINDEX_OF_HDMI_O_PHY_TX2P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2P
#define PADINDEX_OF_HDMI_O_PHY_TX2N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2N
#define PADINDEX_OF_HDMI_O_PHY_TXCP PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCP
#define PADINDEX_OF_HDMI_O_PHY_TXCN PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCN
#define PADINDEX_OF_HDMI_I_HOTPLUG PADINDEX_OF_DISPLAYTOP_I_HDMI_HOTPLUG_5V
#define PADINDEX_OF_HDMI_IO_PAD_CEC PADINDEX_OF_DISPLAYTOP_IO_HDMI_CEC
#define NUMBER_OF_LVDS_MODULE 1
#define RESETINDEX_OF_LVDS_MODULE_I_RESETN \
RESETINDEX_OF_DISPLAYTOP_MODULE_I_LVDS_NRST
#define RESETINDEX_OF_LVDS_MODULE RESETINDEX_OF_LVDS_MODULE_I_RESETN
#define PADINDEX_OF_LVDS_TAP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_A
#define PADINDEX_OF_LVDS_TAN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_A
#define PADINDEX_OF_LVDS_TBP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_B
#define PADINDEX_OF_LVDS_TBN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_B
#define PADINDEX_OF_LVDS_TCP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_C
#define PADINDEX_OF_LVDS_TCN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_C
#define PADINDEX_OF_LVDS_TDP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_D
#define PADINDEX_OF_LVDS_TDN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_D
#define PADINDEX_OF_LVDS_TCLKP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_CLK
#define PADINDEX_OF_LVDS_TCLKN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_CLK
#define PADINDEX_OF_LVDS_ROUT PADINDEX_OF_DISPLAYTOP_LVDS_ROUT
#define PADINDEX_OF_LVDS_TEP PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E
#define PADINDEX_OF_LVDS_TEN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E
#define NUMBER_OF_DISPTOP_CLKGEN_MODULE 5
enum disptop_clkgen_module_index {
res_conv_clkgen = 0,
lcdif_clkgen = 1,
to_mipi_clkgen = 2,
to_lvds_clkgen = 3,
hdmi_clkgen = 4,
};
enum disptop_res_conv_iclk_cclk {
res_conv_iclk = 0,
res_conv_cclk = 1,
};
enum disptop_res_conv_oclk {
res_conv_oclk = 1,
};
enum disptop_lcdif_clk {
lcdif_pixel_clkx_n = 0,
lcdif_pixel_clk = 1,
};
#define HDMI_SPDIF_CLKGEN 2
#define HDMI_SPDIF_CLKOUT 0
#define HDMI_I_VCLK_CLKOUT 0
#define PHY_BASEADDR_DISPTOP_CLKGEN0_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x006000)
#define PHY_BASEADDR_DISPTOP_CLKGEN1_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x007000)
#define PHY_BASEADDR_DISPTOP_CLKGEN2_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x005000)
#define PHY_BASEADDR_DISPTOP_CLKGEN3_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x008000)
#define PHY_BASEADDR_DISPTOP_CLKGEN4_MODULE \
(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x009000)
struct nx_disp_top_register_set {
u32 resconv_mux_ctrl;
u32 interconv_mux_ctrl;
u32 mipi_mux_ctrl;
u32 lvds_mux_ctrl;
u32 hdmifixctrl0;
u32 hdmisyncctrl0;
u32 hdmisyncctrl1;
u32 hdmisyncctrl2;
u32 hdmisyncctrl3;
u32 tftmpu_mux;
u32 hdmifieldctrl;
u32 greg0;
u32 greg1;
u32 greg2;
u32 greg3;
u32 greg4;
u32 greg5;
};
int nx_disp_top_initialize(void);
u32 nx_disp_top_get_number_of_module(void);
u32 nx_disp_top_get_physical_address(void);
u32 nx_disp_top_get_size_of_register_set(void);
void nx_disp_top_set_base_address(void *base_address);
void *nx_disp_top_get_base_address(void);
int nx_disp_top_open_module(void);
int nx_disp_top_close_module(void);
int nx_disp_top_check_busy(void);
enum mux_index {
primary_mlc = 0,
secondary_mlc = 1,
resolution_conv = 2,
};
enum prim_pad_mux_index {
padmux_primary_mlc = 0,
padmux_primary_mpu = 1,
padmux_secondary_mlc = 2,
padmux_resolution_conv = 3,
};
void nx_disp_top_set_resconvmux(int benb, u32 sel);
void nx_disp_top_set_hdmimux(int benb, u32 sel);
void nx_disp_top_set_mipimux(int benb, u32 sel);
void nx_disp_top_set_lvdsmux(int benb, u32 sel);
void nx_disp_top_set_primary_mux(u32 sel);
void nx_disp_top_hdmi_set_vsync_start(u32 sel);
void nx_disp_top_hdmi_set_vsync_hsstart_end(u32 start, u32 end);
void nx_disp_top_hdmi_set_hactive_start(u32 sel);
void nx_disp_top_hdmi_set_hactive_end(u32 sel);
void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,
u32 field_use, u32 muxsel);
enum padclk_config {
padclk_clk = 0,
padclk_inv_clk = 1,
padclk_reserved_clk = 2,
padclk_reserved_inv_clk = 3,
padclk_clk_div2_0 = 4,
padclk_clk_div2_90 = 5,
padclk_clk_div2_180 = 6,
padclk_clk_div2_270 = 7,
};
void nx_disp_top_set_padclock(u32 mux_index, u32 padclk_cfg);
void nx_disp_top_set_lcdif_enb(int enb);
void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,
u32 field_use, u32 muxsel);
#endif
|