~funderscore blog cgit wiki get in touch
aboutsummaryrefslogtreecommitdiff
blob: bf2bc2d45c09994409bd6fe52b236d38c76d978d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 *
 * Author: Weijie Gao <weijie.gao@mediatek.com>
 */

#ifndef __CONFIG_MT7621_H
#define __CONFIG_MT7621_H

#define CFG_SYS_SDRAM_BASE		0x80000000

#define CFG_MAX_MEM_MAPPED		0x1c000000

#define CFG_SYS_INIT_SP_OFFSET		0x800000

/* MMC */
#define MMC_SUPPORTS_TUNING

/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CFG_SYS_NS16550_CLK		50000000
#define CFG_SYS_NS16550_COM1		0xbe000c00
#endif

/* Serial common */
#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200, \
					  230400, 460800, 921600 }

/* Dummy value */
#define CFG_SYS_UBOOT_BASE		0

#endif /* __CONFIG_MT7621_H */