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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015-2019 Altera Corporation <www.altera.com>
*/
#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
#define __CONFIG_SOCFGPA_ARRIA10_H__
#include <asm/arch/base_addr_a10.h>
/*
* U-Boot general configurations
*/
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000
/*
* Serial / UART configurations
*/
#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
/*
* L4 OSC1 Timer 0
*/
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0xFFFFFFFF
/*
* Flash configurations
*/
/* SPL memory allocation configuration, this is for FAT implementation */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */
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