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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
#ifndef _DT_BINDINGS_MT7620_CLK_H_
#define _DT_BINDINGS_MT7620_CLK_H_
/* Base clocks */
#define CLK_SYS 34
#define CLK_CPU 33
#define CLK_XTAL 32
/* Peripheral clocks */
#define CLK_SDHC 30
#define CLK_MIPS_CNT 28
#define CLK_PCIE 26
#define CLK_UPHY_12M 25
#define CLK_EPHY 24
#define CLK_ESW 23
#define CLK_UPHY_48M 22
#define CLK_FE 21
#define CLK_UARTL 19
#define CLK_SPI 18
#define CLK_I2S 17
#define CLK_I2C 16
#define CLK_NAND 15
#define CLK_GDMA 14
#define CLK_PIO 13
#define CLK_UARTF 12
#define CLK_PCM 11
#define CLK_MC 10
#define CLK_INTC 9
#define CLK_TIMER 8
#define CLK_GE2 7
#define CLK_GE1 6
#endif /* _DT_BINDINGS_MT7620_CLK_H_ */
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