blob: 5b1bef38c77d9ae546c2e6007cdd2eb3e9282dc1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*/
/*
* Timer
*/
#ifndef __FTTMR010_H
#define __FTTMR010_H
struct fttmr010 {
unsigned int timer1_counter; /* 0x00 */
unsigned int timer1_load; /* 0x04 */
unsigned int timer1_match1; /* 0x08 */
unsigned int timer1_match2; /* 0x0c */
unsigned int timer2_counter; /* 0x10 */
unsigned int timer2_load; /* 0x14 */
unsigned int timer2_match1; /* 0x18 */
unsigned int timer2_match2; /* 0x1c */
unsigned int timer3_counter; /* 0x20 */
unsigned int timer3_load; /* 0x24 */
unsigned int timer3_match1; /* 0x28 */
unsigned int timer3_match2; /* 0x2c */
unsigned int cr; /* 0x30 */
unsigned int interrupt_state; /* 0x34 */
unsigned int interrupt_mask; /* 0x38 */
unsigned int revision; /* 0x3c */
};
/*
* Timer Control Register
*/
#define FTTMR010_TM3_UPDOWN (1 << 11)
#define FTTMR010_TM2_UPDOWN (1 << 10)
#define FTTMR010_TM1_UPDOWN (1 << 9)
#define FTTMR010_TM3_OFENABLE (1 << 8)
#define FTTMR010_TM3_CLOCK (1 << 7)
#define FTTMR010_TM3_ENABLE (1 << 6)
#define FTTMR010_TM2_OFENABLE (1 << 5)
#define FTTMR010_TM2_CLOCK (1 << 4)
#define FTTMR010_TM2_ENABLE (1 << 3)
#define FTTMR010_TM1_OFENABLE (1 << 2)
#define FTTMR010_TM1_CLOCK (1 << 1)
#define FTTMR010_TM1_ENABLE (1 << 0)
/*
* Timer Interrupt State & Mask Registers
*/
#define FTTMR010_TM3_OVERFLOW (1 << 8)
#define FTTMR010_TM3_MATCH2 (1 << 7)
#define FTTMR010_TM3_MATCH1 (1 << 6)
#define FTTMR010_TM2_OVERFLOW (1 << 5)
#define FTTMR010_TM2_MATCH2 (1 << 4)
#define FTTMR010_TM2_MATCH1 (1 << 3)
#define FTTMR010_TM1_OVERFLOW (1 << 2)
#define FTTMR010_TM1_MATCH2 (1 << 1)
#define FTTMR010_TM1_MATCH1 (1 << 0)
#endif /* __FTTMR010_H */
|