1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2020-2021 Texas Instruments Incorporated - http://www.ti.com
* Tero Kristo <t-kristo@ti.com>
*/
#ifndef __K3_CLK_H__
#define __K3_CLK_H__
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/types.h>
#include <stdint.h>
struct dev_clk {
int dev_id;
int clk_id;
const char *clk_name;
};
#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \
.clk_id = _clk_id, .clk_name = _clk_name, }
#define CLK_TYPE_MUX 0x01
#define CLK_TYPE_DIV 0x02
#define CLK_TYPE_PLL 0x03
#define CLK_TYPE_HFOSC 0x04
#define CLK_TYPE_POSTDIV 0x05
#define CLK_TYPE_MUX_PLLCTRL 0x06
#define CLK_TYPE_FIXED_RATE 0x07
struct pll_data {
u32 reg;
const char *name;
const char *parent;
u32 flags;
};
struct mux_data {
u32 reg;
const char *name;
const char * const *parents;
int num_parents;
u32 flags;
int shift;
int width;
};
struct div_data {
u32 reg;
const char *name;
const char *parent;
u32 flags;
int shift;
int width;
u32 div_flags;
};
struct hfosc_data {
const char *name;
u32 flags;
};
struct fixed_rate_data {
const char *name;
u64 rate;
u32 flags;
};
struct postdiv_data {
const char *name;
const char *parent;
int width;
u32 flags;
};
struct mux_pllctrl_data {
u32 reg;
const char *name;
const char * const *parents;
int num_parents;
u32 flags;
};
struct clk_data {
int type;
u32 default_freq;
union {
struct pll_data pll;
struct mux_data mux;
struct div_data div;
struct hfosc_data hfosc;
struct postdiv_data postdiv;
struct mux_pllctrl_data mux_pllctrl;
struct fixed_rate_data fixed_rate;
} clk;
};
#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \
{ \
.type = CLK_TYPE_MUX, \
.clk.mux = { .name = _name, .parents = _parents, \
.reg = _reg, \
.num_parents = _num_parents, .shift = _shift, \
.width = _width, .flags = _flags } \
}
#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags, _div_flags) \
{ \
.type = CLK_TYPE_DIV, \
.clk.div = { \
.name = _name, .parent = _parent, .reg = _reg, \
.shift = _shift, .width = _width, \
.flags = _flags, .div_flags = _div_flags } \
}
#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _div_flags, _freq) \
{ \
.type = CLK_TYPE_DIV, \
.default_freq = _freq, \
.clk.div = { \
.name = _name, .parent = _parent, .reg = _reg, \
.shift = _shift, .width = _width, \
.flags = _flags, .div_flags = _div_flags } \
}
#define CLK_PLL(_name, _parent, _reg, _flags) \
{ \
.type = CLK_TYPE_PLL, \
.clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \
}
#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \
{ \
.type = CLK_TYPE_PLL, \
.default_freq = _freq, \
.clk.pll = { .name = _name, .parent = _parent, \
.reg = _reg, .flags = _flags } \
}
#define CLK_HFOSC(_name, _flags) \
{ \
.type = CLK_TYPE_HFOSC, \
.clk.hfosc = { .name = _name, .flags = _flags } \
}
#define CLK_FIXED_RATE(_name, _rate, _flags) \
{ \
.type = CLK_TYPE_FIXED_RATE, \
.clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \
}
#define CLK_POSTDIV(_name, _parent, _width, _flags) \
{ \
.type = CLK_TYPE_POSTDIV, \
.clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \
}
#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags) \
{ \
.type = CLK_TYPE_MUX, \
.clk.mux_pllctrl = { .name = _name, .parents = _parents,\
.num_parents = _num_parents, .flags = _flags } \
}
struct ti_k3_clk_platdata {
const struct clk_data *clk_list;
int clk_list_cnt;
const struct dev_clk *soc_dev_clk_data;
int soc_dev_clk_data_cnt;
};
extern const struct ti_k3_clk_platdata j721e_clk_platdata;
extern const struct ti_k3_clk_platdata j7200_clk_platdata;
extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
extern const struct ti_k3_clk_platdata am62x_clk_platdata;
extern const struct ti_k3_clk_platdata am62ax_clk_platdata;
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
void __iomem *reg);
#endif /* __K3_CLK_H__ */
|