diff options
Diffstat (limited to 'plat/gxb/ddr')
| -rw-r--r-- | plat/gxb/ddr/ddr.c | 863 | ||||
| -rw-r--r-- | plat/gxb/ddr/ddr_detect.c | 96 | ||||
| -rw-r--r-- | plat/gxb/ddr/ddr_pctl_define.h | 282 | ||||
| -rw-r--r-- | plat/gxb/ddr/ddr_pub_define.h | 305 | ||||
| -rw-r--r-- | plat/gxb/ddr/dmc_define.h | 372 | ||||
| -rw-r--r-- | plat/gxb/ddr/mmc_define.h | 87 | ||||
| -rw-r--r-- | plat/gxb/ddr/sec_mmc_define.h | 712 |
7 files changed, 2717 insertions, 0 deletions
diff --git a/plat/gxb/ddr/ddr.c b/plat/gxb/ddr/ddr.c new file mode 100644 index 0000000..68438c6 --- /dev/null +++ b/plat/gxb/ddr/ddr.c @@ -0,0 +1,863 @@ + +/* + * arch/arm/cpu/armv8/common/firmware/plat/gxb/ddr/ddr.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <stdio.h> +#include "ddr_pctl_define.h" +#include "ddr_pub_define.h" +#include "dmc_define.h" +#include "mmc_define.h" +#include "sec_mmc_define.h" +#include <timer.h> +#include <asm/arch/ddr.h> +#include <asm/arch/secure_apb.h> +#include <pll.h> +#include <config.h> +#include <asm/arch/cpu.h> +#include <asm/arch/timing.h> +#include <memtest.h> +#include <asm/arch/watchdog.h> +#include <cache.h> +#include "timing.c" +#include "ddr_detect.c" + +static ddr_set_t * p_ddr_set = &__ddr_setting; +static ddr_timing_t * p_ddr_timing = NULL; +static unsigned int ddr0_enabled; +static unsigned int ddr1_enabled; + +unsigned int ddr_init(void){ + /*detect hot boot or cold boot*/ + //if(hot_boot()){ + // serial_puts("hot boot, skip ddr init!\n"); + // return 0; + //} + + ddr_init_pll(); + ddr_pre_init(); + ddr_init_pctl(); + ddr_init_dmc(); + ddr_print_info(); +#ifndef CONFIG_PXP_EMULATOR +//can not enable ddr test on pxp, for kernel and dtb already load in ddr +#ifdef CONFIG_SPL_DDR_DUMP + if (CONFIG_SPL_DDR_DUMP_FLAG != readl(P_PREG_STICKY_REG0)) { + ddr_test(); + } +#else + ddr_test(); +#endif +#endif + return 0; +} + +unsigned int ddr_init_pll(void){ + wr_reg(P_AM_ANALOG_TOP_REG1, rd_reg(P_AM_ANALOG_TOP_REG1) | (1<<0)); + wr_reg(P_HHI_MPLL_CNTL5, rd_reg(P_HHI_MPLL_CNTL5) | (1<<0)); + + /* DDR PLL BANDGAP */ + wr_reg(AM_DDR_PLL_CNTL4, rd_reg(AM_DDR_PLL_CNTL4) & (~(1<<12))); + wr_reg(AM_DDR_PLL_CNTL4, rd_reg(AM_DDR_PLL_CNTL4)|(1<<12)); + _udelay(10); + + /* set ddr pll reg */ + if ((p_ddr_set->ddr_clk >= CONFIG_DDR_CLK_LOW) && (p_ddr_set->ddr_clk < 750)) { + // OD N M + p_ddr_set->ddr_pll_ctrl = (2 << 16) | (1 << 9) | ((((p_ddr_set->ddr_clk/6)*6)/12) << 0); + } + else if((p_ddr_set->ddr_clk >= 750) && (p_ddr_set->ddr_clk < CONFIG_DDR_CLK_HIGH)) { + // OD N M + p_ddr_set->ddr_pll_ctrl = (1 << 16) | (1 << 9) | ((((p_ddr_set->ddr_clk/12)*12)/24) << 0); + } + + /* if enabled, change ddr pll setting */ +#ifdef CONFIG_CMD_DDR_TEST + serial_puts("STICKY_REG0: 0x"); + serial_put_hex(rd_reg(P_PREG_STICKY_REG0), 32); + serial_puts("\n"); + serial_puts("STICKY_REG1: 0x"); + serial_put_hex(rd_reg(P_PREG_STICKY_REG1), 32); + serial_puts("\n"); + if ((rd_reg(P_PREG_STICKY_REG0)>>20) == 0xf13) { + unsigned zqcr = rd_reg(P_PREG_STICKY_REG0) & 0xfffff; + if (0 == zqcr) + zqcr = p_ddr_set->t_pub_zq0pr; + serial_puts("ZQCR: 0x"); + serial_put_hex(p_ddr_set->t_pub_zq0pr, 32); + serial_puts(" -> 0x"); + serial_put_hex(zqcr, 32); + serial_puts("\n"); + p_ddr_set->t_pub_zq0pr = zqcr; + p_ddr_set->t_pub_zq1pr = zqcr; + p_ddr_set->t_pub_zq2pr = zqcr; + p_ddr_set->t_pub_zq3pr = zqcr; + serial_puts("PLL : 0x"); + serial_put_hex(p_ddr_set->ddr_pll_ctrl, 32); + serial_puts(" -> 0x"); + serial_put_hex(rd_reg(P_PREG_STICKY_REG1), 32); + serial_puts("\n"); + p_ddr_set->ddr_pll_ctrl = rd_reg(P_PREG_STICKY_REG1); + wr_reg(P_PREG_STICKY_REG0,0); + wr_reg(P_PREG_STICKY_REG1,0); + } +#endif + + /* ddr pll init */ + do { + //wr_reg(AM_DDR_PLL_CNTL1, 0x1); + wr_reg(AM_DDR_PLL_CNTL, (1<<29)); + wr_reg(AM_DDR_PLL_CNTL1, CFG_DDR_PLL_CNTL_1); + wr_reg(AM_DDR_PLL_CNTL2, CFG_DDR_PLL_CNTL_2); + wr_reg(AM_DDR_PLL_CNTL3, CFG_DDR_PLL_CNTL_3); + wr_reg(AM_DDR_PLL_CNTL4, CFG_DDR_PLL_CNTL_4); + wr_reg(AM_DDR_PLL_CNTL, ((1<<29) | (p_ddr_set->ddr_pll_ctrl))); + wr_reg(AM_DDR_PLL_CNTL, rd_reg(AM_DDR_PLL_CNTL)&(~(1<<29))); + _udelay(200); + }while(pll_lock_check(AM_DDR_PLL_CNTL, "DDR PLL")); + + /* Enable the DDR DLL clock input from PLL */ + wr_reg(DDR_CLK_CNTL, 0xb0000000); + wr_reg(DDR_CLK_CNTL, 0xb0000000); + + /* update ddr_clk */ + unsigned int ddr_pll = rd_reg(AM_DDR_PLL_CNTL)&(~(1<<29)); + unsigned int ddr_clk = 2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3)); + p_ddr_set->ddr_clk = ddr_clk; + + return 0; +} + +void ddr_print_info(void){ + if (p_ddr_set->ddr_size_detect) + ddr_size_detect(p_ddr_set); + + unsigned int dmc_reg = rd_reg(DMC_DDR_CTRL); + unsigned char ddr_2t_mode = 0; + unsigned char ddr_chl = DDR_USE_2_CHANNEL(p_ddr_set->ddr_channel_set); + + /* 0:1t, 1:2t, 2:f2t(force) */ + ddr_2t_mode = ((rd_reg(DDR0_PCTL_MCFG) >> 3) & 0x1); + if (p_ddr_set->ddr_channel_set == CONFIG_DDR01_SHARE_AC) + ddr_2t_mode = 2; + + for (int i=0; i<=ddr_chl; i++) { + /* ddr info */ + serial_puts("DDR"); + serial_put_dec(i); + serial_puts(": "); + serial_put_dec(1 << (((dmc_reg>>(3*i)) & 0x7)+7)); + serial_puts("MB"); + if (p_ddr_set->ddr_size_detect) + serial_puts("(auto)"); + serial_puts(" @ "); + serial_put_dec(p_ddr_set->ddr_clk); + serial_puts("MHz("); + serial_puts(((ddr_2t_mode==2)?"F1T":((ddr_2t_mode==1)?"2T":"1T"))); + serial_puts(")-"); + serial_put_dec(p_ddr_set->ddr_timing_ind); + serial_puts("\n"); + } + + /* write ddr size to reg */ + wr_reg(SEC_AO_SEC_GP_CFG0, ((rd_reg(SEC_AO_SEC_GP_CFG0) & 0x0000ffff) | ((p_ddr_set->ddr_size) << 16))); +} + +unsigned int ddr_init_dmc(void){ + unsigned int ddr0_size = 0, ddr1_size = 0; + unsigned int ddr0_size_reg = 0, ddr1_size_reg = 0; +// unsigned int i=0, j=0, convert_reg_size = 6; + + /* transfer correct dmc ctrl setting */ + unsigned int ddr_one_chl = DDR_USE_1_CHANNEL(p_ddr_set->ddr_channel_set); + ddr0_size = (p_ddr_set->ddr_size)>>(7-ddr_one_chl); + ddr1_size = ddr_one_chl?0x7:((p_ddr_set->ddr_size)>>7); + ddr1_size_reg=ddr_one_chl?0x5:0x0; + while (!((ddr0_size>>=1)&0x1)) + ddr0_size_reg++; + while (!((ddr1_size>>=1)&0x1)) + ddr1_size_reg++; + + p_ddr_set->ddr_dmc_ctrl &= (~0x3f); //clear ddr capacity reg bits + p_ddr_set->ddr_dmc_ctrl |= ((ddr0_size_reg)|(ddr1_size_reg<<3)); + + wr_reg(DMC_DDR_CTRL, p_ddr_set->ddr_dmc_ctrl); + if ((p_ddr_set->ddr_channel_set == CONFIG_DDR01_SHARE_AC)|| + (p_ddr_set->ddr_channel_set == CONFIG_DDR0_ONLY_16BIT))//jiaxing find use 16bit channel 0 only must write map0-4? + { + //CONIFG DDR PHY comamnd address map to 32bits linear address. + //DDR0 ROW 14:0. DDR1 ROW 13:0. COL 9:0. + wr_reg( DDR0_ADDRMAP_0, ( 0 | 5 << 5 | 6 << 10 | 7 << 15 | 8 << 20 | 9 << 25 )); + wr_reg( DDR0_ADDRMAP_1, ( 13| 30<< 5 | 0 << 10 | 10 << 15 | 11 << 20 | 12 << 25 )); + //wr_reg( DDR0_ADDRMAP_1, ( 0| 0 << 5 | 0 << 10 | 10 << 15 | 11 << 20 | 12 << 25 )); + wr_reg( DDR0_ADDRMAP_2, ( 16| 17 << 5 | 18 << 10 | 19 << 15 | 20 << 20 | 21 << 25 )); + wr_reg( DDR0_ADDRMAP_3, ( 22| 23 << 5 | 24 << 10 | 25 << 15 | 26 << 20 | 27 << 25 )); + wr_reg( DDR0_ADDRMAP_4, ( 29| 14 << 5 | 15 << 10 | 28 << 15 | 0 << 20 | 0 << 25 )); + + wr_reg( DDR1_ADDRMAP_0, ( 0 | 5 << 5 | 6 << 10 | 7 << 15 | 8 << 20 | 9 << 25 )); + wr_reg( DDR1_ADDRMAP_1, ( 13| 30<< 5 | 0 << 10 | 10 << 15 | 11 << 20 | 12 << 25 )); + //wr_reg( DDR1_ADDRMAP_1, ( 13| 0 << 5 | 0 << 10 | 10 << 15 | 11 << 20 | 12 << 25 )); + wr_reg( DDR1_ADDRMAP_2, ( 16| 17 << 5 | 18 << 10 | 19 << 15 | 20 << 20 | 21 << 25 )); + wr_reg( DDR1_ADDRMAP_3, ( 22| 23 << 5 | 24 << 10 | 25 << 15 | 26 << 20 | 27 << 25 )); + wr_reg( DDR1_ADDRMAP_4, ( 29| 14 << 5 | 15 << 10 | 28 << 15 | 0 << 20 | 0 << 25 )); + } + else if(p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK01_SAME){ + //wr_reg( DDR0_ADDRMAP_1, ( 11| 0 << 5 | 0 << 10 | 0 << 15 | 15 << 20 | 16 << 25 )); + wr_reg( DDR0_ADDRMAP_1, ( 11| 31 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 )); + wr_reg( DDR0_ADDRMAP_4, ( 30| 12 << 5 | 13 << 10 | 29 << 15 | 0 << 20 | 0 << 25 )); + } + else if(p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK01_DIFF){ + //wr_reg( DDR0_ADDRMAP_1, ( 11| 0 << 5 | 0 << 10 | 0 << 15 | 15 << 20 | 16 << 25 )); + wr_reg( DDR0_ADDRMAP_1, ( 11| 31 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 )); + wr_reg( DDR0_ADDRMAP_4, ( 0| 12 << 5 | 13 << 10 | 29 << 15 | 0 << 20 | 30 << 25 )); + } + + wr_reg(DMC_PCTL_LP_CTRL, 0x440620); + //wr_reg(DDR0_APD_CTRL, 0x45); + wr_reg(DDR0_APD_CTRL, (0x20<<8)|(0x20)); + wr_reg(DDR0_CLK_CTRL, 0x5); + + // disable AXI port0 (CPU) IRQ/FIQ security control. + wr_reg(DMC_AXI0_QOS_CTRL1, 0x11); + + //CONFIG DMC security register to enable the all reqeust can access all DDR region. + wr_reg(DMC_SEC_RANGE_CTRL, 0x0 ); + wr_reg(DMC_SEC_CTRL, 0x80000000 ); + wr_reg(DMC_SEC_AXI_PORT_CTRL, 0x55555555); + wr_reg(DMC_DEV_SEC_READ_CTRL, 0x55555555 ); + wr_reg(DMC_DEV_SEC_WRITE_CTRL, 0x55555555 ); + wr_reg(DMC_GE2D_SEC_CTRL, 0x15); + wr_reg(DMC_PARSER_SEC_CTRL, 0x5); + wr_reg(DMC_VPU_SEC_CFG, 0xffffffff); + wr_reg(DMC_VPU_SEC_WRITE_CTRL, 0x55555555 ); + wr_reg(DMC_VPU_SEC_READ_CTRL, 0x55555555 ); + wr_reg(DMC_VDEC_SEC_CFG, 0xffffffff); + wr_reg(DMC_VDEC_SEC_WRITE_CTRL, 0x55555555 ); + wr_reg(DMC_VDEC_SEC_READ_CTRL, 0x55555555 ); + wr_reg(DMC_HCODEC_SEC_CFG, 0xffffffff); + wr_reg(DMC_HCODEC_SEC_WRITE_CTRL, 0x55555555 ); + wr_reg(DMC_HCODEC_SEC_READ_CTRL, 0x55555555 ); + wr_reg(DMC_HEVC_SEC_CFG, 0xffffffff); + wr_reg(DMC_HEVC_SEC_WRITE_CTRL, 0x55555555 ); + wr_reg(DMC_HEVC_SEC_READ_CTRL, 0x55555555 ); + + //// ENABLE THE DC_REQS. + wr_reg(DMC_REQ_CTRL, 0xFFFF); + + // SCRATCH1 + wr_reg(0xC1107d40, 0xbaadf00d); + + // PUT SOME CODE HERE TO TRY TO STOP BUS TRAFFIC + __asm__ volatile("NOP"); + __asm__ volatile("DMB SY"); + __asm__ volatile("ISB"); + + // REMAP THE ADDRESS SPACE BY WRITING TO NIC400 REMAP REGISTER + //wr_reg(0xC1300000, 0x00000001); + //__asm__ volatile("ISB"); + //__asm__ volatile("DMB SY"); + + return 0; +} + +unsigned int ddr_init_pctl(void){ + ddr0_enabled = !(((p_ddr_set->ddr_dmc_ctrl) >> 7) & 0x1); //check if ddr1 only enabled + ddr1_enabled = !(((p_ddr_set->ddr_dmc_ctrl) >> 6) & 0x1); //check if ddr0 only enabled + + // RELEASE THE DDR DLL RESET PIN. + wr_reg(DMC_SOFT_RST, 0xFFFFFFFF); + wr_reg(DMC_SOFT_RST1, 0xFFFFFFFF); + + // ENABLE UPCTL AND PUB CLOCK AND RESET. + //@@@ enable UPCTL and PUB clock and reset. + wr_reg(DMC_PCTL_LP_CTRL, 0x550620); + wr_reg(DDR0_SOFT_RESET, 0xf); + + // INITIALIZATION PHY. + // FOR SIMULATION TO REDUCE THE INIT TIME. + //wr_reg(DDR0_PUB_PTR0, p_ddr_set->t_pub_ptr[0]); + //wr_reg(DDR0_PUB_PTR1, p_ddr_set->t_pub_ptr[1]); + //wr_reg(DDR0_PUB_PTR3, p_ddr_set->t_pub_ptr[3]); + //wr_reg(DDR0_PUB_PTR4, p_ddr_set->t_pub_ptr[4]); + + wr_reg(DDR0_PUB_IOVCR0, 0x49494949); + wr_reg(DDR0_PUB_IOVCR1, 0x49494949); + + // CONFIGURE DDR PHY PUBL REGISTERS. + wr_reg(DDR0_PUB_ODTCR, p_ddr_set->t_pub_odtcr); + + // PROGRAM PUB MRX REGISTERS. + wr_reg(DDR0_PUB_MR0, p_ddr_set->t_pub_mr[0]); + wr_reg(DDR0_PUB_MR1, p_ddr_set->t_pub_mr[1]); + wr_reg(DDR0_PUB_MR2, p_ddr_set->t_pub_mr[2]); + wr_reg(DDR0_PUB_MR3, p_ddr_set->t_pub_mr[3]); + + // PROGRAM DDR SDRAM TIMING PARAMETER. + wr_reg(DDR0_PUB_DTPR0, p_ddr_set->t_pub_dtpr[0]); + wr_reg(DDR0_PUB_DTPR1, p_ddr_set->t_pub_dtpr[1]); + //wr_reg(DDR0_PUB_PGCR0, p_ddr_set->t_pub_pgcr0); //Jiaxing debug low freq issue + wr_reg(DDR0_PUB_PGCR1, p_ddr_set->t_pub_pgcr1); + wr_reg(DDR0_PUB_PGCR2, p_ddr_set->t_pub_pgcr2); + //wr_reg(DDR0_PUB_PGCR2, 0x00f05f97); + wr_reg(DDR0_PUB_PGCR3, p_ddr_set->t_pub_pgcr3); + wr_reg(DDR0_PUB_DXCCR, p_ddr_set->t_pub_dxccr); + + wr_reg(DDR0_PUB_DTPR2, p_ddr_set->t_pub_dtpr[2]); + wr_reg(DDR0_PUB_DTPR3, p_ddr_set->t_pub_dtpr[3]); + wr_reg(DDR0_PUB_DTCR, p_ddr_set->t_pub_dtcr); //use mpr |(1<<6) + + //DDR0_DLL_LOCK_WAIT + wait_set(DDR0_PUB_PGSR0, 0); + + //wr_reg(DDR0_PUB_DTCR, 0x430030c7); + //wr_reg(DDR0_PUB_DTPR3, 0x2010a902); //tmp disable + wr_reg(DDR0_PUB_ACIOCR1, 0); + wr_reg(DDR0_PUB_ACIOCR2, 0); + wr_reg(DDR0_PUB_ACIOCR3, 0); + wr_reg(DDR0_PUB_ACIOCR4, 0); + wr_reg(DDR0_PUB_ACIOCR5, 0); + wr_reg(DDR0_PUB_DX0GCR1, 0); + wr_reg(DDR0_PUB_DX0GCR2, 0); + wr_reg(DDR0_PUB_DX0GCR3, (0x1<<10)|(0x2<<12)); //power down dm recevier + wr_reg(DDR0_PUB_DX1GCR1, 0); + wr_reg(DDR0_PUB_DX1GCR2, 0); + wr_reg(DDR0_PUB_DX1GCR3, (0x1<<10)|(0x2<<12));//power down dm recevier + wr_reg(DDR0_PUB_DX2GCR1, 0); + wr_reg(DDR0_PUB_DX2GCR2, 0); + wr_reg(DDR0_PUB_DX2GCR3, (0x1<<10)|(0x2<<12));//power down dm recevier + wr_reg(DDR0_PUB_DX3GCR1, 0); + wr_reg(DDR0_PUB_DX3GCR2, 0); + wr_reg(DDR0_PUB_DX3GCR3, (0x1<<10)|(0x2<<12));//power down dm recevier + + // 2:0 011: DDR0_ MODE. 100: LPDDR2 MODE. + // 3: 8 BANK. + // 7; MPR FOR DATA TRAINING. + wr_reg(DDR0_PUB_DCR, p_ddr_set->t_pub_dcr); //use mpr |(1<<7) + + wr_reg(DDR0_PUB_DTAR0, p_ddr_set->t_pub_dtar); + wr_reg(DDR0_PUB_DTAR1, (0X8 | p_ddr_set->t_pub_dtar)); + wr_reg(DDR0_PUB_DTAR2, (0X10 | p_ddr_set->t_pub_dtar)); + wr_reg(DDR0_PUB_DTAR3, (0X18 | p_ddr_set->t_pub_dtar)); + + //// DDR PHY INITIALIZATION +#ifdef CONFIG_PXP_EMULATOR + wr_reg(DDR0_PUB_PIR, 0X581); +#endif + wr_reg(DDR0_PUB_DSGCR, p_ddr_set->t_pub_dsgcr); + + //DDR0_SDRAM_INIT_WAIT : + wait_set(DDR0_PUB_PGSR0, 0); + + if (ddr0_enabled) { + // configure DDR0 IP. + wr_reg(DDR0_PCTL_TOGCNT1U, p_ddr_set->t_pctl0_1us_pck); + wr_reg(DDR0_PCTL_TOGCNT100N, p_ddr_set->t_pctl0_100ns_pck); + wr_reg(DDR0_PCTL_TINIT, p_ddr_set->t_pctl0_init_us); //20 + wr_reg(DDR0_PCTL_TRSTH, p_ddr_set->t_pctl0_rsth_us); //50 + wr_reg(DDR0_PCTL_MCFG, (p_ddr_set->t_pctl0_mcfg)|((p_ddr_set->ddr_2t_mode)?(1<<3):(0<<3))); + if (p_ddr_set->ddr_channel_set == CONFIG_DDR01_SHARE_AC) + wr_reg(DDR0_PCTL_MCFG1, ((p_ddr_set->t_pctl0_mcfg1)&0xFFFFFF00)); + else + wr_reg(DDR0_PCTL_MCFG1, p_ddr_set->t_pctl0_mcfg1); + } + + if (ddr1_enabled) { + // configure DDR1 IP. + wr_reg(DDR1_PCTL_TOGCNT1U, p_ddr_set->t_pctl0_1us_pck); + wr_reg(DDR1_PCTL_TOGCNT100N, p_ddr_set->t_pctl0_100ns_pck); + wr_reg(DDR1_PCTL_TINIT, p_ddr_set->t_pctl0_init_us); //20 + wr_reg(DDR1_PCTL_TRSTH, p_ddr_set->t_pctl0_rsth_us); //50 + wr_reg(DDR1_PCTL_MCFG, (p_ddr_set->t_pctl0_mcfg)|((p_ddr_set->ddr_2t_mode)?(1<<3):(0<<3))); + //wr_reg(DDR1_PCTL_MCFG1, p_ddr_set->t_pctl0_mcfg1); + if (p_ddr_set->ddr_channel_set == CONFIG_DDR01_SHARE_AC) + wr_reg(DDR1_PCTL_MCFG1, ((p_ddr_set->t_pctl0_mcfg1)&0xFFFFFF00)); + else + wr_reg(DDR1_PCTL_MCFG1, p_ddr_set->t_pctl0_mcfg1); + } + + _udelay(500); + + // MONITOR DFI INITIALIZATION STATUS. + if (ddr0_enabled) { + wait_set(DDR0_PCTL_DFISTSTAT0, 0); + wr_reg(DDR0_PCTL_POWCTL, 1); + //DDR0_POWER_UP_WAIT + wait_set(DDR0_PCTL_POWSTAT, 0); + } + if (ddr1_enabled) { + wait_set(DDR1_PCTL_DFISTSTAT0, 0); + wr_reg(DDR1_PCTL_POWCTL, 1); + //DDR0_POWER_UP_WAIT + wait_set(DDR1_PCTL_POWSTAT, 0); + } + + if (ddr0_enabled) { + wr_reg(DDR0_PCTL_TRFC, p_ddr_timing->cfg_ddr_rfc); + wr_reg(DDR0_PCTL_TREFI_MEM_DDR3, p_ddr_timing->cfg_ddr_refi_mddr3); + wr_reg(DDR0_PCTL_TMRD, p_ddr_timing->cfg_ddr_mrd); + wr_reg(DDR0_PCTL_TRP, p_ddr_timing->cfg_ddr_rp); + wr_reg(DDR0_PCTL_TAL, p_ddr_timing->cfg_ddr_al); + wr_reg(DDR0_PCTL_TCWL, p_ddr_timing->cfg_ddr_cwl); + wr_reg(DDR0_PCTL_TCL, p_ddr_timing->cfg_ddr_cl); + wr_reg(DDR0_PCTL_TRAS, p_ddr_timing->cfg_ddr_ras); + wr_reg(DDR0_PCTL_TRC, p_ddr_timing->cfg_ddr_rc); + wr_reg(DDR0_PCTL_TRCD, p_ddr_timing->cfg_ddr_rcd); + wr_reg(DDR0_PCTL_TRRD, p_ddr_timing->cfg_ddr_rrd); + wr_reg(DDR0_PCTL_TRTP, p_ddr_timing->cfg_ddr_rtp); + wr_reg(DDR0_PCTL_TWR, p_ddr_timing->cfg_ddr_wr); + wr_reg(DDR0_PCTL_TWTR, p_ddr_timing->cfg_ddr_wtr); + wr_reg(DDR0_PCTL_TEXSR, p_ddr_timing->cfg_ddr_exsr); + wr_reg(DDR0_PCTL_TXP, p_ddr_timing->cfg_ddr_xp); + wr_reg(DDR0_PCTL_TDQS, p_ddr_timing->cfg_ddr_dqs); + wr_reg(DDR0_PCTL_TRTW, p_ddr_timing->cfg_ddr_rtw); + wr_reg(DDR0_PCTL_TCKSRE, p_ddr_timing->cfg_ddr_cksre); + wr_reg(DDR0_PCTL_TCKSRX, p_ddr_timing->cfg_ddr_cksrx); + wr_reg(DDR0_PCTL_TMOD, p_ddr_timing->cfg_ddr_mod); + wr_reg(DDR0_PCTL_TCKE, p_ddr_timing->cfg_ddr_cke); + wr_reg(DDR0_PCTL_TCKESR, p_ddr_timing->cfg_ddr_cke+1); + wr_reg(DDR0_PCTL_TZQCS, p_ddr_timing->cfg_ddr_zqcs); + wr_reg(DDR0_PCTL_TZQCL, p_ddr_timing->cfg_ddr_zqcl); + wr_reg(DDR0_PCTL_TXPDLL, p_ddr_timing->cfg_ddr_xpdll); + wr_reg(DDR0_PCTL_TZQCSI, p_ddr_timing->cfg_ddr_zqcsi); + } + + if (ddr1_enabled) { + wr_reg(DDR1_PCTL_TRFC, p_ddr_timing->cfg_ddr_rfc); + wr_reg(DDR1_PCTL_TREFI_MEM_DDR3, p_ddr_timing->cfg_ddr_refi_mddr3); + wr_reg(DDR1_PCTL_TMRD, p_ddr_timing->cfg_ddr_mrd); + wr_reg(DDR1_PCTL_TRP, p_ddr_timing->cfg_ddr_rp); + wr_reg(DDR1_PCTL_TAL, p_ddr_timing->cfg_ddr_al); + wr_reg(DDR1_PCTL_TCWL, p_ddr_timing->cfg_ddr_cwl); + wr_reg(DDR1_PCTL_TCL, p_ddr_timing->cfg_ddr_cl); + wr_reg(DDR1_PCTL_TRAS, p_ddr_timing->cfg_ddr_ras); + wr_reg(DDR1_PCTL_TRC, p_ddr_timing->cfg_ddr_rc); + wr_reg(DDR1_PCTL_TRCD, p_ddr_timing->cfg_ddr_rcd); + wr_reg(DDR1_PCTL_TRRD, p_ddr_timing->cfg_ddr_rrd); + wr_reg(DDR1_PCTL_TRTP, p_ddr_timing->cfg_ddr_rtp); + wr_reg(DDR1_PCTL_TWR, p_ddr_timing->cfg_ddr_wr); + wr_reg(DDR1_PCTL_TWTR, p_ddr_timing->cfg_ddr_wtr); + wr_reg(DDR1_PCTL_TEXSR, p_ddr_timing->cfg_ddr_exsr); + wr_reg(DDR1_PCTL_TXP, p_ddr_timing->cfg_ddr_xp); + wr_reg(DDR1_PCTL_TDQS, p_ddr_timing->cfg_ddr_dqs); + wr_reg(DDR1_PCTL_TRTW, p_ddr_timing->cfg_ddr_rtw); + wr_reg(DDR1_PCTL_TCKSRE, p_ddr_timing->cfg_ddr_cksre); + wr_reg(DDR1_PCTL_TCKSRX, p_ddr_timing->cfg_ddr_cksrx); + wr_reg(DDR1_PCTL_TMOD, p_ddr_timing->cfg_ddr_mod); + wr_reg(DDR1_PCTL_TCKE, p_ddr_timing->cfg_ddr_cke); + wr_reg(DDR1_PCTL_TCKESR, p_ddr_timing->cfg_ddr_cke+1); + wr_reg(DDR1_PCTL_TZQCS, p_ddr_timing->cfg_ddr_zqcs); + wr_reg(DDR1_PCTL_TZQCL, p_ddr_timing->cfg_ddr_zqcl); + wr_reg(DDR1_PCTL_TXPDLL, p_ddr_timing->cfg_ddr_xpdll); + wr_reg(DDR1_PCTL_TZQCSI, p_ddr_timing->cfg_ddr_zqcsi); + } + + if (ddr0_enabled) { + wr_reg(DDR0_PCTL_SCFG, p_ddr_set->t_pctl0_scfg); + wr_reg(DDR0_PCTL_SCTL, p_ddr_set->t_pctl0_sctl); + } + + if (ddr1_enabled) { + wr_reg(DDR1_PCTL_SCFG, p_ddr_set->t_pctl0_scfg); + wr_reg(DDR1_PCTL_SCTL, p_ddr_set->t_pctl0_sctl); + } + + // SCRATCH1 + wr_reg(0xC1107d40, 0xdeadbeef); + + // NEW HIU + wr_reg(0xC883c010, 0x88776655); + + //DDR0_STAT_CONFIG_WAIT + if (ddr0_enabled) + wait_set(DDR0_PCTL_STAT, 0); + if (ddr1_enabled) + wait_set(DDR1_PCTL_STAT, 0); + + if (ddr0_enabled) { + wr_reg(DDR0_PCTL_PPCFG, p_ddr_set->t_pctl0_ppcfg); /* 16bit or 32bit mode */ + wr_reg(DDR0_PCTL_DFISTCFG0, p_ddr_set->t_pctl0_dfistcfg0); + wr_reg(DDR0_PCTL_DFISTCFG1, p_ddr_set->t_pctl0_dfistcfg1); + wr_reg(DDR0_PCTL_DFITCTRLDELAY, p_ddr_set->t_pctl0_dfitctrldelay); + wr_reg(DDR0_PCTL_DFITPHYWRDATA, p_ddr_set->t_pctl0_dfitphywrdata); + wr_reg(DDR0_PCTL_DFITPHYWRLAT, p_ddr_set->t_pctl0_dfitphywrlta); + wr_reg(DDR0_PCTL_DFITRDDATAEN, p_ddr_set->t_pctl0_dfitrddataen); + wr_reg(DDR0_PCTL_DFITPHYRDLAT, p_ddr_set->t_pctl0_dfitphyrdlat); + wr_reg(DDR0_PCTL_DFITDRAMCLKDIS, p_ddr_set->t_pctl0_dfitdramclkdis); + wr_reg(DDR0_PCTL_DFITDRAMCLKEN, p_ddr_set->t_pctl0_dfitdramclken); + wr_reg(DDR0_PCTL_DFILPCFG0, p_ddr_set->t_pctl0_dfilpcfg0); + wr_reg(DDR0_PCTL_DFITPHYUPDTYPE1, p_ddr_set->t_pctl0_dfitphyupdtype1); + wr_reg(DDR0_PCTL_DFITCTRLUPDMIN, p_ddr_set->t_pctl0_dfitctrlupdmin); + wr_reg(DDR0_PCTL_DFIODTCFG, p_ddr_set->t_pctl0_dfiodtcfg); + wr_reg(DDR0_PCTL_DFIODTCFG1, p_ddr_set->t_pctl0_dfiodtcfg1); + wr_reg(DDR0_PCTL_CMDTSTATEN, p_ddr_set->t_pctl0_cmdtstaten); + } + + if (ddr1_enabled) { + wr_reg(DDR1_PCTL_PPCFG, p_ddr_set->t_pctl0_ppcfg); /* 16bit or 32bit mode */ + wr_reg(DDR1_PCTL_DFISTCFG0, p_ddr_set->t_pctl0_dfistcfg0); + wr_reg(DDR1_PCTL_DFISTCFG1, p_ddr_set->t_pctl0_dfistcfg1); + wr_reg(DDR1_PCTL_DFITCTRLDELAY, p_ddr_set->t_pctl0_dfitctrldelay); + wr_reg(DDR1_PCTL_DFITPHYWRDATA, p_ddr_set->t_pctl0_dfitphywrdata); + wr_reg(DDR1_PCTL_DFITPHYWRLAT, p_ddr_set->t_pctl0_dfitphywrlta); + wr_reg(DDR1_PCTL_DFITRDDATAEN, p_ddr_set->t_pctl0_dfitrddataen); + wr_reg(DDR1_PCTL_DFITPHYRDLAT, p_ddr_set->t_pctl0_dfitphyrdlat); + wr_reg(DDR1_PCTL_DFITDRAMCLKDIS, p_ddr_set->t_pctl0_dfitdramclkdis); + wr_reg(DDR1_PCTL_DFITDRAMCLKEN, p_ddr_set->t_pctl0_dfitdramclken); + wr_reg(DDR1_PCTL_DFILPCFG0, p_ddr_set->t_pctl0_dfilpcfg0); + wr_reg(DDR1_PCTL_DFITPHYUPDTYPE1, p_ddr_set->t_pctl0_dfitphyupdtype1); + wr_reg(DDR1_PCTL_DFITCTRLUPDMIN, p_ddr_set->t_pctl0_dfitctrlupdmin); + wr_reg(DDR1_PCTL_DFIODTCFG, p_ddr_set->t_pctl0_dfiodtcfg); + wr_reg(DDR1_PCTL_DFIODTCFG1, p_ddr_set->t_pctl0_dfiodtcfg1); + wr_reg(DDR1_PCTL_CMDTSTATEN, p_ddr_set->t_pctl0_cmdtstaten); + } + +#ifndef CONFIG_PXP_EMULATOR + wr_reg(DDR0_PUB_ZQ0PR, p_ddr_set->t_pub_zq0pr); + wr_reg(DDR0_PUB_ZQ1PR, p_ddr_set->t_pub_zq1pr); + wr_reg(DDR0_PUB_ZQ2PR, p_ddr_set->t_pub_zq2pr); + wr_reg(DDR0_PUB_ZQ3PR, p_ddr_set->t_pub_zq3pr); + + wr_reg(DDR0_PUB_PIR, 3); + wait_set(DDR0_PUB_PGSR0, 0); + wr_reg(DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))|(1<<2)|(1<<27)); //jiaxing debug must force update + _udelay(10); + wr_reg(DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))&(~((1<<2)|(1<<27)))); + _udelay(30); + if (p_ddr_set->ddr_channel_set == CONFIG_DDR0_ONLY_16BIT) + { + wr_reg(DDR0_PUB_DX2GCR0, (0xfffffffe&rd_reg(DDR0_PUB_DX2GCR0))); + wr_reg(DDR0_PUB_DX3GCR0, (0xfffffffe&rd_reg(DDR0_PUB_DX3GCR0))); + } + +#ifdef CONFIG_DDR_CMD_BDL_TUNE + wr_reg(DDR0_PUB_ACLCDLR, DDR_AC_LCDLR); //ck0 + wr_reg(DDR0_PUB_ACBDLR0, DDR_CK0_BDL); //ck0 + wr_reg(DDR0_PUB_ACBDLR1, (DDR_WE_BDL<<16)|(DDR_CAS_BDL<<8)|(DDR_RAS_BDL)); //ras cas we + wr_reg(DDR0_PUB_ACBDLR2, ((DDR_ACPDD_BDL<<24)|(DDR_BA2_BDL<<16)|(DDR_BA1_BDL<<8)|(DDR_BA0_BDL))); //ba0 ba1 ba2 + wr_reg(DDR0_PUB_ACBDLR3, ((DDR_CS1_BDL<<8)|(DDR_CS0_BDL))); //cs0 cs1 + wr_reg(DDR0_PUB_ACBDLR4, ((DDR_ODT1_BDL<<8)|(DDR_ODT0_BDL))); //odt0 odt1 + wr_reg(DDR0_PUB_ACBDLR5, ((DDR_CKE1_BDL<<8)|(DDR_CKE0_BDL))); //cke0 cke1 + wr_reg(DDR0_PUB_ACBDLR6, ((DDR_A3_BDL<<24)|(DDR_A2_BDL<<16)|(DDR_A1_BDL<<8)|(DDR_A0_BDL))); //a0 a1 a2 a3 + wr_reg(DDR0_PUB_ACBDLR7, ((DDR_A7_BDL<<24)|(DDR_A6_BDL<<16)|(DDR_A5_BDL<<8)|(DDR_A4_BDL))); //a4 a5 a6 a7 + wr_reg(DDR0_PUB_ACBDLR8, ((DDR_A11_BDL<<24)|(DDR_A10_BDL<<16)|(DDR_A9_BDL<<8)|(DDR_A8_BDL))); //a8 a9 a10 a11 + wr_reg(DDR0_PUB_ACBDLR9, ((DDR_A15_BDL<<24)|(DDR_A14_BDL<<16)|(DDR_A13_BDL<<8)|(DDR_A12_BDL))); //a12 a13 a14 a15 +#endif + + wr_reg(DDR0_PUB_PIR, (DDR_PIR | PUB_PIR_INIT)); + do { + _udelay(20); + } while(DDR_PGSR0_CHECK()); +#endif + + if ((p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK0_ONLY) || \ + (p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK01_SAME)) + { + unsigned int i=0, j=0; + i=(rd_reg(DDR0_PUB_DX2LCDLR0)); + wr_reg(DDR0_PUB_DX2LCDLR0,((i>>8)|(i&(0xffffff00)))); + i=(((rd_reg(DDR0_PUB_DX2GTR))>>3)&((7<<0))); + j=(((rd_reg(DDR0_PUB_DX2GTR))>>14)&((3<<0))); + wr_reg(DDR0_PUB_DX2GTR,i|(i<<3)|(j<<12)|(j<<14)); + i=(rd_reg(DDR0_PUB_DX2LCDLR2)); + wr_reg(DDR0_PUB_DX2LCDLR2,((i>>8)|(i&(0xffffff00)))); + i=(rd_reg(DDR0_PUB_DX3LCDLR0)); + wr_reg(DDR0_PUB_DX3LCDLR0,((i>>8)|(i&(0xffffff00)))); + i=(((rd_reg(DDR0_PUB_DX3GTR))>>3)&((7<<0))); + j=(((rd_reg(DDR0_PUB_DX3GTR))>>14)&((3<<0))); + wr_reg(DDR0_PUB_DX3GTR,i|(i<<3)|(j<<12)|(j<<14)); + i=(rd_reg(DDR0_PUB_DX3LCDLR2)); + wr_reg(DDR0_PUB_DX3LCDLR2,((i>>8)|(i&(0xffffff00)))); + i=(rd_reg(DDR0_PUB_DX0LCDLR0)); + wr_reg(DDR0_PUB_DX0LCDLR0,((i<<8)|(i&(0xffff00ff)))); + i=(((rd_reg(DDR0_PUB_DX0GTR))<<0)&((7<<0))); + j=(((rd_reg(DDR0_PUB_DX0GTR))>>12)&((3<<0))); + wr_reg(DDR0_PUB_DX0GTR,i|(i<<3)|(j<<12)|(j<<14)); + i=(rd_reg(DDR0_PUB_DX0LCDLR2)); + wr_reg(DDR0_PUB_DX0LCDLR2,((i<<8)|(i&(0xffff00ff)))); + i=(rd_reg(DDR0_PUB_DX1LCDLR0)); + wr_reg(DDR0_PUB_DX1LCDLR0,((i<<8)|(i&(0xffff00ff)))); + i=(((rd_reg(DDR0_PUB_DX1GTR))<<0)&((7<<0))); + j=(((rd_reg(DDR0_PUB_DX1GTR))>>12)&((3<<0))); + wr_reg(DDR0_PUB_DX1GTR,i|(i<<3)|(j<<12)|(j<<14)); + i=(rd_reg(DDR0_PUB_DX1LCDLR2)); + wr_reg(DDR0_PUB_DX1LCDLR2,((i<<8)|(i&(0xffff00ff)))); + } + if ((p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK0_ONLY) || \ + (p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK01_SAME) || \ + (p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK01_DIFF)) { + //wr_reg(DDR0_PUB_PGCR2,((((1<<28))|p_ddr_set->t_pub_pgcr2))); + wr_reg(DDR0_PUB_PGCR2,(((~(1<<28))&p_ddr_set->t_pub_pgcr2))); + } + + if ((p_ddr_set->ddr_2t_mode) && \ + (p_ddr_set->ddr_channel_set != CONFIG_DDR01_SHARE_AC) && \ + (((p_ddr_set->t_pub_dcr)&0x7)== 0x3)) { + //jiaxing mark----must place after training ,because training is 1t mode ,if delay too much training will not ok + wr_reg(DDR0_PUB_ACLCDLR, 0x1f); //delay cmd/address 2t signle not effect cs cke odt + //wr_reg(DDR0_PUB_ACBDLR0, 0x10); //ck0 + /* + wr_reg(DDR0_PUB_ACBDLR1, (0x18<<16)|(0x18<<8)|(0x18)); //ras cas we + wr_reg(DDR0_PUB_ACBDLR2, ((0x18<<16)|(0x18<<8)|(0x18))); //ba0 ba1 ba2 + //wr_reg(DDR0_PUB_ACBDLR3, ((0<<8)|(0))); //cs0 cs1 + //wr_reg(DDR0_PUB_ACBDLR4, ((0<<8)|(0))); //odt0 odt1 + //wr_reg(DDR0_PUB_ACBDLR5, ((0<<8)|(0))); //cke0 cke1 + wr_reg(DDR0_PUB_ACBDLR6, ((0x18<<24)|(0x18<<16)|(0x18<<8)|(0x18))); //a0 a1 a2 a3 + wr_reg(DDR0_PUB_ACBDLR7, ((0x18<<24)|(0x18<<16)|(0x18<<8)|(0x18))); //a4 a5 a6 a7 + wr_reg(DDR0_PUB_ACBDLR8, ((0x18<<24)|(0x18<<16)|(0x18<<8)|(0x18))); //a8 a9 a10 a11 + wr_reg(DDR0_PUB_ACBDLR9, ((0x18<<24)|(0x18<<16)|(0x18<<8)|(0x18))); //a12 a13 a14 a15 + */ + } + //DDR0_CMD_TIMER_WAIT + if (ddr0_enabled) + wait_set(DDR0_PCTL_CMDTSTAT, 0); + if (ddr1_enabled) + wait_set(DDR1_PCTL_CMDTSTAT, 0); + + ////APB_WR(PCTL_PCTL_SCTL, 2); // INIT: 0, CFG: 1, GO: 2, SLEEP: 3, WAKEUP: 4 + if (ddr0_enabled) + wr_reg(DDR0_PCTL_SCTL, UPCTL_CMD_GO); + if (ddr1_enabled) + wr_reg(DDR1_PCTL_SCTL, UPCTL_CMD_GO); + + ////WHILE ((APB_RD(DDR0_PCTL_STAT) & 0x7 ) != 3 ) {} + //DDR0_STAT_GO_WAIT: + if (ddr0_enabled) + wait_equal(DDR0_PCTL_STAT, UPCTL_STAT_ACCESS); + if (ddr1_enabled) + wait_equal(DDR1_PCTL_STAT, UPCTL_STAT_ACCESS); + + wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))|(1<<2)); + wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))&(~(1<<2))); + +/* power down zq for power saving */ +#ifdef CONFIG_DDR_ZQ_POWER_DOWN + wr_reg( DDR0_PUB_ZQCR,(rd_reg(DDR0_PUB_ZQCR))|(1<<2)); +#endif + +/* power down phy vref for power saving */ +#ifdef CONFIG_DDR_POWER_DOWN_PHY_VREF + wr_reg(DDR0_PUB_IOVCR0, 0); + wr_reg(DDR0_PUB_IOVCR1, 0); +#endif + + //// ENABLE THE DMC AUTO REFRESH FUNCTION + if (ddr0_enabled) { + wr_reg(DMC_REFR_CTRL1, 0X8800191|(0x3<<2)|(0x1<<0)); + rd_reg(DDR0_PCTL_MCFG); + } + if (ddr1_enabled) { + wr_reg(DMC_REFR_CTRL1, 0X8800191|(0x3<<2)|(0x1<<1)); + rd_reg(DDR1_PCTL_MCFG); + } + wr_reg(DMC_REFR_CTRL2, 0X20100000|(p_ddr_set->ddr_clk/20)|(39<<8)); + + return 0; +} + +void ddr_pre_init(void){ + /* find match ddr timing */ + if ((p_ddr_set->ddr_clk >= CONFIG_DDR_CLK_LOW) && (p_ddr_set->ddr_clk < 533)) { + p_ddr_set->ddr_timing_ind = CONFIG_DDR_TIMMING_DDR3_7; + } + else if ((p_ddr_set->ddr_clk >= 533) && (p_ddr_set->ddr_clk < 667)) { + p_ddr_set->ddr_timing_ind = CONFIG_DDR_TIMMING_DDR3_9; + } + else if ((p_ddr_set->ddr_clk >= 667) && (p_ddr_set->ddr_clk < 800)) { + p_ddr_set->ddr_timing_ind = CONFIG_DDR_TIMMING_DDR3_11; + } + else if ((p_ddr_set->ddr_clk >= 800) && (p_ddr_set->ddr_clk < 933)) { + p_ddr_set->ddr_timing_ind = CONFIG_DDR_TIMMING_DDR3_13; + } + else if ((p_ddr_set->ddr_clk >= 933) && (p_ddr_set->ddr_clk < CONFIG_DDR_CLK_HIGH)) { + p_ddr_set->ddr_timing_ind = CONFIG_DDR_TIMMING_DDR3_14; + } + else { + serial_puts("DDR clk setting error! Reset...\n"); + reset_system(); + } + + p_ddr_set->t_pctl0_1us_pck = (p_ddr_set->ddr_clk / 2); + p_ddr_set->t_pctl0_100ns_pck = (p_ddr_set->ddr_clk / 20); + + /* get match timing config */ + unsigned loop; + for (loop = 0; loop < (sizeof(__ddr_timming)/sizeof(ddr_timing_t)); loop++) { + if (__ddr_timming[loop].identifier == p_ddr_set->ddr_timing_ind) { + p_ddr_timing = &__ddr_timming[loop]; + break; + } + } + if (NULL == p_ddr_timing) { + serial_puts("Can't find ddr timing setting! Reset...\n"); + reset_system(); + } + + unsigned int ddr_dual_rank_sel = 0; + unsigned int ddr_chl_set = 0; + + //BIT22. 1:RANK1 IS SAME AS RANK0 + //BIT21. 0:SEC RANK DISABLE, 1:SEC RANK ENABLE + //BIT20. SHARE AC MODE, 0:DISABLE, 1:ENABLE + if (p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK0_ONLY) { + serial_puts("DDR channel setting: DDR0 Rank0 only\n"); + ddr_chl_set = ((0x2 << 20) | //b'010: BIT22, BIT21, BIT20 + (0 << 16) | //BIT[17:16], DDR0_DDR1 DATA WIDTH, 0:32BIT, 1:16BIT + (1 << 6)); //b'00:DDR0_DDR1, b'01: DDR0_ONLY, b'10:DDR1_ONLY + ddr_dual_rank_sel = 0; //SET PGCR2[28], RANK0 AND RANK1 USE SAME RANK SELECT SIGNAL + p_ddr_set->t_pctl0_ppcfg = (0xF0 << 1); + p_ddr_set->t_pctl0_dfiodtcfg = 0x0808; + } + else if (p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK01_SAME) { + serial_puts("DDR channel setting: DDR0 Rank0+1 same\n"); + ddr_chl_set = ((0x4 << 20) | (0 << 16) | (1 << 6)); + ddr_dual_rank_sel = 1; + p_ddr_set->t_pctl0_ppcfg = (0xF0 << 1); + p_ddr_set->t_pctl0_dfiodtcfg = 0x08; + } + else if (p_ddr_set->ddr_channel_set == CONFIG_DDR0_RANK01_DIFF) { + serial_puts("DDR channel setting: DDR0 Rank0+1 diff\n"); + ddr_chl_set = ((0x2 << 20) | (0 << 16) | (1 << 6)); + ddr_dual_rank_sel = 0; + p_ddr_set->t_pctl0_ppcfg = (0xF0 << 1); + p_ddr_set->t_pctl0_dfiodtcfg = 0x08; + } + else if (p_ddr_set->ddr_channel_set == CONFIG_DDR0_ONLY_16BIT) { + serial_puts("DDR channel setting: ONLY DDR0 16bit mode\n"); + ddr_chl_set = ((0x2 << 20) | (3 << 16) | (1 << 6)); + ddr_dual_rank_sel = 0; + //p_ddr_set->t_pctl0_ppcfg = (0xF0 << 1); + p_ddr_set->t_pctl0_ppcfg =(0x1fc | 1 ); + p_ddr_set->t_pctl0_dfiodtcfg = 0x08; + } + else if (p_ddr_set->ddr_channel_set == CONFIG_DDR01_SHARE_AC) { + serial_puts("DDR channel setting: DDR0+1 share ac\n"); + ddr_chl_set = ((0x1 << 20) | (3 << 16) | (0 << 6)); + ddr_dual_rank_sel = 1; + p_ddr_set->t_pctl0_ppcfg = (0x1fc | 1 ); + p_ddr_set->t_pctl0_dfiodtcfg = 0x08; + p_ddr_set->ddr_dmc_ctrl |= (5 << 8); + p_ddr_set->ddr_2t_mode = 1; + } + p_ddr_set->ddr_dmc_ctrl |= (ddr_chl_set | + (0x5 << 3) | //set to max size + (0x5 << 0)); //set to max size + /* config t_pub_pgcr2[28] share-ac-dual */ + p_ddr_set->t_pub_pgcr2 |= (ddr_dual_rank_sel << 28); + + /* update pctl timing */ + int tmp_val = 0; + tmp_val =( p_ddr_timing->cfg_ddr_cwl + p_ddr_timing->cfg_ddr_al); + tmp_val = (tmp_val - ((tmp_val%2) ? 3:4))/2; + p_ddr_set->t_pctl0_dfitphywrlta=tmp_val; + + tmp_val = p_ddr_timing->cfg_ddr_cl + p_ddr_timing->cfg_ddr_al; + tmp_val = (tmp_val - ((tmp_val%2) ? 3:4))/2; + p_ddr_set->t_pctl0_dfitrddataen=tmp_val; + + //p_ddr_set->t_pctl0_dfitphyrdlat=16; + if ((p_ddr_timing->cfg_ddr_cl+p_ddr_timing->cfg_ddr_al)%2) { + p_ddr_set->t_pctl0_dfitphyrdlat=14; + } + + /* update pub mr */ + p_ddr_set->t_pub_mr[0] = ((((p_ddr_timing->cfg_ddr_cl - 4) & 0x8)>>1) | + (((p_ddr_timing->cfg_ddr_cl - 4) & 0x7) << 4) | + ((((p_ddr_timing->cfg_ddr_wr <= 8)?(p_ddr_timing->cfg_ddr_wr - 4):(p_ddr_timing->cfg_ddr_wr>>1)) & 7) << 9) | + (0x0) | (0x0 << 3) | (0x0 << 7) | (0x0 << 8) | (0x6 << 9) | (1 << 12)), + p_ddr_set->t_pub_mr[1] = ( ((p_ddr_set->ddr_drv<<1)|((p_ddr_set->ddr_odt&1)<<2) | + (((p_ddr_set->ddr_odt&2)>>1)<<6) | + (((p_ddr_set->ddr_odt&4)>>2)<<9) | + (1<<7) | + ((p_ddr_timing->cfg_ddr_al ? ((p_ddr_timing->cfg_ddr_cl - p_ddr_timing->cfg_ddr_al)&3): 0) << 3 ))), + p_ddr_set->t_pub_mr[2] = ((1<<6) | + (((p_ddr_timing->cfg_ddr_cwl-5)&0x7)<<3)), + p_ddr_set->t_pub_mr[3] = 0x0, + /* update pub dtpr */ + p_ddr_set->t_pub_dtpr[0] = (p_ddr_timing->cfg_ddr_rtp | + (p_ddr_timing->cfg_ddr_wtr << 4) | + (p_ddr_timing->cfg_ddr_rp << 8) | + (p_ddr_timing->cfg_ddr_ras << 16) | + (p_ddr_timing->cfg_ddr_rrd << 22) | + (p_ddr_timing->cfg_ddr_rcd << 26)); + p_ddr_set->t_pub_dtpr[1] = ((p_ddr_timing->cfg_ddr_mod << 2) | + (p_ddr_timing->cfg_ddr_faw << 5) | + (p_ddr_timing->cfg_ddr_rfc << 11) | + (p_ddr_timing->cfg_ddr_wlmrd << 20) | + (p_ddr_timing->cfg_ddr_wlo << 26) | + (0 << 30) ); //TAOND + p_ddr_set->t_pub_dtpr[2] = (p_ddr_timing->cfg_ddr_xs | + (p_ddr_timing->cfg_ddr_xp << 10) | + (p_ddr_timing->cfg_ddr_dllk << 19) | + (0 << 29) | //TRTODT ADDITIONAL + (0 << 30) | //TRTW ADDITIONAL + (0 << 31 )); //TCCD ADDITIONAL + p_ddr_set->t_pub_dtpr[3] = (0 | (0 << 3) | + (p_ddr_timing->cfg_ddr_rc << 6) | + (p_ddr_timing->cfg_ddr_cke << 13) | + (p_ddr_timing->cfg_ddr_mrd << 18) | + (0 << 29)); //tAOFDx + p_ddr_set->t_pctl0_mcfg = ((p_ddr_set->t_pctl0_mcfg)&(~(0x3<<18))) | + (((((p_ddr_timing->cfg_ddr_faw+p_ddr_timing->cfg_ddr_rrd-1)/p_ddr_timing->cfg_ddr_rrd)-4)&0x3)<<18); + p_ddr_set->t_pctl0_mcfg1 |= ((((p_ddr_timing->cfg_ddr_faw%p_ddr_timing->cfg_ddr_rrd)?(p_ddr_timing->cfg_ddr_rrd-(p_ddr_timing->cfg_ddr_faw%p_ddr_timing->cfg_ddr_rrd)):0)&0x7)<<8); +} + +void ddr_test(void){ + if (memTestDataBus((volatile unsigned int *)(uint64_t) \ + (p_ddr_set->ddr_base_addr + p_ddr_set->ddr_start_offset))) { + serial_puts("DataBus test failed!!!\n"); + reset_system(); + } + else + serial_puts("DataBus test pass!\n"); + if (memTestAddressBus((volatile unsigned int *)(uint64_t) \ + (p_ddr_set->ddr_base_addr + p_ddr_set->ddr_start_offset), \ + ((p_ddr_set->ddr_size << 20) - p_ddr_set->ddr_start_offset))) { + serial_puts("AddrBus test failed!!!\n"); + reset_system(); + } + else + serial_puts("AddrBus test pass!\n"); +#if MEM_TEST_DEVICE + if (p_ddr_set->ddr_full_test) { + extern void watchdog_disable(void); + //disable_mmu_el1(); + watchdog_disable(); + if (memTestDevice((volatile unsigned int *)(uint64_t) \ + (p_ddr_set->ddr_base_addr + p_ddr_set->ddr_start_offset), \ + ((p_ddr_set->ddr_size << 20) - p_ddr_set->ddr_start_offset))) { + serial_puts("Device test failed!!!\n"); + reset_system(); + } + else + serial_puts("Device test pass!\n"); + } +#endif// #if MEM_TEST_DEVICE +} + +#if 0 +unsigned int hot_boot(void){ + if (((rd_reg(SCRATCH0) >> 24) & 0xFF) == 0x11) { + /*hot boot*/ + return 0; + } + else{ + return 1; + } +} +#endif diff --git a/plat/gxb/ddr/ddr_detect.c b/plat/gxb/ddr/ddr_detect.c new file mode 100644 index 0000000..a3b28d5 --- /dev/null +++ b/plat/gxb/ddr/ddr_detect.c @@ -0,0 +1,96 @@ + +#define SIZE_16MB 0x01000000 +#define DDR_SIZE_PATTERN 0xAABBCCDD +#define DDR_SIZE_VERI_ADDR SIZE_16MB + +#define DDR_VERI_PATTERN_256M 0 +#define DDR_VERI_PATTERN_512M 0 +#define DDR_VERI_PATTERN_1024M 0xAC7E5AC0 +#define DDR_VERI_PATTERN_2048M 0x1A182515 + +#define DDR_VERI_PATTERN_384M 0 +#define DDR_VERI_PATTERN_768M 0 +#define DDR_VERI_PATTERN_1536M 0 +#define DDR_VERI_PATTERN_3072M 0 + +#define DDR_SIZE_LOOP_MAX 29 + +#ifndef DDR_DETECT_DEBUG +#define DDR_DETECT_DEBUG 0 +#endif + +#if DDR_DETECT_DEBUG +#define debug_serial_puts(a) serial_puts(a) +#define debug_serial_put_hex(a, b) serial_put_hex(a, b) +#else +#define debug_serial_puts(a) +#define debug_serial_put_hex(a, b) +#endif + +#if (CONFIG_DDR_SIZE_AUTO_DETECT) +void ddr_size_detect(ddr_set_t * p_ddr_set) { + /* Set max col, row, bank size */ + debug_serial_puts("DMC_DDR_CTRL: 0x"); + debug_serial_put_hex(rd_reg(DMC_DDR_CTRL), 32); + debug_serial_puts("\n"); + wr_reg(DMC_DDR_CTRL, ((rd_reg(DMC_DDR_CTRL))&(~0x3F))|((5<<3)|5)); + debug_serial_puts("DMC_DDR_CTRL: 0x"); + debug_serial_put_hex(rd_reg(DMC_DDR_CTRL), 32); + debug_serial_puts("\n"); + + uint32_t size_loop=0; + uint64_t write_addr=0; + uint32_t ddr0_size=0; + uint32_t ddr1_size=0; + uint32_t ddr0_size_reg=0; + uint32_t ddr1_size_reg=0; + + //first detect aligned size + for (size_loop=0; size_loop<=DDR_SIZE_LOOP_MAX; size_loop++) { + write_addr = (uint32_t)((0x4<<size_loop)+DDR_SIZE_VERI_ADDR); + debug_serial_puts("size_loop1=0x"); + debug_serial_put_hex(size_loop, 32); + debug_serial_puts("\n"); + wr_reg((unsigned long)DDR_SIZE_VERI_ADDR, 0); + debug_serial_puts("write 0x"); + debug_serial_put_hex(write_addr, 32); + debug_serial_puts("\n"); + wr_reg(write_addr, DDR_SIZE_PATTERN); + _udelay(10); + debug_serial_puts("rd_reg(0):0x"); + debug_serial_put_hex(rd_reg(DDR_SIZE_VERI_ADDR), 32); + debug_serial_puts(", rd_reg(0x4<<size_loop):0x"); + debug_serial_put_hex(rd_reg(write_addr), 32); + debug_serial_puts("\n"); + if ((rd_reg(DDR_SIZE_VERI_ADDR) != 0) && (rd_reg(DDR_SIZE_VERI_ADDR) != DDR_SIZE_PATTERN)) { + debug_serial_puts("find match size1: 0x"); + debug_serial_put_hex(size_loop, 32); + debug_serial_puts("\n"); + /* get correct ddr size */ + p_ddr_set->ddr_size = 1<<(size_loop+2-20); //MB + /* set correct dmc cntl reg */ + unsigned int ddr_one_chl = DDR_USE_1_CHANNEL(p_ddr_set->ddr_channel_set); + ddr0_size = (p_ddr_set->ddr_size)>>(7-ddr_one_chl); + ddr1_size = ddr_one_chl?0x7:((p_ddr_set->ddr_size)>>7); + ddr1_size_reg=ddr_one_chl?0x5:0x0; + while (!((ddr0_size>>=1)&0x1)) + ddr0_size_reg++; + while (!((ddr1_size>>=1)&0x1)) + ddr1_size_reg++; + break; + } + } + debug_serial_puts("DMC_DDR_CTRL: 0x"); + debug_serial_put_hex(rd_reg(DMC_DDR_CTRL), 32); + debug_serial_puts("\n"); + wr_reg(DMC_DDR_CTRL, ((rd_reg(DMC_DDR_CTRL))&(~0x3F))|(ddr1_size_reg<<3|ddr0_size_reg)); + debug_serial_puts("DMC_DDR_CTRL: 0x"); + debug_serial_put_hex(rd_reg(DMC_DDR_CTRL), 32); + debug_serial_puts("\n"); + return; +} +#else +void ddr_size_detect(ddr_set_t * p_ddr_set) { + return; +} +#endif
\ No newline at end of file diff --git a/plat/gxb/ddr/ddr_pctl_define.h b/plat/gxb/ddr/ddr_pctl_define.h new file mode 100644 index 0000000..146391b --- /dev/null +++ b/plat/gxb/ddr/ddr_pctl_define.h @@ -0,0 +1,282 @@ + +/* + * arch/arm/cpu/armv8/common/firmware/plat/gxb/ddr/ddr_pctl_define.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#define DDR0_PCTL_SCFG 0xc8839000 +#define DDR0_PCTL_SCTL 0xc8839004 +#define DDR0_PCTL_STAT 0xc8839008 +#define DDR0_PCTL_INTRSTAT 0xc883900c +#define DDR0_PCTL_POWSTAT 0xc8839048 +#define DDR0_PCTL_MRRSTAT0 0xc8839064 +#define DDR0_PCTL_CMDTSTAT 0xc883904c +#define DDR0_PCTL_MCMD 0xc8839040 +#define DDR0_PCTL_MRRSTAT1 0xc8839068 +#define DDR0_PCTL_MRRCFG0 0xc8839060 +#define DDR0_PCTL_CMDTSTATEN 0xc8839050 +#define DDR0_PCTL_POWCTL 0xc8839044 +#define DDR0_PCTL_PPCFG 0xc8839084 +#define DDR0_PCTL_LPDDR23ZQCFG 0xc883908c +#define DDR0_PCTL_MCFG1 0xc883907c +#define DDR0_PCTL_MSTAT 0xc8839088 +#define DDR0_PCTL_MCFG 0xc8839080 +#define DDR0_PCTL_DTUAWDT 0xc88390b0 +#define DDR0_PCTL_DTUPRD2 0xc88390a8 +#define DDR0_PCTL_DTUPRD3 0xc88390ac +#define DDR0_PCTL_DTUNE 0xc883909c +#define DDR0_PCTL_DTUPDES 0xc8839094 +#define DDR0_PCTL_DTUNA 0xc8839098 +#define DDR0_PCTL_DTUPRD0 0xc88390a0 +#define DDR0_PCTL_DTUPRD1 0xc88390a4 +#define DDR0_PCTL_TCKSRE 0xc8839124 +#define DDR0_PCTL_TZQCSI 0xc883911c +#define DDR0_PCTL_TINIT 0xc88390c4 +#define DDR0_PCTL_TDPD 0xc8839144 +#define DDR0_PCTL_TOGCNT1U 0xc88390c0 +#define DDR0_PCTL_TCKE 0xc883912c +#define DDR0_PCTL_TMOD 0xc8839130 +#define DDR0_PCTL_TEXSR 0xc883910c +#define DDR0_PCTL_TAL 0xc88390e4 +#define DDR0_PCTL_TRTP 0xc8839100 +#define DDR0_PCTL_TCKSRX 0xc8839128 +#define DDR0_PCTL_TRTW 0xc88390e0 +#define DDR0_PCTL_TCWL 0xc88390ec +#define DDR0_PCTL_TWR 0xc8839104 +#define DDR0_PCTL_TCL 0xc88390e8 +#define DDR0_PCTL_TDQS 0xc8839120 +#define DDR0_PCTL_TRSTH 0xc88390c8 +#define DDR0_PCTL_TRCD 0xc88390f8 +#define DDR0_PCTL_TXP 0xc8839110 +#define DDR0_PCTL_TOGCNT100N 0xc88390cc +#define DDR0_PCTL_TMRD 0xc88390d4 +#define DDR0_PCTL_TRSTL 0xc8839134 +#define DDR0_PCTL_TREFI 0xc88390d0 +#define DDR0_PCTL_TRAS 0xc88390f0 +#define DDR0_PCTL_TREFI_MEM_DDR3 0xc8839148 +#define DDR0_PCTL_TWTR 0xc8839108 +#define DDR0_PCTL_TRC 0xc88390f4 +#define DDR0_PCTL_TRFC 0xc88390d8 +#define DDR0_PCTL_TMRR 0xc883913c +#define DDR0_PCTL_TCKESR 0xc8839140 +#define DDR0_PCTL_TZQCL 0xc8839138 +#define DDR0_PCTL_TRRD 0xc88390fc +#define DDR0_PCTL_TRP 0xc88390dc +#define DDR0_PCTL_TZQCS 0xc8839118 +#define DDR0_PCTL_TXPDLL 0xc8839114 +#define DDR0_PCTL_ECCCFG 0xc8839180 +#define DDR0_PCTL_ECCLOG 0xc883918c +#define DDR0_PCTL_ECCCLR 0xc8839188 +#define DDR0_PCTL_ECCTST 0xc8839184 +#define DDR0_PCTL_DTUWD0 0xc8839210 +#define DDR0_PCTL_DTUWD1 0xc8839214 +#define DDR0_PCTL_DTUWACTL 0xc8839200 +#define DDR0_PCTL_DTULFSRRD 0xc8839238 +#define DDR0_PCTL_DTUWD2 0xc8839218 +#define DDR0_PCTL_DTUWD3 0xc883921c +#define DDR0_PCTL_DTULFSRWD 0xc8839234 +#define DDR0_PCTL_DTURACTL 0xc8839204 +#define DDR0_PCTL_DTUWDM 0xc8839220 +#define DDR0_PCTL_DTURD0 0xc8839224 +#define DDR0_PCTL_DTURD1 0xc8839228 +#define DDR0_PCTL_DTURD2 0xc883922c +#define DDR0_PCTL_DTURD3 0xc8839230 +#define DDR0_PCTL_DTUCFG 0xc8839208 +#define DDR0_PCTL_DTUEAF 0xc883923c +#define DDR0_PCTL_DTUECTL 0xc883920c +#define DDR0_PCTL_DFIODTCFG1 0xc8839248 +#define DDR0_PCTL_DFITCTRLDELAY 0xc8839240 +#define DDR0_PCTL_DFIODTRANKMAP 0xc883924c +#define DDR0_PCTL_DFIODTCFG 0xc8839244 +#define DDR0_PCTL_DFITPHYWRLAT 0xc8839254 +#define DDR0_PCTL_DFITPHYWRDATA 0xc8839250 +#define DDR0_PCTL_DFITRDDATAEN 0xc8839260 +#define DDR0_PCTL_DFITPHYRDLAT 0xc8839264 +#define DDR0_PCTL_DFITREFMSKI 0xc8839294 +#define DDR0_PCTL_DFITPHYUPDTYPE0 0xc8839270 +#define DDR0_PCTL_DFITPHYUPDTYPE1 0xc8839274 +#define DDR0_PCTL_DFITCTRLUPDDLY 0xc8839288 +#define DDR0_PCTL_DFITPHYUPDTYPE2 0xc8839278 +#define DDR0_PCTL_DFITCTRLUPDMIN 0xc8839280 +#define DDR0_PCTL_DFITPHYUPDTYPE3 0xc883927c +#define DDR0_PCTL_DFIUPDCFG 0xc8839290 +#define DDR0_PCTL_DFITCTRLUPDMAX 0xc8839284 +#define DDR0_PCTL_DFITCTRLUPDI 0xc8839298 +#define DDR0_PCTL_DFITRRDLVLEN 0xc88392b8 +#define DDR0_PCTL_DFITRSTAT0 0xc88392b0 +#define DDR0_PCTL_DFITRWRLVLEN 0xc88392b4 +#define DDR0_PCTL_DFITRCFG0 0xc88392ac +#define DDR0_PCTL_DFITRRDLVLGATEEN 0xc88392bc +#define DDR0_PCTL_DFISTSTAT0 0xc88392c0 +#define DDR0_PCTL_DFISTPARLOG 0xc88392e0 +#define DDR0_PCTL_DFITDRAMCLKEN 0xc88392d0 +#define DDR0_PCTL_DFISTPARCLR 0xc88392dc +#define DDR0_PCTL_DFISTCFG0 0xc88392c4 +#define DDR0_PCTL_DFISTCFG1 0xc88392c8 +#define DDR0_PCTL_DFISTCFG2 0xc88392d8 +#define DDR0_PCTL_DFITDRAMCLKDIS 0xc88392d4 +#define DDR0_PCTL_DFILPCFG0 0xc88392f0 +#define DDR0_PCTL_DFITRWRLVLDELAY0 0xc8839318 +#define DDR0_PCTL_DFITRWRLVLDELAY1 0xc883931c +#define DDR0_PCTL_DFITRWRLVLDELAY2 0xc8839320 +#define DDR0_PCTL_DFITRRDLVLRESP0 0xc883930c +#define DDR0_PCTL_DFITRRDLVLRESP1 0xc8839310 +#define DDR0_PCTL_DFITRRDLVLRESP2 0xc8839314 +#define DDR0_PCTL_DFITRWRLVLRESP0 0xc8839300 +#define DDR0_PCTL_DFITRRDLVLDELAY0 0xc8839324 +#define DDR0_PCTL_DFITRRDLVLDELAY1 0xc8839328 +#define DDR0_PCTL_DFITRWRLVLRESP1 0xc8839304 +#define DDR0_PCTL_DFITRRDLVLDELAY2 0xc883932c +#define DDR0_PCTL_DFITRWRLVLRESP2 0xc8839308 +#define DDR0_PCTL_DFITRRDLVLGATEDELAY0 0xc8839330 +#define DDR0_PCTL_DFITRCMD 0xc883933c +#define DDR0_PCTL_DFITRRDLVLGATEDELAY1 0xc8839334 +#define DDR0_PCTL_DFITRRDLVLGATEDELAY2 0xc8839338 +#define DDR0_PCTL_IPTR 0xc88393fc +#define DDR0_PCTL_IPVR 0xc88393f8 + +#define DDR1_PCTL_SCFG 0xc8839400 +#define DDR1_PCTL_SCTL 0xc8839404 +#define DDR1_PCTL_STAT 0xc8839408 +#define DDR1_PCTL_INTRSTAT 0xc883940c +#define DDR1_PCTL_POWSTAT 0xc8839448 +#define DDR1_PCTL_MRRSTAT0 0xc8839464 +#define DDR1_PCTL_CMDTSTAT 0xc883944c +#define DDR1_PCTL_MCMD 0xc8839440 +#define DDR1_PCTL_MRRSTAT1 0xc8839468 +#define DDR1_PCTL_MRRCFG0 0xc8839460 +#define DDR1_PCTL_CMDTSTATEN 0xc8839450 +#define DDR1_PCTL_POWCTL 0xc8839444 +#define DDR1_PCTL_PPCFG 0xc8839484 +#define DDR1_PCTL_LPDDR23ZQCFG 0xc883948c +#define DDR1_PCTL_MCFG1 0xc883947c +#define DDR1_PCTL_MSTAT 0xc8839488 +#define DDR1_PCTL_MCFG 0xc8839480 +#define DDR1_PCTL_DTUAWDT 0xc88394b0 +#define DDR1_PCTL_DTUPRD2 0xc88394a8 +#define DDR1_PCTL_DTUPRD3 0xc88394ac +#define DDR1_PCTL_DTUNE 0xc883949c +#define DDR1_PCTL_DTUPDES 0xc8839494 +#define DDR1_PCTL_DTUNA 0xc8839498 +#define DDR1_PCTL_DTUPRD0 0xc88394a0 +#define DDR1_PCTL_DTUPRD1 0xc88394a4 +#define DDR1_PCTL_TCKSRE 0xc8839524 +#define DDR1_PCTL_TZQCSI 0xc883951c +#define DDR1_PCTL_TINIT 0xc88394c4 +#define DDR1_PCTL_TDPD 0xc8839544 +#define DDR1_PCTL_TOGCNT1U 0xc88394c0 +#define DDR1_PCTL_TCKE 0xc883952c +#define DDR1_PCTL_TMOD 0xc8839530 +#define DDR1_PCTL_TEXSR 0xc883950c +#define DDR1_PCTL_TAL 0xc88394e4 +#define DDR1_PCTL_TRTP 0xc8839500 +#define DDR1_PCTL_TCKSRX 0xc8839528 +#define DDR1_PCTL_TRTW 0xc88394e0 +#define DDR1_PCTL_TCWL 0xc88394ec +#define DDR1_PCTL_TWR 0xc8839504 +#define DDR1_PCTL_TCL 0xc88394e8 +#define DDR1_PCTL_TDQS 0xc8839520 +#define DDR1_PCTL_TRSTH 0xc88394c8 +#define DDR1_PCTL_TRCD 0xc88394f8 +#define DDR1_PCTL_TXP 0xc8839510 +#define DDR1_PCTL_TOGCNT100N 0xc88394cc +#define DDR1_PCTL_TMRD 0xc88394d4 +#define DDR1_PCTL_TRSTL 0xc8839534 +#define DDR1_PCTL_TREFI 0xc88394d0 +#define DDR1_PCTL_TRAS 0xc88394f0 +#define DDR1_PCTL_TREFI_MEM_DDR3 0xc8839548 +#define DDR1_PCTL_TWTR 0xc8839508 +#define DDR1_PCTL_TRC 0xc88394f4 +#define DDR1_PCTL_TRFC 0xc88394d8 +#define DDR1_PCTL_TMRR 0xc883953c +#define DDR1_PCTL_TCKESR 0xc8839540 +#define DDR1_PCTL_TZQCL 0xc8839538 +#define DDR1_PCTL_TRRD 0xc88394fc +#define DDR1_PCTL_TRP 0xc88394dc +#define DDR1_PCTL_TZQCS 0xc8839518 +#define DDR1_PCTL_TXPDLL 0xc8839514 +#define DDR1_PCTL_ECCCFG 0xc8839580 +#define DDR1_PCTL_ECCLOG 0xc883958c +#define DDR1_PCTL_ECCCLR 0xc8839588 +#define DDR1_PCTL_ECCTST 0xc8839584 +#define DDR1_PCTL_DTUWD0 0xc8839610 +#define DDR1_PCTL_DTUWD1 0xc8839614 +#define DDR1_PCTL_DTUWACTL 0xc8839600 +#define DDR1_PCTL_DTULFSRRD 0xc8839638 +#define DDR1_PCTL_DTUWD2 0xc8839618 +#define DDR1_PCTL_DTUWD3 0xc883961c +#define DDR1_PCTL_DTULFSRWD 0xc8839634 +#define DDR1_PCTL_DTURACTL 0xc8839604 +#define DDR1_PCTL_DTUWDM 0xc8839620 +#define DDR1_PCTL_DTURD0 0xc8839624 +#define DDR1_PCTL_DTURD1 0xc8839628 +#define DDR1_PCTL_DTURD2 0xc883962c +#define DDR1_PCTL_DTURD3 0xc8839630 +#define DDR1_PCTL_DTUCFG 0xc8839608 +#define DDR1_PCTL_DTUEAF 0xc883963c +#define DDR1_PCTL_DTUECTL 0xc883960c +#define DDR1_PCTL_DFIODTCFG1 0xc8839648 +#define DDR1_PCTL_DFITCTRLDELAY 0xc8839640 +#define DDR1_PCTL_DFIODTRANKMAP 0xc883964c +#define DDR1_PCTL_DFIODTCFG 0xc8839644 +#define DDR1_PCTL_DFITPHYWRLAT 0xc8839654 +#define DDR1_PCTL_DFITPHYWRDATA 0xc8839650 +#define DDR1_PCTL_DFITRDDATAEN 0xc8839660 +#define DDR1_PCTL_DFITPHYRDLAT 0xc8839664 +#define DDR1_PCTL_DFITREFMSKI 0xc8839694 +#define DDR1_PCTL_DFITPHYUPDTYPE0 0xc8839670 +#define DDR1_PCTL_DFITPHYUPDTYPE1 0xc8839674 +#define DDR1_PCTL_DFITCTRLUPDDLY 0xc8839688 +#define DDR1_PCTL_DFITPHYUPDTYPE2 0xc8839678 +#define DDR1_PCTL_DFITCTRLUPDMIN 0xc8839680 +#define DDR1_PCTL_DFITPHYUPDTYPE3 0xc883967c +#define DDR1_PCTL_DFIUPDCFG 0xc8839690 +#define DDR1_PCTL_DFITCTRLUPDMAX 0xc8839684 +#define DDR1_PCTL_DFITCTRLUPDI 0xc8839698 +#define DDR1_PCTL_DFITRRDLVLEN 0xc88396b8 +#define DDR1_PCTL_DFITRSTAT0 0xc88396b0 +#define DDR1_PCTL_DFITRWRLVLEN 0xc88396b4 +#define DDR1_PCTL_DFITRCFG0 0xc88396ac +#define DDR1_PCTL_DFITRRDLVLGATEEN 0xc88396bc +#define DDR1_PCTL_DFISTSTAT0 0xc88396c0 +#define DDR1_PCTL_DFISTPARLOG 0xc88396e0 +#define DDR1_PCTL_DFITDRAMCLKEN 0xc88396d0 +#define DDR1_PCTL_DFISTPARCLR 0xc88396dc +#define DDR1_PCTL_DFISTCFG0 0xc88396c4 +#define DDR1_PCTL_DFISTCFG1 0xc88396c8 +#define DDR1_PCTL_DFISTCFG2 0xc88396d8 +#define DDR1_PCTL_DFITDRAMCLKDIS 0xc88396d4 +#define DDR1_PCTL_DFILPCFG0 0xc88396f0 +#define DDR1_PCTL_DFITRWRLVLDELAY0 0xc8839718 +#define DDR1_PCTL_DFITRWRLVLDELAY1 0xc883971c +#define DDR1_PCTL_DFITRWRLVLDELAY2 0xc8839720 +#define DDR1_PCTL_DFITRRDLVLRESP0 0xc883970c +#define DDR1_PCTL_DFITRRDLVLRESP1 0xc8839710 +#define DDR1_PCTL_DFITRRDLVLRESP2 0xc8839714 +#define DDR1_PCTL_DFITRWRLVLRESP0 0xc8839700 +#define DDR1_PCTL_DFITRRDLVLDELAY0 0xc8839724 +#define DDR1_PCTL_DFITRRDLVLDELAY1 0xc8839728 +#define DDR1_PCTL_DFITRWRLVLRESP1 0xc8839704 +#define DDR1_PCTL_DFITRRDLVLDELAY2 0xc883972c +#define DDR1_PCTL_DFITRWRLVLRESP2 0xc8839708 +#define DDR1_PCTL_DFITRRDLVLGATEDELAY0 0xc8839730 +#define DDR1_PCTL_DFITRCMD 0xc883973c +#define DDR1_PCTL_DFITRRDLVLGATEDELAY1 0xc8839734 +#define DDR1_PCTL_DFITRRDLVLGATEDELAY2 0xc8839738 +#define DDR1_PCTL_IPTR 0xc88397fc +#define DDR1_PCTL_IPVR 0xc88397f8 diff --git a/plat/gxb/ddr/ddr_pub_define.h b/plat/gxb/ddr/ddr_pub_define.h new file mode 100644 index 0000000..471965d --- /dev/null +++ b/plat/gxb/ddr/ddr_pub_define.h @@ -0,0 +1,305 @@ + +/* + * arch/arm/cpu/armv8/common/firmware/plat/gxb/ddr/ddr_pub_define.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#define DDR0_PUB_REG_BASE 0xc8836000 + +#define DDR0_PUB_RIDR (DDR0_PUB_REG_BASE+(0x00<<2)) +#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2)) +#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE+(0x02<<2)) +#define DDR0_PUB_PGCR1 (DDR0_PUB_REG_BASE+(0x03<<2)) +#define DDR0_PUB_PGCR2 (DDR0_PUB_REG_BASE+(0x04<<2)) +#define DDR0_PUB_PGCR3 (DDR0_PUB_REG_BASE+(0x05<<2)) +#define DDR0_PUB_PGSR0 (DDR0_PUB_REG_BASE+(0x06<<2)) +#define DDR0_PUB_PGSR1 (DDR0_PUB_REG_BASE+(0x07<<2)) +#define DDR0_PUB_PLLCR (DDR0_PUB_REG_BASE+(0x08<<2)) +#define DDR0_PUB_PTR0 (DDR0_PUB_REG_BASE+(0x09<<2)) +#define DDR0_PUB_PTR1 (DDR0_PUB_REG_BASE+(0x0A<<2)) +#define DDR0_PUB_PTR2 (DDR0_PUB_REG_BASE+(0x0B<<2)) +#define DDR0_PUB_PTR3 (DDR0_PUB_REG_BASE+(0x0C<<2)) +#define DDR0_PUB_PTR4 (DDR0_PUB_REG_BASE+(0x0D<<2)) +#define DDR0_PUB_ACMDLR (DDR0_PUB_REG_BASE+(0x0E<<2)) +#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE+(0x0F<<2)) +#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE+(0x10<<2)) +#define DDR0_PUB_ACBDLR1 (DDR0_PUB_REG_BASE+(0x11<<2)) +#define DDR0_PUB_ACBDLR2 (DDR0_PUB_REG_BASE+(0x12<<2)) +#define DDR0_PUB_ACBDLR3 (DDR0_PUB_REG_BASE+(0x13<<2)) +#define DDR0_PUB_ACBDLR4 (DDR0_PUB_REG_BASE+(0x14<<2)) +#define DDR0_PUB_ACBDLR5 (DDR0_PUB_REG_BASE+(0x15<<2)) +#define DDR0_PUB_ACBDLR6 (DDR0_PUB_REG_BASE+(0x16<<2)) +#define DDR0_PUB_ACBDLR7 (DDR0_PUB_REG_BASE+(0x17<<2)) +#define DDR0_PUB_ACBDLR8 (DDR0_PUB_REG_BASE+(0x18<<2)) +#define DDR0_PUB_ACBDLR9 (DDR0_PUB_REG_BASE+(0x19<<2)) +#define DDR0_PUB_ACIOCR0 (DDR0_PUB_REG_BASE+(0x1A<<2)) +#define DDR0_PUB_ACIOCR1 (DDR0_PUB_REG_BASE+(0x1B<<2)) +#define DDR0_PUB_ACIOCR2 (DDR0_PUB_REG_BASE+(0x1C<<2)) +#define DDR0_PUB_ACIOCR3 (DDR0_PUB_REG_BASE+(0x1D<<2)) +#define DDR0_PUB_ACIOCR4 (DDR0_PUB_REG_BASE+(0x1E<<2)) +#define DDR0_PUB_ACIOCR5 (DDR0_PUB_REG_BASE+(0x1F<<2)) +#define DDR0_PUB_DXCCR (DDR0_PUB_REG_BASE+(0x20<<2)) +#define DDR0_PUB_DSGCR (DDR0_PUB_REG_BASE+(0x21<<2)) +#define DDR0_PUB_DCR (DDR0_PUB_REG_BASE+(0x22<<2)) +#define DDR0_PUB_DTPR0 (DDR0_PUB_REG_BASE+(0x23<<2)) +#define DDR0_PUB_DTPR1 (DDR0_PUB_REG_BASE+(0x24<<2)) +#define DDR0_PUB_DTPR2 (DDR0_PUB_REG_BASE+(0x25<<2)) +#define DDR0_PUB_DTPR3 (DDR0_PUB_REG_BASE+(0x26<<2)) +#define DDR0_PUB_MR0 (DDR0_PUB_REG_BASE+(0x27<<2)) +#define DDR0_PUB_MR1 (DDR0_PUB_REG_BASE+(0x28<<2)) +#define DDR0_PUB_MR2 (DDR0_PUB_REG_BASE+(0x29<<2)) +#define DDR0_PUB_MR3 (DDR0_PUB_REG_BASE+(0x2A<<2)) +#define DDR0_PUB_ODTCR (DDR0_PUB_REG_BASE+(0x2B<<2)) +#define DDR0_PUB_DTCR (DDR0_PUB_REG_BASE+(0x2C<<2)) +#define DDR0_PUB_DTAR0 (DDR0_PUB_REG_BASE+(0x2D<<2)) +#define DDR0_PUB_DTAR1 (DDR0_PUB_REG_BASE+(0x2E<<2)) +#define DDR0_PUB_DTAR2 (DDR0_PUB_REG_BASE+(0x2F<<2)) +#define DDR0_PUB_DTAR3 (DDR0_PUB_REG_BASE+(0x30<<2)) +#define DDR0_PUB_DTDR0 (DDR0_PUB_REG_BASE+(0x31<<2)) +#define DDR0_PUB_DTDR1 (DDR0_PUB_REG_BASE+(0x32<<2)) +#define DDR0_PUB_DTEDR0 (DDR0_PUB_REG_BASE+(0x33<<2)) +#define DDR0_PUB_DTEDR1 (DDR0_PUB_REG_BASE+(0x34<<2)) +#define DDR0_PUB_RDIMMGCR0 (DDR0_PUB_REG_BASE+(0x35<<2)) +#define DDR0_PUB_RDIMMGCR1 (DDR0_PUB_REG_BASE+(0x36<<2)) +#define DDR0_PUB_RDIMMCR0 (DDR0_PUB_REG_BASE+(0x37<<2)) +#define DDR0_PUB_RDIMMCR1 (DDR0_PUB_REG_BASE+(0x38<<2)) +#define DDR0_PUB_GPR0 (DDR0_PUB_REG_BASE+(0x39<<2)) +#define DDR0_PUB_GPR1 (DDR0_PUB_REG_BASE+(0x3A<<2)) +#define DDR0_PUB_CATR0 (DDR0_PUB_REG_BASE+(0x3B<<2)) +#define DDR0_PUB_CATR1 (DDR0_PUB_REG_BASE+(0x3C<<2)) +//0x3D-32'h5F reserved) +#define DDR0_PUB_DCUAR (DDR0_PUB_REG_BASE+(0x60<<2)) +#define DDR0_PUB_DCUDR (DDR0_PUB_REG_BASE+(0x61<<2)) +#define DDR0_PUB_DCURR (DDR0_PUB_REG_BASE+(0x62<<2)) +#define DDR0_PUB_DCULR (DDR0_PUB_REG_BASE+(0x63<<2)) +#define DDR0_PUB_DCUGCR (DDR0_PUB_REG_BASE+(0x64<<2)) +#define DDR0_PUB_DCUTPR (DDR0_PUB_REG_BASE+(0x65<<2)) +#define DDR0_PUB_DCUSR0 (DDR0_PUB_REG_BASE+(0x66<<2)) +#define DDR0_PUB_DCUSR1 (DDR0_PUB_REG_BASE+(0x67<<2)) +//0x68-32'h6F reserved) +#define DDR0_PUB_BISTRR (DDR0_PUB_REG_BASE+(0x70<<2)) +#define DDR0_PUB_BISTWCR (DDR0_PUB_REG_BASE+(0x71<<2)) +#define DDR0_PUB_BISTMSKR0 (DDR0_PUB_REG_BASE+(0x72<<2)) +#define DDR0_PUB_BISTMSKR1 (DDR0_PUB_REG_BASE+(0x73<<2)) +#define DDR0_PUB_BISTMSKR2 (DDR0_PUB_REG_BASE+(0x74<<2)) +#define DDR0_PUB_BISTLSR (DDR0_PUB_REG_BASE+(0x75<<2)) +#define DDR0_PUB_BISTAR0 (DDR0_PUB_REG_BASE+(0x76<<2)) +#define DDR0_PUB_BISTAR1 (DDR0_PUB_REG_BASE+(0x77<<2)) +#define DDR0_PUB_BISTAR2 (DDR0_PUB_REG_BASE+(0x78<<2)) +#define DDR0_PUB_BISTUDPR (DDR0_PUB_REG_BASE+(0x79<<2)) +#define DDR0_PUB_BISTGSR (DDR0_PUB_REG_BASE+(0x7A<<2)) +#define DDR0_PUB_BISTWER (DDR0_PUB_REG_BASE+(0x7B<<2)) +#define DDR0_PUB_BISTBER0 (DDR0_PUB_REG_BASE+(0x7C<<2)) +#define DDR0_PUB_BISTBER1 (DDR0_PUB_REG_BASE+(0x7D<<2)) +#define DDR0_PUB_BISTBER2 (DDR0_PUB_REG_BASE+(0x7E<<2)) +#define DDR0_PUB_BISTBER3 (DDR0_PUB_REG_BASE+(0x7F<<2)) +#define DDR0_PUB_BISTWCSR (DDR0_PUB_REG_BASE+(0x80<<2)) +#define DDR0_PUB_BISTFWR0 (DDR0_PUB_REG_BASE+(0x81<<2)) +#define DDR0_PUB_BISTFWR1 (DDR0_PUB_REG_BASE+(0x82<<2)) +#define DDR0_PUB_BISTFWR2 (DDR0_PUB_REG_BASE+(0x83<<2)) +//0x84-32'h8D reserved) +#define DDR0_PUB_IOVCR0 (DDR0_PUB_REG_BASE+(0x8E<<2)) +#define DDR0_PUB_IOVCR1 (DDR0_PUB_REG_BASE+(0x8F<<2)) +#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2)) +#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2)) +#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2)) +#define DDR0_PUB_ZQ0SR (DDR0_PUB_REG_BASE+(0x93<<2)) +//0x94 reserved) +#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2)) +#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2)) +#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2)) +//0x98 reserved) +#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2)) +#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2)) +#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2)) +//0x9c reserved) +#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2)) +#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2)) +#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2)) +#define DDR0_PUB_DX0GCR0 (DDR0_PUB_REG_BASE+(0xA0<<2)) +#define DDR0_PUB_DX0GCR1 (DDR0_PUB_REG_BASE+(0xA1<<2)) +#define DDR0_PUB_DX0GCR2 (DDR0_PUB_REG_BASE+(0xA2<<2)) +#define DDR0_PUB_DX0GCR3 (DDR0_PUB_REG_BASE+(0xA3<<2)) +#define DDR0_PUB_DX0GSR0 (DDR0_PUB_REG_BASE+(0xA4<<2)) +#define DDR0_PUB_DX0GSR1 (DDR0_PUB_REG_BASE+(0xA5<<2)) +#define DDR0_PUB_DX0GSR2 (DDR0_PUB_REG_BASE+(0xA6<<2)) +#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE+(0xA7<<2)) +#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE+(0xA8<<2)) +#define DDR0_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE+(0xA9<<2)) +#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE+(0xAA<<2)) +#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE+(0xAB<<2)) +#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE+(0xAC<<2)) +#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE+(0xAD<<2)) +#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE+(0xAE<<2)) +#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE+(0xAF<<2)) +#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE+(0xB0<<2)) +#define DDR0_PUB_DX0MDLR (DDR0_PUB_REG_BASE+(0xB1<<2)) +#define DDR0_PUB_DX0GTR (DDR0_PUB_REG_BASE+(0xB2<<2)) +//0xB4-32'hBF reserved) +#define DDR0_PUB_DX1GCR0 (DDR0_PUB_REG_BASE+(0xC0<<2)) +#define DDR0_PUB_DX1GCR1 (DDR0_PUB_REG_BASE+(0xC1<<2)) +#define DDR0_PUB_DX1GCR2 (DDR0_PUB_REG_BASE+(0xC2<<2)) +#define DDR0_PUB_DX1GCR3 (DDR0_PUB_REG_BASE+(0xC3<<2)) +#define DDR0_PUB_DX1GSR0 (DDR0_PUB_REG_BASE+(0xC4<<2)) +#define DDR0_PUB_DX1GSR1 (DDR0_PUB_REG_BASE+(0xC5<<2)) +#define DDR0_PUB_DX1GSR2 (DDR0_PUB_REG_BASE+(0xC6<<2)) +#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE+(0xC7<<2)) +#define DDR0_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE+(0xC8<<2)) +#define DDR0_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE+(0xC9<<2)) +#define DDR0_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE+(0xCA<<2)) +#define DDR0_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE+(0xCB<<2)) +#define DDR0_PUB_DX1BDLR5 (DDR0_PUB_REG_BASE+(0xCC<<2)) +#define DDR0_PUB_DX1BDLR6 (DDR0_PUB_REG_BASE+(0xCD<<2)) +#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE+(0xCE<<2)) +#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE+(0xCF<<2)) +#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE+(0xD0<<2)) +#define DDR0_PUB_DX1MDLR (DDR0_PUB_REG_BASE+(0xD1<<2)) +#define DDR0_PUB_DX1GTR (DDR0_PUB_REG_BASE+(0xD2<<2)) +#define DDR0_PUB_DX2GCR0 (DDR0_PUB_REG_BASE+(0xE0<<2)) +#define DDR0_PUB_DX2GCR1 (DDR0_PUB_REG_BASE+(0xE1<<2)) +#define DDR0_PUB_DX2GCR2 (DDR0_PUB_REG_BASE+(0xE2<<2)) +#define DDR0_PUB_DX2GCR3 (DDR0_PUB_REG_BASE+(0xE3<<2)) +#define DDR0_PUB_DX2GSR0 (DDR0_PUB_REG_BASE+(0xE4<<2)) +#define DDR0_PUB_DX2GSR1 (DDR0_PUB_REG_BASE+(0xE5<<2)) +#define DDR0_PUB_DX2GSR2 (DDR0_PUB_REG_BASE+(0xE6<<2)) +#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE+(0xE7<<2)) +#define DDR0_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE+(0xE8<<2)) +#define DDR0_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE+(0xE9<<2)) +#define DDR0_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE+(0xEA<<2)) +#define DDR0_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE+(0xEB<<2)) +#define DDR0_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE+(0xEC<<2)) +#define DDR0_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE+(0xED<<2)) +#define DDR0_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE+(0xEE<<2)) +#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE+(0xEF<<2)) +#define DDR0_PUB_DX2LCDLR2 (DDR0_PUB_REG_BASE+(0xF0<<2)) +#define DDR0_PUB_DX2MDLR (DDR0_PUB_REG_BASE+(0xF1<<2)) +#define DDR0_PUB_DX2GTR (DDR0_PUB_REG_BASE+(0xF2<<2)) +#define DDR0_PUB_DX3GCR0 (DDR0_PUB_REG_BASE+(0x100<<2)) +#define DDR0_PUB_DX3GCR1 (DDR0_PUB_REG_BASE+(0x101<<2)) +#define DDR0_PUB_DX3GCR2 (DDR0_PUB_REG_BASE+(0x102<<2)) +#define DDR0_PUB_DX3GCR3 (DDR0_PUB_REG_BASE+(0x103<<2)) +#define DDR0_PUB_DX3GSR0 (DDR0_PUB_REG_BASE+(0x104<<2)) +#define DDR0_PUB_DX3GSR1 (DDR0_PUB_REG_BASE+(0x105<<2)) +#define DDR0_PUB_DX3GSR2 (DDR0_PUB_REG_BASE+(0x106<<2)) +#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE+(0x107<<2)) +#define DDR0_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE+(0x108<<2)) +#define DDR0_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE+(0x109<<2)) +#define DDR0_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE+(0x10A<<2)) +#define DDR0_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE+(0x10B<<2)) +#define DDR0_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE+(0x10C<<2)) +#define DDR0_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE+(0x10D<<2)) +#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE+(0x10E<<2)) +#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE+(0x10F<<2)) +#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE+(0x110<<2)) +#define DDR0_PUB_DX3MDLR (DDR0_PUB_REG_BASE+(0x111<<2)) +#define DDR0_PUB_DX3GTR (DDR0_PUB_REG_BASE+(0x112<<2)) +#define DDR0_PUB_DX4GCR0 (DDR0_PUB_REG_BASE+(0x120<<2)) +#define DDR0_PUB_DX4GCR1 (DDR0_PUB_REG_BASE+(0x121<<2)) +#define DDR0_PUB_DX4GCR2 (DDR0_PUB_REG_BASE+(0x122<<2)) +#define DDR0_PUB_DX4GCR3 (DDR0_PUB_REG_BASE+(0x123<<2)) +#define DDR0_PUB_DX4GSR0 (DDR0_PUB_REG_BASE+(0x124<<2)) +#define DDR0_PUB_DX4GSR1 (DDR0_PUB_REG_BASE+(0x125<<2)) +#define DDR0_PUB_DX4GSR2 (DDR0_PUB_REG_BASE+(0x126<<2)) +#define DDR0_PUB_DX4BDLR0 (DDR0_PUB_REG_BASE+(0x127<<2)) +#define DDR0_PUB_DX4BDLR1 (DDR0_PUB_REG_BASE+(0x128<<2)) +#define DDR0_PUB_DX4BDLR2 (DDR0_PUB_REG_BASE+(0x129<<2)) +#define DDR0_PUB_DX4BDLR3 (DDR0_PUB_REG_BASE+(0x12A<<2)) +#define DDR0_PUB_DX4BDLR4 (DDR0_PUB_REG_BASE+(0x12B<<2)) +#define DDR0_PUB_DX4BDLR5 (DDR0_PUB_REG_BASE+(0x12C<<2)) +#define DDR0_PUB_DX4BDLR6 (DDR0_PUB_REG_BASE+(0x12D<<2)) +#define DDR0_PUB_DX4LCDLR0 (DDR0_PUB_REG_BASE+(0x12E<<2)) +#define DDR0_PUB_DX4LCDLR1 (DDR0_PUB_REG_BASE+(0x12F<<2)) +#define DDR0_PUB_DX4LCDLR2 (DDR0_PUB_REG_BASE+(0x130<<2)) +#define DDR0_PUB_DX4MDLR (DDR0_PUB_REG_BASE+(0x131<<2)) +#define DDR0_PUB_DX4GTR (DDR0_PUB_REG_BASE+(0x132<<2)) +#define DDR0_PUB_DX5GCR0 (DDR0_PUB_REG_BASE+(0x140<<2)) +#define DDR0_PUB_DX5GCR1 (DDR0_PUB_REG_BASE+(0x141<<2)) +#define DDR0_PUB_DX5GCR2 (DDR0_PUB_REG_BASE+(0x142<<2)) +#define DDR0_PUB_DX5GCR3 (DDR0_PUB_REG_BASE+(0x143<<2)) +#define DDR0_PUB_DX5GSR0 (DDR0_PUB_REG_BASE+(0x144<<2)) +#define DDR0_PUB_DX5GSR1 (DDR0_PUB_REG_BASE+(0x145<<2)) +#define DDR0_PUB_DX5GSR2 (DDR0_PUB_REG_BASE+(0x146<<2)) +#define DDR0_PUB_DX5BDLR0 (DDR0_PUB_REG_BASE+(0x147<<2)) +#define DDR0_PUB_DX5BDLR1 (DDR0_PUB_REG_BASE+(0x148<<2)) +#define DDR0_PUB_DX5BDLR2 (DDR0_PUB_REG_BASE+(0x149<<2)) +#define DDR0_PUB_DX5BDLR3 (DDR0_PUB_REG_BASE+(0x14A<<2)) +#define DDR0_PUB_DX5BDLR4 (DDR0_PUB_REG_BASE+(0x14B<<2)) +#define DDR0_PUB_DX5BDLR5 (DDR0_PUB_REG_BASE+(0x14C<<2)) +#define DDR0_PUB_DX5BDLR6 (DDR0_PUB_REG_BASE+(0x14D<<2)) +#define DDR0_PUB_DX5LCDLR0 (DDR0_PUB_REG_BASE+(0x14E<<2)) +#define DDR0_PUB_DX5LCDLR1 (DDR0_PUB_REG_BASE+(0x14F<<2)) +#define DDR0_PUB_DX5LCDLR2 (DDR0_PUB_REG_BASE+(0x150<<2)) +#define DDR0_PUB_DX5MDLR (DDR0_PUB_REG_BASE+(0x151<<2)) +#define DDR0_PUB_DX5GTR (DDR0_PUB_REG_BASE+(0x152<<2)) +#define DDR0_PUB_DX6GCR0 (DDR0_PUB_REG_BASE+(0x160<<2)) +#define DDR0_PUB_DX6GCR1 (DDR0_PUB_REG_BASE+(0x161<<2)) +#define DDR0_PUB_DX6GCR2 (DDR0_PUB_REG_BASE+(0x162<<2)) +#define DDR0_PUB_DX6GCR3 (DDR0_PUB_REG_BASE+(0x163<<2)) +#define DDR0_PUB_DX6GSR0 (DDR0_PUB_REG_BASE+(0x164<<2)) +#define DDR0_PUB_DX6GSR1 (DDR0_PUB_REG_BASE+(0x165<<2)) +#define DDR0_PUB_DX6GSR2 (DDR0_PUB_REG_BASE+(0x166<<2)) +#define DDR0_PUB_DX6BDLR0 (DDR0_PUB_REG_BASE+(0x167<<2)) +#define DDR0_PUB_DX6BDLR1 (DDR0_PUB_REG_BASE+(0x168<<2)) +#define DDR0_PUB_DX6BDLR2 (DDR0_PUB_REG_BASE+(0x169<<2)) +#define DDR0_PUB_DX6BDLR3 (DDR0_PUB_REG_BASE+(0x16A<<2)) +#define DDR0_PUB_DX6BDLR4 (DDR0_PUB_REG_BASE+(0x16B<<2)) +#define DDR0_PUB_DX6BDLR5 (DDR0_PUB_REG_BASE+(0x16C<<2)) +#define DDR0_PUB_DX6BDLR6 (DDR0_PUB_REG_BASE+(0x16D<<2)) +#define DDR0_PUB_DX6LCDLR0 (DDR0_PUB_REG_BASE+(0x16E<<2)) +#define DDR0_PUB_DX6LCDLR1 (DDR0_PUB_REG_BASE+(0x16F<<2)) +#define DDR0_PUB_DX6LCDLR2 (DDR0_PUB_REG_BASE+(0x170<<2)) +#define DDR0_PUB_DX6MDLR (DDR0_PUB_REG_BASE+(0x171<<2)) +#define DDR0_PUB_DX6GTR (DDR0_PUB_REG_BASE+(0x172<<2)) +#define DDR0_PUB_DX7GCR0 (DDR0_PUB_REG_BASE+(0x180<<2)) +#define DDR0_PUB_DX7GCR1 (DDR0_PUB_REG_BASE+(0x181<<2)) +#define DDR0_PUB_DX7GCR2 (DDR0_PUB_REG_BASE+(0x182<<2)) +#define DDR0_PUB_DX7GCR3 (DDR0_PUB_REG_BASE+(0x183<<2)) +#define DDR0_PUB_DX7GSR0 (DDR0_PUB_REG_BASE+(0x184<<2)) +#define DDR0_PUB_DX7GSR1 (DDR0_PUB_REG_BASE+(0x185<<2)) +#define DDR0_PUB_DX7GSR2 (DDR0_PUB_REG_BASE+(0x186<<2)) +#define DDR0_PUB_DX7BDLR0 (DDR0_PUB_REG_BASE+(0x187<<2)) +#define DDR0_PUB_DX7BDLR1 (DDR0_PUB_REG_BASE+(0x188<<2)) +#define DDR0_PUB_DX7BDLR2 (DDR0_PUB_REG_BASE+(0x189<<2)) +#define DDR0_PUB_DX7BDLR3 (DDR0_PUB_REG_BASE+(0x18A<<2)) +#define DDR0_PUB_DX7BDLR4 (DDR0_PUB_REG_BASE+(0x18B<<2)) +#define DDR0_PUB_DX7BDLR5 (DDR0_PUB_REG_BASE+(0x18C<<2)) +#define DDR0_PUB_DX7BDLR6 (DDR0_PUB_REG_BASE+(0x18D<<2)) +#define DDR0_PUB_DX7LCDLR0 (DDR0_PUB_REG_BASE+(0x18E<<2)) +#define DDR0_PUB_DX7LCDLR1 (DDR0_PUB_REG_BASE+(0x18F<<2)) +#define DDR0_PUB_DX7LCDLR2 (DDR0_PUB_REG_BASE+(0x190<<2)) +#define DDR0_PUB_DX7MDLR (DDR0_PUB_REG_BASE+(0x191<<2)) +#define DDR0_PUB_DX7GTR (DDR0_PUB_REG_BASE+(0x192<<2)) +#define DDR0_PUB_DX8GCR0 (DDR0_PUB_REG_BASE+(0x1A0<<2)) +#define DDR0_PUB_DX8GCR1 (DDR0_PUB_REG_BASE+(0x1A1<<2)) +#define DDR0_PUB_DX8GCR2 (DDR0_PUB_REG_BASE+(0x1A2<<2)) +#define DDR0_PUB_DX8GCR3 (DDR0_PUB_REG_BASE+(0x1A3<<2)) +#define DDR0_PUB_DX8GSR0 (DDR0_PUB_REG_BASE+(0x1A4<<2)) +#define DDR0_PUB_DX8GSR1 (DDR0_PUB_REG_BASE+(0x1A5<<2)) +#define DDR0_PUB_DX8GSR2 (DDR0_PUB_REG_BASE+(0x1A6<<2)) +#define DDR0_PUB_DX8BDLR0 (DDR0_PUB_REG_BASE+(0x1A7<<2)) +#define DDR0_PUB_DX8BDLR1 (DDR0_PUB_REG_BASE+(0x1A8<<2)) +#define DDR0_PUB_DX8BDLR2 (DDR0_PUB_REG_BASE+(0x1A9<<2)) +#define DDR0_PUB_DX8BDLR3 (DDR0_PUB_REG_BASE+(0x1AA<<2)) +#define DDR0_PUB_DX8BDLR4 (DDR0_PUB_REG_BASE+(0x1AB<<2)) +#define DDR0_PUB_DX8BDLR5 (DDR0_PUB_REG_BASE+(0x1AC<<2)) +#define DDR0_PUB_DX8BDLR6 (DDR0_PUB_REG_BASE+(0x1AD<<2)) +#define DDR0_PUB_DX8LCDLR0 (DDR0_PUB_REG_BASE+(0x1AE<<2)) +#define DDR0_PUB_DX8LCDLR1 (DDR0_PUB_REG_BASE+(0x1AF<<2)) +#define DDR0_PUB_DX8LCDLR2 (DDR0_PUB_REG_BASE+(0x1B0<<2)) +#define DDR0_PUB_DX8MDLR (DDR0_PUB_REG_BASE+(0x1B1<<2)) +#define DDR0_PUB_DX8GTR (DDR0_PUB_REG_BASE+(0x1B2<<2)) diff --git a/plat/gxb/ddr/dmc_define.h b/plat/gxb/ddr/dmc_define.h new file mode 100644 index 0000000..20a607e --- /dev/null +++ b/plat/gxb/ddr/dmc_define.h @@ -0,0 +1,372 @@ + +/* + * arch/arm/cpu/armv8/common/firmware/plat/gxb/ddr/dmc_define.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#define DMC_REG_BASE 0xc8838000 + +#define DMC_REQ_CTRL (DMC_REG_BASE + (0x00 <<2 )) + //bit 11. enable dmc request of chan 11. Audio + //bit 10. enable dmc request of chan 10. Device. + //bit 9. enable dmc request of chan 9. VDEC2 + //bit 8. enable dmc request of chan 8. HCODEC + //bit 7. enable dmc request of chan 7. VDEC + //bit 6. enable dmc request of chan 6. VDIN + //bit 5. enable dmc request of chan 5. VDISP2 + //bit 4. enable dmc request of chan 4. VDISP + //bit 3. enable dmc request of chan 3. Mali + //bit 2. enable dmc request of chan 2. Mali + //bit 1. enable dmc request of chan 1. Mali + //bit 0. enable dmc request of chan 0. A9 +#define DMC_SOFT_RST (DMC_REG_BASE + (0x01 <<2 )) +#define DMC_SOFT_RST1 (DMC_REG_BASE + (0x02 <<2 )) +#define DMC_RST_STS (DMC_REG_BASE + (0x03 <<2 )) +#define DMC_RST_STS1 (DMC_REG_BASE + (0x04 <<2 )) +#define DMC_VERSION (DMC_REG_BASE + (0x05 <<2 )) + //read only default = 1. + +#define DMC_RAM_PD (DMC_REG_BASE + (0x11 <<2 )) + +#define DC_CAV_LUT_DATAL (DMC_REG_BASE + (0x12 <<2 )) + //low 32 bits of canvas data which need to be configured to canvas memory. +#define DC_CAV_LUT_DATAH (DMC_REG_BASE + (0x13 <<2 )) + //high 32bits of cavnas data which need to be configured to canvas memory. +#define DC_CAV_LUT_ADDR (DMC_REG_BASE + (0x14 <<2 )) + //bit 9:8. write 9:8 2'b10. the canvas data will saved in canvas memory with addres 7:0. + //bit 7:0. canvas address. +#define DC_CAV_LUT_RDATAL (DMC_REG_BASE + (0x15 <<2 )) +#define DC_CAV_LUT_RDATAH (DMC_REG_BASE + (0x16 <<2 )) +#define DMC_2ARB_CTRL (DMC_REG_BASE + (0x20 <<2 )) + +#define DMC_REFR_CTRL1 (DMC_REG_BASE + (0x23 <<2 )) + //bit23:16 tRFC waiting time, when hold nif command after refresh. + //bit 9 after refresh, hold nif command enable + //bit 8 when refresh req, hold nif command enable + //bit 7 dmc to control auto_refresh enable + //bit 6:4 refresh number per refresh cycle.. + //bit 3 pvt enable + //bit 2 zqc enable + //bit 1 ddr1 auto refresh dmc control select. + //bit 0 ddr0 auto refresh dmc control select. + +#define DMC_REFR_CTRL2 (DMC_REG_BASE + (0x24 <<2 )) + //bit 31:24 tZQCI + //bit 23:16 tPVTI + //bit 15:8 tREFI + //bit 7:0 t100ns + +#define DMC_PARB_CTRL (DMC_REG_BASE + (0x25 <<2 )) + //bit 17. default port1(MALI AXI port) urgent bit. + //bit 16 default port0(A9 AXI port ) urgent bit. + //bit 15:8 t_ugt_gap. when the consecutive urgent request granted over the t_ugt_wd times, we allow the number of non urgent request was granted by the port arbiter. + //bit 7:0. t_ugt_wd. + + +#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 )) + //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. + //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. + //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer. + //bit 19:16. qos monitor channel select. select one at one time only. + //bit 15:0. port select for the selected channel. +#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 )) + // qos_mon_clk_timer. How long to measure the bandwidth. + + +#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 )) + // at the test period, the whole MMC request time. +#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 )) + // at the test period, the whole MMC granted data cycles. 64bits unit. +#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 )) + // at the test period, the granted data cycles for the selected channel and ports. + +#define DMC_CLKG_CTRL0 (DMC_REG_BASE + (0x30 <<2 )) + //bit 29. enalbe auto clock gating for write rsp generation. + //bit 28. enalbe auto clock gating for read rsp generation. + //bit 27. enalbe auto clock gating for ddr1 read back data buffer. + //bit 26. enalbe auto clock gating for ddr0 read back data buffer. + //bit 25. enalbe auto clock gating for ddr1 command filter. + //bit 24. enalbe auto clock gating for ddr0 command filter. + //bit 23. enalbe auto clock gating for ddr1 write reorder buffer. + //bit 22. enalbe auto clock gating for ddr0 write reorder buffer. + //bit 21. enalbe auto clock gating for ddr1 write data buffer. + //bit 20. enalbe auto clock gating for ddr0 write data buffer. + //bit 19. enalbe auto clock gating for ddr1 read reorder buffer. + //bit 18. enalbe auto clock gating for ddr0 read reorder buffer. + //bit 17. enalbe auto clock gating for read canvas. + //bit 16. enalbe auto clock gating for write canvas. + //bit 15. enalbe auto clock gating for chan 15. + //bit 14. enalbe auto clock gating for chan 14. + //bit 13. enalbe auto clock gating for chan 13. + //bit 12. enalbe auto clock gating for chan 12. + //bit 11. enalbe auto clock gating for chan 11. + //bit 10. enalbe auto clock gating for chan 10. + //bit 9. enalbe auto clock gating for chan 9. + //bit 8. enalbe auto clock gating for chan 8. + //bit 7. enalbe auto clock gating for chan 7. + //bit 6. enalbe auto clock gating for chan 6. + //bit 5. enalbe auto clock gating for chan 5. + //bit 4. enalbe auto clock gating for chan 4. + //bit 3. enalbe auto clock gating for chan 3. + //bit 2. enalbe auto clock gating for chan 2. + //bit 1. enalbe auto clock gating for chan 1. + //bit 0. enalbe auto clock gating for chan 0. + +#define DMC_CLKG_CTRL1 (DMC_REG_BASE + (0x31 <<2 )) + //bit 29. force to disalbe the clock of write rsp generation. + //bit 28. force to disalbe the clock of read rsp generation. + //bit 27. force to disalbe the clock of ddr1 read back data buffer. + //bit 26. force to disalbe the clock of ddr0 read back data buffer. + //bit 25. force to disalbe the clock of ddr1 command filter. + //bit 24. force to disalbe the clock of ddr0 command filter. + //bit 23. force to disalbe the clock of ddr1 write reorder buffer. + //bit 22. force to disalbe the clock of ddr0 write reorder buffer. + //bit 21. force to disalbe the clock of ddr1 write data buffer. + //bit 20. force to disalbe the clock of ddr0 write data buffer. + //bit 19. force to disalbe the clock of ddr1 read reorder buffer. + //bit 18. force to disalbe the clock of ddr0 read reorder buffer. + //bit 17. force to disalbe the clock of read canvas. + //bit 16. force to disalbe the clock of write canvas. + //bit 15. force to disalbe the clock of chan 15. + //bit 14. force to disalbe the clock of chan 14. + //bit 13. force to disalbe the clock of chan 13. + //bit 12. force to disalbe the clock of chan 12. + //bit 11. force to disalbe the clock of chan 11. + //bit 10. force to disalbe the clock of chan 10. + //bit 9. force to disalbe the clock of chan 9. + //bit 8. force to disalbe the clock of chan 8. + //bit 7. force to disalbe the clock of chan 7. + //bit 6. force to disalbe the clock of chan 6. + //bit 5. force to disalbe the clock of chan 5. + //bit 4. force to disalbe the clock of chan 4. + //bit 3. force to disalbe the clock of chan 3. + //bit 2. force to disalbe the clock of chan 2. + //bit 1. force to disalbe the clock of chan 1. + //bit 0. force to disalbe the clock of chan 0. + + +#define DMC_CHAN_STS (DMC_REG_BASE + (0x32 <<2 )) + +#define DMC_CMD_FILTER_CTRL1 (DMC_REG_BASE + (0x40 <<2 )) + //bit 29:20 nugt read buf full access limit + //bit 19:10. ugt read access limit. + //bit 9:0 nugt read access limit + +#define DMC_CMD_FILTER_CTRL2 (DMC_REG_BASE + (0x41 <<2 )) + //bit 29:20 ugt read buf full access limit + //bit 9:0 nugt write access pending limit + //bit 19:10. ugt write access pending limit. + +#define DMC_CMD_FILTER_CTRL3 (DMC_REG_BASE + (0x42 <<2 )) + //bit 26:22 wbuf high level number + //bit 21:17 wbuf mid level number + //bit 16:12 wbuf low level number + //bit 11:8 rbuf high level number + //bit 7:4 rbuf middle level number + //bit 3:0 rbuf low level number + +#define DMC_CMD_FILTER_CTRL4 (DMC_REG_BASE + (0x43 <<2 )) + //bit 24:20. tHIT latency. page hit command latency for next same page not hit command. + //bit 19:15. tIDLE latency. page idle command latency for next same page not hit command. + //bit 14:10. tMISS latency. page miss command latency for next same page not hit command. + //bit 9:0. rbuf idle timer to let the wbuf output. +#define DMC_CMD_FILTER_CTRL5 (DMC_REG_BASE + ( 0x44 << 2)) + +#define DMC_CMD_BUFFER_CTRL (DMC_REG_BASE + (0x45 <<2 )) + //bit 30:25 total write buffer number. default 32. + //bit 24:20 total read buffer number. default 16. + //bit 19:10 ugt age limit. over this age limit, this read buffer would turn to super urgent. + //bit 9:0 nugt age limit. over this age limit, this read buffer would turn to super urgent. +#define DMC_PCTL_LP_CTRL (DMC_REG_BASE + ( 0x46 << 2)) + +#define DMC_AM0_CHAN_CTRL (DMC_REG_BASE + (0x60 <<2 )) +#define DMC_AM0_HOLD_CTRL (DMC_REG_BASE + (0x61 <<2 )) +#define DMC_AM0_QOS_INC (DMC_REG_BASE + (0x62 <<2 )) +#define DMC_AM0_QOS_INCBK (DMC_REG_BASE + (0x63 <<2 )) +#define DMC_AM0_QOS_DEC (DMC_REG_BASE + (0x64 <<2 )) +#define DMC_AM0_QOS_DECBK (DMC_REG_BASE + (0x65 <<2 )) +#define DMC_AM0_QOS_DIS (DMC_REG_BASE + (0x66 <<2 )) +#define DMC_AM0_QOS_DISBK (DMC_REG_BASE + (0x67 <<2 )) +#define DMC_AM0_QOS_CTRL0 (DMC_REG_BASE + (0x68 <<2 )) +#define DMC_AM0_QOS_CTRL1 (DMC_REG_BASE + (0x69 <<2 )) + +#define DMC_AM1_CHAN_CTRL (DMC_REG_BASE + (0x6a <<2 )) +#define DMC_AM1_HOLD_CTRL (DMC_REG_BASE + (0x6b <<2 )) +#define DMC_AM1_QOS_INC (DMC_REG_BASE + (0x6c <<2 )) +#define DMC_AM1_QOS_INCBK (DMC_REG_BASE + (0x6d <<2 )) +#define DMC_AM1_QOS_DEC (DMC_REG_BASE + (0x6e <<2 )) +#define DMC_AM1_QOS_DECBK (DMC_REG_BASE + (0x6f <<2 )) +#define DMC_AM1_QOS_DIS (DMC_REG_BASE + (0x70 <<2 )) +#define DMC_AM1_QOS_DISBK (DMC_REG_BASE + (0x71 <<2 )) +#define DMC_AM1_QOS_CTRL0 (DMC_REG_BASE + (0x72 <<2 )) +#define DMC_AM1_QOS_CTRL1 (DMC_REG_BASE + (0x73 <<2 )) + +#define DMC_AM2_CHAN_CTRL (DMC_REG_BASE + (0x74 <<2 )) +#define DMC_AM2_HOLD_CTRL (DMC_REG_BASE + (0x75 <<2 )) +#define DMC_AM2_QOS_INC (DMC_REG_BASE + (0x76 <<2 )) +#define DMC_AM2_QOS_INCBK (DMC_REG_BASE + (0x77 <<2 )) +#define DMC_AM2_QOS_DEC (DMC_REG_BASE + (0x78 <<2 )) +#define DMC_AM2_QOS_DECBK (DMC_REG_BASE + (0x79 <<2 )) +#define DMC_AM2_QOS_DIS (DMC_REG_BASE + (0x7a <<2 )) +#define DMC_AM2_QOS_DISBK (DMC_REG_BASE + (0x7b <<2 )) +#define DMC_AM2_QOS_CTRL0 (DMC_REG_BASE + (0x7c <<2 )) +#define DMC_AM2_QOS_CTRL1 (DMC_REG_BASE + (0x7d <<2 )) + +#define DMC_AM3_CHAN_CTRL (DMC_REG_BASE + (0x7e <<2 )) +#define DMC_AM3_HOLD_CTRL (DMC_REG_BASE + (0x7f <<2 )) +#define DMC_AM3_QOS_INC (DMC_REG_BASE + (0x80 <<2 )) +#define DMC_AM3_QOS_INCBK (DMC_REG_BASE + (0x81 <<2 )) +#define DMC_AM3_QOS_DEC (DMC_REG_BASE + (0x82 <<2 )) +#define DMC_AM3_QOS_DECBK (DMC_REG_BASE + (0x83 <<2 )) +#define DMC_AM3_QOS_DIS (DMC_REG_BASE + (0x84 <<2 )) +#define DMC_AM3_QOS_DISBK (DMC_REG_BASE + (0x85 <<2 )) +#define DMC_AM3_QOS_CTRL0 (DMC_REG_BASE + (0x86 <<2 )) +#define DMC_AM3_QOS_CTRL1 (DMC_REG_BASE + (0x87 <<2 )) + +#define DMC_AM4_CHAN_CTRL (DMC_REG_BASE + (0x88 <<2 )) +#define DMC_AM4_HOLD_CTRL (DMC_REG_BASE + (0x89 <<2 )) +#define DMC_AM4_QOS_INC (DMC_REG_BASE + (0x8a <<2 )) +#define DMC_AM4_QOS_INCBK (DMC_REG_BASE + (0x8b <<2 )) +#define DMC_AM4_QOS_DEC (DMC_REG_BASE + (0x8c <<2 )) +#define DMC_AM4_QOS_DECBK (DMC_REG_BASE + (0x8d <<2 )) +#define DMC_AM4_QOS_DIS (DMC_REG_BASE + (0x8e <<2 )) +#define DMC_AM4_QOS_DISBK (DMC_REG_BASE + (0x8f <<2 )) +#define DMC_AM4_QOS_CTRL0 (DMC_REG_BASE + (0x90 <<2 )) +#define DMC_AM4_QOS_CTRL1 (DMC_REG_BASE + (0x91 <<2 )) + +#define DMC_AM5_CHAN_CTRL (DMC_REG_BASE + (0x92 <<2 )) +#define DMC_AM5_HOLD_CTRL (DMC_REG_BASE + (0x93 <<2 )) +#define DMC_AM5_QOS_INC (DMC_REG_BASE + (0x94 <<2 )) +#define DMC_AM5_QOS_INCBK (DMC_REG_BASE + (0x95 <<2 )) +#define DMC_AM5_QOS_DEC (DMC_REG_BASE + (0x96 <<2 )) +#define DMC_AM5_QOS_DECBK (DMC_REG_BASE + (0x97 <<2 )) +#define DMC_AM5_QOS_DIS (DMC_REG_BASE + (0x98 <<2 )) +#define DMC_AM5_QOS_DISBK (DMC_REG_BASE + (0x99 <<2 )) +#define DMC_AM5_QOS_CTRL0 (DMC_REG_BASE + (0x9a <<2 )) +#define DMC_AM5_QOS_CTRL1 (DMC_REG_BASE + (0x9b <<2 )) + +#define DMC_AM6_CHAN_CTRL (DMC_REG_BASE + (0x9c <<2 )) +#define DMC_AM6_HOLD_CTRL (DMC_REG_BASE + (0x9d <<2 )) +#define DMC_AM6_QOS_INC (DMC_REG_BASE + (0x9e <<2 )) +#define DMC_AM6_QOS_INCBK (DMC_REG_BASE + (0x9f <<2 )) +#define DMC_AM6_QOS_DEC (DMC_REG_BASE + (0xa0 <<2 )) +#define DMC_AM6_QOS_DECBK (DMC_REG_BASE + (0xa1 <<2 )) +#define DMC_AM6_QOS_DIS (DMC_REG_BASE + (0xa2 <<2 )) +#define DMC_AM6_QOS_DISBK (DMC_REG_BASE + (0xa3 <<2 )) +#define DMC_AM6_QOS_CTRL0 (DMC_REG_BASE + (0xa4 <<2 )) +#define DMC_AM6_QOS_CTRL1 (DMC_REG_BASE + (0xa5 <<2 )) + +#define DMC_AM7_CHAN_CTRL (DMC_REG_BASE + (0xa6 <<2 )) +#define DMC_AM7_HOLD_CTRL (DMC_REG_BASE + (0xa7 <<2 )) +#define DMC_AM7_QOS_INC (DMC_REG_BASE + (0xa8 <<2 )) +#define DMC_AM7_QOS_INCBK (DMC_REG_BASE + (0xa9 <<2 )) +#define DMC_AM7_QOS_DEC (DMC_REG_BASE + (0xaa <<2 )) +#define DMC_AM7_QOS_DECBK (DMC_REG_BASE + (0xab <<2 )) +#define DMC_AM7_QOS_DIS (DMC_REG_BASE + (0xac <<2 )) +#define DMC_AM7_QOS_DISBK (DMC_REG_BASE + (0xad <<2 )) +#define DMC_AM7_QOS_CTRL0 (DMC_REG_BASE + (0xae <<2 )) +#define DMC_AM7_QOS_CTRL1 (DMC_REG_BASE + (0xaf <<2 )) + +#define DMC_AXI0_CHAN_CTRL (DMC_REG_BASE + (0xb0 <<2 )) +#define DMC_AXI0_HOLD_CTRL (DMC_REG_BASE + (0xb1 <<2 )) +#define DMC_AXI0_QOS_INC (DMC_REG_BASE + (0xb2 <<2 )) +#define DMC_AXI0_QOS_INCBK (DMC_REG_BASE + (0xb3 <<2 )) +#define DMC_AXI0_QOS_DEC (DMC_REG_BASE + (0xb4 <<2 )) +#define DMC_AXI0_QOS_DECBK (DMC_REG_BASE + (0xb5 <<2 )) +#define DMC_AXI0_QOS_DIS (DMC_REG_BASE + (0xb6 <<2 )) +#define DMC_AXI0_QOS_DISBK (DMC_REG_BASE + (0xb7 <<2 )) +#define DMC_AXI0_QOS_CTRL0 (DMC_REG_BASE + (0xb8 <<2 )) +#define DMC_AXI0_QOS_CTRL1 (DMC_REG_BASE + (0xb9 <<2 )) + +#define DMC_AXI1_CHAN_CTRL (DMC_REG_BASE + (0xba <<2 )) +#define DMC_AXI1_HOLD_CTRL (DMC_REG_BASE + (0xbb <<2 )) +#define DMC_AXI1_QOS_INC (DMC_REG_BASE + (0xbc <<2 )) +#define DMC_AXI1_QOS_INCBK (DMC_REG_BASE + (0xbd <<2 )) +#define DMC_AXI1_QOS_DEC (DMC_REG_BASE + (0xbe <<2 )) +#define DMC_AXI1_QOS_DECBK (DMC_REG_BASE + (0xbf <<2 )) +#define DMC_AXI1_QOS_DIS (DMC_REG_BASE + (0xc0 <<2 )) +#define DMC_AXI1_QOS_DISBK (DMC_REG_BASE + (0xc1 <<2 )) +#define DMC_AXI1_QOS_CTRL0 (DMC_REG_BASE + (0xc2 <<2 )) +#define DMC_AXI1_QOS_CTRL1 (DMC_REG_BASE + (0xc3 <<2 )) + +#define DMC_AXI2_CHAN_CTRL (DMC_REG_BASE + (0xc4 <<2 )) +#define DMC_AXI2_HOLD_CTRL (DMC_REG_BASE + (0xc5 <<2 )) +#define DMC_AXI2_QOS_INC (DMC_REG_BASE + (0xc6 <<2 )) +#define DMC_AXI2_QOS_INCBK (DMC_REG_BASE + (0xc7 <<2 )) +#define DMC_AXI2_QOS_DEC (DMC_REG_BASE + (0xc8 <<2 )) +#define DMC_AXI2_QOS_DECBK (DMC_REG_BASE + (0xc9 <<2 )) +#define DMC_AXI2_QOS_DIS (DMC_REG_BASE + (0xca <<2 )) +#define DMC_AXI2_QOS_DISBK (DMC_REG_BASE + (0xcb <<2 )) +#define DMC_AXI2_QOS_CTRL0 (DMC_REG_BASE + (0xcc <<2 )) +#define DMC_AXI2_QOS_CTRL1 (DMC_REG_BASE + (0xcd <<2 )) + +#define DMC_AXI3_CHAN_CTRL (DMC_REG_BASE + (0xce <<2 )) +#define DMC_AXI3_HOLD_CTRL (DMC_REG_BASE + (0xcf <<2 )) +#define DMC_AXI3_QOS_INC (DMC_REG_BASE + (0xd0 <<2 )) +#define DMC_AXI3_QOS_INCBK (DMC_REG_BASE + (0xd1 <<2 )) +#define DMC_AXI3_QOS_DEC (DMC_REG_BASE + (0xd2 <<2 )) +#define DMC_AXI3_QOS_DECBK (DMC_REG_BASE + (0xd3 <<2 )) +#define DMC_AXI3_QOS_DIS (DMC_REG_BASE + (0xd4 <<2 )) +#define DMC_AXI3_QOS_DISBK (DMC_REG_BASE + (0xd5 <<2 )) +#define DMC_AXI3_QOS_CTRL0 (DMC_REG_BASE + (0xd6 <<2 )) +#define DMC_AXI3_QOS_CTRL1 (DMC_REG_BASE + (0xd7 <<2 )) + +#define DMC_AXI4_CHAN_CTRL (DMC_REG_BASE + (0xd8 <<2 )) +#define DMC_AXI4_HOLD_CTRL (DMC_REG_BASE + (0xd9 <<2 )) +#define DMC_AXI4_QOS_INC (DMC_REG_BASE + (0xda <<2 )) +#define DMC_AXI4_QOS_INCBK (DMC_REG_BASE + (0xdb <<2 )) +#define DMC_AXI4_QOS_DEC (DMC_REG_BASE + (0xdc <<2 )) +#define DMC_AXI4_QOS_DECBK (DMC_REG_BASE + (0xdd <<2 )) +#define DMC_AXI4_QOS_DIS (DMC_REG_BASE + (0xde <<2 )) +#define DMC_AXI4_QOS_DISBK (DMC_REG_BASE + (0xdf <<2 )) +#define DMC_AXI4_QOS_CTRL0 (DMC_REG_BASE + (0xe0 <<2 )) +#define DMC_AXI4_QOS_CTRL1 (DMC_REG_BASE + (0xe1 <<2 )) + +#define DMC_AXI5_CHAN_CTRL (DMC_REG_BASE + (0xe2 <<2 )) +#define DMC_AXI5_HOLD_CTRL (DMC_REG_BASE + (0xe3 <<2 )) +#define DMC_AXI5_QOS_INC (DMC_REG_BASE + (0xe4 <<2 )) +#define DMC_AXI5_QOS_INCBK (DMC_REG_BASE + (0xe5 <<2 )) +#define DMC_AXI5_QOS_DEC (DMC_REG_BASE + (0xe6 <<2 )) +#define DMC_AXI5_QOS_DECBK (DMC_REG_BASE + (0xe7 <<2 )) +#define DMC_AXI5_QOS_DIS (DMC_REG_BASE + (0xe8 <<2 )) +#define DMC_AXI5_QOS_DISBK (DMC_REG_BASE + (0xe9 <<2 )) +#define DMC_AXI5_QOS_CTRL0 (DMC_REG_BASE + (0xea <<2 )) +#define DMC_AXI5_QOS_CTRL1 (DMC_REG_BASE + (0xeb <<2 )) + +#define DMC_AXI6_CHAN_CTRL (DMC_REG_BASE + (0xec <<2 )) +#define DMC_AXI6_HOLD_CTRL (DMC_REG_BASE + (0xed <<2 )) +#define DMC_AXI6_QOS_INC (DMC_REG_BASE + (0xee <<2 )) +#define DMC_AXI6_QOS_INCBK (DMC_REG_BASE + (0xef <<2 )) +#define DMC_AXI6_QOS_DEC (DMC_REG_BASE + (0xf0 <<2 )) +#define DMC_AXI6_QOS_DECBK (DMC_REG_BASE + (0xf1 <<2 )) +#define DMC_AXI6_QOS_DIS (DMC_REG_BASE + (0xf2 <<2 )) +#define DMC_AXI6_QOS_DISBK (DMC_REG_BASE + (0xf3 <<2 )) +#define DMC_AXI6_QOS_CTRL0 (DMC_REG_BASE + (0xf4 <<2 )) +#define DMC_AXI6_QOS_CTRL1 (DMC_REG_BASE + (0xf5 <<2 )) + +#define DMC_AXI7_CHAN_CTRL (DMC_REG_BASE + (0xf6 <<2 )) +#define DMC_AXI7_HOLD_CTRL (DMC_REG_BASE + (0xf7 <<2 )) +#define DMC_AXI7_QOS_INC (DMC_REG_BASE + (0xf8 <<2 )) +#define DMC_AXI7_QOS_INCBK (DMC_REG_BASE + (0xf9 <<2 )) +#define DMC_AXI7_QOS_DEC (DMC_REG_BASE + (0xfa <<2 )) +#define DMC_AXI7_QOS_DECBK (DMC_REG_BASE + (0xfb <<2 )) +#define DMC_AXI7_QOS_DIS (DMC_REG_BASE + (0xfc <<2 )) +#define DMC_AXI7_QOS_DISBK (DMC_REG_BASE + (0xfd <<2 )) +#define DMC_AXI7_QOS_CTRL0 (DMC_REG_BASE + (0xfe <<2 )) +#define DMC_AXI7_QOS_CTRL1 (DMC_REG_BASE + (0xff <<2 )) + diff --git a/plat/gxb/ddr/mmc_define.h b/plat/gxb/ddr/mmc_define.h new file mode 100644 index 0000000..7f738d8 --- /dev/null +++ b/plat/gxb/ddr/mmc_define.h @@ -0,0 +1,87 @@ + +/* + * arch/arm/cpu/armv8/common/firmware/plat/gxb/ddr/mmc_define.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#define AM_DDR_PLL_CNTL 0xc8836800 + //bit 31. PLL lock. read only + //bit 30. PLL power down. 1 = PLL powerdown. 0 = PLL enable. + //bit 29. PLL reset. + //bit 28. SSEN + //bit 27:24. SS_AMP + //bit 23:20. SS_CLK + //bit 17:16. OD. + //bit 15:14. OD1. + //bit 13:9. N. + //bit 8:0 M +#define AM_DDR_PLL_CNTL1 0xc8836804 + //bit 31:28. DPLL_LM_W + //bit 27:22. DPLL_LM_S. + //bit 21. DPFD_LMODE + //bit 20:19. DC_VC_IN. + //bit 18:17. DCO_SDMCK_SEL + //bit 16. DCO_M_EN. + //bit 15. SDM_PR_EN. + //bit 14 DIV_MODE. + //bit 13:2 DIV_FRAC + //bit 1 AFC_DSEL_BYPASS. + //bit 0. AFC_DSEL_IN. +#define AM_DDR_PLL_CNTL2 0xc8836808 + //bit 29:26. FILTER_PVT2. + //bit 25:22. FILTER PVT1. + //bit 21:11. FILTER ACQ2. + //bit 10:0. FILTER ACQ1. +#define AM_DDR_PLL_CNTL3 0xc883680c + //bit 31:20. DPLL REVE. + //bit 13:6. TDC_BUF. + //bit 5. PVT_FIX_EN. + //bit 4:3. DCO_IUP. + //bit 2. IIR_BYPASS_N. + //bit 1 TDC_EN +#define AM_DDR_PLL_CNTL4 0xc8836810 + //bit 21:20. DPLL_CLK_EN. + //bit 13. DCO_SDM_EN + //bit 12. BGP_EN. + //bit 11:8. GPB_C +#define AM_DDR_PLL_STS 0xc8836814 + //bit 31. DDR_PLL lock. + //bit 8:1. DPLL_OUT_RSV + //bit 0. AFC DONE. + +#define DDR_CLK_CNTL 0xc8836818 + //bit 31 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion. + // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again. + //bit 30. ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin. + //bit 29. ddr_phy_ctl_clk enable. + //bit 28. clock generation logic soft reset. 0 = reset. + //bit 27. phy_4xclk phase inverter.. + //bit 26. pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk. this setting is used for the synopsys DDR PHY PLL fast lock mode. + +#define DDR0_CLK_CTRL 0xc8836c00 +//bit 3. force to disable PUB PCLK. +//bit 2. PUB auto ctrl n_clk clock gating enable. when the DFI_LP_REQ and DFI_LP_ACK detected , auto gated PUB n_clk. +//bit 1. force to disable PUB PCLK. +//bit 0. PUB pclk auto clock gating enable. when the IP detected PCTL enter power down mode, use this bit to gating pub pclk. +#define DDR0_SOFT_RESET 0xc8836c04 +//bit 3. pub n_clk domain soft reset. 1 active. +//bit 2. pub p_clk domain soft reset. + +#define DDR0_APD_CTRL 0xc8836c08 +//bit 15:8. power down enter latency. when IP checked the dfi_lp_req && dfi_lp_ack, give PCTL and pub additional latency let them settle down, then gating the clock. +//bit 7:0. no active latency. after c_active_in become to low, wait additional latency to check the pctl low power state. diff --git a/plat/gxb/ddr/sec_mmc_define.h b/plat/gxb/ddr/sec_mmc_define.h new file mode 100644 index 0000000..2d4508c --- /dev/null +++ b/plat/gxb/ddr/sec_mmc_define.h @@ -0,0 +1,712 @@ + +/* + * arch/arm/cpu/armv8/common/firmware/plat/gxb/ddr/sec_mmc_define.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#define DMC_SEC_REG_BASE 0xda838400 +#define DMC_SEC_CTRL (DMC_SEC_REG_BASE + (0x00 <<2)) + + //security range defination have to be atom option. all the range controll register will be shadowed. + //write bit 31 to 1 to update the setting in shadow register to be used. +#define DMC_SEC_RANGE0_CTRL (DMC_SEC_REG_BASE + (0x01 <<2)) + //bit 31:16 : range 0 end address higher 16bits. + //bit 15:0 : range 0 start address higher 16bits. +#define DMC_SEC_RANGE1_CTRL (DMC_SEC_REG_BASE + (0x02 <<2)) + //bit 31:16 : range 1 end address higher 16bits. + //bit 15:0 : range 1 start address higher 16bits. +#define DMC_SEC_RANGE2_CTRL (DMC_SEC_REG_BASE + (0x03 <<2)) + //bit 31:16 : range 2 end address higher 16bits. + //bit 15:0 : range 2 start address higher 16bits. +#define DMC_SEC_RANGE3_CTRL (DMC_SEC_REG_BASE + (0x04 <<2)) + //bit 31:16 : range 3 end address higher 16bits. + //bit 15:0 : range 3 start address higher 16bits. +#define DMC_SEC_RANGE4_CTRL (DMC_SEC_REG_BASE + (0x05 <<2)) + //bit 31:16 : range 4 end address higher 16bits. + //bit 15:0 : range 4 start address higher 16bits. +#define DMC_SEC_RANGE5_CTRL (DMC_SEC_REG_BASE + (0x06 <<2)) + //bit 31:16 : range 5 end address higher 16bits. + //bit 15:0 : range 5 start address higher 16bits. +#define DMC_SEC_RANGE_CTRL (DMC_SEC_REG_BASE + (0x07 <<2)) + //bit 31:7 : not used + //bit 6 : default range security level. 1 : secure region. 0 : non secure region. + //bit 5 : range 5 security level. 1 : secure region. 0 : non secure region. + //bit 4 : range 4 security level. 1 : secure region. 0 : non secure region. + //bit 3 : range 3 security level. 1 : secure region. 0 : non secure region. + //bit 2 : range 2 security level. 1 : secure region. 0 : non secure region. + //bit 1 : range 1 security level. 1 : secure region. 0 : non secure region. + //bit 0 : range 0 security level. 1 : secure region. 0 : non secure region. + +#define DMC_SEC_AXI_PORT_CTRL (DMC_SEC_REG_BASE + (0x0e <<2)) + //bit 31~24. not used. + //bit 23. AXI port3 (HDCP ) secure region write access enable bit. 1: enable. 0 : disable. + //bit 22. AXI port3 (HDCP ) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 21. AXI port2 (Mali 1) secure region write access enable bit. 1: enable. 0 : disable. + //bit 20. AXI port2 (Mali 1) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 19. AXI port1 (Mali 0) secure region write access enable bit. 1: enable. 0 : disable. + //bit 18. AXI port1 (Mali 0) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 17. AXI port0 (CPU) secure region write access enable bit. 1: enable. 0 : disable. + //bit 16. AXI port0 (CPU) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 15~8. not used. + //bit 7. AXI port3 (HDCP ) secure region read access enable bit. 1: enable. 0 : disable. + //bit 6. AXI port3 (HDCP ) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 5. AXI port2 (Mali 1) secure region read access enable bit. 1: enable. 0 : disable. + //bit 4. AXI port2 (Mali 1) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 3. AXI port1 (Mali 0) secure region read access enable bit. 1: enable. 0 : disable. + //bit 2. AXI port1 (Mali 0) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 1. AXI port0 (CPU) secure region read access enable bit. 1: enable. 0 : disable. + //bit 0. AXI port0 (CPU) non secure region read access enable bit. 1: enable. 0 : disable. + +#define DMC_VDEC_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x10 <<2)) + //bit 31. VDEC subID14 ( not used ) secure region read access enable bit. 1: enable. 0 : disable. + //bit 30. VDEC subID14 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 29. VDEC subID14 ( not used ) secure region read access enable bit. 1: enable. 0 : disable. + //bit 28. VDEC subID14 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 27. VDEC subID13 ( not used ) secure region read access enable bit. 1: enable. 0 : disable. + //bit 26. VDEC subID13 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 25. VDEC subID12 ( not used ) secure region read access enable bit. 1: enable. 0 : disable. + //bit 24. VDEC subID12 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 23. VDEC subID11 ( not used ) secure region read access enable bit. 1: enable. 0 : disable. + //bit 22. VDEC subID11 ( not used ) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 21. VDEC subID10 ( mbbot ) secure region read access enable bit. 1: enable. 0 : disable. + //bit 20. VDEC subID10 ( mbbot ) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 19. VDEC subID9 ( not used.) secure region read access enable bit. 1: enable. 0 : disable. + //bit 18. VDEC subID9 ( not used) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 17. VDEC subID8 ( not used.) secure region read access enable bit. 1: enable. 0 : disable. + //bit 16. VDEC subID8 ( not used) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 15. VDEC subID7 (dw) secure region read access enable bit. 1: enable. 0 : disable. + //bit 14. VDEC subID7 (dw) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 13. VDEC subID6 (comb) secure region read access enable bit. 1: enable. 0 : disable. + //bit 12. VDEC subID6 (comb) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 11. VDEC subID5 (lmem) secure region read access enable bit. 1: enable. 0 : disable. + //bit 10. VDEC subID5 (lmem) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 9. VDEC subID4 (imem) secure region read access enable bit. 1: enable. 0 : disable. + //bit 8. VDEC subID4 (imem) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 7. VDEC subID3 (picdc) secure region read access enable bit. 1: enable. 0 : disable. + //bit 6. VDEC subID3 (picdc) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 5. VDEC subID2 (psc) secure region read access enable bit. 1: enable. 0 : disable. + //bit 4. VDEC subID2 (psc) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 3. VDEC subID1 (dcac) secure region read access enable bit. 1: enable. 0 : disable. + //bit 2. VDEC subID1 (dcac) non secure region read access enable bit. 1: enable. 0 : disable. + //bit 1. VDEC subID0 (vld) secure region read access enable bit. 1: enable. 0 : disable. + //bit 0. VDEC subID0 (vld) non secure region read access enable bit. 1: enable. 0 : disable. +#define DMC_VDEC_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x11 <<2)) + //bit 31. VDEC subID14 ( not used ) secure region write access enable bit. 1: enable. 0 : disable. + //bit 30. VDEC subID14 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 29. VDEC subID14 ( not used ) secure region write access enable bit. 1: enable. 0 : disable. + //bit 28. VDEC subID14 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 27. VDEC subID13 ( not used ) secure region write access enable bit. 1: enable. 0 : disable. + //bit 26. VDEC subID13 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 25. VDEC subID12 ( not used ) secure region write access enable bit. 1: enable. 0 : disable. + //bit 24. VDEC subID12 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 23. VDEC subID11 ( not used ) secure region write access enable bit. 1: enable. 0 : disable. + //bit 22. VDEC subID11 ( not used ) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 21. VDEC subID10 ( mbbot ) secure region write access enable bit. 1: enable. 0 : disable. + //bit 20. VDEC subID10 ( mbbot ) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 19. VDEC subID9 ( not used.) secure region write access enable bit. 1: enable. 0 : disable. + //bit 18. VDEC subID9 ( not used) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 17. VDEC subID8 ( not used.) secure region write access enable bit. 1: enable. 0 : disable. + //bit 16. VDEC subID8 ( not used) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 15. VDEC subID7 (dw) secure region write access enable bit. 1: enable. 0 : disable. + //bit 14. VDEC subID7 (dw) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 13. VDEC subID6 (comb) secure region write access enable bit. 1: enable. 0 : disable. + //bit 12. VDEC subID6 (comb) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 11. VDEC subID5 (lmem) secure region write access enable bit. 1: enable. 0 : disable. + //bit 10. VDEC subID5 (lmem) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 9. VDEC subID4 (imem) secure region write access enable bit. 1: enable. 0 : disable. + //bit 8. VDEC subID4 (imem) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 7. VDEC subID3 (picdc) secure region write access enable bit. 1: enable. 0 : disable. + //bit 6. VDEC subID3 (picdc) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 5. VDEC subID2 (psc) secure region write access enable bit. 1: enable. 0 : disable. + //bit 4. VDEC subID2 (psc) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 3. VDEC subID1 (dcac) secure region write access enable bit. 1: enable. 0 : disable. + //bit 2. VDEC subID1 (dcac) non secure region write access enable bit. 1: enable. 0 : disable. + //bit 1. VDEC subID0 (vld) secure region write access enable bit. 1: enable. 0 : disable. + //bit 0. VDEC subID0 (vld) non secure region write access enable bit. 1: enable. 0 : disable. +#define DMC_VDEC_SEC_CFG (DMC_SEC_REG_BASE + (0x12 <<2)) + //DWC_VDEC_SEC_READ_CTRL and DMC_VDEC_SEC_WRITE_CTRL register APB bus configuation enable. 2 bit for each port. one for read, one for write. + //bit 31. VDEC subID15 () To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 30. VDEC subID14 () To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 29. VDEC subID13 () To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 28. VDEC subID12 () To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 27. VDEC subID11 () To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 26. VDEC subID10 (mbbot) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 25. VDEC subID9 () To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 24. VDEC subID8 () To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 23. VDEC subID7 (dw) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 22. VDEC subID6 (comb) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 21. VDEC subID5 (lmem) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 20. VDEC subID4 (imem) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 19. VDEC subID3 (picdc) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 18. VDEC subID2 (psc) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 17. VDEC subID1 (dcac) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 16. VDEC subID0 (vld) To enable APB bus modifiy the write security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 15. VDEC subID15 () To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 14. VDEC subID14 () To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 13. VDEC subID13 () To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 12. VDEC subID12 () To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 11. VDEC subID11 () To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 10. VDEC subID10 (mbbot) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 9. VDEC subID9 () To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 8. VDEC subID8 () To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 7. VDEC subID7 (dw) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 6. VDEC subID6 (comb) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 5. VDEC subID5 (lmem) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 4. VDEC subID4 (imem) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 3. VDEC subID3 (picdc) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 2. VDEC subID2 (psc) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 1. VDEC subID1 (dcac) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + //bit 0. VDEC subID0 (vld) To enable APB bus modifiy the read security control bits. 1 : eable the APB modify. 0 : disable APB bus modify. + +#define DMC_VDEC_EF_TRIG_CTRL (DMC_SEC_REG_BASE + (0x13 <<2)) + // VDEC Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port. + //Electronic would be triggered by the read from defined secure level from selected subIDs. + //bit 31. trigger type selection for subID15 (). 1 = secure access. 0 : non secure access. + //bit 30. trigger type selection for subID14 (). 1 = secure access. 0 : non secure access. + //bit 29. trigger type selection for subID13 (). 1 = secure access. 0 : non secure access. + //bit 28. trigger type selection for subID12 (). 1 = secure access. 0 : non secure access. + //bit 27. trigger type selection for subID11 (). 1 = secure access. 0 : non secure access. + //bit 26. trigger type selection for subID10 (). 1 = secure access. 0 : non secure access. + //bit 25. trigger type selection for subID9 (). 1 = secure access. 0 : non secure access. + //bit 24. trigger type selection for subID8 (). 1 = secure access. 0 : non secure access. + //bit 23. trigger type selection for subID7 (dw). 1 = secure access. 0 : non secure access. + //bit 22. trigger type selection for subID6 (comb). 1 = secure access. 0 : non secure access. + //bit 21. trigger type selection for subID5 (lmem). 1 = secure access. 0 : non secure access. + //bit 20. trigger type selection for subID4 (imem). 1 = secure access. 0 : non secure access. + //bit 19. trigger type selection for subID3 (picdc). 1 = secure access. 0 : non secure access. + //bit 18. trigger type selection for subID2 (psc). 1 = secure access. 0 : non secure access. + //bit 17. trigger type selection for subID1 (dcac). 1 = secure access. 0 : non secure access. + //bit 16. trigger type selection for subID0 (vld). 1 = secure access. 0 : non secure access. + //bit 15. trigger source selection for subID15 (). 1 = selected. 0 : not selected. + //bit 14. trigger source selection for subID14 (). 1 = selected. 0 : not selected. + //bit 13. trigger source selection for subID13 (). 1 = selected. 0 : not selected. + //bit 12. trigger source selection for subID12 (). 1 = selected. 0 : not selected. + //bit 11. trigger source selection for subID11 (). 1 = selected. 0 : not selected. + //bit 10. trigger source selection for subID10 (). 1 = selected. 0 : not selected. + //bit 9. trigger source selection for subID9 (). 1 = selected. 0 : not selected. + //bit 8. trigger source selection for subID8 (). 1 = selected. 0 : not selected. + //bit 7. trigger source selection for subID7 (dw). 1 = selected. 0 : not selected. + //bit 6. trigger source selection for subID6 (comb). 1 = selected. 0 : not selected. + //bit 5. trigger source selection for subID5 (lmem). 1 = selected. 0 : not selected. + //bit 4. trigger source selection for subID4 (imem). 1 = selected. 0 : not selected. + //bit 3. trigger source selection for subID3 (picdc). 1 = selected. 0 : not selected. + //bit 2. trigger source selection for subID2 (psc). 1 = selected. 0 : not selected. + //bit 1. trigger source selection for subID1 (dcac). 1 = selected. 0 : not selected. + //bit 0. trigger source selection for subID0 (vld). 1 = selected. 0 : not selected. + +#define DMC_VDEC_EF_PROT (DMC_SEC_REG_BASE + (0x14 <<2)) + //to define which subID would be affected if the EF got triggered. + //bit 31. EF would affect subID15 () write access secure control. 1 = selected. 0 : not selected. + //bit 30. EF would affect subID14 () write access secure control. 1 = selected. 0 : not selected. + //bit 29. EF would affect subID13 () write access secure control. 1 = selected. 0 : not selected. + //bit 28. EF would affect subID12 () write access secure control. 1 = selected. 0 : not selected. + //bit 27. EF would affect subID11 () write access secure control. 1 = selected. 0 : not selected. + //bit 26. EF would affect subID10 () write access secure control. 1 = selected. 0 : not selected. + //bit 25. EF would affect subID9 () write access secure control. 1 = selected. 0 : not selected. + //bit 24. EF would affect subID8 () write access secure control. 1 = selected. 0 : not selected. + //bit 23. EF would affect subID7 (dw) write access secure control. 1 = selected. 0 : not selected. + //bit 22. EF would affect subID6 (comb) write access secure control. 1 = selected. 0 : not selected. + //bit 21. EF would affect subID5 (lmem) write access secure control. 1 = selected. 0 : not selected. + //bit 20. EF would affect subID4 (imem) write access secure control. 1 = selected. 0 : not selected. + //bit 19. EF would affect subID3 (picdc) write access secure control. 1 = selected. 0 : not selected. + //bit 18. EF would affect subID2 (psc) write access secure control. 1 = selected. 0 : not selected. + //bit 17. EF would affect subID1 (dcac) write access secure control. 1 = selected. 0 : not selected. + //bit 16. EF would affect subID0 (vld) write access secure control. 1 = selected. 0 : not selected. + //bit 15. EF would affect subID15 () read access secure control. 1 = selected. 0 : not selected. + //bit 14. EF would affect subID14 () read access secure control. 1 = selected. 0 : not selected. + //bit 13. EF would affect subID13 () read access secure control. 1 = selected. 0 : not selected. + //bit 12. EF would affect subID12 () read access secure control. 1 = selected. 0 : not selected. + //bit 11. EF would affect subID11 () read access secure control. 1 = selected. 0 : not selected. + //bit 10. EF would affect subID10 () read access secure control. 1 = selected. 0 : not selected. + //bit 9. EF would affect subID9 () read access secure control. 1 = selected. 0 : not selected. + //bit 8. EF would affect subID8 () read access secure control. 1 = selected. 0 : not selected. + //bit 7. EF would affect subID7 (dw) read access secure control. 1 = selected. 0 : not selected. + //bit 6. EF would affect subID6 (comb) read access secure control. 1 = selected. 0 : not selected. + //bit 5. EF would affect subID5 (lmem) read access secure control. 1 = selected. 0 : not selected. + //bit 4. EF would affect subID4 (imem) read access secure control. 1 = selected. 0 : not selected. + //bit 3. EF would affect subID3 (picdc) read access secure control. 1 = selected. 0 : not selected. + //bit 2. EF would affect subID2 (psc) read access secure control. 1 = selected. 0 : not selected. + //bit 1. EF would affect subID1 (dcac) read access secure control. 1 = selected. 0 : not selected. + //bit 0. EF would affect subID0 (vld) read access secure control. 1 = selected. 0 : not selected. +#define DMC_VDEC_EF_READ (DMC_SEC_REG_BASE + (0x15 <<2)) + //this register contains the vdec read security control bits after the EF got triggered. + //if the DMC_VDEC_EF_PROT register bit 15:0 related bit was enable, then the related secure control bits would be copied to DMC_VDEC_SEC_READ_CTRL related bits. + +#define DMC_VDEC_EF_WRITE (DMC_SEC_REG_BASE + (0x16 <<2)) + //this register contains the vdec write security control bits after the EF got triggered. + //if the DMC_VDEC_EF_PROT register bit 15:0 related bit was enable, then the related secure control bits would be copied to DMC_VDEC_SEC_READ_CTRL related bits. + + //HCODEC security and Electronic fence is same as VDEC with different SUBID define.. + //subID15:13 : not used. + //subID12 : ME. + //subID11 : mfdin + //subID10 : mcmbot + //subID9 : i_pred. + //subID8 : qdct + //subID7 : vlc + //subID6 : comb + //subID5 : LMEM + //subID4 : IMEM. + //subID3 : mcrcc + //subID2 : PSC + //subID1 : dcac + //subID0 : vld +#define DMC_HCODEC_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x17 <<2)) + //each subID with 2bits. one for secure region. one for unsecure region. + +#define DMC_HCODEC_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x18 <<2)) + //each subID with 2bits. one for secure region. one for unsecure region. + +#define DMC_HCODEC_SEC_CFG (DMC_SEC_REG_BASE + (0x19 <<2)) + //DWC_HCODEC_SEC_READ_CTRL and DMC_HCODEC_SEC_WRITE_CTRL register APB bus configuation enable. 2 bit for each port. one for read, one for write. + +#define DMC_HCODEC_EF_TRIG_CTRL (DMC_SEC_REG_BASE + (0x1a <<2)) + // HCODEC Electronic fence trigger selection and trigger secure type. 1 bit for trigger select for one read port. 1 bit for trigger type for one read port. + +#define DMC_HCODEC_EF_PROT (DMC_SEC_REG_BASE + (0x1b <<2)) + // HCODEC EF protected access control. each subID 2 bits. one for read one for write. +#define DMC_HCODEC_EF_READ (DMC_SEC_REG_BASE + (0x1c <<2)) + //the DWC_HCODEC_SEC_READ_CTRL value need to be changed after HCODEC EF fence triggered. once the trigger happens, the DMC_HCODEC_EF_PROT[15:0] bit enabled subIDs value will be copied to DWC_HCODEC_SEC_READ_CTRL register. +#define DMC_HCODEC_EF_WRITE (DMC_SEC_REG_BASE + (0x1d <<2)) + //the DWC_HCODEC_SEC_WRITE_CTRL value need to be changed after HCODEC EF fence triggered. once the trigger happens, the DMC_HCODEC_EF_PROT[31:16] bit enabled subIDs value will be copied to DWC_HCODEC_SEC_WRITE_CTRL register. + +//HEVC security and electronic fence control is similar with VDEC/HCODE. only difference is in HEVC, the LMEM/IMEM are shared in one SUBID. so we need to have seperate seting for them. + //subID 7 : mpred. + //subID 6 : dblk_d + //subID 5 : dblk_p + //subID 4 : ipp + //subID 3 : mpp + //subID 2 : SAO + //subID 1 : stream. + //subID 0 : AMRISC CPU. include IMEM and LMEM. AR/WID[3:0] == 0 IMEM. LMEM. + //HEVC ID 7. [6:4] for subID. +#define DMC_HEVC_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x1e <<2)) + //bit 31:18. not used. + //bit 17. READ secure area eable bit for HEVC subID0 CPU with IDbits 3:0 != 4'h0 read access. 1 : enable. 0 : disable. + //bit 16. READ non secure area eable bit for HEVC subID 0 CPU with IDbits 3:0 != 4'h0 read access. 1 : enable. 0 : disable. + //bit 15. READ secure area eable bit for HEVC subID 7 mpred read access. 1 : enable. 0 : disable. + //bit 14. READ non secure area eable bit for HEVC subID 7 mpred read access. 1 : enable. 0 : disable. + //bit 13. READ secure area eable bit for HEVC subID 6 dblk_d read access. 1 : enable. 0 : disable. + //bit 12. READ non secure area eable bit for HEVC subID 6 dblk_d read access. 1 : enable. 0 : disable. + //bit 11. READ secure area eable bit for HEVC subID 5 dblk_p read access. 1 : enable. 0 : disable. + //bit 10. READ non secure area eable bit for HEVC subID 5 dblk_p read access. 1 : enable. 0 : disable. + //bit 9. READ secure area eable bit for HEVC subID 4 ipp read access. 1 : enable. 0 : disable. + //bit 8. READ non secure area eable bit for HEVC subID 4 ipp read access. 1 : enable. 0 : disable. + //bit 7. READ secure area eable bit for HEVC subID 3 mpp read access. 1 : enable. 0 : disable. + //bit 6. READ non secure area eable bit for HEVC subID 3 mpp read access. 1 : enable. 0 : disable. + //bit 5. READ secure area eable bit for HEVC subID 2 SAO read access. 1 : enable. 0 : disable. + //bit 4. READ non secure area eable bit for HEVC subID 2 SAO read access. 1 : enable. 0 : disable. + //bit 3. READ secure area eable bit for HEVCsubID 1 stream read access. 1 : enable. 0 : disable. + //bit 2. READ non secure area eable bit for HEVC subID 1 stream read access. 1 : enable. 0 : disable. + //bit 1. READ secure area eable bit for HEVC CPU access with ID bit 3:0 = 4'h0. 1 : enable. 0 : disable. + //bit 0. READ non secure area eable bit for HEVC CPU access with ID bit 3:0 = 4'h0. 1 : enable. 0 : disable. + +#define DMC_HEVC_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x1f <<2)) + //bit 31:18. not used. + //bit 17. WRITE secure area eable bit for HEVC subID0 CPU with IDbits[7:4] == 4'h1 write access. 1 : enable. 0 : disable. + //bit 16. WRITE non secure area eable bit for HEVC subID 0 CPU IDbits[7:4] == 4'h1 write access. 1 : enable. 0 : disable. + //bit 15. WRITE secure area eable bit for HEVC subID [7:5] ==7 mpred write access. 1 : enable. 0 : disable. + //bit 14. WRITE non secure area eable bit for HEVC subID 7 mpred write access. 1 : enable. 0 : disable. + //bit 13. WRITE secure area eable bit for HEVC subID [7:5] == 6 dblk_d write access. 1 : enable. 0 : disable. + //bit 12. WRITE non secure area eable bit for HEVC subID [7:5] == 6 dblk_d write access. 1 : enable. 0 : disable. + //bit 11. WRITE secure area eable bit for HEVC subID [7:5] == 5 dblk_p write access. 1 : enable. 0 : disable. + //bit 10. WRITE non secure area eable bit for HEVC subID [7:5] == 5 dblk_p write access. 1 : enable. 0 : disable. + //bit 9. WRITE secure area eable bit for HEVC subID [7:5] == 4 ipp write access. 1 : enable. 0 : disable. + //bit 8. WRITE non secure area eable bit for HEVC subID [7:5] == 4 ipp write access. 1 : enable. 0 : disable. + //bit 7. WRITE secure area eable bit for HEVC subID [7:5] == 3 mpp write access. 1 : enable. 0 : disable. + //bit 6. WRITE non secure area eable bit for HEVC subID [7:5] == 3 mpp write access. 1 : enable. 0 : disable. + //bit 5. WRITE secure area eable bit for HEVC subID [7:5] == 2 SAO write access. 1 : enable. 0 : disable. + //bit 4. WRITE non secure area eable bit for HEVC subID 2 SAO write access. 1 : enable. 0 : disable. + //bit 3. WRITE secure area eable bit for HEVCsubID [7:5] == 1 stream write access. 1 : enable. 0 : disable. + //bit 2. WRITE non secure area eable bit for HEVC subID [7:5] == 1 stream write access. 1 : enable. 0 : disable. + //bit 1. WRITE secure area eable bit for HEVC CPU access with ID bit 7 :4 = 4'h0. 1 : enable. 0 : disable. + //bit 0. WRITE non secure area eable bit for HEVC CPU access with ID bit 7:4 = 4'h0. 1 : enable. 0 : disable. + +#define DMC_HEVC_SEC_CFG (DMC_SEC_REG_BASE + (0x20 <<2)) + //24:16 9 CBUS modfiy enable bit for 9 write secure cotnrol SUBIDs + // 8:0. 9 CBUS modify enable bit for 9 READ secure control SUBIDs. +#define DMC_HEVC_EF_TRIG_CTRL (DMC_SEC_REG_BASE + (0x21 <<2)) + //bit 24:16. 9 HEVC EF trigger selection type for 9 SUBID read access. + //bit 8:0. 9 HEVC EF trigger selection for 9 SUBID read acess. + +#define DMC_HEVC_EF_PROT (DMC_SEC_REG_BASE + (0x22 <<2)) + //bit 24:16. 9 HEVC EF controlled write subID selection. + //bit 8:0. 9 HEVC EF controlled read subIDs selection. + +#define DMC_HEVC_EF_READ (DMC_SEC_REG_BASE + (0x23 <<2)) + //bit 17:0. DWC_HEVC_SEC_READ_CTRL value need to be changed after HEVC EF fence triggered. +#define DMC_HEVC_EF_WRITE (DMC_SEC_REG_BASE + (0x24 <<2)) + //bit 17:0. DWC_HEVC_SEC_WRITE_CTRL value need to be changed after HEVC EF fence triggered. + + + +//there are upto 16 read subID inside VPU and dynamic allocated 3 VPU read ports. +//there are upto 16 write subIDs insdie VPU and dynamic allocated 2 VPU write ports +//there are 3 electronic fences for VPU domain. we can allocated any of those 16 read ports as the trigger of the 3 EF. +//the 3 EF also can control any of those read ports and write ports security levels. +//the Software should make sure there's no conflit setting between these 3 EFs. +#define DMC_VPU_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x32 <<2)) +//bit 31:0. each read subID have 2 bits securty control. one is for seucre area access. one is for unsecure aread access. + +#define DMC_VPU_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x33 <<2)) +//bit 31:0. each write subID have 2 bits securty control. one is for seucre area access. one is for unsecure aread access. + +#define DMC_VPU_SEC_CFG (DMC_SEC_REG_BASE + (0x25 <<2)) + //31:16 enable APB bus configure VPU write SubIDs security contrl register DMC_VPU_SEC_WRITE_CTRL. + //15:0 enable APB bus configure for VPU read SubIDs security control register. DMC_VPU_SEC_READ_CTRL +#define DMC_VPU_EF0_TRIG_CTRL (DMC_SEC_REG_BASE + (0x26 <<2)) + //31:16. VPU EF0 trigger selection read source type. + //15:0. VPU EF0 trigger selection read source select. +#define DMC_VPU_EF0_PROT (DMC_SEC_REG_BASE + (0x27 <<2)) + //bit 24:16. 16 VPU EF0 controlled write subIDs selection. + //bit 15:0. 16 VPU EF0 controlled read subIDs selection. +#define DMC_VPU_EF0_READ (DMC_SEC_REG_BASE + (0x28 <<2)) + //EF0 controlled DMC_VPU_SEC_READ_CTRL. +#define DMC_VPU_EF0_WRITE (DMC_SEC_REG_BASE + (0x29 <<2)) + //EF0 controlled DMC_VPU_SEC_WRITE_CTRL. + +#define DMC_VPU_EF1_TRIG_CTRL (DMC_SEC_REG_BASE + (0x2a <<2)) + //31:16. VPU EF1 trigger selection read source type. + //15:0. VPU EF1 trigger selection read source select. +#define DMC_VPU_EF1_PROT (DMC_SEC_REG_BASE + (0x2b <<2)) + //bit 24:16. 16 VPU EF1 controlled write subIDs selection. + //bit 15:0. 16 VPU EF1 controlled read subIDs selection. +#define DMC_VPU_EF1_READ (DMC_SEC_REG_BASE + (0x2c <<2)) + //EF1 controlled DMC_VPU_SEC_READ_CTRL. +#define DMC_VPU_EF1_WRITE (DMC_SEC_REG_BASE + (0x2d <<2)) + //EF1 controlled DMC_VPU_SEC_WRITE_CTRL. +#define DMC_VPU_EF2_TRIG_CTRL (DMC_SEC_REG_BASE + (0x2e <<2)) + //31:16. VPU EF2 trigger selection read source type. + //15:0. VPU EF2 trigger selection read source select. +#define DMC_VPU_EF2_PROT (DMC_SEC_REG_BASE + (0x2f <<2)) + //bit 24:16. 16 VPU EF2 controlled write subIDs selection. + //bit 15:0. 16 VPU EF2 controlled read subIDs selection. +#define DMC_VPU_EF2_READ (DMC_SEC_REG_BASE + (0x30 <<2)) + //EF2 controlled DMC_VPU_SEC_READ_CTRL. +#define DMC_VPU_EF2_WRITE (DMC_SEC_REG_BASE + (0x31 <<2)) + //EF2 controlled DMC_VPU_SEC_WRITE_CTRL. + + //GE2D is seperated port in GX. +#define DMC_GE2D_SEC_CTRL (DMC_SEC_REG_BASE + (0x34 <<2)) + //bit 31:22 NOT USED. + //bit 21:16. GE2D secure control after EF triggered. + //bit 14:12 GE2D EF proection selection after EF triggered.. + //bit 11:10 GE2D Electronic fence trigger read source secure type selection. + //bit 9:8 GE2D Electronic fence trigger read source selection. + //bit 5:4. GE2D write destination 2 secruity control bits. + //bit 3:2. GE2D read source 2 secruity control bits. + //bit 1:0. GE2D read source 1 secruity control bits. + +#define DMC_PARSER_SEC_CTRL (DMC_SEC_REG_BASE + (0x35 <<2)) + //bit 11:8. Pasrese write and read security contrl bits after EF triggered. + //bit 7:6. Parser EF trigger protection enable. + //bit 5. Parser EF trigger read source type. + //bit 4 Pasrer EF trigger read source enable. + //bit 3:2. Parser write security control bits. + //bit 1:0. Parser read security control bits. +#define DMC_DEV_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x36 <<2)) + //16 device subID read access security control bits. each subID 2 bits. +#define DMC_DEV_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x37 <<2)) + //16 device subID write access security control bits. each subID 2 bits. + + +//2 DES key one for secure region and one for non-secure region. +#define DMC_DES_KEY0_H (DMC_SEC_REG_BASE + (0x90 <<2)) +#define DMC_DES_KEY0_L (DMC_SEC_REG_BASE + (0x91 <<2)) + //64bits data descrable key for security level 0 ( DES key) + +#define DMC_DES_KEY1_H (DMC_SEC_REG_BASE + (0x92 <<2)) +#define DMC_DES_KEY1_L (DMC_SEC_REG_BASE + (0x93 <<2)) + //64bits data descrable key for security level 1( DES key) + +#define DMC_DES_PADDING (DMC_SEC_REG_BASE + (0x9a <<2)) + //32bits address padding used for DES data generation. + +#define DMC_CA_REMAP_L (DMC_SEC_REG_BASE + (0x9b <<2)) +#define DMC_CA_REMAP_H (DMC_SEC_REG_BASE + (0x9c <<2)) + //This is a 16x4 address remap look up table. + //the column address bit 7:4 would be the index input and be replace with the value stored in these register. + //{DMC_CA_REMAP_H, DMC_CA_REMAP_L} + //bit 63:60: new address for index 15 + //bit 59:56: new address for index 14 + //bit 55:52: new address for index 13 + //bit 51:48: new address for index 12 + //bit 47:44: new address for index 11 + //bit 43:40: new address for index 10 + //bit 39:36: new address for index 9 + //bit 35:32: new address for index 8 + //bit 31:28: new address for index 7 + //bit 27:24: new address for index 6 + //bit 23:20: new address for index 5 + //bit 19:16: new address for index 4 + //bit 15:12: new address for index 3 + //bit 11:8: new address for index 2 + //bit 7:4: new address for index 1 + //bit 3:0: new address for index 0 + + +// two range protection function. +#define DMC_PROT0_RANGE (DMC_SEC_REG_BASE + (0xa0 <<2)) + //protection 0 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address. + //bit 31:16 : range end address. + //bit 15:0 : range start address +#define DMC_PROT0_CTRL (DMC_SEC_REG_BASE + (0xa1 <<2)) + //bit 19. protection 0 for write access enable bit. + //bit 18. protection 0 for read access enable bit. + //bit 17. protection 0 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR. + //bit 16. not used. + //bit 15:0 each bit to enable one of the 15 channel input for the protection function. + +#define DMC_PROT1_RANGE (DMC_SEC_REG_BASE + (0xa2 <<2)) + //protection 1 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address. + //bit 31:16 : range end address. + //bit 15:0 : range start address +#define DMC_PROT1_CTRL (DMC_SEC_REG_BASE + (0xa3 <<2)) + //bit 19. protection 1 for write access enable bit. + //bit 18. protection 1 for read access enable bit. + //bit 17. protection 1 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR. +//two data point +#define DMC_WTCH0_D0 (DMC_SEC_REG_BASE + (0xa4 <<2)) + //WTCH0 will watch upto 128bits data access. +#define DMC_WTCH0_D1 (DMC_SEC_REG_BASE + (0xa5 <<2)) +#define DMC_WTCH0_D2 (DMC_SEC_REG_BASE + (0xa6 <<2)) +#define DMC_WTCH0_D3 (DMC_SEC_REG_BASE + (0xa7 <<2)) + // the watch point 0 data {d3, d2,d1,d0} +#define DMC_WTCH0_RANGE (DMC_SEC_REG_BASE + (0xa8 <<2)) + //address range. 64Kbyte boundary. + // 31:16 start address high 16. + // 15:0 start address high 16. +#define DMC_WTCH0_CTRL (DMC_SEC_REG_BASE + (0xa9 <<2)) + //bit 31:16. 16bits write data strb. + //bit 15:0. 16bits input channels select. +#define DMC_WTCH0_CTRL1 (DMC_SEC_REG_BASE + (0xaa <<2)) + //bit 2. watch point 0 enable. + //bit 1:0. watch point0 type. 2'b00 : double bytes. only watchpoint data 15:0 and data strb 1:0 is valid. 2'b01: 4 bytes. 2'b10: 8 bytes. 2'b11, all 16bytes. + +#define DMC_WTCH1_D0 (DMC_SEC_REG_BASE + (0xab <<2)) +#define DMC_WTCH1_D1 (DMC_SEC_REG_BASE + (0xac <<2)) +#define DMC_WTCH1_D2 (DMC_SEC_REG_BASE + (0xad <<2)) +#define DMC_WTCH1_D3 (DMC_SEC_REG_BASE + (0xae <<2)) + // the watch point 1 data {d3, d2,d1,d0} +#define DMC_WTCH1_RANGE (DMC_SEC_REG_BASE + (0xaf <<2)) + //address range. 64Kbyte boundary. + // 31:16 start address high 16. + // 15:0 start address high 16. +#define DMC_WTCH1_CTRL (DMC_SEC_REG_BASE + (0xb0 <<2)) + //bit 31:16. 16bits write data strb. + //bit 15:0. 16bits input channels select. +#define DMC_WTCH1_CTRL1 (DMC_SEC_REG_BASE + (0xb1 <<2)) + //bit 2. watch point 0 enable. + //bit 1:0. watch point0 type. 2'b00 : double bytes. only watchpoint data 15:0 and data strb 1:0 is valid. 2'b01: 4 bytes. 2'b10: 8 bytes. 2'b11, all 16bytes. + + +//trap function: all the enable the port ID read access or enable PORT ID and subID read access must be in the predefine range. otherwire the read access would be blocked. +// and an error will be generated. +#define DMC_TRAP0_RANGE (DMC_SEC_REG_BASE + (0xb2 <<2)) + // address trap0 range register. + //31:16. trap0 end address + //15:0 start0 address. +#define DMC_TRAP0_CTRL (DMC_SEC_REG_BASE + (0xb3 <<2)) + //bit 30 trap0 port ID 2 enable. + //bit 29 trap0 port ID 1 enable. + //bit 28 trap0 port ID 0 enable. + //bit 27 trap0 port ID 2 subid enable. + //bit 26 trap0 port ID 1 subid enable. + //bit 25 trap0 port ID 0 subid enable. + //bit 23:20. trap0 port port ID 2 channel ID number. + //bit 19:16. trap0 port port ID 2 subID ID number. + //bit 15:12. trap0 port ID 1 ID number. + //bit 11:8. trap0 port ID 1 subID ID number. + //bit 7:4. trap0 port ID 0 ID number. + //bit 3:0. trap0 port ID 0 subID ID number. + +#define DMC_TRAP1_RANGE (DMC_SEC_REG_BASE + (0xb4 <<2)) + //address trap range register. + //31:16. trap end address + //15:0 start address. +#define DMC_TRAP1_CTRL (DMC_SEC_REG_BASE + (0xb5 <<2)) + //bit 30 trap1 port ID 2 enable. + //bit 29 trap1 port ID 1 enable. + //bit 28 trap1 port ID 0 enable. + //bit 27 trap1 port ID 2 subid enable. + //bit 26 trap1 port ID 1 subid enable. + //bit 25 trap1 port ID 0 subid enable. + //bit 23:20. trap1 port port ID 2 channel ID number. + //bit 19:16. trap1 port port ID 2 subID ID number. + //bit 15:12. trap1 port ID 1 ID number. + //bit 11:8. trap1 port ID 1 subID ID number. + //bit 7:4. trap1 port ID 0 ID number. + //bit 3:0. trap1 port ID 0 subID ID number. + + + +//registers to check the security protection and watch point error information. +#define DMC_SEC_STATUS (DMC_SEC_REG_BASE + (0xb6 <<2)) + +#define DMC_VIO_ADDR0 (DMC_SEC_REG_BASE + (0xb7 <<2)) + //ddr0 write secure violation address. +#define DMC_VIO_ADDR1 (DMC_SEC_REG_BASE + (0xb8 <<2)) + //22 secure check violation. + //21 protection 1 vilation. + //20 protection 0 vilation. + //19:18. not use.d + //17 ddr0 write address overflow. write out of DDR size. + //16:14. ddr0 write violation AWPROT bits. + //13:0 ddr0_write violation ID. +#define DMC_VIO_ADDR2 (DMC_SEC_REG_BASE + (0xb9 <<2)) + //ddr1 write seure violation address +#define DMC_VIO_ADDR3 (DMC_SEC_REG_BASE + (0xba <<2)) + //22 ddr1 write secure check violation. + //21 ddr1 write protection 1 vilation. + //20 ddr1 write protection 0 vilation. + //19 ddr1 watch 1 catch + //18. ddr1 watch 0 catch. + //17 ddr1 write address overflow. write out of DDR size. + //16:14. ddr1 write violation AWPROT bits. + //13:0 ddr1_write violation ID. + +#define DMC_VIO_ADDR4 (DMC_SEC_REG_BASE + (0xbb <<2)) + //ddr0 read seure violation address +#define DMC_VIO_ADDR5 (DMC_SEC_REG_BASE + (0xbc <<2)) + //22 ddr0 read secure check violation. + //21 ddr0 read protection 1 violation. + //20 ddr0 read protection 0 violation. + //19 ddr0 read trap1 violation + //18 ddr0 read trap0 violation + //17 ddr 0 read address overflow. write out of DDR size. + //16:14. ddr 0 read violation ARPROT bits. + //13:0 ddr 0 read violation ID. + +#define DMC_VIO_ADDR6 (DMC_SEC_REG_BASE + (0xbd <<2)) + //ddr1 read seure violation address + +#define DMC_VIO_ADDR7 (DMC_SEC_REG_BASE + (0xbe <<2)) + //22 ddr1 read secure check violation. + //21 ddr1 read protection 1 violation. + //20 ddr1 read protection 0 violation. + //19 ddr1 read trap1 violation + //18 ddr1 read trap0 violation + //17 ddr 1 read address overflow. write out of DDR size. + //16:14. ddr 1 read violation ARPROT bits. + //13:0 ddr 1 read violation ID. + + +//each row bank and rank address can be selected from any address. +#define DDR0_ADDRMAP_4 (DMC_SEC_REG_BASE + (0xd4 <<2)) + //29:25 rank select. + //24:20 ba3 //for bank group or 16banks.. + //19:15 ba2. + //14:10 ba1. + //9:5 ba0. + //4:0 ra15. +#define DDR0_ADDRMAP_3 (DMC_SEC_REG_BASE + (0xd3 <<2)) + //29:25 ra14. + //24:20 ra13. + //19:15 ra12. + //14:10 ra11. + //9:5 ra10. + //4:0 ra9. +#define DDR0_ADDRMAP_2 (DMC_SEC_REG_BASE + (0xd2 <<2)) + //29:25 ra8. + //24:20 ra7. + //19:15 ra6. + //14:10 ra5. + //9:5 ra4. + //4:0 ra3. +#define DDR0_ADDRMAP_1 (DMC_SEC_REG_BASE + (0xd1 <<2)) + //29:25 ra2. + //24:20 ra1. + //19:15 ra0. + //14:10 ca11. + //9:5 ca10. + //4:0 ca9. + +#define DDR0_ADDRMAP_0 (DMC_SEC_REG_BASE + (0xd0 <<2)) + //29:25 ca8. + //24:20 ca7. + //19:15 ca6. + //14:10 ca5. + //9:5 ca4. + //4:0 ca3. + +#define DDR1_ADDRMAP_4 (DMC_SEC_REG_BASE + (0xd9 <<2)) + //29:25 rank select. + //24:20 ba3 //for bank group or 16banks.. + //19:15 ba2. + //14:10 ba1. + //9:5 ba0. + //4:0 ra15. +#define DDR1_ADDRMAP_3 (DMC_SEC_REG_BASE + (0xd8 <<2)) + //29:25 ra14. + //24:20 ra13. + //19:15 ra12. + //14:10 ra11. + //9:5 ra10. + //4:0 ra9. +#define DDR1_ADDRMAP_2 (DMC_SEC_REG_BASE + (0xd7 <<2)) + //29:25 ra8. + //24:20 ra7. + //19:15 ra6. + //14:10 ra5. + //9:5 ra4. + //4:0 ra3. +#define DDR1_ADDRMAP_1 (DMC_SEC_REG_BASE + (0xd6 <<2)) + //29:25 ra2. + //24:20 ra1. + //19:15 ra0. + //14:10 ca11. + //9:5 ca10. + //4:0 ca9. +#define DDR1_ADDRMAP_0 (DMC_SEC_REG_BASE + (0xd5 <<2)) + //29:25 ca8. + //24:20 ca7. + //19:15 ca6. + //14:10 ca5. + //9:5 ca4. + //4:0 ca3. + + +#define DMC_DDR_CTRL (DMC_SEC_REG_BASE + (0xda <<2)) + //bit 22. rank1 is same as rank0. only in not shared-AC mdoe. and chan0 second rank not selected. that's means still in rank0 32bits mode. + //bit 21. channel0 second rank selection enable. only in not shared-AC mode. + //bit 20. Shared AC mode. + //bit 19 :18 must be 0 always. becasue we'll use 32bits PHY data. + //bit 19: DDR channel 1 16bits data interface. 1 : 16bits data inteface. 0 : 32bits data interface + //bit 18: DDR channel 0 16bits data interface. 1 : 16bits data inteface. 0 : 32bits data interface + + //bit 17: for DDR channel 1. 1: only use 16bits data in a 32bits phy data interface. 0: normal 32bits data interface. + //bit 16. for DDR channel 0. 1: only use 16bits data in a 32bits phy data interface. 0: normal 32bits data interface. + //bit 10:8 channel bit selection in shared range. + //bit 7. DDR1_ONLY. 1: DDR channel 1 only. when both channel 0 and 1 in the design. 0 : normal. + //bit 6. DDR0_ONLY. 1: DDR channel 0 only. when both channel 0 and 1 in the design. 0 : normal. + //bit 5:3 : DDR channel 1 size. + //3'b000 : DDR channel 1 is 128MB. + //3'b001 : DDR channel 1 is 256MB. + //3'b010 : DDR channel 1 is 512MB. + //3'b011 : DDR channel 1 is 1GB. + //3'b100 : DDR channel 1 is 2GB. + //3'b101 : DDR channel 1 is 4GB. + //others : reserved. + //bit 2:0 : DDR channel 0 size. + //3'b000 : DDR channel 0 is 128MB. + //3'b001 : DDR channel 0 is 256MB. + //3'b010 : DDR channel 0 is 512MB. + //3'b011 : DDR channel 0 is 1GB. + //3'b100 : DDR channel 0 is 2GB. + //3'b101 : DDR channel 0 is 4GB. + //others : reserved.
\ No newline at end of file |