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path: root/arch/riscv/cpu
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* riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callbackChanho Park2023-08-22
* common: return type board_get_usable_ram_topHeinrich Schuchardt2023-08-15
* riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USEShengyu Qu2023-08-10
* riscv: Add SPL_ZERO_MEM_BEFORE_USE implementationShengyu Qu2023-08-10
* riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZEMinda Chen2023-08-10
* riscv: define a cache line size for the generic CPUHeinrich Schuchardt2023-07-24
* riscv: setup per-hart stack earlierBo Gan2023-07-24
* riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng2023-07-12
* ram: starfive: Read memory size information from EEPROMYanhong Wang2023-07-12
* riscv: Fix alignment of RELA sections in the linker scriptsBin Meng2023-06-27
* dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass2023-05-11
* riscv: Update alignment for some sections in linker scriptsBin Meng2023-04-20
* riscv: spl: Remove relocation sectionsBin Meng2023-04-20
* riscv: Avoid updating the link registerBin Meng2023-04-20
* riscv: Change to use positive offset to access relocation entriesBin Meng2023-04-20
* riscv: Optimize loading relocation typeBin Meng2023-04-20
* riscv: Optimize source end address calculation in start.SBin Meng2023-04-20
* riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoCYanhong Wang2023-04-20
* riscv: cpu: jh7110: Add support for jh7110 SoCYanhong Wang2023-04-20
* riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang2023-02-17
* configs: ae350: Enable v5l2 cache for AE350 platforms in SPLYu Chien Peter Lin2023-02-17
* riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPLYu Chien Peter Lin2023-02-17
* riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()Yu Chien Peter Lin2023-02-17
* riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang2023-02-17
* riscv: ax25: bypass malloc when spl fit boots from ramRick Chen2023-02-01
* riscv: ae350: Enable CCTL_SUENRick Chen2023-02-01
* riscv: cpu: check U-Mode before counteren writeNikita Shubin2023-02-01
* riscv: Fix detecting FPU support in standard extensionYu Chien Peter Lin2022-11-15
* riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin2022-11-03
* Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ...Tom Rini2022-09-26
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| * riscv: Introduce AVAILABLE_HARTSRick Chen2022-09-26
| * spl: introduce SPL_XIP to configNikita Shubin2022-09-26
* | board_f: Fix types for board_get_usable_ram_top()Pali Rohár2022-09-23
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* riscv: ae350: Fix XIP config boot failureLeo Yu-Chi Liang2022-08-11
* riscv: cpu: set gp before board_init_f_init_reserveNikita Shubin2022-08-11
* linker_lists: Rename sections to remove . prefixAndrew Scull2022-06-23
* Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.hTom Rini2022-06-06
* event: Convert arch_cpu_init_dm() to use eventsSimon Glass2022-03-10
* riscv: Enable SPI flash env for SiFive Unmatched.Thomas Skibo2021-12-02
* riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas2021-10-18
* riscv: ae350: enable Coherence Manager for ae350Leo Yu-Chi Liang2021-10-07
* sysreset: provide SBI based sysreset driverHeinrich Schuchardt2021-10-07
* board: sifive: use ccache driver instead of helper functionZong Li2021-09-07
* riscv: cpu: fu740: Fix typo of dateZong Li2021-08-17
* i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass2021-07-28
* riscv: sifive: fu740: Support i2c in splZong Li2021-07-06
* riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li2021-07-06
* riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-31
* drivers: clk: add fu740 supportGreen Wan2021-05-31
* riscv: cpu: fu740: Add support for cpu fu740Green Wan2021-05-31