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path: root/arch/riscv/cpu/fu540
Commit message (Expand)AuthorAge
* common: return type board_get_usable_ram_topHeinrich Schuchardt2023-08-15
* riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng2023-07-12
* board_f: Fix types for board_get_usable_ram_top()Pali Rohár2022-09-23
* board: sifive: use ccache driver instead of helper functionZong Li2021-09-07
* drivers: clk: add fu740 supportGreen Wan2021-05-31
* riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng2021-05-17
* Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng2021-05-14
* riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-05
* cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-27
* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-15
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| * common: Drop asm/global_data.h from common headerSimon Glass2021-02-02
* | riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng2021-02-03
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* riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controllerPragnesh Patel2020-11-28
* riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-30
* riscv: fu540: Use correct API to get L2 cache controller base addressBin Meng2020-08-25
* riscv: sifive: fu540: redundant initializationHeinrich Schuchardt2020-08-14
* riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC levelBin Meng2020-08-14
* riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng2020-08-14
* env: Enable SPI flash env for SiFive FU540Jagan Teki2020-07-24
* riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel2020-07-03
* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-04
* riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel2020-06-04