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path: root/arch/riscv/dts/ae350_32.dts
Commit message (Expand)AuthorAge
* riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin2023-02-17
* riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin2022-11-03
* riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng2021-06-17
* riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng2021-06-17
* riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng2021-06-17
* riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng2021-06-17
* riscv: ae350: dts: Add SPDX license headerBin Meng2021-06-17
* riscv: ae350: Switch to use binman to generate u-boot.itbBin Meng2021-05-19
* riscv: dts: Add #address-cells and #size-cells in nor nodeRick Chen2019-12-10
* riscv: dts: Support four cores SMPRick Chen2019-12-10
* riscv: dts: move out AE350 L2 node from cpus nodeRick Chen2019-09-03
* dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2019-04-12
* riscv: dts: ae350 support SMPRick Chen2019-04-08
* riscv: dts: Add ae350_32.dts for RV32IRick Chen2018-11-26