| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | riscv: define a cache line size for the generic CPU | Heinrich Schuchardt | 2023-07-24 |
| * | riscv: Rename SiFive CLINT to RISC-V ALINT | Bin Meng | 2023-07-12 |
| * | riscv: qemu: Switch to use binman to generate u-boot.itb | Bin Meng | 2021-05-19 |
| * | riscv: Split SiFive CLINT support between SPL and U-Boot proper | Bin Meng | 2021-05-17 |
| * | cpu: Rename SPL_CPU_SUPPORT to SPL_CPU | Simon Glass | 2021-03-27 |
| * | riscv: Rework riscv timer driver to only support S-mode | Sean Anderson | 2020-09-30 |
| * | riscv: add SPL support | Lukas Auer | 2019-08-26 |
| * | riscv: add run mode configuration for SPL | Lukas Auer | 2019-08-26 |
| * | riscv: Rename cpu/qemu to cpu/generic | Anup Patel | 2019-02-27 |
| index : misc/u-boot-kii-pro.git | |
| U-Boot fork with work-in-progress stuff | Ferass |
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